Data access latency evaluation system and method

Abstract

The present disclosure relates to a data access latency evaluation system and method, which comprises: a parameter configuration module configured to provide memory access parameters during data access latency testing; at least two data access units coupled to the parameter configuration module and to a memory via an on-chip network, and configured to read and write a two-dimensional data matrix in the memory based on the memory access parameters, wherein at least one of the at least two data access units is a pseudo-computing core; a latency data register group coupled to the at least two data access units, and configured to obtain latency data of the at least two data access units during access to the memory; and a latency evaluation module coupled to the latency data register group, and configured to obtain a latency evaluation result based on the latency data of the at least two data access units and preset latency design conditions. The present disclosure helps to improve the testing efficiency of the memory and the on-chip network, and helps to improve the development efficiency of the SoC.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chip testing, and in particular, to a data access delay evaluation system and method. BACKGROUND

[0002] A Network on Chip (NoC) is a communication network structure used in a System on Chip (SoC), in which integrated small chips (or dies) perform data read and write between the memory, such as a High Bandwidth Memory (HBM), through the Network on Chip. In order to improve the memory read and write efficiency, the memory can be provided with a main memory and a secondary cache, and the secondary cache has a higher read and write speed than the main memory. When the small chip reads the memory, it first checks whether the data to be read is stored in the secondary cache. If the data to be read is stored in the secondary cache (this case is called a hit), the data is read from the secondary cache. If the data to be read is not stored in the secondary cache (this case is called a miss), the data is read from the main memory.

[0003] With the development of the SoC system, the number of integrated small chips (or dies) is increasing, and the number of various computing cores in the small chips is also increasing, thereby bringing more and more pressure to the data throughput of the Network on Chip and the memory.

[0004] In order to ensure the design requirements of the Network on Chip and the memory for the computing core access, the memory and the Network on Chip need to be optimized and adjusted in the design stage. Therefore, how to complete the design and optimization of the memory and the Network on Chip as early as possible in the design stage to help shorten the design cycle of the SoC has become a problem to be solved. SUMMARY

[0005] Therefore, the present disclosure provides a data access delay evaluation system and method to help improve the test efficiency of the memory and the Network on Chip, shorten the test time of the memory and the Network on Chip, and help complete the test of the memory and the Network on Chip before the design of the computing core in the SoC system is completed, so that the test time of the memory and the Network on Chip can overlap with the design time of the computing core, thereby helping to shorten the development cycle of the SoC and helping to improve the development efficiency of the SoC.

[0006] The technical solution of the present disclosure is implemented as follows:

[0007] According to an aspect of an embodiment of the present disclosure, a data access delay evaluation system is provided, comprising:

[0008] a parameter configuration module, configured to provide a memory access parameter in a data access latency test;

[0009] at least two data access units, coupled to the parameter configuration module and to a memory through a network on chip, configured to read and write a two-dimensional data matrix in the memory through the network on chip based on the memory access parameter, wherein at least one of the at least two data access units is a dummy core, the dummy core having the same memory access function as a compute core, and the memory comprises a level two cache and a main memory;

[0010] a latency data register group, coupled to the at least two data access units, configured to obtain latency data of the at least two data access units during the access to the memory by the at least two data access units; and

[0011] a latency evaluation module, coupled to the latency data register group, configured to obtain a latency evaluation result according to the latency data of the at least two data access units and a preset latency design condition.

[0012] In a possible implementation, at least one of the at least two data access units is a compute core.

[0013] In a possible implementation, the data access latency evaluation system further comprises:

[0014] a data dump module, configured to dump waveform data during the reading and writing of the two-dimensional data matrix in the memory in a case where the latency evaluation result indicates that the latency data does not meet the requirement of the latency design condition.

[0015] In a possible implementation, the memory access parameter comprises at least one of a start parameter, a stop parameter, a process identification parameter, a global process identification parameter, a read-write request arbitration weight parameter, a maximum number of uncompleted write requests parameter, a maximum number of uncompleted read requests parameter, a write request length parameter, a write request height parameter, a write request burst transmission length parameter, a write request step parameter, a write address parameter, a read request length parameter, a read request height parameter, a read request burst transmission length parameter, a read request step parameter, and a read address parameter.

[0016] In a possible implementation, the latency data comprises at least one of a number of read requests, a total read request latency, a number of completed read requests, a number of completed write requests, and a total busy duration of the data access unit.

[0017] The latency data register group comprises at least one of a number of read request latency register, a read request latency register, a number of completed read request register, a number of completed write request register, and a busy period register.

[0018] The read delay request number register is configured to record the number of read requests for counting read delay, the read delay register is configured to record the total read delay of the read request, the completed read request number register is configured to record the number of completed read requests, the completed write request number register is configured to record the number of completed write requests, and the busy period register is configured to record the total busy time of the data access unit.

[0019] In a possible implementation, the delay evaluation module comprises:

[0020] a calculation sub-module configured to calculate, according to delay data of the at least two data access units, a first delay of any one of the at least two data access units in a case of all cache miss of secondary cache data read and a second delay of the any one of the at least two data access units in a case of cache hit of secondary cache data read;

[0021] a judgment sub-module configured to obtain the delay evaluation result according to the first delay, the second delay and a delay design condition.

[0022] In a possible implementation, the delay design condition is:

[0023] the first delay of any one of the at least two data access units in a case of all cache miss of secondary cache data read is greater than the second delay of the any one of the at least two data access units in a case of cache hit of secondary cache data read, and a hit delay ratio obtained according to the first delay and the second delay is within a preset hit delay ratio interval.

[0024] According to another aspect of the embodiments of the present disclosure, a data access delay evaluation method is provided, comprising:

[0025] configuring memory access parameters for at least two data access units coupled to a memory through a network on chip, wherein at least one of the at least two data access units is a pseudo computing core, the pseudo computing core has the same memory access function as a computing core, and the memory comprises a secondary cache and a main memory;

[0026] reading and writing a two-dimensional data matrix in the memory by the at least two data access units based on the configured memory access parameters through the network on chip;

[0027] obtaining delay data of the at least two data access units during the access of the at least two data access units to the memory;

[0028] According to the delay data of the at least two data access units and preset delay design conditions, a delay evaluation result is obtained.

[0029] In a possible implementation, the memory access parameter configures no overlap between the two-dimensional data matrices respectively read and written by different data access units, or the memory access parameter configures overlap between the two-dimensional data matrices respectively read and written by different data access units.

[0030] In a possible implementation, the obtaining of the delay evaluation result according to the delay data of the at least two data access units and preset delay design conditions comprises:

[0031] According to the delay data of the at least two data access units, a first delay of any one of the at least two data access units in a case of all misses in a second cache data read and a second delay of the any one of the at least two data access units in a case of a hit in the second cache data read are calculated;

[0032] According to the first delay, the second delay and the delay design conditions, the delay evaluation result is obtained.

[0033] As can be seen from the above solution, in the data access latency evaluation system and method of the present disclosure, the memory access function of the computing core is implemented using a pseudo-computing core. On the one hand, it enables the testing phase of the memory and on-chip network to start in advance before the design of the computing core is completed, allowing the testing time of the memory and on-chip network to overlap with the design time of the computing core, which helps to shorten the development cycle of the SoC and improve the development efficiency of the SoC. On the other hand, since the pseudo-computing core does not have the computing function of the computing core but only has the same memory access function as the computing core, using the pseudo-computing core also helps to save the time required for the computing core to perform calculations, thus helping to shorten the testing time of the memory and on-chip network and improve the testing efficiency of the memory and on-chip network. At the same time, in the related art, the SoC sets relevant registers for the memory access of the computing core. Therefore, in the data access latency evaluation system and method of the present disclosure, the pseudo-computing core can reuse these relevant registers required for the computing core to access the memory. Thus, there is no need to separately design corresponding registers for accessing the memory for each pseudo-computing core, saving the design time of the relevant registers. And because the pseudo-computing core reuses these registers for accessing the memory, it enables the pseudo-computing core to simulate the real computing core accessing the memory. As a result, testers at each stage can simulate the real behavior of the computing core accessing the memory by configuring these registers without software programming, and then test the performance of the memory and on-chip network. On this basis, the present disclosure also allows the process control of multiple cores within the chip to be achieved by configuring these registers, enabling multi-core and multi-process operation within the chip. Therefore, the real chip behavior can be simulated during testing, and thus it can be directly used to test the relevant read and write performance of the on-chip bus and inter-chip bus between multiple processes of the chip, reducing the software programming complexity. In addition, the present disclosure also allows controlling the maximum outstanding requests for reading and writing and the arbitration weights of related read and write requests through the registers, so as to more accurately control the read and write traffic on the bus, which is more flexible and convenient and closer to the actual scenario. The present disclosure also allows directly reading and writing two-dimensional data matrices to the memory through the configuration of the registers. During the read performance test of the memory, the overlap situation between different two-dimensional data matrices and the impact of the secondary cache are also considered, making the test scenario closer to the actual operation scenario of the artificial intelligence chip and making the test results more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of the connection structure of the computing core, NoC, and memory in a chip in the related art;

[0035] Figure 2 is a schematic diagram of the structure of a data access latency evaluation system shown according to an exemplary embodiment;

[0036] Figure 3Ais an embodiment structure diagram of the data access unit in the data access delay evaluation system in the case of all using pseudo computing cores;

[0037] Figure 3B is an embodiment structure diagram of the data access unit in the data access delay evaluation system in the case of part of the data access units using pseudo computing cores and the other part of the data access units using computing cores;

[0038] Figure 4A is a logical arrangement structure diagram of a two-dimensional data matrix according to an illustrative embodiment;

[0039] Figure 4B is a distribution diagram of a two-dimensional data matrix in a memory according to an illustrative embodiment;

[0040] Figure 5 is a structure diagram of a delay evaluation module according to an illustrative embodiment;

[0041] Figure 6 is a flow diagram of a data access delay evaluation method according to an illustrative embodiment;

[0042] Figure 7A is a relationship diagram of a two-dimensional data matrix accessed by multiple data access units according to an illustrative embodiment;

[0043] Figure 7B is another relationship diagram of a two-dimensional data matrix accessed by multiple data access units according to an illustrative embodiment;

[0044] Figure 8 is a step diagram of obtaining a delay evaluation result according to an illustrative embodiment;

[0045] Figure 9 is a flow diagram of an application scenario of a data access delay evaluation system and method using the embodiments of the present disclosure.

[0046] In the drawings, the component names represented by the respective reference numerals are as follows:

[0047] 101, chiplet,

[0048] 1011, computing core,

[0049] 102, network on chip,

[0050] 103, memory,

[0051] 1031, level 2 cache,

[0052] 1032, main memory,

[0053] 201, parameter configuration module,

[0054] 202, data access unit,

[0055] 2021, pseudo-computing core,

[0056] 203, delay data register group,

[0057] 204, delay evaluation module,

[0058] 2041, computing sub-module,

[0059] 2042, judging sub-module,

[0060] 205, data dumping module,

[0061] 701, first data matrix,

[0062] 702, second data matrix,

[0063] 703, third data matrix,

[0064] 704, fourth data matrix,

[0065] 710, large two-dimensional data matrix,

[0066] 711, first data access unit,

[0067] 712, second data access unit,

[0068] 713, third data access unit,

[0069] 714, fourth data access unit. DETAILED DESCRIPTION

[0070] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the present disclosure is further described in detail below with reference to the accompanying drawings and embodiments.

[0071] It should be noted that the terms "first", "second", and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0072] The "coupling (or connection)" used in the specification and claims of the present disclosure can refer to any direct or indirect connection means, for example, the first device is coupled (or connected) to the second device, which should be interpreted as the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or certain connection means.

[0073] Figure 1is a connection structure diagram of a computing core, a network on chip and a memory in a chip in the related art. As shown in Figure 1 The chip, in particular, a SoC chip, can contain a plurality of small chips 101, and each small chip 101 contains a plurality of computing cores 1011, and the computing cores 1011 are coupled to a memory 103 through a network on chip 102. In order to improve the read and write speed of the memory 103, the memory 103 further includes a secondary cache 1031 and a main memory 1032. Because the secondary cache 1031 has a higher access speed, the frequently used data in the main memory 1032 and the data just accessed to the memory 103 are usually backed up in the secondary cache 1031 for fast access by each small chip 101.

[0074] In the chip development process, each component of the chip needs to be tested to ensure that the chip meets the design requirements. The complexity of the chip structure causes the development progress of each component in the chip to be different. If the chip is tested as a whole or each part of the chip after the chip design is completed, and then modified or passed according to the test results, the design and testing will be alternated in time, and the development cycle of the chip will be difficult to shorten because the development time and the testing time cannot be executed synchronously. Therefore, testing the completed design part of the chip during the design process will help shorten the development cycle of the chip.

[0075] Referring to Figure 1 If the memory 103 and the network on chip 102 need to be tested during the chip development stage, the participation of all computing cores 1011 coupled to the network on chip 102 is required. In one possible case, the network on chip 102 and the memory 103 have been designed, but the computing cores 1011 have not been completely designed, so it is difficult to test the network on chip 102 and the memory 103. In another possible case, the network on chip 102, the memory 103 and all computing cores 1011 have been designed, so the network on chip 102 and the memory 103 can be tested. However, during the testing process, the computing cores 1011 need to occupy part of the time in the testing process due to the implementation of their own related computing functions, so the testing of the network on chip 102 and the memory 103 will be delayed due to the waiting for the completion of the computing task of the computing cores 1011.

[0076] Therefore, the embodiments of the present disclosure provide a data access delay evaluation system and method to help improve the test efficiency of the memory and the network on chip, shorten the test time of the memory and the network on chip, and help complete the test of the memory and the network on chip before the design of the computing core in the SoC system is completed, so that the test time of the memory and the network on chip can overlap with the design time of the computing core, thereby helping to shorten the development cycle of the SoC and improve the development efficiency of the SoC.

[0077] Figure 2 is a structural schematic diagram of a data access delay evaluation system according to an illustrative embodiment, which can be used for data access test of the memory and the network on chip to obtain test data such as data transmission bandwidth of the network on chip and data read-write bandwidth of the memory. As shown in Figure 2 the data access delay evaluation system mainly includes a parameter configuration module 201, at least two data access units 202, a delay data register group 203, and a delay evaluation module 204. The parameter configuration module 201 is used to provide memory access parameters during data access delay test. The at least two data access units 202 are coupled to the parameter configuration module 201 and coupled to the memory 103 through the network on chip 102, and are used to read and write a two-dimensional data matrix in the memory 103 through the network on chip 102 based on the memory access parameters, wherein at least one of the at least two data access units 202 is a pseudo computing core, the pseudo computing core has the same memory access function as the computing core, and the memory 103 includes a secondary cache 1031 and a main memory 1032. The delay data register group 203 is coupled to the at least two data access units 202, and is used to obtain delay data of the at least two data access units 202 during access to the memory 103 by the at least two data access units 202. The delay evaluation module 204 is coupled to the delay data register group 203, and is used to obtain a delay evaluation result according to the delay data of the at least two data access units 202 and a preset delay design condition. As a more specific embodiment, the pseudo computing core does not have the computing function of the computing core, but only has the same memory access function as the computing core.

[0078] The delay design condition is a condition for evaluating whether the system or device meets the design requirement. If the delay data satisfies the delay design condition, the system or device meets the design requirement. If the delay data does not satisfy the delay design condition, the system or device does not meet the design requirement. For example, in the embodiments of the present disclosure, if the on-chip network and the memory are collectively referred to as a storage device, the delay design condition can be a condition for evaluating whether the storage device (including the on-chip network and the memory) meets the design requirement. If the delay data satisfies the delay design condition, the storage device meets the design requirement. If the delay data does not satisfy the delay design condition, the storage device does not meet the design requirement. For example, in the embodiments of the present disclosure, assuming that the on-chip network has been tested or evaluated in advance and is proved to meet the design requirement, the delay design condition can be a condition for evaluating whether the memory meets the design requirement. If the delay data satisfies the delay design condition, the memory meets the design requirement. If the delay data does not satisfy the delay design condition, the memory does not meet the design requirement.

[0079] In the data access delay evaluation system of the embodiments of the present disclosure, at least one of the at least two data access units 202 is a pseudo computing core, so that the memory access function of the computing core is realized by using the pseudo computing core to replace the computing core, thereby on one hand, when the design of the computing core is not completed, the pseudo computing core can be used to enter the test stage of the on-chip network 102 and the memory 103 in advance, and on the other hand, because the pseudo computing core does not have the computing function of the computing core, but only has the same memory access function as the computing core, the pseudo computing core can save the circuit space related to the computing function of the computing core and help to save the time required for the computing core to perform computation, thereby helping to save the software and hardware resources of the data access delay evaluation system and helping to shorten the test time of the on-chip network and the memory, and improve the test efficiency of the on-chip network and the memory.

[0080] In the data access delay evaluation system of the embodiments of the present disclosure, at least two data access units 202 read and write a two-dimensional data matrix in the memory 103 through the network on chip 102 based on the memory access parameters, thereby helping to adapt to the requirements of scenarios such as matrix operation (for example, operation of an artificial intelligence chip). For example, in a matrix operation scenario, a large two-dimensional data matrix is stored in the memory 103, and each data access unit 202 simulates a corresponding calculation core to obtain a small two-dimensional data matrix in a different region of the large two-dimensional data matrix. These small two-dimensional data matrices may or may not overlap. In a case where the small two-dimensional data matrices overlap, for example, between two small two-dimensional data matrices, at least the last row of data of one small two-dimensional data matrix and at least the first row of data of another small two-dimensional data matrix are data stored in the same address location in the memory 103, and the same address location needs to be accessed by at least two calculation cores. In the case where there is no overlap between the small two-dimensional data matrices, when each data access unit 202 reads the respective two-dimensional data matrix from the memory 103: if it is the first time to read from the memory 103, because there is no corresponding backup data in the secondary cache 1031, each data access unit 202 reads from the main memory 1032, at this time the delay of each data access unit 202 reading the main memory 1032 is obtained, and then it can be evaluated whether the delay in this case meets the design requirements; if it is not the first time to read from the memory 103, because there may be corresponding backup data in the secondary cache 1031, each data access unit 202 can read the respective two-dimensional data matrix from the secondary cache 1031, at this time the delay of each data access unit 202 reading the secondary cache 1031 is obtained, and then it can be evaluated whether the delay in this case meets the design requirements.

[0081] In the case of overlap between the small two-dimensional data matrices, when each data access unit 202 reads the respective two-dimensional data matrix from the memory 103: if it is the first time to read from the memory 103, because there is no corresponding backup data in the secondary cache 1031, each data access unit 202 reads from the main memory 1032, wherein, because the two-dimensional data matrix is read, the two-dimensional data matrix is read row by row according to the rows of the matrix, and at the same time, in order to improve the access speed of the memory 103, the read data is backed up in the secondary cache 1031 for subsequent fast reading, in this case, when two data access units 202 read two small two-dimensional data matrices that overlap at the same time, the two data access units 202 will read the first row of data of the respective small two-dimensional data matrix at the same time, because at least the last row of data of one small two-dimensional data matrix (assuming it is matrix A) and at least the first row of data of another small two-dimensional data matrix (assuming it is matrix B) are data stored in the same address location in the memory 103 (assuming it is called overlapping data), therefore, the data access unit 202 reading matrix B will read the overlapping data before the data access unit 202 reading matrix A, and the data of matrix B being read will also be backed up in the secondary cache 1031 at the same time, and then when the data access unit 202 reading matrix A reads the overlapping data, it can directly read the overlapping data from the secondary cache 1031 without reading from the main memory 1032, thereby improving the data read speed of the data access unit 202 of matrix A and reducing the data read delay. At this time, the delay of each data access unit 202 reading the two-dimensional data matrix from the memory 103 in the case of overlap is obtained, and then it can be evaluated whether the delay in this case meets the design requirements.

[0082] The above is an example of a plurality of test purposes that can be achieved by at least two data access units 202 reading and writing two-dimensional data matrices in the memory 103 through the network on chip 102, other test purposes, such as delay testing in the case of some data access units 202 performing read data and other data access units 202 performing write data, can also be tested using the reading and writing of two-dimensional data matrices. At least two data access units 202 using the reading and writing of two-dimensional data matrices can achieve more kinds of test purposes.

[0083] Figure 3A is an embodiment structure diagram of the data access delay evaluation system in the case of all data access units using pseudo computing cores, like Figure 3AAs shown, in the illustrative embodiment, the data access delay evaluation system mainly comprises a parameter configuration module 201, at least two pseudo computing cores 2021, a delay data register group 203, and a delay evaluation module 204. The parameter configuration module 201 is configured to provide memory access parameters during data access delay testing. The at least two pseudo computing cores 2021 are coupled to the parameter configuration module 201 and coupled to the memory 103 through the network on chip 102, and are configured to read and write a two-dimensional data matrix in the memory 103 through the network on chip 102 based on the memory access parameters, wherein the pseudo computing cores 2021 have the same memory access function as the computing cores, and the memory 103 comprises a secondary cache 1031 and a main memory 1032. The delay data register group 203 is coupled to the at least two pseudo computing cores 2021, and is configured to obtain delay data of the at least two pseudo computing cores 2021 during the at least two pseudo computing cores 2021 accessing the memory 103. The delay evaluation module 204 is coupled to the delay data register group 203, and is configured to obtain a delay evaluation result according to the delay data of the at least two pseudo computing cores 2021 and a preset delay design condition.

[0084] In the illustrative embodiment, in the case that part of the computing cores are completed in design and testing, the data access delay evaluation system of the embodiments of the present disclosure can further comprise the computing cores completed in design and testing. Figure 3B is an embodiment structure diagram in the case that part of data access units in the data access delay evaluation system adopt pseudo computing cores and another part of data access units adopt computing cores, as shown in Figure 3BAs shown, the data access delay evaluation system mainly comprises a parameter configuration module 201, at least one pseudo-compute core 2021, at least one compute core 1011, a delay data register group 203, and a delay evaluation module 204. The parameter configuration module 201 is configured to provide memory access parameters during data access delay testing. The at least one pseudo-compute core 2021 and the at least one compute core 1011 are coupled to the parameter configuration module 201 and coupled to the memory 103 through the network on chip 102, and are configured to read and write a two-dimensional data matrix in the memory 103 through the network on chip 102 based on the memory access parameters, wherein the pseudo-compute core 2021 has the same memory access function as the compute core 1011, and the memory 103 comprises a secondary cache 1031 and a main memory 1032. The delay data register group 203 is coupled to the at least one pseudo-compute core 2021 and the at least one compute core 1011, and is configured to obtain delay data of the at least one pseudo-compute core 2021 and the at least one compute core 1011 during access to the memory 103 by the at least one pseudo-compute core 2021 and the at least one compute core 1011. The delay evaluation module 204 is coupled to the delay data register group 203, and is configured to obtain a delay evaluation result according to the delay data of the at least two pseudo-compute cores 2021 and a preset delay design condition. In an illustrative embodiment, the compute core 1011 is configured to perform computation in addition to reading and writing the two-dimensional data matrix in the memory 103 through the network on chip 102 based on the memory access parameters. In an illustrative embodiment, the transmission bandwidth of the at least one pseudo-compute core 2021 is the same as that of the at least one compute core 1011.

[0085] In an illustrative embodiment, as shown in Figure 2 、 Figure 3A all the data access units 202 can be pseudo-compute cores 2021; in an illustrative embodiment, as shown in Figure 2 、 Figure 3B some of the data access units 202 can be pseudo-compute cores 2021 and the others can be compute cores 1011; in an illustrative embodiment, as shown in Figure 2 、 Figure 3B in the case where some of the data access units 202 are pseudo-compute cores 2021 and the others are compute cores 1011, the number of pseudo-compute cores 2021 is greater than that of compute cores 1011, for example, as shown in Figure 3B the data access delay evaluation system can comprise at least two pseudo-compute cores 2021 and at least one compute core 1011, and the number of pseudo-compute cores 2021 is greater than that of compute cores 1011.

[0086] In the illustrative embodiment, the computing cores can be at least one of vector cores, tensor cores. For example, in the case of one computing core, the computing core can be a vector core or a tensor core, in the case of more than one computing core, the computing cores can all be vector cores, or the computing cores can all be tensor cores, or a part of the computing cores are vector cores and another part of the computing cores are tensor cores.

[0087] Figure 3B The computing core 1011 is introduced in the data access delay evaluation system of the embodiment, so that the test process of the on-chip network 102 and the memory 103 can be closer to the real running scene of the chip, and the obtained delay data can be more reliable.

[0088] For Figure 3B In order to shorten the test time of the data access delay as much as possible and improve the test efficiency of the data access delay, the data access delay evaluation system of the embodiment, in the illustrative embodiment, the number of pseudo-computing cores 2021 is greater than the number of computing cores 1011. Because the number of pseudo-computing cores 2021 is greater than the number of computing cores 1011, it helps to reduce the proportion of the time occupied by the computing cores 1011 in performing the computing task in the test process in the whole test process, so as to help achieve a better balance between the reliability of the delay data and the improvement of the test efficiency.

[0089] As Figure 2 , Figure 3A , Figure 3B In the illustrative embodiment, in order to facilitate modification and optimization of the on-chip network 102 and the memory 103 according to the delay evaluation result, in the illustrative embodiment, the data access delay evaluation system of the embodiment further comprises a data dumping module 205. The data dumping module 205 is used to dump the waveform data during the two-dimensional data matrix in the read-write memory 103 in the case that the delay evaluation result indicates that the delay data does not meet the delay design condition requirement.

[0090] In the illustrative embodiment, the memory access parameters include at least one of a start parameter, a stop parameter, a maximum number of uncompleted write request parameters, a maximum number of uncompleted read request parameters, a write request length parameter, a write request height parameter, a write request burst transmission length parameter, a write request step parameter, a write address parameter, a read request length parameter, a read request height parameter, a read request burst transmission length parameter, a read request step parameter, and a read address parameter.

[0091] In the hardware system of the chip, the pseudo-computing core and the computing core control are usually implemented by registers, and therefore, corresponding to the memory access parameters, the configured registers include at least one of a start register (cfg_start), an end register (cfg_end), a maximum number of outstanding write request register (write_outstanding), a maximum number of outstanding read request register (read_outstanding), a write request length register (write_length), a write request height register (write_height), a write request burst transmission length register (write_burst_length), a write request stride register (write_stride), a write address register (write_address), a read request length register (read_length), a read request height register (read_height), a read request burst transmission length register (read_burst_length), a read request stride register (read_stride), and a read address register (read_address).

[0092] In the illustrative embodiment, the start register is configured to 1 to indicate to start issuing write requests and write data and to receive returned write return signals; the stop register is configured to 1 to indicate to immediately stop issuing write requests, and thus, based on the stop register, a tester can be allowed to stop the pseudo-compute core from issuing write requests and data in the middle of the process; the maximum outstanding write request number register is configured to allow a maximum number of outstanding write requests, i.e., when the number of write requests that have not received write return signals is equal to the maximum outstanding write request number, issuing of write requests is suspended to limit write data traffic on the bus; the maximum outstanding read request number register is configured to allow a maximum number of outstanding read requests, i.e., when the number of read requests that have not received returned data is equal to the maximum outstanding read request number, issuing of read requests is suspended to limit read data traffic on the bus; the write request length register is configured to the length of the main memory addresses accessed continuously by a write request, i.e., the length of each row in a two-dimensional data matrix and the total number of burst requests for each row; the write request height register is configured to the height of the two-dimensional data matrix of write requests, i.e., the number of rows in the two-dimensional data matrix; the write request burst length register is configured to the burst length of each write request issued, i.e., the length of the data corresponding to each write request, in the illustrative embodiment, burst_length = 0 represents that the length of the data corresponding to each write request is 128 bytes, burst_length = 1 represents that the length of the data corresponding to each write request is 256 bytes, and burst_length = 3 represents that the length of the data corresponding to each write request is 512 bytes; the write request step register is configured to the interval step length between the continuous main memory addresses of each two write requests issued, i.e., the interval step length between each two rows of data in the two-dimensional data matrix in the main memory; the write address register is configured to the starting main memory address of the write request issued; the read request length register is configured to the length of the main memory addresses accessed continuously by a read request, i.e., the length of each row in a two-dimensional data matrix and the total number of burst requests for each row; the read request height register is configured to the height of the two-dimensional data matrix of read requests, i.e., the number of rows in the two-dimensional data matrix; the read request burst length register is configured to the burst length of each read request issued, i.e., the length of the data corresponding to each read request, in the illustrative embodiment, burst_length = 0 represents that the length of the data corresponding to each read request is 128 bytes, burst_length = 1 represents that the length of the data corresponding to each write request is 256 bytes, and burst_length = 3 represents that the length of the data corresponding to each write request is 512 bytes; the read request step register is configured to the interval step length between the continuous main memory addresses of each two read requests issued, i.e., the interval step length between each two rows of data in the two-dimensional data matrix in the main memory; and the read address register is configured to the starting main memory address of the read request issued.

[0093] In the illustrative embodiment, in order to facilitate the management of the process and the control of the read-write weight, the memory access parameter can further include at least one of a process identification parameter, a global process identification parameter, and a read-write request arbitration weight parameter. Corresponding to the process identification parameter, the global process identification parameter, and the read-write request arbitration weight parameter, the configured register can further include at least one of a process identification register (context_id), a global process identification register (global_context_id), and a read-write request arbitration weight register (arb_weight).

[0094] The process identification register is configured to run the process of the computing core simulated by the pseudo computing core; the global process identification register is configured to run the process of the whole chip corresponding to the process run by the computing core simulated by the current pseudo computing core, and the process identification parameter and the global process identification parameter, i.e., the information configured by the process identification register and the global process identification register, represent the mapping relationship between the in-core process and the chip process.

[0095] The read-write request arbitration weight register is configured to be the arbitration weight when the read-write request is simultaneously issued. In the illustrative embodiment, the read-write request arbitration weight register is configured to 1, indicating that the weight of the write request is 1:1 compared with the read request, the read-write request arbitration weight register is configured to 2, indicating that the weight of the write request is 1:2 compared with the read request, and the read-write request arbitration weight register is configured to 3, indicating that the weight of the write request is 1:3 compared with the read request. Generally, in the SoC, the read request and the write request of the computing core to the bus (for example, UCIe (Universal Chiplet Interconnect Express)) cannot be parallel, but the data is transmitted through other channels other than the read request and the write request, so the transmission of the data can be parallel with the access request. Generally, the access on the bus is more read than write, so in the illustrative embodiment, the proportion of the read-write request of the pseudo computing core can be configured through the read-write request arbitration weight register, so that it is more consistent with the proportion relationship of the read-write request on the actual bus, and the data access of the pseudo computing core is closer to the actual application scenario.

[0096] Through the control of each register on each data access unit 202, the access to the memory 103 according to the demand can be realized.

[0097] Figure 4A is a schematic diagram of the logical arrangement structure of a two-dimensional data matrix according to an illustrative embodiment, Figure 4B is a distribution schematic diagram of a two-dimensional data matrix in a memory according to an illustrative embodiment. As Figure 4AAs shown, the logical arrangement of the two-dimensional data matrix is in the form of row-column arrangement, and the access of any one data access unit 202 to a two-dimensional data matrix is combined in the disclosure, Figure 4A and Figure 4B In the case of a write request, each burst represents the burst transfer length of each write request represented by the write request burst transfer length parameter, height represents the height of the two-dimensional data matrix represented by the write request height parameter, i.e. the number of rows of the two-dimensional data matrix, length represents the length of the main memory address continuously accessed by the write request represented by the write request length parameter, i.e. the length of each row in the two-dimensional data matrix, the sum of the burst transfer lengths of the write requests in each row, address represents the starting main memory address of the write request represented by the write address parameter, and stride represents the interval stride between the continuous main memory addresses of each two write requests represented by the write request stride parameter, i.e. the interval stride in the main memory between each two rows of data in the two-dimensional data matrix. In the case of a read request, each burst represents the burst transfer length of each read request represented by the read request burst transfer length parameter, height represents the height of the two-dimensional data matrix represented by the read request height parameter, i.e. the number of rows of the two-dimensional data matrix, length represents the length of the main memory address continuously accessed by the read request represented by the read request length parameter, i.e. the length of each row in the two-dimensional data matrix, the sum of the burst transfer lengths of the read requests in each row, address represents the starting main memory address of the read request represented by the read address parameter, and stride represents the interval stride between the continuous main memory addresses of each two read requests represented by the read request stride parameter, i.e. the interval stride in the main memory between each two rows of data in the two-dimensional data matrix.

[0098] As shown in Figure 4A , Figure 4B In the logical arrangement structure, the two-dimensional data matrix is arranged in the form of rows and columns, but in the actual storage location in the memory, the two-dimensional data matrix is continuously stored in the main memory space, and the data in each row of the two-dimensional data matrix is separated by the continuous main memory address space represented by the write request stride parameter or the read request stride parameter in the main memory space.

[0099] As shown in Figure 4A , Figure 4BAs shown, in the illustrative embodiment, during the write access process, when the start register of any one data access unit 202 is read as 1, the write request is issued through the network on a chip 102 to the memory 103 from the start memory 1032 address recorded in the write address register to start writing a two-dimensional data matrix into the memory 103, each piece of write request (including burst transmission of multiple write requests) continuously accesses the memory address length (i.e. the length of each row in the two-dimensional data matrix, the total amount of burst transmission request for each row write) specified by the write request length register, the data length corresponding to each write request is specified by the write request burst transmission length register, the interval step length between the continuous memory addresses of each two pieces of write request is specified by the write request step length register, and the total number of rows of write requests issued is specified by the write request height register. After receiving the write return signal returned by the memory 103, the operation is stopped.

[0100] During the write access process, when the stop register of any one data access unit 202 is read as 1, the write request is immediately stopped, the write data continues to be issued until the number of write requests is stopped, and after all the return signals of the issued write requests are received, the behavior of the arbitrary data access unit 202 is stopped. The write data corresponding to each write request is aligned with the write request, and the write data is not issued before the corresponding write request, so that the write data issued when stopped is not more than the write request. In the illustrative embodiment, an unfinished write request number counter is arranged in the pseudo-computing core to count the number of unfinished write requests. When the value of the unfinished write request number counter is greater than or equal to the configuration value of the maximum unfinished write request number register, the write request is stopped, and only when the value of the unfinished write request number counter is less than the configuration value of the maximum unfinished write request number register, the write request can be continuously issued, so as to realize the flow control when writing data into the memory 103. In the illustrative embodiment, the issuance of the write request and the write data by the data access unit 202 and the reception of the write return are completed based on the communication protocol designed in the SoC chip, so that the write return signal is not back-pressured to the bus.

[0101] As Figure 4A , Figure 4BAs shown, in the illustrative embodiment, during the read access process, when the start register of any one data access unit 202 is read to be 1, the read request is issued through the network-on-chip 102 to the memory 103 from the start main memory address recorded in the read address register to start reading a two-dimensional data matrix from the memory 103, each piece of read request (including burst transmission of multiple read requests) continuously accesses the main memory address length (i.e. the length of each row in the two-dimensional data matrix, the total amount of burst transmission request for each row read) specified by the read request length register, the data length corresponding to each read request is the length specified by the read request burst transmission length register, the interval step length between the continuous main memory addresses of each two pieces of read request is the interval step length specified by the read request step length register, and the total number of rows of read requests issued is the number of rows specified by the read request height register, and after receiving the read return data returned by the memory 103, the operation is stopped.

[0102] During the read access process, when the abort register of any one data access unit 202 is read to be 1, the read request is immediately stopped, and after all read return data is collected, all behaviors of the arbitrary data access unit 202 are stopped. In the illustrative embodiment, an unfinished read request number counter is arranged in the pseudo-computing core to count the number of unfinished read requests, and when the value of the unfinished read request number counter is greater than or equal to the configuration value of the maximum unfinished read request number register, the read request is stopped, and only when the value of the unfinished read request number counter is less than the configuration value of the maximum unfinished read request number register, the read request can be continuously issued, thereby realizing the flow control when reading data from the memory 103. In the illustrative embodiment, the data access unit 202 issues the read request and receives the read data based on the communication protocol designed in the SoC chip, and thus the bus is not back-pressured when receiving the read data.

[0103] In the illustrative embodiment, in order to facilitate the intuitiveness of the delay evaluation, the delay data can include the read request number for the statistical read delay, the total read request delay, the completed read request number, the completed write request number, the total busy time length of the data access unit 202, and the delay data register set 203 can include at least one of the read delay request number register (pfc_read_latecy_req_cnt), the read delay register (pfc_read_latecy_cnt), the completed read request number register (read_req_done_cnt), the completed write request number register (write_req_done_cnt), and the busy cycle register (busy_cycle_cnt) with respect to each delay data. The read delay request number register is used to record the read request number for the statistical read delay, the read delay register is used to record the total read request delay, the completed read request number register is used to record the completed read request number, the completed write request number register is used to record the completed write request number, and the busy cycle register is used to record the total busy time length of the data access unit. The average delay of the read request completed by the current data access unit can be intuitively seen through the read delay register and the read delay request number register. The read / write request number completed by the current data access unit can be intuitively seen through the completed read request number register and the completed write request number register, and the running time of the current data access unit can be intuitively seen through the busy cycle register, which facilitates the tester to understand the working time and state of the data access unit (pseudo-computing core, computing core) corresponding to the busy cycle register.

[0104] The access of the memory 103 mainly includes the read operation of the data stored in the memory 103 and the write operation of the data into the memory 103. For the read operation, because of the existence of the secondary cache 1031, the data can be obtained from the secondary cache 1031, which can help to improve the data read speed, and for the write operation, the data is usually written into the main memory 1032, which may not need the participation of the secondary cache 1031, so the process of the read operation is more complex than that of the write operation. Therefore, the evaluation condition of the read operation of the memory 103 can be different or more complex than that of the write operation, because the read operation of the memory 103 includes whether the data read of the secondary cache 1031 hits, and generally, the data read of the secondary cache 1031 hit means the improvement of the data read speed and the shortening of the delay. The following mainly combines the read data to explain the delay evaluation.

[0105] Figure 5 is a structural schematic diagram of a delay evaluation module according to an illustrative embodiment, as Figure 5In the illustrative embodiment, the delay evaluation module 204 includes a calculation submodule 2041 and a judgment submodule 2042. The calculation submodule 2041 is configured to calculate, according to the delay data of the at least two data access units 202, a first delay of any one of the at least two data access units 202 in a case of all misses in the data read of the second level cache 1031 and a second delay of the any one of the at least two data access units 202 in a case of a hit in the data read of the second level cache 1031. The judgment submodule 2042 is configured to obtain a delay evaluation result according to the first delay, the second delay and a delay design condition.

[0106] In the illustrative embodiment, for the write data, since there is no case of a hit or miss in the second level cache, the calculation submodule 2041 is configured to calculate, according to the delay data of the at least two data access units 202, a write data delay of any one of the at least two data access units 202. The judgment submodule 2042 is configured to obtain a delay evaluation result for the write data according to a comparison result of the write data delay and a preset write data delay threshold.

[0107] In the illustrative embodiment, the delay design condition is that the first delay of any one of the at least two data access units 202 in a case of all misses in the data read of the second level cache is greater than the second delay of the any one of the at least two data access units 202 in a case of a hit in the data read of the second level cache, and a hit delay ratio obtained according to the first delay and the second delay is within a preset hit delay ratio range. The delay design condition is expressed in a formula as follows:

[0108] T miss > T hit (1)

[0109] (T miss - T hit ) / T miss ∈ [LR Hit ratio range] (2)

[0110] wherein T miss is the first delay, T hit is the second delay, and [LR Hit ratio range] is the hit delay ratio range, wherein [LR Hit ratio range] is associated with a hit ratio, and the hit ratio refers to a hit rate of a cache block in the second level cache. The relationship between [LR Hit ratio range] and the hit ratio can be obtained through relevant tests. The delay design condition is satisfied when both the formula (1) and the formula (2) are satisfied, and the delay design condition is not satisfied when either the formula (1) or the formula (2) is not satisfied.

[0111] In the illustrative embodiment, the implementation of at least one of the data access unit 202, the pseudo computing core 2021, the computing core 1011, the network on chip 102, the memory 103, the parameter configuration module 201, the delay data register group 203, the delay evaluation module 204, the computing sub-module 2041, the judging sub-module 2042, and the data dumping module 205 can be a combination of multiple of hardware, firmware, and software (i.e., programs) according to different designs.

[0112] In hardware form, at least one of the data access unit 202, the pseudo computing core 2021, the computing core 1011, the network on chip 102, the memory 103, the parameter configuration module 201, the delay data register group 203, the delay evaluation module 204, the computing sub-module 2041, the judging sub-module 2042, and the data dumping module 205 can be implemented as logic circuits on an integrated circuit, e.g., various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units for implementing the functions of at least one of the data access unit 202, the pseudo computing core 2021, the computing core 1011, the network on chip 102, the memory 103, the parameter configuration module 201, the delay data register group 203, the delay evaluation module 204, the computing sub-module 2041, the judging sub-module 2042, and the data dumping module 205. The functions of at least one of the data access unit 202, the pseudo computing core 2021, the computing core 1011, the network on chip 102, the memory 103, the parameter configuration module 201, the delay data register group 203, the delay evaluation module 204, the computing sub-module 2041, the judging sub-module 2042, and the data dumping module 205 can be implemented as hardware circuits, e.g., various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0113] In software or firmware form, at least one of the related functions of the data access unit 202, pseudo-computing core 2021, computing core 1011, on-chip network 102, memory 103, parameter configuration module 201, delay data register group 203, delay evaluation module 204, computing submodule 2041, judgment submodule 2042, and data dump module 205 can be implemented as programming codes. For example, at least one of the data access unit 202, pseudo-computing core 2021, computing core 1011, on-chip network 102, memory 103, parameter configuration module 201, delay data register group 203, delay evaluation module 204, computing submodule 2041, judgment submodule 2042, and data dump module 205 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. Programming code can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium to implement at least one of the functions of the data access unit 202, pseudo-computing core 2021, computing core 1011, on-chip network 102, memory 103, parameter configuration module 201, delay data register group 203, delay evaluation module 204, computing submodule 2041, judgment submodule 2042, and data dump module 205.

[0114] In an illustrative embodiment, the data access latency evaluation system of the present disclosure is applicable to a SoC chip, etc., wherein the SoC chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0115] Figure 6 is a flowchart of a data access latency evaluation method according to an illustrative embodiment, which is applicable to the data access latency evaluation system of any one of the above embodiments, such as Figure 6 As shown in the figure, in an illustrative embodiment, the data access latency evaluation method mainly includes the following steps 601 to 604.

[0116] Step 601, configuring memory access parameters to at least two data access units coupled to a memory through a network on chip, wherein at least one of the at least two data access units is a dummy compute core, the dummy compute core has the same memory access function as a compute core, and the memory includes a secondary cache and a main memory.

[0117] Step 602, reading and writing a two-dimensional data matrix in the memory by the at least two data access units based on the configured memory access parameters through the network on chip.

[0118] Step 603, obtaining latency data of the at least two data access units during the access of the memory by the at least two data access units.

[0119] Step 604, obtaining a latency evaluation result according to the latency data of the at least two data access units and a preset latency design condition.

[0120] In the illustrative embodiment, the two-dimensional data matrices read and written by data access units with different memory access parameter configurations do not overlap. In this way, each data access unit is responsible for reading and writing a memory region without interfering with each other. Based on this, data access latency tests can be performed when the access addresses of each data access unit do not affect each other. This eliminates the latency caused by access address conflicts between data access units, and can be used to test whether the bandwidth allocation and latency balance of the on-chip network and / or memory for each data access unit meets the corresponding design requirements.

[0121] Figure 7A This is a schematic diagram illustrating the relationship between multiple data access units accessing a two-dimensional data matrix according to an illustrative embodiment. For example... Figure 7A As shown, this embodiment includes four two-dimensional data matrices accessed by four data access units, namely a first data matrix 701, a second data matrix 702, a third data matrix 703, and a fourth data matrix 704. The first data matrix 701 is accessed by the first data access unit 711, the second data matrix 702 by the second data access unit 712, the third data matrix 703 by the third data access unit 713, and the fourth data matrix 704 by the fourth data access unit 714. In this illustrative embodiment, the first data access unit 711 may be, for example, a real computing core, while the second, third, and fourth data access units 712, 713, and 714 may be, for example, pseudo-computing cores. Figure 7A As shown, the four two-dimensional data matrices can be a part of a large two-dimensional data matrix 710. Figure 7A In the illustrated embodiment, the first data matrix 701, the second data matrix 702, the third data matrix 703, and the fourth data matrix 704 do not overlap.

[0122] In the illustrative embodiment, there is an overlap between the two-dimensional data matrices read and written by the data access units configured with memory access parameters. In this way, the memory reads and writes of each data access unit will cause memory management operations for resource access and process coordination and scheduling due to the overlap between the two-dimensional data matrices, resulting in corresponding access latency. Furthermore, the presence of a secondary cache during read operations will also shorten the read latency to some extent, which can be used to test whether the memory meets the corresponding design requirements.

[0123] Figure 7B This is a schematic diagram illustrating the relationship between multiple data access units accessing a two-dimensional data matrix, according to an illustrative embodiment. For example... Figure 7BAs shown, the embodiment includes four two-dimensional data matrices respectively accessed by four data access units, which are a first data matrix 701, a second data matrix 702, a third data matrix 703, and a fourth data matrix 704. The first data matrix 701 is accessed by a first data access unit 711, the second data matrix 702 is accessed by a second data access unit 712, the third data matrix 703 is accessed by a third data access unit 713, and the fourth data matrix 704 is accessed by a fourth data access unit 714. In the illustrative embodiment, the first data access unit 711 can be a real computing core, and the second data access unit 712, the third data access unit 713, and the fourth data access unit 714 can be pseudo computing cores. Figure 7B As shown, the four two-dimensional data matrices can be part of a large two-dimensional data matrix 710. Unlike the embodiment shown in FIG. 7, Figure 7A Unlike the embodiment shown in FIG. 7, Figure 7BIn the shown embodiment, there is overlap between the first data matrix 701, the second data matrix 702, the third data matrix 703, and the fourth data matrix 704. For example, the last row of data of the first data matrix 701 is the first row of data of the second data matrix 702, the last row of data of the second data matrix 702 is the first row of data of the third data matrix 703, and the last row of data of the third data matrix 703 is the first row of data of the fourth data matrix 704. Thus, the data accessed by the first data access unit 711, the second data access unit 712, the third data access unit 713, and the fourth data access unit 714 are correlated, which in turn affects the respective access delays.For example, when the first data access unit 711, the second data access unit 712, the third data access unit 713, and the fourth data access unit 714 read the first data matrix 701, the second data matrix 702, the third data matrix 703, and the fourth data matrix 704 respectively for the first time at the same time, the four data access units read the first row data of the corresponding two-dimensional data matrix respectively at the same time, that is, at the same time, the first data access unit 711 reads the first row data of the first data matrix 701, the second data access unit 712 reads the first row data of the second data matrix 702, the third data access unit 713 reads the first row data of the third data matrix 703, and the fourth data access unit 714 reads the first row data of the fourth data matrix 704. Since it is the first reading, these data are stored in the main memory and there is no corresponding copy backup in the secondary cache. After the first reading, the first row data of the first data matrix 701, the first row data of the second data matrix 702, the first row data of the third data matrix 703, and the first row data of the fourth data matrix 704 are all backed up in the secondary cache. After reading the first row data of the corresponding two-dimensional data matrix, the four data access units read the second row data of the corresponding two-dimensional data matrix respectively at the same time, and so on. When the four access units read the last row data of the corresponding two-dimensional data matrix respectively at the same time, since the last row data of the first data matrix 701 is the first row data of the second data matrix 702 and has been backed up in the secondary cache, the first data access unit 711 only needs to read from the secondary cache when reading the last row data of the first data matrix 701, and the second data access unit 712, the third data access unit 713, and the fourth data access unit 714 also only need to read from the secondary cache when reading the last row data of the corresponding two-dimensional data matrix. It can be seen that the overlapping mode between the first data matrix 701, the second data matrix 702, the third data matrix 703, and the fourth data matrix 704 can improve the speed of the first data access unit 711, the second data access unit 712, and the third data access unit 713 in reading the corresponding two-dimensional data matrix for the first time to a certain extent. Since the fourth data access unit 714 needs to read each row data from the main memory, the speed of the first data access unit 711, the second data access unit 712, and the third data access unit 713 in reading the corresponding two-dimensional data matrix for the first time is faster than that of the fourth data access unit 714 in reading the fourth data matrix 704 for the first time, and the delay in reading data is lower. However, since not all data are obtained from the secondary cache, the delay is not the lowest.In this case, the delay design condition can be set to evaluate the delay.

[0124] Figure 8 Fig. 6 is a flowchart illustrating a method for obtaining a delay evaluation result according to an exemplary embodiment. Figure 8 As shown in Fig. 6, in the exemplary embodiment, step 604 can include steps 801 and 802.

[0125] Step 801: according to the delay data of the at least two data access units, calculating a first delay of any one of the at least two data access units in the case of all misses in the second cache data read and a second delay of the any one of the at least two data access units in the case of a hit in the second cache data read.

[0126] Step 802: obtaining a delay evaluation result according to the first delay, the second delay and the delay design condition.

[0127] In the exemplary embodiment, the delay design condition is that the first delay of any one of the at least two data access units in the case of all misses in the second cache data read is greater than the second delay of the any one of the at least two data access units in the case of a hit in the second cache data read, and a hit delay ratio obtained according to the first delay and the second delay is within a preset hit delay ratio range. The formula of the delay design condition is:

[0128] T miss > T hit (1)

[0129] (T miss - T hit ) / T miss ∈ [LR Hit ratio range] (2)

[0130] wherein T miss is the first delay, T hit is the second delay, and [LR Hit ratio range] is the hit delay ratio range, wherein [LR Hit ratio range] is associated with Hit ratio, and Hit ratio refers to a hit rate of a cache block in the second cache, and the relationship between [LR Hit ratio range] and Hit ratio can be obtained through relevant tests. Meanwhile satisfying the above formula (1) and formula (2) means satisfying the delay design condition, and not satisfying any one of formula (1) and formula (2) means not satisfying the delay design condition.

[0131] In a specific application scenario of the data access latency evaluation system and method according to embodiments of this disclosure, a network topology can be deployed on a hardware emulator. One real computing core and three pseudo computing cores are connected to the L2 cache and main memory via an on-chip network. Both the real and pseudo computing cores read two-dimensional data matrices of the same size. Figure 7A , Figure 7B For example, the large two-dimensional data matrix 710 stored in the main memory of the memory is 60×40, that is, 60 rows and 40 columns. In the illustrative embodiment, combined with Figure 4A As shown, 40 columns can represent 40 bursts in each row. Due to computational limitations, the computational core and three pseudo-computational cores will each compute an 8×8 small matrix in the large two-dimensional data matrix 710.

[0132] Figure 7A The corresponding computation task involves a situation where there is no overlap between the two-dimensional data matrices accessed by the computational core and the three pseudo-computational cores. Therefore, the first access to memory will not result in a cache miss. Assume that under this condition, the latency required for the computational core (first data access unit 711) to read its corresponding 8×8 first data matrix 701 is 800ns (nanoseconds).

[0133] Figure 7B The corresponding computational task involves partial overlap between the two-dimensional data matrices accessed by the computational core and the three pseudo-computational cores. Therefore, theoretically, when the computational core and the three pseudo-computational cores read data from memory, there will be partial cache hits in the L2 cache, resulting in a shorter read latency for the computational core (first data access unit 711). Assuming... Figure 7B Under certain conditions, the latency required for the computational core (first data access unit 711) to read its corresponding 8×8 first data matrix 701 is greater than the test result. Figure 7A In this case, a latency of 800ns is definitely not in line with design expectations (because there are partial cache hits in the L2 cache, the latency should be less than 800ns). Therefore, the actual data access waveform can be dumped and given to the L2 cache designers to observe the actual behavior of the computation core (first data access unit 711) when reading data from memory in the L2 cache, analyze the reasons for the latency not meeting expectations, and verify whether the L2 cache behavior meets design expectations. Assuming... Figure 7B Under the tested conditions, the latency required for the computing core (first data access unit 711) to read its corresponding 8×8 first data matrix 701 is 780ns, which is only slightly less than... Figure 7A The 800ns latency in this case is slightly low and does not conform to the theoretical latency of the L2 cache hit rate under the current situation. It is also possible to dump the actual data access waveform to the L2 cache designer for analysis and comparison to see if the L2 cache hit rate matches the theoretical value.

[0134] By using the data access delay evaluation system and method of the embodiments of the present disclosure, the size of the two-dimensional data matrix read and written by each pseudo-computing core and the starting address in the memory can be controlled to control the hit rate of the secondary cache under multi-core parallel tasks, and the reuse situation of the matrix of the multi-core concurrent computing task in the real computing task can be simulated.

[0135] Figure 9 is an application scenario flowchart of the data access delay evaluation system and method of the embodiments of the present disclosure. In this application scenario, each data access unit reads the two-dimensional data matrix in the memory to test the read data delay of the secondary cache. As shown in Figure 9 the application scenario mainly includes the following steps 901 to 914.

[0136] Step 901, the memory access parameters are issued to each data access unit in the data access delay evaluation system, and then step 902 is executed.

[0137] Step 902, each data access unit is synchronously started based on the memory access parameters, and then step 903 is executed.

[0138] Step 903, each data access unit reads data from the memory, and then step 904 is executed.

[0139] Step 904, for any one data access unit, it is judged whether the secondary cache is all miss when reading the two-dimensional data matrix. If yes, step 905 is executed, otherwise step 907 is executed.

[0140] Step 905, the delay data of the delay data register group of the data access unit with all misses is read, and then step 906 is executed.

[0141] Step 906, the first delay of the data access unit when all misses is calculated according to the read delay data, and then step 909 is executed.

[0142] Step 907, the delay data of the delay data register group of the data access unit with hits is read, and then step 908 is executed.

[0143] Step 908, the second delay of the data access unit when there are hits is calculated according to the read delay data, and then step 909 is executed.

[0144] Step 909, it is judged whether the first delay is greater than the second delay. If yes, step 910 is executed, otherwise step 914 is executed.

[0145] Step 910, the hit rate of the cache block in the secondary cache is obtained, and then step 911 is executed.

[0146] wherein, because the amount of overlapping data between the two-dimensional data matrices read and written by different data access units will be different, such as, Figure 7B In the relationship of the two-dimensional data matrices shown, according to different memory access parameters, there can be one row of data overlapping between the first data matrix and the second data matrix, or two rows of data overlapping, and so on, so that various data overlapping situations will result in different hit rates of the cache block in the secondary cache, and the higher the hit rate means the faster the reading speed of the data in the memory, and further means the shorter the second delay.

[0147] Step 911, obtaining a hit delay ratio according to the first delay and the second delay, and then performing step 912.

[0148] Step 912, judging whether the hit delay ratio meets the expected requirement of the hit rate of the cache block in the secondary cache, if yes, performing step 913, otherwise, performing step 914.

[0149] In the illustrative embodiment, in step 912, first, the hit delay ratio interval associated with the hit rate of the cache block in the secondary cache can be determined according to the hit rate of the cache block in the secondary cache, and then it is determined whether the hit delay ratio meets the expected requirement of the hit rate of the cache block in the secondary cache by judging whether the hit delay ratio is in the hit delay ratio interval. In the illustrative embodiment, if the hit delay ratio is in the hit delay ratio interval, the hit delay ratio meets the expected requirement of the hit rate of the cache block in the secondary cache, and if the hit delay ratio is not in the hit delay ratio interval, the hit delay ratio does not meet the expected requirement of the hit rate of the cache block in the secondary cache.

[0150] In the illustrative embodiment, the hit delay ratio interval corresponding to the different hit rates of the cache block in the secondary cache that meets the design requirement can be obtained in advance by testing means, and then called in step 912.

[0151] Step 913, the test is passed and the test is completed.

[0152] Step 914, dumping the data access waveform, and completing the test.

[0153] In other application scenarios, the delay of writing data to the memory can also be tested, wherein, because when writing data, data is usually written directly into the main memory, so it is slightly different from reading data, wherein, it can be directly judged whether it meets the design requirement according to the comparison of the write data delay and the preset write data delay threshold.

[0154] In the data access delay evaluation system and method of the embodiments of the present disclosure, the memory access function of the calculation core is implemented by using the pseudo calculation core, which on the one hand enables the memory and the on-chip network to enter the test stage in advance when the design of the calculation core is not completed, so that the test time of the memory and the on-chip network can overlap with the design time of the calculation core, thereby helping to shorten the development cycle of the SoC and improve the development efficiency of the SoC, and on the other hand, because the pseudo calculation core does not have the calculation function of the calculation core and only has the same memory access function as the calculation core, the pseudo calculation core also helps to save the time required for the calculation of the calculation core, thereby helping to shorten the test time of the memory and the on-chip network and improve the test efficiency of the memory and the on-chip network. At the same time, in the related art, the SoC sets related registers for the memory access of the calculation core, and then in the data access delay evaluation system and method of the embodiments of the present disclosure, the pseudo calculation core can reuse the related registers required for the memory access of the calculation core, so that there is no need to design the registers for accessing the memory for each pseudo calculation core, which can save the design time of the related registers. Moreover, because the pseudo calculation core reuses the registers for accessing the memory, the pseudo calculation core can simulate the real memory access of the calculation core, so that the testers at each stage can simulate the real behavior of the calculation core accessing the memory by configuring the registers without software programming, and then test the performance of the memory and the on-chip network. On this basis, the embodiments of the present disclosure can also allow the process control of the multiple cores in the chip to be realized by configuring the registers, and the multiple processes of the multiple cores in the chip to be realized, so that the real chip behavior can be simulated during the test, and therefore the related read-write performance of the on-chip bus and the inter-chip bus between multiple processes of the chip can be directly tested, which reduces the complexity of software programming. In addition, the embodiments of the present disclosure can also allow the maximum unfinished request of the read-write and the arbitration weight of the related read-write request to be controlled by the registers, so as to more accurately control the read-write traffic on the bus, be more flexible and convenient, and be closer to the actual scene. The embodiments of the present disclosure also allow the two-dimensional data matrix of the memory to be read and written by directly configuring the registers, and the overlapping between different two-dimensional data matrices and the influence of the second cache are also considered during the read performance test of the memory, so that the test scene is closer to the actual running scene of the artificial intelligence chip, and the test result is more reliable.

[0155] The above merely describes preferred embodiments of the present disclosure but should not be used to restrict the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A data access latency assessment system, characterized in that, include: The parameter configuration module is used to provide memory access parameters during data access latency testing; At least two data access units are coupled to the parameter configuration module and coupled to the memory via an on-chip network, for reading and writing a two-dimensional data matrix in the memory via the on-chip network based on the memory access parameters. At least one of the at least two data access units is a pseudo-computing core, which has the same memory access function as the computing core. The memory includes a secondary cache and main memory. A delayed data register group, coupled to the at least two data access units, is used to acquire delayed data from the at least two data access units during access to the memory by the at least two data access units; and, The delay evaluation module, coupled to the delay data register group, is used to obtain the delay evaluation result based on the delay data of the at least two data access units and the preset delay design conditions.

2. The data access latency assessment system according to claim 1, characterized in that: At least one of the at least two data access units is a computing core.

3. The data access latency assessment system according to claim 1, characterized in that, The data access latency assessment system also includes: A data dump module is used to dump waveform data during the reading and writing of a two-dimensional data matrix in the memory when the delay evaluation result indicates that the delay data does not meet the delay design requirements.

4. The data access latency assessment system according to claim 1, characterized in that: The memory access parameters include at least one of the following: startup parameters, abort parameters, process identifier parameters, global process identifier parameters, read / write request arbitration weight parameters, maximum number of incomplete write requests parameters, maximum number of incomplete read requests parameters, write request length parameters, write request height parameters, write request burst transfer length parameters, write request step size parameters, write address parameters, read request length parameters, read request height parameters, read request burst transfer length parameters, read request step size parameters, and read address parameters.

5. The data access latency assessment system according to claim 1, characterized in that: The latency data includes at least one of the following: the number of read requests used to calculate read latency, the total latency of read requests, the number of completed read requests, the number of completed write requests, and the total busy time of the data access unit. The delayed data register group includes at least one of the following: a read delay request count register, a read delay register, a completed read request count register, a completed write request count register, and a busy cycle register; wherein... The read latency request count register is used to record the number of read requests used for reading latency statistics. The read latency register is used to record the total read request latency. The completed read request count register is used to record the number of completed read requests. The completed write request count register is used to record the number of completed write requests. The busy cycle register is used to record the total busy time of the data access unit.

6. The data access latency assessment system according to claim 1, characterized in that, The delay assessment module includes: The calculation submodule is used to calculate, based on the latency data of the at least two data access units, a first latency of any one of the at least two data access units when all data reads from the secondary cache miss, and a second latency of any one of the data access units when there is a data read hit from the secondary cache. The judgment submodule is used to obtain the delay evaluation result based on the first delay, the second delay, and the delay design conditions.

7. The data access latency assessment system according to claim 1, characterized in that, The delay design condition is: The first delay of any one of the at least two data access units when all data reads from the second-level cache are missed is greater than the second delay of any one of the data access units when there is a data read from the second-level cache. Furthermore, the hit delay ratio obtained based on the first delay and the second delay is within a preset hit delay ratio range.

8. A method for evaluating data access latency, comprising: Memory access parameters are configured for at least two data access units coupled to memory via an on-chip network, wherein at least one of the at least two data access units is a pseudo-computing core, the pseudo-computing core having the same memory access functions as a computing core, and the memory includes a secondary cache and main memory; The at least two data access units read and write the two-dimensional data matrix in the memory through the on-chip network based on the configured memory access parameters; During the period when the at least two data access units access the memory, the delay data of the at least two data access units is acquired; The latency evaluation result is obtained based on the latency data of the at least two data access units and the preset latency design conditions.

9. The data access latency assessment method according to claim 8, characterized in that: The memory access parameters configure different data access units to read and write two-dimensional data matrices that do not overlap, or the memory access parameters configure different data access units to read and write two-dimensional data matrices that overlap.

10. The data access latency assessment method according to claim 8, characterized in that, The step of obtaining a latency evaluation result based on the latency data of the at least two data access units and preset latency design conditions includes: Based on the latency data of the at least two data access units, calculate the first latency of any one of the at least two data access units when all data reads from the second-level cache miss, and the second latency of any one of the data access units when there is a data read hit from the second-level cache. The delay evaluation result is obtained based on the first delay, the second delay, and the delay design conditions.

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