Simulation model and simulation method of LDMOS

Abstract

The invention provides a simulation model and a simulation method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor). The simulation model comprises a channel, a grid electrode, a source electrode, a drain electrode and a body region of the LDMOS, the leading-out end of the drain electrode is a drain end, and the leading-out end of the body region is a body end; an external resistor is connected between the drain terminal and the channel, and a voltage control current source is connected between the drain terminal and the body terminal; the anode of the voltage-controlled current source is connected with the drain terminal, and the cathode of the voltage-controlled current source is connected with the body terminal; the voltage-controlled current source is used for simulating the second peak characteristic of the characteristic curve of the current of the body region changing along with the voltage difference between the grid electrode and the source electrode. According to the method, the macro model of the external resistor is combined with the voltage control current source specially used for describing the secondary peak value of the current in the body region, the second higher current (secondary peak value) characteristic of the LDMOS is well described or simulated, and more accurate simulation reference can be provided for circuit designers.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a simulation model and a simulation method of LDMOS. Background Art

[0002] Laterally diffused field-effect transistors (LDMOS) are common high-voltage devices used in BCD processes. They offer high voltage withstand capability and low on-resistance. LDMOS is primarily used in power amplifiers, antenna switches, and transmitters.

[0003] The parasitic bipolar junction (BJT) effect at the drain end of the LDMOS device causes the body current Isub to be significantly different from the substrate current of conventional CMOS. Figure 1 As shown, Figure 1 The Isub current characteristics of ordinary CMOS (the x-axis is the gate-source voltage difference Vgs, the y-axis is the Isub current, and the source-drain voltage Vds is 2V, 3V, 4V and 5V respectively). Figure 2 The Isub current characteristics of an N-type LDMOS on a BCD process platform are shown. A comparison shows that the CMOS Isub exhibits a single peak with Vgs, but the LDMOS Isub exhibits a trend of first reaching a peak, then decreasing, then continuing to increase with Vgs, generating a second, higher current (Vds = 36V, 40V, and 44V). Currently, the BSIM model is completely incapable of describing or simulating this second, higher current (secondary peak) characteristic of LDMOS. Summary of the Invention

[0004] The present invention aims to provide a simulation model and method for LDMOS. The method employs a macro model of an external resistor combined with a voltage-controlled current source specifically for describing the secondary peak of the body current. This model effectively describes or simulates the second, higher current (secondary peak) characteristics of the LDMOS, providing a more accurate simulation reference for circuit designers.

[0005] The present invention provides a simulation model of LDMOS, comprising:

[0006] The channel, gate, source, drain and body region of the LDMOS; the lead-out end of the drain is the drain terminal, and the lead-out end of the body region is the body terminal;

[0007] An external resistor is connected between the drain terminal and the channel, and a voltage-controlled current source is connected between the drain terminal and the body terminal; the positive electrode of the voltage-controlled current source is connected to the drain terminal, and the negative electrode of the voltage-controlled current source is connected to the body terminal; the voltage-controlled current source is used to simulate the second peak characteristic of the characteristic curve of the body region current changing with the voltage difference between the gate and the source.

[0008] Furthermore, the LDMOS structure includes: a P-type substrate; an N-type epitaxial layer located on a surface of the P-type substrate; a P-well located within the N-type epitaxial layer; an N-well and a P+ region located within the P-well, wherein the N-well and the P+ region are separated by a first shallow trench isolation; a first N+ region located within the N-well; a second N+ region located within the N-type epitaxial layer, wherein the second N+ region is separated from the P-well by a second shallow trench isolation and a gate oxide and a gate on the gate oxide surface; wherein the gate covers a portion of the P-well and a portion of the second shallow trench isolation.

[0009] The P+ region is connected as the body terminal, the first N+ region is connected as the source terminal of the LDMOS, the gate is connected as the gate terminal of the LDMOS, and the second N+ region is connected as the drain terminal of the LDMOS.

[0010] Furthermore, when the LDMOS is an N-type channel, the expression of the current of the voltage-controlled current source as a function of voltage is:

[0011]

[0012] Wherein, Isub is the body current, the positive and negative currents represent the current direction of LDMOS, the simulator has its own max function, W and L represent the channel width and channel length of LDMOS, L modify is the channel length correction factor, WL modify Is the channel area correction factor; Is peak is the exponential empirical coefficient, peak co is the exponential slope in logarithmic coordinates, V gs is the gate-source voltage, V peak is a custom voltage fixed value, A and B are process experience coefficients; V ds is the drain-source voltage; N gm It is a fixed value and can be customized by the user; m vds It is V ds correction factor.

[0013] Furthermore, in the second peak curve describing the Isub, the peak co Determine the logarithmic slope of the Isub after it drops from the first peak and then rises in the second peak curve, the Is peak Determine the upper and lower amplitudes of the Isub after it is lifted, and the coefficients A and B determine the different V values ​​of the Isub after it is lifted. ds The spacing of the V peak Adjust where the current is raised.

[0014] Furthermore, when the LDMOS is a P-type channel, the expression of the current of the voltage-controlled current source as a function of voltage is:

[0015]

[0016] The simulator has a built-in min function.

[0017] Furthermore, the first peak characteristic of the characteristic curve of the body current is described by the substrate current model in the BSIM model, and the substrate current is described by formula (b):

[0018]

[0019] Among them, I ii is the substrate current, alpha0 is the proportional coefficient of the impact ionization rate, beta0 is the electric field attenuation coefficient, alpha1 is the high-order correction term for alpha0, V ds is the drain-source voltage, V dseff is the effective drain-source voltage, L eff is the effective channel length, and I0 is a preset current value.

[0020] Furthermore, the three parameters beta0, alpha0 and alpha1 in the substrate current model need to be turned on during simulation.

[0021] The present invention also provides a simulation method for LDMOS.

[0022] The simulation model of the LDMOS is used for simulation;

[0023] In the LDMOS simulation model, an external resistor is connected between the drain terminal and the channel of the LDMOS, and a voltage-controlled current source is connected between the drain terminal and the body terminal of the LDMOS. The voltage-controlled current source is used to simulate the second peak characteristic of the characteristic curve of the body region current changing with the voltage difference between the gate and source of the LDMOS.

[0024] Furthermore, the substrate current model in the BSIM model is used to simulate the first peak characteristic of the characteristic curve of the body current, and the three parameters beta0, alpha0 and alpha1 in the substrate current model need to be turned on during the simulation.

[0025] Furthermore, when the LDMOS is an N-type channel, the expression of the current of the voltage-controlled current source as a function of voltage is:

[0026]

[0027] Wherein, Isub is the body current, the positive and negative currents represent the current direction of LDMOS, the simulator has its own max function, W and L represent the channel width and channel length of LDMOS, L modify is the channel length correction factor, WL modify Is the channel area correction factor; Is peak is the exponential empirical coefficient, peak co is the exponential slope in logarithmic coordinates, V gs is the gate-source voltage, V peak is a custom voltage fixed value, A and B are process experience coefficients; V ds is the drain-source voltage; N gm It is a fixed value and can be customized by the user; m vds It is V ds correction factor.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention provides a simulation model and method for an LDMOS, comprising: a channel, gate, source, drain, and body region of the LDMOS; the lead end of the drain is the drain terminal, and the lead end of the body region is the body terminal; an external resistor is connected between the drain terminal and the channel, and a voltage-controlled current source is connected between the drain terminal and the body terminal; the positive electrode of the voltage-controlled current source is connected to the drain terminal, and the negative electrode of the voltage-controlled current source is connected to the body terminal; the voltage-controlled current source is used to simulate the secondary peak characteristic of a characteristic curve of the body region current varying with the voltage difference between the gate and the source. The present invention uses a macro model of the external resistor in combination with a voltage-controlled current source specifically used to describe the secondary peak of the body region current, thereby effectively describing or simulating the secondary, higher current (secondary peak) characteristic of the LDMOS, and can provide a more accurate simulation reference for circuit designers. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the Isub current characteristics of ordinary CMOS.

[0031] Figure 2 Schematic diagram of the Isub current characteristics of an N-channel LDMOS.

[0032] Figure 3 This is the first schematic diagram of the failure of the existing BSIM model to simulate the secondary peak of the LDMOS body current Isub.

[0033] Figure 4 This is the second schematic diagram showing the failure of the existing BSIM model simulation of the secondary peak value of the LDMOS body current Isub.

[0034] Figure 5Schematic diagram of the mechanism of the secondary peak of the body current Isub studied and analyzed in the present invention.

[0035] Figure 6 A schematic structural diagram of an LDMOS simulation model according to an embodiment of the present invention.

[0036] Figure 7 Schematic diagram of an equivalent circuit of a simulation model of LDMOS according to an embodiment of the present invention.

[0037] Figure 8 This is the first simulation diagram obtained using the existing reference empirical formula (a).

[0038] Figure 9 This is a second simulation diagram obtained using the existing reference empirical formula (a).

[0039] Figure 10 Schematic diagram of the body current Isub characteristics (solid line) when the improved formula of the present invention is adopted and the three parameters beta0, alpha0 and alpha1 in the BSIM model are turned off.

[0040] Figure 11 1 is a first schematic diagram of the body current Isub characteristic (solid line) when the improved formula of the present invention is adopted and the three parameters beta0, alpha0 and alpha1 in the BSIM model are turned on.

[0041] Figure 12 This is a second schematic diagram of the body current Isub characteristic (solid line) when the improved formula of the present invention is adopted and the three parameters beta0, alpha0 and alpha1 in the BSIM model are turned on.

[0042] Figure 13 This is a third schematic diagram of the body current Isub simulated using the improved formula of the present invention.

[0043] Figure 14 This is a fourth schematic diagram of the body current Isub simulated using the improved formula of the present invention.

[0044] The accompanying drawings are numerals as follows:

[0045] 110-P-type substrate; 121-drift region; 122-channel; 130-P-well; 140-N-well; 150-body region; 160-first shallow trench isolation; 170-source; 180-drain; 190-second shallow trench isolation; 200-gate oxide; 210-gate; 300-voltage-controlled current source; S-source terminal; B-body terminal; G-gate terminal; D-drain terminal; R1-external resistor. DETAILED DESCRIPTION

[0046] As background art, the BSIM model currently has no ability to describe or simulate the second higher current (secondary peak) characteristic of LDMOS.

[0047] Specifically, Figure 3 The first schematic diagram for the failure of the existing BSIM model to simulate the secondary peak of the body region current Isub of LDMOS. Figure 3 The simulation result (solid line) and the actual body region current Isub characteristic (dotted line) of LDMOS are shown in the figure, and the y-axis body region current Isub is in logarithmic coordinates. From Figure 3 It can be seen that the simulation result (solid line) of the secondary peak of the body region current Isub deviates seriously from the actual curve (dotted line).

[0048] Figure 4 The second schematic diagram for the failure of the existing BSIM model to simulate the secondary peak of the body region current Isub of LDMOS. Figure 4 The simulation result (solid line) and the actual body region current Isub characteristic (dotted line) of LDMOS are shown in the figure, and the y-axis body region current Isub is in linear coordinates. From Figure 4 It can be seen that the simulation result (solid line) of the secondary peak of the body region current Isub deviates seriously from the actual curve (dotted line).

[0049] In combination with Figure 2 As shown in the figure, the trend of the body region current Isub of LDMOS with the increase of Vgs is to first reach a peak, then the current decreases and then continues to increase, which will produce a second higher current. The body region current Isub in LDMOS is mainly composed of two parts. The first part: the influence of electron-hole pairs. Under large bias (high Vds), the electric field in the drift region is strong, which will cause impact ionization, generating electron-hole pairs. Electrons move towards the drain, while holes flow towards the substrate (base), forming the body region current Isub. The second part: the role of the parasitic BJT. The source, body region and drain of LDMOS can actually form a parasitic P-N-P BJT, with the source as the emitter, the body region as the base, and the drain as the collector. Under certain conditions, the BJT will be partially turned on, causing changes in the body region current Isub.

[0050] In-depth research has found that before the breakdown of the LDMOS device, the body region current Isub will usually exhibit two peaks with the change of the source-drain voltage Vds, corresponding to two mechanisms respectively. The first peak: the traditional impact ionization effect; under a small source-drain voltage Vds (close to the critical voltage of the device), such as Figure 5As shown, the electric field of the drift region 121 near the drain gradually increases, and the electrons accelerate in the high field region and collide with the lattice to produce impact ionization. The generated holes flow to the P-type substrate 110, forming the first peak of the body current Isub. The second peak: the opening of the parasitic BJT; when Vds further increases, the drift region 121 of the LDMOS enters a higher electric field state, impact ionization is further enhanced, causing more holes to be injected into the body region 150, causing the potential of the body region 150 to rise, which will make the PN junction between the body region 150 and the drift region 121 forward biased. This will open the parasitic P-N-P BJT (as shown in Figure 5 ), causing the body region 150 to further inject holes into the P-type substrate 110, forming a stronger body current Isub resulting in the second peak.

[0051] The application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the application will be more apparent. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting in the description of the embodiments of the application.

[0052] For ease of description, some embodiments of the present application can use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or another) element or component as shown in the drawings of the embodiments. It should be understood that in addition to the orientation described in the drawings, the spatial relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element or component described as "below" or "under" the other element or component will then be positioned "above" or "over" the other element or component. The terms "first", "second", etc. are used to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It is understood that these terms as used can be replaced under appropriate circumstances.

[0053] The embodiments of the present application provide a simulation model of an LDMOS, as shown in Figure 6 and Figure 7 , comprising:

[0054] The channel 122, the gate 210, the source 170, the drain 180, and the body region 150 of the LDMOS; the lead-out end of the drain 180 is the drain end D, and the lead-out end of the body region 150 is the body end B; the lead-out end of the source 170 is the source end S, and the lead-out end of the gate 210 is the gate end G.

[0055] An external resistor R1 is connected between the drain terminal D and the channel 122, and a voltage-controlled current source 300 is connected between the drain terminal D and the body terminal B; the positive electrode of the voltage-controlled current source 300 is connected to the drain terminal D, and the negative electrode of the voltage-controlled current source 300 is connected to the body terminal B; the voltage-controlled current source 300 is used to simulate the second peak characteristic of the characteristic curve of the body region current Isub changing with the voltage difference between the gate 210 and the source 170.

[0056] The structure of the LDMOS includes: a P-type substrate 110; an N-type epitaxial layer located on the surface of the P-type substrate 110; a drift region 121 formed in the N-type epitaxial layer; a P-well 130 located in the N-type epitaxial layer; an N-well 140 and a P+ region (i.e., body region 150) located in the P-well 130, the N-well 140 and the body region 150 being separated by a first shallow trench isolation 160; a first N+ region (i.e., source 170) located in the N-well 140; a second N+ region located in the N-type epitaxial layer; Region (i.e., drain 180), the drain 180 and the P-well 130 are separated by a second shallow trench isolation 190, a gate oxide 200, and a gate 210 on the surface of the gate oxide 200; the gate 210 covers part of the P-well 130 and part of the second shallow trench isolation 190; wherein, the body region 150 is connected as the body terminal B, the source 170 is connected as the source terminal S of the LDMOS, the gate 210 is connected as the gate terminal G of the LDMOS, and the drain 180 is connected as the drain terminal D of the LDMOS.

[0057] Figure 8 In order to improve the variation of the current of the voltage-controlled current source with the voltage, the first simulation schematic diagram is obtained using the existing reference empirical formula (a). Figure 9 In order to improve the current variation of the voltage-controlled current source, the second simulation diagram is obtained by using the existing reference empirical formula (a). Figure 8 and Figure 9 As shown, before the improvement, the conventional expression (empirical formula) was used to express the variation of the current of the voltage-controlled current source 300 with voltage in the BSIM model. During the model simulation, it was found that the empirical formula (a) had limitations. The empirical formula (a) showed a purely exponential relationship with Vg. Therefore, the simulated body current Isub (solid line) calculated by the empirical formula exceeded the actual LDMOS body current Isub value before Vg reached the primary peak of Isub. Therefore, the primary peak of the body current Isub simulated using the empirical formula (a) was seriously distorted.

[0058] Specifically, the empirical formula (a) for the change of the current of the voltage-controlled current source 300 with the voltage is:

[0059] Isub=L*exp(M*Vg)(AVd 2 +BVd)+N

[0060] Where Isub is the body current, L is the process experience coefficient, M is the slope of the exponential function in logarithmic coordinates; A and B are process experience coefficients; Vg is the gate voltage, Vd is the drain voltage; and N is a fixed value.

[0061] like Figure 8 As shown in the figure, when the beta0, alpha0 and alpha1 parameters in the BSIM substrate current model are turned off, the body current Isub (solid line) calculated using the empirical formula (a) and the actual body current Isub (dotted or dashed line) are obviously severely distorted.

[0062] like Figure 9 As shown, after the beta0, alpha0 and alpha1 parameters in the BSIM substrate current model are turned on, the body current Isub effect (solid line) after the substrate current in BSIM and the current of the voltage-controlled current source 300 in the empirical formula (a) are superimposed, and the actual body current Isub (dotted line or dashed line) can be clearly seen to be seriously distorted.

[0063] The present invention improves the empirical formula (a). After the improvement, when the LDMOS is an N-type channel, the expression of the current of the voltage-controlled current source 300 as a inverse of the voltage is: Formula (1)

[0064]

[0065] Among them, Isub is the body current, the positive and negative currents represent the current direction of LDMOS, the simulator has its own max function, W and L represent the channel width and channel length of LDMOS, L modify is the channel length correction factor, WL modify Is the channel area correction factor; Is peak is the exponential empirical coefficient, peak co is the exponential slope in logarithmic coordinates, V gs is the gate-source voltage, V peak is a custom voltage fixed value, A and B are process experience coefficients; V ds is the drain-source voltage; m vds It is V ds The correction factor of peak co Determines the logarithmic slope of Isub after lifting, Is peak Determines the up and down amplitude of Isub after it is lifted. Coefficients A and B determine the different V values ​​of Isub after it is lifted. ds The spacing, V peak Adjust where the current is raised.

[0066] peak co It is the exponential slope in logarithmic coordinates. Unlike the pure exponential function, the expression uses (e(x-x0) -1 ) in the form of a mathematical function, so that the function can exhibit exponential characteristics after x is greater than a certain fixed value x0. peak x0 is a custom-defined value. gm is a fixed value, which can be 1e-12 or 1e-14, and it can ensure the convergence of the simulator during simulation, ensuring the minimum value range of the function, which can be customized by the user. The entire exponential function is then taken by the max function in the simulator to take the positive value of Isub. In order to ensure the continuity of the function at 0, when V gs is negative, the entire Isub current does not exceed -1e-14 (A).

[0067] The present application adopts the BSIM external resistance macro model combined with the voltage-controlled current source 300 for specifically describing the secondary peak value of the body current Isub, and obtains good simulation accuracy, improves the expression of current and voltage, and adds Is peak , peak co , V peak , L modify , WL modify , A, B and N gm A total of 8 model parameters, making the model method applicable to various sizes and voltage adjustments, and can flexibly adjust the accuracy of the body current Isub under various conditions, providing good help for users to improve design accuracy.

[0068] When LDMOS is P-type channel, the expression of the current of the voltage-controlled current source with voltage is formula (2)

[0069]

[0070] Wherein, the min function is built-in in the simulator, and the meanings of the remaining parameters are the same as those in the expression of the parameters when LDMOS is N-type.

[0071] BSIM is a model used to simulate metal-oxide-semiconductor field-effect transistors (MOSFETs). BSIM is a mathematical model that describes the relationship between current and voltage in MOSFET devices, and is widely used in integrated circuit design. BSIM provides detailed parameter settings to accurately simulate the electrical characteristics of MOSFETs.

[0072] The substrate current model in the BSIM model adopts the following formula (b):

[0073]

[0074] Wherein, I iiis the substrate current, alpha0 is the proportional coefficient of the impact ionization rate, beta0 is the electric field attenuation coefficient, alpha1 is the high-order correction term for alpha0, V ds is the drain-source voltage, V dseff is the effective drain-source voltage, L eff is the effective channel length, and I0 is a preset current value. For details of formula (b), please refer to the BSIM user manual.

[0075] In the simulation model of the LDMOS provided in an embodiment of the present invention, an external resistor R1 is connected between the drain terminal D and the channel 122. The macro model of the external resistor R1 in the BSIM model is used to describe the drift region resistance between the drain terminal D and the channel 122. Specifically, the BSIM model can be used to describe the channel characteristics of the LDMOS. The first peak characteristic of the characteristic curve of the body current of the present invention is described using the substrate current model in the BSIM model, using the improved formula (1) or formula (2), and the three parameters beta0, alpha0, and alpha1 in the substrate current model need to be enabled.

[0076] Figure 10 The body current Isub characteristic (solid line) is shown when the three parameters beta0, alpha0, and alpha1 in the BSIM model are turned off using the improved formula (1) of the present invention. Figure 10 It can be seen that when the three parameters are closed, the simulation curve is seriously distorted. co Determines the logarithmic slope of Isub after lifting, Is peak Determines the up and down amplitude of Isub after it is lifted. Coefficients A and B determine the different V values ​​of Isub after it is lifted. ds The spacing, V peak Adjust where the current is raised.

[0077] Figure 11 The first schematic diagram of the body current Isub simulated by the improved formula (1) with the three parameters beta0, alpha0 and alpha1 turned on in the present invention, where the y-axis is a logarithmic coordinate. Figure 12 The second schematic diagram of the body current Isub simulated by the improved formula (1) with the three parameters beta0, alpha0 and alpha1 turned on in the present invention, where the y-axis is a linear coordinate. Figure 11 and Figure 12As shown, the three parameters beta0, alpha0, and alpha1 in the substrate current model in the BSIM model are enabled. The substrate current formula in the BSIM and the improved formula (1), i.e., the current formula for the voltage-controlled current source 300, are superimposed to show the simulated body current Isub (solid line) and the actual body current Isub (dotted or dashed line). It is clear that the simulation effect is good, and the simulation curve faithfully describes the current trend of the actual body current Isub. The substrate current formula mainly describes the first peak characteristic of the body current Isub, while the improved formula (1) mainly describes the second peak characteristic of the body current Isub. The final simulated body current Isub is obtained after superposition.

[0078] Figure 13 This is a third schematic diagram of the body current Isub simulated by the improved formula (1) of the present invention. Figure 14 FIG4 is a fourth schematic diagram of the body current Isub simulated by the improved formula (1) of the present invention. Figure 13 and Figure 14 As shown in the figure, the simulated body current Isub effect (solid line) after the substrate current formula in BSIM and the improved formula (1), i.e., the current formula of the voltage-controlled current source 300, are superimposed, and the actual body current Isub (dotted or dashed line) is obtained. It can be clearly seen that the simulation effect is good, and the simulation curve faithfully describes the current trend of the actual body current Isub. It can be seen that this model method can well describe the secondary peak of the body current Isub of the LDMOS, and can provide a more accurate simulation reference for circuit designers. The comparison results of the body current Isub simulation and actual characteristics of different LDMOS sizes show that the channel length correction factor L modify and channel area correction factor WL modify The modified model can ensure that the body current Isub of LDMOS of different sizes presents different peak characteristics.

[0079] The present invention also provides a simulation method for LDMOS, which uses the above-mentioned LDMOS simulation model for simulation;

[0080] In the LDMOS simulation model, an external resistor is connected between the drain and channel of the LDMOS, and a voltage-controlled current source is connected between the drain and the body of the LDMOS. The voltage-controlled current source is used to simulate the second peak characteristic of the characteristic curve of the body region current changing with the voltage difference between the gate and source of the LDMOS.

[0081] Specifically, the substrate current model in the BSIM model is used to simulate the first peak characteristic of the characteristic curve of the body current, and the three parameters beta0, alpha0 and alpha1 in the substrate current model need to be turned on during the simulation.

[0082] When LDMOS is an N-type channel, the expression of the current of the voltage-controlled current source as a inverse of the voltage is:

[0083]

[0084] Among them, Isub is the body current, the positive and negative currents represent the current direction of LDMOS, the simulator has its own max function, W and L represent the channel width and channel length of LDMOS, L modify is the channel length correction factor, WL modify Is the channel area correction factor; Is peak is the exponential empirical coefficient, peak co is the exponential slope in logarithmic coordinates, V gs is the gate-source voltage, V peak is a custom voltage fixed value, A and B are process experience coefficients; V ds is the drain-source voltage; N gm It is a fixed value and can be customized by the user; m vds It is V ds correction factor.

[0085] In summary, the present invention provides a simulation model and simulation method for LDMOS, including: a channel, gate, source, drain, and body region of the LDMOS; the lead end of the drain is the drain terminal, and the lead end of the body region is the body terminal; an external resistor is connected between the drain terminal and the channel, and a voltage-controlled current source is connected between the drain terminal and the body terminal; the positive electrode of the voltage-controlled current source is connected to the drain terminal, and the negative electrode of the voltage-controlled current source is connected to the body terminal; the voltage-controlled current source is used to simulate the secondary peak characteristic of the characteristic curve of the body region current changing with the voltage difference between the gate and the source. The present invention uses a macro model of the external resistor in combination with a voltage-controlled current source for specifically describing the secondary peak of the body region current, and can well describe or simulate the second higher current (secondary peak) characteristic of the LDMOS, providing a more accurate simulation reference for circuit designers.

[0086] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The methods disclosed in the embodiments are described briefly because they correspond to the devices disclosed in the embodiments. For relevant details, refer to the method description.

[0087] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A simulation model of LDMOS, characterized in that: include: The channel, gate, source, drain and body region of the LDMOS; the lead-out end of the drain is the drain terminal, and the lead-out end of the body region is the body terminal; An external resistor is connected between the drain terminal and the channel, and a voltage-controlled current source is connected between the drain terminal and the body terminal; the positive electrode of the voltage-controlled current source is connected to the drain terminal, and the negative electrode of the voltage-controlled current source is connected to the body terminal; the voltage-controlled current source is used to simulate the second peak characteristic of the characteristic curve of the body region current changing with the voltage difference between the gate and the source.

2. The LDMOS simulation model according to claim 1, wherein: The LDMOS structure includes: a P-type substrate; an N-type epitaxial layer located on the surface of the P-type substrate; a P-well located in the N-type epitaxial layer; an N-well and a P+ region located in the P-well, wherein the N-well and the P+ region are separated by a first shallow trench isolation; a first N+ region located in the N-well; a second N+ region located in the N-type epitaxial layer, wherein the second N+ region is separated from the P-well by a second shallow trench isolation and a gate oxide and a gate on the surface of the gate oxide; the gate covers a portion of the P-well and a portion of the second shallow trench isolation. The P+ region is connected as the body terminal, the first N+ region is connected as the source terminal of the LDMOS, the gate is connected as the gate terminal of the LDMOS, and the second N+ region is connected as the drain terminal of the LDMOS.

3. The LDMOS simulation model according to claim 1, wherein: When the LDMOS is an N-type channel, the expression of the current of the voltage-controlled current source following the voltage is: Formula (1) Wherein, Isub is the body current, the positive and negative currents represent the current direction of LDMOS, the simulator has its own max function, W and L represent the channel width and channel length of LDMOS, L modify is the channel length correction factor, WL modify Is the channel area correction factor; Is peak is the exponential empirical coefficient, peak co is the exponential slope in logarithmic coordinates, V gs is the gate-source voltage, V peak is a custom voltage fixed value, A and B are process experience coefficients; V ds is the drain-source voltage; N gm It is a fixed value and can be customized by the user; m vds It is V ds correction factor.

4. The LDMOS simulation model according to claim 3, wherein: In the second peak curve describing the Isub, the peak co Determine the logarithmic slope of the Isub after it drops from the first peak and then rises in the second peak curve, the Is peak Determine the upper and lower amplitudes of the Isub after it is lifted, and the coefficients A and B determine the different V values ​​of the Isub after it is lifted. ds The spacing of the V peak Adjust where the current is raised.

5. The LDMOS simulation model according to claim 3, wherein: When the LDMOS is a P-type channel, the expression of the current of the voltage-controlled current source following the voltage is: Formula (2) The simulator has a built-in min function.

6. The LDMOS simulation model according to claim 1, wherein: The first peak characteristic of the characteristic curve of the body current is described by the substrate current model in the BSIM model. The substrate current is described by formula (b): Among them, I ii is the substrate current, alpha0 is the proportional coefficient of the impact ionization rate, beta0 is the electric field attenuation coefficient, alpha1 is the high-order correction term for alpha0, V ds is the drain-source voltage, V dseff is the effective drain-source voltage, L eff is the effective channel length, and I0 is a preset current value.

7. The LDMOS simulation model according to claim 6, wherein: The three parameters beta0, alpha0 and alpha1 in the substrate current model need to be turned on during simulation.

8. A simulation method for LDMOS, characterized in that: Performing simulation using the LDMOS simulation model described in any one of claims 1 to 7; In the simulation model of the LDMOS, an external resistor is connected between the drain terminal and the channel of the LDMOS, and a voltage-controlled current source is connected between the drain terminal and the body terminal of the LDMOS; The voltage-controlled current source is used to simulate the second peak characteristic of the characteristic curve of the body current changing with the voltage difference between the gate and the source of the LDMOS.

9. The LDMOS simulation method according to claim 8, wherein: The substrate current model in the BSIM model is used to simulate the first peak characteristic of the characteristic curve of the body current, and the three parameters beta0, alpha0 and alpha1 in the substrate current model need to be turned on during the simulation.

10. The LDMOS simulation method according to claim 8, wherein: When the LDMOS is an N-type channel, the expression of the current of the voltage-controlled current source as a function of voltage is: Formula (1) Wherein, Isub is the body current, the positive and negative currents represent the current direction of LDMOS, the simulator has its own max function, W and L represent the channel width and channel length of LDMOS, L modify is the channel length correction factor, WL modify Is the channel area correction factor; Is peak is the exponential empirical coefficient, peak co is the exponential slope in logarithmic coordinates, V gs is the gate-source voltage, V peak is a custom voltage fixed value, A and B are process experience coefficients; V ds is the drain-source voltage; N gm It is a fixed value and can be customized by the user; m vds It is V ds correction factor.

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