Matrix decomposition machine learning training method, device and equipment for integrated circuit simulation analysis

Abstract

The invention discloses a matrix decomposition machine learning training method, device and equipment for integrated circuit simulation analysis, and relates to the technical field of integrated circuit design automation, and the method comprises the steps: generating an integrated circuit simulation analysis demand according to an integrated circuit simulation analysis task; acquiring a feature vector of a node admittance matrix in integrated circuit simulation from an integrated circuit simulation analysis demand; performing non-uniform blocking and uniform blocking processing on the node admittance matrix to generate a corresponding target non-uniform blocking elimination tree and a target uniform blocking elimination tree; obtaining a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix according to respective elimination tree indexes of the target non-uniform block elimination tree and the target uniform block elimination tree, and determining a block mode label of the node admittance matrix; and forming a training data set by the feature vectors and the blocking mode labels, and performing blocking recognition training on the initial classification model by using the training data set to obtain a machine learning model. And a blocking strategy is adaptively selected for a simulation demand.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design automation technology, and in particular to a matrix decomposition machine learning training method, device, and equipment for integrated circuit simulation analysis. Background Art

[0002] Circuit simulation of integrated circuits can be used to analyze and simulate the performance of electronic circuits. Circuit simulation of integrated circuits is the core means of analyzing the performance of electronic circuits. As the integration of chips leaps from millions of gates to hundreds of millions of gates, the circuit scale and the complexity of parasitic parameters grow exponentially. Taking integrated circuits as an example, the dimension of their node admittance matrix often exceeds 10 6 ×10 6 ,The matrix symbolic characteristics present unstructured complex patterns. Therefore, circuit simulation analysis requires solving a large number of sparse linear equations. The efficiency of solving sparse matrices directly affects the performance of circuit simulators.

[0003] For matrices with obvious symbolic features, such as low-frequency circuit matrices with strip-like symmetry, a block partitioning method can be selected empirically. However, for complex matrices widely found in integrated circuits, such as multi-layer PCB matrices with parasitic vias, the lack of an effective mapping mechanism between matrix features and block partitioning strategies leads to the following drawbacks:

[0004] Blindness in partitioning strategies: Relying on engineers' experience to select the multi-wavefront method or PanguLU, in FinFET circuit simulation, incorrect strategies may lead to extended simulation times;

[0005] Wasted parallelism: The tree dependency elimination is not optimized enough, and the parallel efficiency on GPU clusters is too low;

[0006] Memory out-of-control risk: When the filling element of the uneven block is not controlled, 10 6 The memory usage of the dimension matrix is ​​large, causing the simulation to be interrupted.

[0007] In summary, how to adaptively select a block strategy for the simulation requirements in integrated circuit simulation analysis to improve computational parallelism and load balancing is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0008] The purpose of the embodiments of the present invention is to provide a matrix decomposition machine learning training method, device, and equipment for integrated circuit simulation analysis, which can adaptively select a blocking strategy for the simulation requirements in integrated circuit simulation analysis, thereby improving computational parallelism and load balancing.

[0009] To solve the above technical problems, an embodiment of the present invention provides a matrix decomposition machine learning training method for integrated circuit simulation analysis, comprising:

[0010] Generate corresponding integrated circuit simulation analysis requirements according to the integrated circuit simulation analysis tasks;

[0011] Obtaining eigenvectors of a node admittance matrix in an integrated circuit simulation based on an integrated circuit simulation analysis requirement; the eigenvectors include any one or more of the following: matrix dimension, number of non-zero elements, node average degree, sparsity, maximum node degree, minimum node degree, and maximum node distance;

[0012] Perform non-uniform block partitioning and uniform block partitioning on the node admittance matrix, and generate corresponding target non-uniform block elimination tree and target uniform block elimination tree;

[0013] Obtaining a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix according to the elimination tree indexes of the target non-uniform block elimination tree and the target uniform block elimination tree, so as to determine a block mode label of the node admittance matrix; the block mode label includes a non-uniform block label and a uniform block label;

[0014] The feature vectors and the block mode labels constitute a training data set, and the initial classification model is trained for block recognition using the training data set to obtain a machine learning model for the block mode of the classification node admittance matrix in integrated circuit simulation analysis.

[0015] Optionally, determine the block mode label of the node admittance matrix, including:

[0016] If the first comprehensive balance degree is less than the second comprehensive balance degree, determining that the block mode label of the node admittance matrix is ​​a non-uniform block label;

[0017] If the first comprehensive balance degree is greater than the second comprehensive balance degree, it is determined that the block mode label of the node admittance matrix is ​​a uniform block label.

[0018] Optionally, performing non-uniform block processing on the node admittance matrix and generating a corresponding target non-uniform block elimination tree includes:

[0019] Performing a matrix reordering operation on the node admittance matrix to obtain a reordered optimized matrix;

[0020] Merge the diagonal nodes of the reordered optimized matrix to obtain a merged optimized matrix;

[0021] Perform irregular matrix block processing on the merged optimized matrix to obtain non-uniform matrix blocks, and perform symbolic analysis optimization on the non-uniform matrix blocks to obtain the non-uniform block elimination tree in the optimization;

[0022] When the non-uniform block elimination tree in the optimization process meets the preset optimization conditions, the optimization is stopped, and the current non-uniform block elimination tree in the optimization process is output as the target non-uniform block elimination tree;

[0023] When the non-uniform block elimination tree during optimization does not meet the preset optimization conditions, the corresponding matrix optimization steps are re-executed until the non-uniform block elimination tree during optimization meets the preset optimization conditions.

[0024] Optionally, the node admittance matrix is ​​uniformly partitioned and a corresponding target uniformly partitioned elimination tree is generated, including:

[0025] Performing a matrix reordering operation on the node admittance matrix to obtain a reordered optimized matrix;

[0026] Performing regular matrix block processing on the reordered optimized matrix to obtain uniform matrix blocks, and performing symbolic analysis optimization on the uniform matrix blocks to obtain the optimized uniform block elimination tree;

[0027] When the optimized uniform block elimination tree meets the preset optimization conditions, the optimization is stopped and the current optimized uniform block elimination tree is output as the target uniform block elimination tree;

[0028] When the optimized uniform block elimination tree does not meet the preset optimization conditions, the corresponding matrix optimization steps are re-executed until the optimized uniform block elimination tree meets the preset optimization conditions.

[0029] Optionally, the elimination tree metrics include tree depth, total number of nodes, number of leaf nodes, factorization complexity, forward and backward complexity, and node balance;

[0030] Accordingly, obtaining a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix according to the elimination tree indexes of the target non-uniform block elimination tree and the target uniform block elimination tree includes:

[0031] Calculate the first comprehensive balance degree of the node admittance matrix according to the elimination tree index of the target non-uniform block elimination tree and the corresponding first index weight coefficient;

[0032] The second comprehensive balance degree of the node admittance matrix is ​​calculated according to the elimination tree index of the target uniform block elimination tree and the corresponding second index weight coefficient.

[0033] Optionally, the initial classification model is a multilayer perceptron neural network, which includes an input layer, several hidden layers, and an output layer. The activation functions of the input layer and the hidden layer are ReLU functions, the number of neurons in the output layer is 2, and the activation function of the output layer is softmax.

[0034] Accordingly, the training data set is used to perform block recognition training on the initial classification model to obtain a machine learning model for the block mode of the classification node admittance matrix in the integrated circuit simulation analysis, including:

[0035] Normalize the training dataset and convert the block labels into one-hot encoding to obtain the input feature vector;

[0036] Initialize the weight parameters and bias parameters of the multilayer perceptron neural network;

[0037] Input the input feature vector to the input layer of the multilayer perceptron neural network so that the input layer can pass the input feature vector to each layer of the network through forward propagation calculation, and apply the Relu activation function to the hidden layer and the softmax activation function to the output layer to obtain the corresponding predicted probability distribution;

[0038] Calculate the cross entropy loss function value based on the predicted probability distribution and the block method label;

[0039] The gradient of the cross entropy loss function value with respect to the multilayer perceptron neural network parameters is calculated through the back propagation algorithm;

[0040] The weight parameters and bias parameters of the multilayer perceptron neural network are updated according to the gradient and using an adaptive moment estimation algorithm until the model performance of the multilayer perceptron neural network meets the preset training stop condition, so that the multilayer perceptron neural network under the current multilayer perceptron neural network parameters is used as a machine learning model.

[0041] Optionally, the eigenvectors in the training data set are eigenvectors of node admittance matrices covering different sign features.

[0042] Optionally, after obtaining the machine learning model for classifying the node admittance matrix block mode in the integrated circuit simulation analysis, the method further includes:

[0043] receiving a target integrated circuit simulation analysis requirement, and extracting a target eigenvector of a target node admittance matrix from the target integrated circuit simulation analysis requirement;

[0044] Use the machine learning model to classify and predict the eigenvectors of the target node admittance matrix in a block-wise manner and output the target block-wise label;

[0045] If the target block label is a non-uniform block label, the target node admittance matrix is ​​decomposed using the multi-wavefront method or the super-node method to obtain the corresponding decomposition result;

[0046] If the target block label is a uniform block label, the target node admittance matrix is ​​decomposed using the PanguLU method to obtain the corresponding decomposition result;

[0047] Use the decomposition results to solve the circuit equations and generate a simulation analysis report.

[0048] In a second aspect, an embodiment of the present invention discloses a matrix decomposition machine learning training device for integrated circuit simulation analysis, comprising:

[0049] A requirement generation module, used to generate corresponding integrated circuit simulation analysis requirements according to the integrated circuit simulation analysis task;

[0050] A feature acquisition module is used to obtain the eigenvectors of the node admittance matrix in the integrated circuit simulation from the requirements of the integrated circuit simulation analysis; the eigenvectors include any one or more of the matrix dimension, number of non-zero elements, node average degree, sparsity, maximum node degree, minimum node degree, and maximum node distance;

[0051] A block processing module is used to perform non-uniform block processing and uniform block processing on the node admittance matrix, and generate corresponding target non-uniform block elimination tree and target uniform block elimination tree;

[0052] a label determination module, configured to obtain a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix based on elimination tree indices of the target non-uniform block elimination tree and the target uniform block elimination tree, so as to determine a block mode label of the node admittance matrix; the block mode label includes a non-uniform block label and a uniform block label;

[0053] The model training module is used to form a training data set with feature vectors and block labels, so as to use the training data set to perform block recognition training on the initial classification model and obtain a machine learning model of the classification node admittance matrix block method for integrated circuit simulation analysis.

[0054] In a third aspect, an embodiment of the present invention discloses an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the aforementioned disclosed matrix decomposition machine learning training method for integrated circuit simulation analysis.

[0055] In a fourth aspect, an embodiment of the present invention discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the aforementioned matrix decomposition machine learning training method for integrated circuit simulation analysis are implemented.

[0056] It can be seen that the application provides a matrix decomposition machine learning training method for integrated circuit simulation analysis, comprising the following steps: generating a corresponding integrated circuit simulation analysis requirement according to an integrated circuit simulation analysis task; obtaining a feature vector of a node admittance matrix in integrated circuit simulation from the integrated circuit simulation analysis requirement; the feature vector comprises any one or several of a matrix dimension, a number of non-zero elements, a node average degree, a sparsity, a maximum node degree, a minimum node degree, and a maximum node distance; performing non-uniform blocking and uniform blocking on the node admittance matrix respectively, and generating a corresponding target non-uniform blocking elimination tree and a target uniform blocking elimination tree; obtaining a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix according to the elimination tree indexes of the target non-uniform blocking elimination tree and the target uniform blocking elimination tree, so as to determine a blocking mode label of the node admittance matrix; the blocking mode label comprises a non-uniform blocking label and a uniform blocking label; and constructing a training data set by using the feature vector and the blocking mode label, so as to perform blocking recognition training on an initial classification model by using the training data set, and obtain a machine learning model for classifying the blocking mode of the node admittance matrix in integrated circuit simulation analysis.

[0057] As can be seen from the above technical solution, by extracting the original features of the node admittance matrix in the integrated circuit simulation analysis requirement, that is, the feature vector, the reordering interference is avoided, the inherent structural characteristics of the node admittance matrix are directly reflected, then the double-path blocking optimization is performed, the two kinds of elimination trees are constructed synchronously, the load balance is quantitatively compared, the blindness of manual selection of the blocking mode is eliminated, and the loss of parallelism caused by single blocking is avoided. Then the comprehensive balance degree is calculated, and the blocking mode label of the node admittance matrix is reasonably determined in a numerical manner. In this way, the obtained blocking mode label is not selected according to experience, and then the training data set composed of the blocking mode label and the corresponding feature vector is used to train the corresponding machine learning model. As can be seen from this, the real-time adaptive classification of the admittance matrix in integrated circuit simulation can be realized by using the machine learning model. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0059] Figure 1 A matrix decomposition machine learning training method for integrated circuit simulation analysis provided by the embodiments of the present application is shown in the flowchart.

[0060] Figure 2 A MLP structure diagram for confirming the sparse matrix blocking solving method provided by the embodiments of the present application is shown in the flowchart.

[0061] Figure 3 An MLP training flow chart provided by an embodiment of the present invention;

[0062] Figure 4 A schematic diagram of the structure of a matrix decomposition machine learning training device for integrated circuit simulation analysis provided by an embodiment of the present invention;

[0063] Figure 5 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0064] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0065] The terms "including" and "having," as used in the present description and accompanying drawings, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0066] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0067] Circuit simulation of integrated circuits can be used to analyze and simulate the performance of electronic circuits. Circuit simulation of integrated circuits is the core means of analyzing the performance of electronic circuits. As the integration of chips leaps from millions of gates to hundreds of millions of gates, the circuit scale and the complexity of parasitic parameters grow exponentially. Taking integrated circuits as an example, the dimension of their node admittance matrix often exceeds 10 6 ×10 6 ,The matrix symbolic characteristics present unstructured complex patterns. Therefore, circuit simulation analysis requires solving a large number of sparse linear equations. The efficiency of solving sparse matrices directly affects the performance of circuit simulators.

[0068] For matrices with obvious symbolic features, such as low-frequency circuit matrices with strip-like symmetry, a block partitioning method can be selected empirically. However, for complex matrices widely found in integrated circuits, such as multi-layer PCB matrices with parasitic vias, the lack of an effective mapping mechanism between matrix features and block partitioning strategies leads to the following drawbacks:

[0069] Blindness in partitioning strategies: Relying on engineers' experience to select the multi-wavefront method or PanguLU, in FinFET circuit simulation, incorrect strategies may lead to extended simulation times;

[0070] Wasted parallelism: The tree dependency elimination is not optimized enough, and the parallel efficiency on GPU clusters is too low;

[0071] Memory out-of-control risk: When the filling element of the uneven block is not controlled, 10 6 The memory usage of the dimension matrix is ​​large, causing the simulation to be interrupted.

[0072] To this end, an embodiment of the present invention provides a matrix decomposition machine learning training scheme for integrated circuit simulation analysis, which can adaptively select blocking strategies for simulation requirements in integrated circuit simulation analysis, thereby improving computational parallelism and load balancing.

[0073] Reference Figure 1 As shown, an embodiment of the present invention provides a matrix decomposition machine learning training method for integrated circuit simulation analysis, comprising:

[0074] Step S11: Generate corresponding integrated circuit simulation analysis requirements according to the integrated circuit simulation analysis task.

[0075] In this embodiment, integrated circuit simulation and analysis tasks can be divided into three categories based on circuit type and analysis objective. Each task corresponds to different simulation requirement extraction logic. Specifically, when the integrated circuit simulation and analysis task is a digital circuit timing analysis task, specifically when performing transient analysis of the power supply network of a FinFET (Fin Field-Effect Transistor) chip, the matrix dimension is large, the proportion of transistor transconductance terms among non-zero elements is high, and there are a large number of highly connected power nodes. Therefore, in the digital circuit timing analysis task scenario, the maximum allowable delay time and number of parallel computing cores are extracted from the simulation configuration file and converted into an integrated circuit simulation and analysis requirement with a matrix decomposition parallelism of ≥80%.

[0076] When performing frequency-domain analysis of RF circuits, such as S-parameter analysis of 5G base station PA (Power Amplifier) ​​circuits, the parasitic capacitance / inductance components in the matrix have a high proportion of non-zero elements, exhibiting a cross-layer distribution. Therefore, in this RF circuit frequency-domain analysis scenario, the user-entered frequency sweep range and number of sampling points are analyzed. Because high-frequency parasitic parameters require controlled padding to ensure accuracy, the system generates an IC simulation analysis with a padding growth rate that meets a preset growth rate threshold.

[0077] It should be noted that, based on the hierarchical wiring characteristics of the RF circuit, the automatically generated blocking strategy needs to adapt to the implicit requirement of cross-layer non-zero element distribution.

[0078] When the IC simulation analysis task involves mixed-signal circuit compatibility analysis, for example, a mixed circuit consisting of analog op amps and digital logic, the matrix contains both symmetric sub-blocks (analog components) and asymmetric sub-blocks (digital switches), and the distribution of non-zero elements exhibits modularity. Therefore, in this mixed-signal circuit compatibility analysis scenario, identifying the analog / digital module ratio from the circuit netlist and generating a block partitioning strategy must support the IC simulation analysis requirements of mixed-mode decomposition.

[0079] In the above-mentioned process of obtaining IC simulation analysis requirements, taking digital IC transient analysis as an example, the specific parameters are extracted from the simulation configuration file to construct the corresponding IC simulation analysis requirements process as follows:

[0080] 1. Task parameter parsing stage: Read the following .TRAN statement parameters in the SPICE netlist file:

[0081] The simulation time span T and the time step Δt are converted into matrix decomposition time to meet the real-time requirements of the preset decomposition time conditions;

[0082] Generate high priority requirements for pivot stability based on node temperature settings (risk of minimal pivots increases at high temperatures).

[0083] 2. Circuit characteristics derivation stage: Analyze the component type distribution in the netlist:

[0084] Based on the number of MOSFETs (field-effect transistors) and the total amount of parasitic capacitance, the proportion of capacitance terms in the non-zero elements of the matrix is ​​derived. When generating blocks, attention should be paid to the needs of capacitor-intensive areas;

[0085] Based on the number of power network nodes, the demand for load balancing of high-connectivity nodes is generated based on the total number of nodes.

[0086] 3. Computing resource adaptation stage:

[0087] Read the emulator configuration file:

[0088] Based on the available memory, the upper limit of matrix storage is calculated and the limit condition of filling element increment is generated to meet the preset capacity threshold condition;

[0089] Depending on the processor type, the generated block strategy must support the requirements of GPU (Graphics Processing Unit) parallel acceleration.

[0090] Step S12: Obtain the eigenvector of the node admittance matrix in the integrated circuit simulation from the integrated circuit simulation analysis requirements; the eigenvector includes any one or more of the matrix dimension, number of non-zero elements, node average degree, sparsity, maximum node degree, minimum node degree, and maximum node distance.

[0091] In this embodiment, the eigenvector of the node admittance matrix in the integrated circuit simulation is obtained from the integrated circuit simulation analysis requirements, where the matrix dimension corresponds to the number of circuit nodes. For example, the dimension of the node admittance matrix of the radio frequency circuit is often up to 10 6 ×10 6 , reflecting the scale of the circuit; the number of non-zero elements: determined by the connection relationship of circuit elements, for example, the number of non-zero elements formed by MOSFET and parasitic capacitance in digital circuits is very considerable, reflecting the complexity of the circuit; node average degree: calculates the mean value of the non-zero elements connected to each node; sparsity: calculated by 1-number of non-zero elements / (dimension × dimension), the integrated circuit wiring rules make the sparsity often exceed 95%, and the discrete distribution of parasitic parameters in high-frequency circuits can further improve the sparsity; maximum / minimum node degree: identifies key node characteristics, such as the RF circuit pad node has a corresponding pad node maximum degree, and accordingly, the isolated test node has a corresponding minimum degree; node maximum distance: the longest path of non-zero elements in the matrix corresponds to the cross-layer connection depth in the circuit topology. In multi-layer PCB circuits, this distance can reflect the signal integrity risk.

[0092] In this way, obtaining the eigenvectors of the node admittance matrix provides the machine learning model with input data reflecting the matrix structure characteristics, enabling adaptive selection of the partitioning strategy. This data indicates the key characteristics of the matrix and is used to establish a mapping relationship between the matrix structure and the partitioning strategy. The eigenvector is a quantitative representation of the matrix's numerical structure. By extracting these features, the machine learning model can learn the mapping rules from the matrix structure to the optimal partitioning method. For example, in high-frequency circuits, matrices with dense parasitic parameters are more suitable for non-uniform partitioning. Eigenvector-driven machine learning can automatically identify matrix patterns, avoiding blind selection of the partitioning strategy. Furthermore, the eigenvector indicates the circuit scale of the current integrated circuit, which directly affects the computational complexity and memory requirements.

[0093] It's important to note that the node admittance matrix features output by existing integrated circuit simulation tools exhibit format heterogeneity (node ​​numbering rules and parameter unit differences), making the raw data unsuitable for direct model training. To address this, during the dataset construction phase, the received raw data undergoes symbolic standardization and physical dimension normalization. Specifically, symbolic standardization involves applying a layered recoding algorithm (numbering layers from the power layer to the signal layer) to the netlist nodes from different tools, eliminating the issue of node ID disarray caused by tool-specific differences within the same circuit. For example, after recoding, the standard deviation of the node degree feature for a mixed-signal circuit was reduced from 12.5 to 3.2, ensuring feature alignment across tools. For missing features, interpolation is performed using the same process library (based on the average feature values ​​of circuits of the same process and type). This process resolves the compatibility issues of multi-source data, ensuring that the training set covers both laboratory simulation and industrial tape-out data, improving model generalization.

[0094] Step S13: performing non-uniform block partitioning and uniform block partitioning processing on the node admittance matrix respectively, and generating corresponding target non-uniform block elimination tree and target uniform block elimination tree.

[0095] In this embodiment, a node admittance matrix is ​​subjected to non-uniform block processing and a corresponding target non-uniform block elimination tree is generated, including: performing a matrix reordering operation on the node admittance matrix to obtain a reordered optimized matrix; performing diagonal node merging on the reordered optimized matrix to obtain a merged optimized matrix; performing irregular matrix block processing on the merged optimized matrix to obtain a matrix non-uniform block, and performing symbolic analysis optimization on the matrix non-uniform block to obtain an optimized non-uniform block elimination tree; when the optimized non-uniform block elimination tree meets the preset optimization conditions, the optimization is stopped and the current optimized non-uniform block elimination tree is output as the target non-uniform block elimination tree; when the optimized non-uniform block elimination tree does not meet the preset optimization conditions, the corresponding matrix optimization steps are re-executed until the optimized non-uniform block elimination tree meets the preset optimization conditions. It can be understood that when performing the above-mentioned optimization operations on the node admittance matrix, specifically including matrix reordering, diagonal node merging, and matrix block, symbolic analysis is performed to obtain the non-uniform block elimination tree.

[0096] In this embodiment, a matrix reordering operation is performed on the node admittance matrix to obtain a reordered optimized matrix; a regular matrix block processing is performed on the reordered optimized matrix to obtain a uniform matrix block, and a symbolic analysis optimization is performed on the uniform matrix block to obtain an optimized uniform block elimination tree; when the optimized uniform block elimination tree meets the preset optimization conditions, the optimization is stopped and the current optimized uniform block elimination tree is output as the target uniform block elimination tree; when the optimized uniform block elimination tree does not meet the preset optimization conditions, the corresponding matrix optimization steps are re-executed until the optimized uniform block elimination tree meets the preset optimization conditions. It can be understood that in order to train the machine model, the current node admittance matrix is ​​non-uniformly blocked to obtain a non-uniform block elimination tree, and the above-mentioned node admittance matrix is ​​optimized, specifically matrix reordering and uniform blocking. Symbolic analysis is performed to obtain a uniform block elimination tree.

[0097] Among them, the preset optimization conditions of the matrix optimization operation are the termination conditions of the matrix optimization operation, including the filling element restriction condition, the relaxation parameter restriction condition, the elimination tree depth difference condition, and the numerical stability condition. Among them, the filling element restriction condition is that when the filling element surges and exceeds a certain proportion of the initial matrix non-zero elements, the optimization is stopped; the relaxation parameter restriction condition is that when the non-zero pattern difference within the merged block exceeds the preset relaxation parameter, the optimization is stopped; the elimination tree depth difference condition is that when the depth difference of the elimination tree subtree exceeds the threshold, the optimization is stopped. The numerical stability condition is that the numerical stability of the principal element decreases. For example, when an extremely small principal element appears, the matrix of the previous step needs to be rolled back. In this way, by comparing the elimination tree indicators of the two block partitioning methods, quantitative label data can be provided to the machine learning model, thereby realizing the adaptive selection of the block partitioning strategy.

[0098] Step S14: Obtain a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix according to the elimination tree indices of the target non-uniform block elimination tree and the target uniform block elimination tree, so as to determine a block mode label of the node admittance matrix; the block mode label includes a non-uniform block label and a uniform block label.

[0099] In this embodiment, the elimination tree index includes tree depth, total number of nodes, number of leaf nodes, factorization complexity, forward and backward complexity and node balance; accordingly, the first comprehensive balance and second comprehensive balance of the node admittance matrix are obtained according to the elimination tree index of the target non-uniform block elimination tree and the target uniform block elimination tree, including: calculating the first comprehensive balance of the node admittance matrix according to the elimination tree index of the target non-uniform block elimination tree and the corresponding first index weight coefficient; calculating the second comprehensive balance of the node admittance matrix according to the elimination tree index of the target uniform block elimination tree and the corresponding second index weight coefficient. It can be understood that the filling degree Fi of the node admittance matrix before and after optimization is calculated, and the tree depth, total number of nodes, number of leaf nodes, factorization complexity C1, forward and backward complexity C2 and node balance of the non-uniform block elimination tree and the uniform block elimination tree are calculated and analyzed. Specifically, the filling degree is the ratio of the number of non-zero elements before and after optimization. The tree depth represents the longest distance from the root node of the elimination tree to all nodes. Node The factorization complexity C1 and the forward and backward complexity C2 are expressed as follows:

[0100] ;

[0101] in, For nodes The child nodes of For child nodes The forward and backward calculation amount of If it is still the parent node, it needs to be solved recursively. The balance degree is expressed as follows:

[0102] ;

[0103] in, For nodes The number of child nodes, and Represents the average of the subtree factorization complexity and forward and backward complexity respectively. The proportional coefficients α and β satisfy α+β=1. Node balance It reflects whether the load of different sub-nodes is balanced. The closer to 0, the better the balance. Assign weights to each node of the elimination tree The balance of the entire elimination tree is:

[0104] ;

[0105] in, is the total number of nodes in the elimination tree.

[0106] According to the height ratio before and after matrix optimization, the ratio of the average number of parent nodes, the ratio of leaf nodes, the ratio of factorization complexity, the ratio of forward and backward complexity, and the ratio of node balance, the attribute weight values ​​are set, and the sum is 1. Based on the attribute weight values, the comprehensive balance B is obtained.

[0107] According to the calculation method of the above-mentioned comprehensive average degree B, the comprehensive balance degrees of the non-uniform block elimination tree and the uniform block elimination tree under the same optimization end condition are calculated respectively to obtain the first comprehensive balance degree and the second comprehensive balance degree respectively.

[0108] If the first comprehensive balance degree is less than the second comprehensive balance degree, determining that the block mode label of the node admittance matrix is ​​a non-uniform block label;

[0109] If the first comprehensive balance degree is greater than the second comprehensive balance degree, it is determined that the block mode label of the node admittance matrix is ​​a uniform block label.

[0110] In this way, each node admittance matrix is ​​labeled according to the comprehensive balance, and the label is a block method with a small comprehensive balance value, that is, a non-uniform block label or a uniform block label.

[0111] Furthermore, based on non-uniform partitioning, the multi-wavefront method is used to perform LU decomposition on the node admittance matrix, and based on uniform partitioning, the PanguLU method is used to perform LU decomposition on the node admittance matrix. The numerical decomposition time of the non-uniform and uniform partitioned node admittance matrices is calculated, and the node admittance matrices are labeled.

[0112] In addition, the total matrix solution time, memory usage, FLOPs, etc. can be counted, and the node admittance matrix can be labeled based on the comprehensive results of the above properties.

[0113] Step S15: The feature vector and the block mode label constitute a training data set, and the training data set is used to train the initial classification model for block recognition, so as to obtain a machine learning model for classifying the node admittance matrix block mode in integrated circuit simulation analysis.

[0114] In this embodiment, the feature vector of each node admittance matrix is extracted, and the label is combined to constitute an experimental data set. The experimental data set is divided into a training data set and a validation data set. The feature vectors in the training data set are the feature vectors of the node admittance matrices covering different symbol characteristics. It can be understood that the feature vectors of the node admittance matrices covering different symbol characteristics in the training data set are necessary conditions for ensuring that the subsequent machine learning model accurately classifies the block mode in integrated circuit simulation. Through learning of diversified matrix structure patterns, the model can avoid overfitting and can select the optimal block strategy on various circuit matrices such as digital, radio frequency, and mixed signal.

[0115] In this embodiment, the initial classification model is a multilayer perceptron neural network. The multilayer perceptron neural network includes an input layer, a plurality of hidden layers, and an output layer. The activation function of the input layer and the hidden layer is a Relu function. The number of neurons of the output layer is 2. The activation function of the output layer is softmax. Correspondingly, the training data set is used to train the initial classification model for block recognition, so as to obtain a machine learning model for classifying the node admittance matrix block mode in integrated circuit simulation analysis. The machine learning model includes: performing standardization processing on the training data set, and converting the block mode label into a one-hot encoding form to obtain an input feature vector; initializing the weight parameters and the bias parameters of the multilayer perceptron neural network; inputting the input feature vector into the input layer of the multilayer perceptron neural network, so that the input layer transmits the input feature vector to each layer network through forward propagation calculation, and applies a Relu activation function in the hidden layer and a softmax activation function in the output layer to obtain a corresponding prediction probability distribution; calculating a cross-entropy loss function value based on the prediction probability distribution and the block mode label; calculating the gradient of the cross-entropy loss function value on the parameters of the multilayer perceptron neural network through a back propagation algorithm; updating the weight parameters and the bias parameters of the multilayer perceptron neural network according to the gradient and using a stochastic gradient descent algorithm until the model performance of the multilayer perceptron neural network meets a preset training stop condition, so as to take the multilayer perceptron neural network under the current multilayer perceptron neural network parameters as the machine learning model.

[0116] It can be understood that the initial classification model is a multilayer perceptron neural network MLP (Multilayer Perceptron). For example, Figure 2As shown, define an MLP neural network model consisting of an input layer, several hidden layers, and an output layer. The activation function for the input and hidden layers is Relu (Reinforced Lu) and the number of neurons in the output layer is 2, with a softmax activation function. Build and implement the MLP neural network model and train it using the training dataset. Evaluate the model by adjusting the number of neural network layers, number of neurons, learning rate, and optimization function, optimizing the model based on the change in loss function and accuracy. Note that other activation functions can be selected, or alternative model architectures, such as SVM, can be used to classify the experimental dataset.

[0117] Reference Figure 3 As shown in FIG, the present invention provides a training process of the MLP model, which specifically includes five steps, namely: constructing a data set, defining an MLP model, training an MLP model, evaluating and optimizing the MLP model, and packaging and applying the MLP model, wherein:

[0118] 1. Construct a dataset: For the node admittance matrices of digital, RF, and mixed-signal circuits, perform the following steps: Feature extraction: Collect feature vectors such as matrix dimension, number of nonzero elements, and node average degree. The extracted feature vectors must cover symbolic features such as symmetry / asymmetry and dense / sparseness; Label generation: Generate non-uniform block elimination trees and uniform block elimination trees for each matrix. By comparing indicators such as tree depth and balance, determine the optimal block partitioning method as the supervised learning label; Data partitioning: Divide the labeled data into training and test sets in proportion.

[0119] 2. Design a multi-layer perceptron (MLP) structure, where the input layer dimension matches the number of features in the node admittance matrix; the hidden layer uses the ReLU activation function to construct a nonlinear mapping and learn the complex relationship between features and the blocking strategy; the output layer outputs a binary classification prediction of the blocking strategy, that is, predicting non-uniform or uniform blocking, and uses the cross-entropy loss function to adapt to the classification task.

[0120] 3. Training the MLP model:

[0121] Perform the following steps using the training set:

[0122] Forward propagation: input feature vector, model predicts the block strategy;

[0123] Backpropagation: Compare the predicted results with the true labels (eliminating the optimal block of tree comparison) and update the network parameters through the Adam optimizer;

[0124] Iterative optimization: Repeated training until the loss converges, so that the model can master the mapping rules between the parasitic parameter characteristics of the RF circuit and the non-uniform blocks.

[0125] 4. MLP model evaluation and parameter tuning:

[0126] Verified by the test set:

[0127] Performance indicators: evaluate the prediction accuracy of the block partitioning strategy and the actual efficiency of the tree elimination after block partitioning (tree depth reduction rate, parallelism improvement rate);

[0128] Parameter tuning: If the generalization capability is insufficient (e.g., incorrect prediction of the mixed signal matrix), adjust the hidden layer size and learning rate, or add diversified features (e.g., cross-layer connection distance) to ensure coverage of complex circuit scenarios.

[0129] 5. MLP model packaging and application:

[0130] Integration into IC simulation flow:

[0131] Package deployment: package the trained MLP model into a tool module;

[0132] Simulation call: When a new simulation task arrives, the eigenvector of the node admittance matrix is ​​first extracted and input into the model to obtain the block strategy (uniform block adaptation to the digital circuit power network), which guides subsequent matrix decomposition and simulation calculations, ultimately achieving the technical effect of improving efficiency and reducing memory usage.

[0133] This provides an adaptive decomposition method for node admittance matrices with more complex symbolic structures and no obvious symbolic features. Based on the selection of matrix partitioning methods, an elimination tree is constructed. Through elimination tree analysis and comprehensive balance calculation, a quantitative assessment of the sparse matrix symbolic structure can be performed to achieve load balancing, increase the degree of parallelism in the numerical decomposition stage, and improve computational efficiency.

[0134] In this embodiment, after model training and evaluation are completed, when a new simulation task arrives, the target integrated circuit simulation analysis requirements are received, and the target eigenvector of the target node admittance matrix is ​​extracted from the target integrated circuit simulation analysis requirements; the eigenvector of the target node admittance matrix is ​​classified and predicted in a block manner through a machine learning model, and a target block manner label is output; if the target block manner label is a non-uniform block manner label, the target node admittance matrix is ​​decomposed using the multi-wavefront method or the super-node method to obtain a corresponding decomposition result; if the target block manner label is a uniform block manner label, the target node admittance matrix is ​​decomposed using the PanguLU method to obtain a corresponding decomposition result; the decomposition result is used to solve the circuit equation and generate a simulation analysis report.

[0135] The above technical solution demonstrates that by extracting the original features, or eigenvectors, of the node admittance matrix required for integrated circuit simulation analysis, reordering interference is avoided and the inherent structural characteristics of the node admittance matrix are directly reflected. Then, through dual-path block optimization, two elimination trees are simultaneously constructed to quantitatively compare load balancing, eliminate the blindness of manually selecting block partitioning methods, and avoid the loss of parallelism caused by a single block partitioning method. The block partitioning labels of the node admittance matrix are then numerically determined by calculating the overall balance. This allows the obtained block partitioning labels to be selected independently of empirical experience. A corresponding machine learning model is then trained using a training dataset consisting of the block partitioning labels and corresponding eigenvectors. This demonstrates that this machine learning model can achieve real-time adaptive classification of the admittance matrix in integrated circuit simulation analysis.

[0136] Reference Figure 4 As shown, an embodiment of the present invention also provides a matrix decomposition machine learning training device for integrated circuit simulation analysis, including:

[0137] A requirement generation module 11 is used to generate corresponding integrated circuit simulation analysis requirements according to the integrated circuit simulation analysis task;

[0138] A feature acquisition module 12 is configured to acquire a feature vector of a node admittance matrix in an integrated circuit simulation based on an integrated circuit simulation analysis requirement; the feature vector includes any one or more of the following: matrix dimension, number of non-zero elements, node average degree, sparsity, maximum node degree, minimum node degree, and maximum node distance;

[0139] A block processing module 13 is used to perform non-uniform block processing and uniform block processing on the node admittance matrix, and generate corresponding target non-uniform block elimination tree and target uniform block elimination tree;

[0140] A label determination module 14 is configured to obtain a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix based on elimination tree indices of the target non-uniform block elimination tree and the target uniform block elimination tree, so as to determine a block mode label of the node admittance matrix; the block mode label includes a non-uniform block label and a uniform block label;

[0141] The model training module 15 is used to form a training data set with feature vectors and block labels, so as to use the training data set and perform block recognition training on the initial classification model to obtain a machine learning model of the classification node admittance matrix block mode for integrated circuit simulation analysis.

[0142] This demonstrates that by extracting the original features, or eigenvectors, of the node admittance matrix required for integrated circuit simulation analysis, reordering interference is avoided and the inherent structural characteristics of the node admittance matrix are directly reflected. Then, through dual-path block optimization, two elimination trees are simultaneously constructed to quantitatively compare load balancing, eliminate the blindness of manually selecting block partitioning methods, and avoid the loss of parallelism caused by a single block partition. The block partitioning labels of the node admittance matrix are then numerically determined by calculating the overall balance. This allows the obtained block partitioning labels to be selected independently of empirical experience. A corresponding machine learning model is then trained using a training dataset consisting of the block partitioning labels and corresponding eigenvectors. This demonstrates that this machine learning model can achieve real-time adaptive classification of the admittance matrix in integrated circuit simulation analysis.

[0143] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 5 This is a structural diagram of an electronic device according to an exemplary embodiment. The content in the diagram cannot be considered as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the matrix decomposition machine learning training method for integrated circuit simulation analysis disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0144] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0145] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0146] The operating system 221 is used to manage and control the hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of implementing the matrix decomposition machine learning training method for integrated circuit simulation analysis performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 may further include computer programs capable of implementing other specific tasks.

[0147] Furthermore, this application discloses a computer-readable storage medium for storing a computer program; when executed by a processor, the computer program implements the aforementioned matrix decomposition machine learning training method for integrated circuit simulation analysis. The specific steps of this method can be found in the corresponding content disclosed in the aforementioned embodiments and will not be repeated here.

[0148] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0149] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0150] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0151] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0152] The above is a detailed introduction to the technical solution provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A matrix decomposition machine learning training method for integrated circuit simulation analysis, characterized in that: include: Generate corresponding integrated circuit simulation analysis requirements according to the integrated circuit simulation analysis tasks; Obtaining an eigenvector of a node admittance matrix in an integrated circuit simulation from the integrated circuit simulation analysis requirement; the eigenvector includes any one or more of matrix dimension, number of non-zero elements, node average degree, sparsity, maximum node degree, minimum node degree, and maximum node distance; Performing non-uniform block processing and uniform block processing on the node admittance matrix respectively, and generating corresponding target non-uniform block elimination tree and target uniform block elimination tree; Obtaining a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix according to respective elimination tree indices of the target non-uniform block elimination tree and the target uniform block elimination tree, so as to determine a block mode label of the node admittance matrix; The block mode label includes a non-uniform block label and a uniform block label; The feature vector and the block mode label constitute a training data set, and the training data set is used to perform block recognition training on the initial classification model to obtain a machine learning model for the block mode of classification node admittance matrix in integrated circuit simulation analysis.

2. The matrix decomposition machine learning training method for integrated circuit simulation analysis according to claim 1, characterized in that: The determining of the block mode label of the node admittance matrix includes: If the first comprehensive balance degree is less than the second comprehensive balance degree, determining that the block mode label of the node admittance matrix is ​​a non-uniform block label; If the first comprehensive balance degree is greater than the second comprehensive balance degree, it is determined that the block mode label of the node admittance matrix is ​​a uniform block label.

3. The matrix decomposition machine learning training method for integrated circuit simulation analysis according to claim 1, characterized in that: Performing non-uniform block processing on the node admittance matrix and generating a corresponding target non-uniform block elimination tree, including: Performing a matrix reordering operation on the node admittance matrix to obtain a reordered optimized matrix; Merging diagonal nodes of the reordered optimized matrix to obtain a merged optimized matrix; Performing irregular matrix block processing on the merged optimized matrix to obtain matrix non-uniform blocks, and performing symbolic analysis optimization on the matrix non-uniform blocks to obtain an optimized non-uniform block elimination tree; When the optimized non-uniform block elimination tree meets the preset optimization conditions, the optimization is stopped, and the current optimized non-uniform block elimination tree is output as the target non-uniform block elimination tree; When the non-uniform block elimination tree in the optimization does not meet the preset optimization conditions, the corresponding matrix optimization steps are re-executed until the non-uniform block elimination tree in the optimization meets the preset optimization conditions.

4. The matrix decomposition machine learning training method for integrated circuit simulation analysis according to claim 1, characterized in that: Performing uniform block processing on the node admittance matrix and generating a corresponding target uniform block elimination tree includes: Performing a matrix reordering operation on the node admittance matrix to obtain a reordered optimized matrix; Performing regular matrix block processing on the reordered optimized matrix to obtain uniform matrix blocks, and performing symbolic analysis optimization on the uniform matrix blocks to obtain an optimized uniform block elimination tree; When the optimized uniform block elimination tree meets the preset optimization conditions, the optimization is stopped, and the current optimized uniform block elimination tree is output as the target uniform block elimination tree; When the optimized uniform block elimination tree does not meet the preset optimization conditions, the corresponding matrix optimization steps are re-executed until the optimized uniform block elimination tree meets the preset optimization conditions.

5. The matrix decomposition machine learning training method for integrated circuit simulation analysis according to claim 1, characterized in that: The elimination tree indicators include tree depth, total number of nodes, number of leaf nodes, factorization complexity, forward and backward complexity and node balance; Accordingly, the obtaining of the first comprehensive balance degree and the second comprehensive balance degree of the node admittance matrix according to the elimination tree indexes of the target non-uniform block elimination tree and the target uniform block elimination tree includes: Calculating a first comprehensive balance degree of the node admittance matrix according to an elimination tree index of the target non-uniform block elimination tree and a corresponding first index weight coefficient; The second comprehensive balance degree of the node admittance matrix is ​​calculated according to the elimination tree index of the target uniform block elimination tree and the corresponding second index weight coefficient.

6. The matrix decomposition machine learning training method for integrated circuit simulation analysis according to claim 1, characterized in that: The initial classification model is a multi-layer perceptron neural network, which includes an input layer, several hidden layers and an output layer, wherein the activation functions of the input layer and the hidden layer are Relu functions, the number of neurons in the output layer is 2, and the activation function of the output layer is softmax; Accordingly, the method of using the training data set and performing block recognition training on the initial classification model to obtain a machine learning model for the block mode of classification node admittance matrix in integrated circuit simulation analysis includes: Normalizing the training data set and converting the block-wise labels into one-hot encoding to obtain an input feature vector; Initializing weight parameters and bias parameters of the multilayer perceptron neural network; Inputting the input feature vector into the input layer of the multilayer perceptron neural network, so that the input layer transfers the input feature vector to each layer of the network through forward propagation calculation, and applying the ReLU activation function in the hidden layer and the softmax activation function in the output layer to obtain the corresponding predicted probability distribution; Calculate a cross entropy loss function value based on the predicted probability distribution and the block mode label; Calculate the gradient of the cross entropy loss function value with respect to the multilayer perceptron neural network parameters through a back propagation algorithm; The weight parameters and bias parameters of the multilayer perceptron neural network are updated according to the gradient and using an adaptive moment estimation algorithm until the model performance of the multilayer perceptron neural network meets the preset training stop condition, so as to use the multilayer perceptron neural network under the current multilayer perceptron neural network parameters as a machine learning model.

7. The matrix decomposition machine learning training method for integrated circuit simulation analysis according to claim 1, characterized in that: The eigenvectors in the training data set are eigenvectors of the node admittance matrix covering different symbol features.

8. The matrix decomposition machine learning training method for integrated circuit simulation analysis according to any one of claims 1 to 6, characterized in that: After obtaining the machine learning model for the block-wise classification of node admittance matrices in the integrated circuit simulation analysis, the method further includes: receiving a target integrated circuit simulation analysis requirement, and extracting a target eigenvector of a target node admittance matrix from the target integrated circuit simulation analysis requirement; Performing block classification prediction on the eigenvector of the admittance matrix of the target node through the machine learning model, and outputting a target block label; If the target block mode label is a non-uniform block label, decompose the target node admittance matrix using a multi-wavefront method or a super-node method to obtain a corresponding decomposition result; If the target block mode label is a uniform block label, the target node admittance matrix is ​​decomposed using the PanguLU method to obtain a corresponding decomposition result; The decomposition results are used to solve circuit equations and generate a simulation analysis report.

9. A matrix decomposition machine learning training device for integrated circuit simulation analysis, characterized in that: include: A requirement generation module, used to generate corresponding integrated circuit simulation analysis requirements according to the integrated circuit simulation analysis task; a feature acquisition module, configured to acquire a feature vector of a node admittance matrix in an integrated circuit simulation from the integrated circuit simulation analysis requirement; the feature vector includes any one or more of the following: matrix dimension, number of non-zero elements, node average degree, sparsity, maximum node degree, minimum node degree, and maximum node distance; A block processing module, configured to perform non-uniform block processing and uniform block processing on the node admittance matrix, and generate corresponding target non-uniform block elimination trees and target uniform block elimination trees; a label determination module, configured to obtain a first comprehensive balance degree and a second comprehensive balance degree of the node admittance matrix based on elimination tree indices of the target non-uniform block elimination tree and the target uniform block elimination tree, so as to determine a block mode label of the node admittance matrix; the block mode label includes a non-uniform block label and a uniform block label; The model training module is used to form a training data set with the feature vector and the block mode label, so as to use the training data set and perform block recognition training on the initial classification model to obtain a machine learning model of the classification node admittance matrix block mode for integrated circuit simulation analysis.

10. An electronic device, characterized in that: include: memory for storing computer programs; A processor for executing the computer program to implement the steps of the matrix decomposition machine learning training method for integrated circuit simulation analysis as described in any one of claims 1 to 8.

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