Etching method of doped polysilicon, semiconductor device and method of forming the same, and semiconductor processing apparatus

Abstract

The present application relates to the technical field of semiconductor, in particular to a kind of doped polysilicon etching method, semiconductor device and its forming method and semiconductor process equipment.The provided doped polysilicon etching method includes: pre-etching step, using first process gas to etch the natural oxide layer on the surface of doped polysilicon, to remove the natural oxide layer;Main etching step, using second process gas to etch the doped polysilicon, the second process gas includes first reaction gas and second reaction gas, the etching rate of the first reaction gas to polysilicon is greater than the etching rate to doping substance, and the second reaction gas includes fluorocarbon gas, and the fluorocarbon gas is suitable for reacting with doping substance and polysilicon.The present application can solve the problem of blocking type defect when etching doped polysilicon at present, and can improve the production stability and yield of product.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an etching method for doped polycrystalline silicon, a semiconductor device, a method for forming the same, and semiconductor process equipment. Background Technology

[0002] MOS (Metal Oxide Semiconductor) devices are widely used in consumer electronics, mobile internet, smart communications, automotive electronics, industrial control, and medical electronics due to their advantages such as low power consumption, high noise margin, and ease of design. In MOS device fabrication, polysilicon is widely used for the gate electrode. As the size of power devices continues to shrink, etching the polysilicon gate becomes increasingly challenging; for example, it's necessary to ensure the polysilicon gate is completely etched without completely etching the gate oxide layer. Polysilicon etching is one of the most important etching processes in MOS device fabrication, determining the transistor yield and the mass production stability of the device. In MOS devices, to increase the conductivity of polysilicon, it is usually doped. Phosphorus-doped polysilicon is commonly used as the conductive material. The morphology and the number of defects after polysilicon etching determine the transistor's performance.

[0003] In related technologies, when etching doped polysilicon, the etching gas used has high selectivity for polysilicon and dopants such as phosphorus. When etching down to the phosphorus-containing polysilicon film, the etching gas tends to react with the polysilicon. As the etching time increases, the dopant gradually blocks the underlying polysilicon from being etched, eventually resulting in a large amount of polysilicon residue after etching. However, this residue is a blocking defect. This polysilicon blocking etching defect causes the polysilicon to conduct electricity, making the device malfunction, significantly reducing product yield, and even causing wafer scrap due to an excessive number of defects. Summary of the Invention

[0004] The purpose of this invention is to provide an etching method for doped polysilicon, a semiconductor device and a method for forming the same, and a semiconductor process equipment, in order to alleviate the blocking defect problem that exists in the current etching of doped polysilicon, and to improve the mass production stability and yield of the product.

[0005] In a first aspect, the present invention discloses an etching method for doped polysilicon, the etching method comprising: a pre-etching step, wherein a first process gas is used to etch a native oxide layer on the surface of the doped polysilicon to remove the native oxide layer; and a main etching step, wherein a second process gas is used to etch the doped polysilicon, the second process gas comprising a first reactive gas and a second reactive gas, wherein the etching rate of the first reactive gas on the polysilicon is greater than the etching rate on the dopant, and the second reactive gas comprises a fluorocarbon gas, wherein the fluorocarbon gas is suitable for reacting with the dopant and the polysilicon.

[0006] In some embodiments of the present invention, the proportion of the first reactive gas in the second process gas is greater than the proportion of the fluorocarbon gas; and / or, the first reactive gas is used to control the overall etching rate, and the fluorocarbon gas is used to etch the dopant material while etching the polysilicon.

[0007] In some embodiments of the present invention, the fluorocarbon gas includes at least one or more of CF4, C4F6, or C4F8.

[0008] In some embodiments of the present invention, the first reactant gas includes at least a fluorine-containing gas and / or a chlorine-containing gas.

[0009] In some embodiments of the present invention, the first reactant gas includes a fluorine-containing gas and a chlorine-containing gas; the fluorine-containing gas includes at least SF6 and / or NF3; and the chlorine-containing gas includes at least Cl2.

[0010] In some embodiments of the present invention, the volume ratio of the fluorine-containing gas, the chlorine-containing gas, and the fluorocarbon gas in the second process gas ranges from (0.6 to 6): (2 to 15): 1.

[0011] In some embodiments of the present invention, the flow rate of the fluorine-containing gas is in the range of 30 sccm to 60 sccm; the flow rate of the chlorine-containing gas is in the range of 100 sccm to 150 sccm; and the flow rate of the fluorocarbon gas is in the range of 10 sccm to 50 sccm.

[0012] In some embodiments of the present invention, the second process gas further includes a dilution gas, wherein the dilution gas is a rare gas.

[0013] In some embodiments of the present invention, the rare gas includes at least helium.

[0014] In some embodiments of the present invention, the flow rate of the rare gas ranges from 100 sccm to 200 sccm.

[0015] In some embodiments of the present invention, the volume ratio of the first reaction gas, the fluorocarbon gas, and the dilution gas in the second process gas is (2-25):1:(2-20).

[0016] In some embodiments of the present invention, the first process gas includes a fluorocarbon gas; the fluorocarbon gas includes at least CF4.

[0017] In some embodiments of the present invention, the gas flow rate of the first process gas ranges from 50 sccm to 150 sccm.

[0018] In some embodiments of the present invention, after the main etching step, the etching method further includes an over-etching step, in which a third process gas is used to continue etching the doped polysilicon until the target etching depth is reached.

[0019] In some embodiments of the present invention, the third process gas includes at least a bromine-containing gas and a dilution gas, wherein the dilution gas is a rare gas.

[0020] In some embodiments of the present invention, the bromine-containing gas includes at least HBr; the rare gas includes at least helium.

[0021] In some embodiments of the present invention, the flow rate of the bromine-containing gas ranges from 20 sccm to 60 sccm; the flow rate of the rare gas ranges from 100 sccm to 200 sccm.

[0022] Secondly, the present invention discloses a method for forming a semiconductor device, the method comprising:

[0023] A substrate is provided; a dielectric layer is formed on the surface of the substrate; and a doped polysilicon layer is formed on the surface of the dielectric layer using the aforementioned etching method for doped polysilicon.

[0024] Thirdly, the present invention discloses a semiconductor device, which is prepared by the aforementioned semiconductor device formation method.

[0025] Fourthly, the present invention discloses a semiconductor process apparatus, including a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory, wherein the memory stores a computer program. When the computer program is executed by the processor, it implements the etching method for doped polycrystalline silicon described above, or the aforementioned method for forming semiconductor devices.

[0026] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0027] The etching method of this application introduces a second reactive gas containing a fluorocarbon gas into the main etching step. By utilizing the reaction between the fluorocarbon gas and the dopant and polysilicon, the dopant can be etched away during the etching process, effectively removing dopant contaminants and reducing polysilicon residue caused by dopant. This reduces barrier defects during the etching process and minimizes or avoids reliability issues caused by residual doped polysilicon or contaminants between the polysilicon and other film layers. Consequently, it can increase the stability and yield of mass production of products. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a semiconductor device based on related technologies.

[0030] Figure 2 This is a schematic flowchart of an etching method for doped polycrystalline silicon provided in an embodiment of the present invention.

[0031] Figure 3 This is a schematic flowchart of another etching method for doped polysilicon provided in an embodiment of the present invention.

[0032] Figure 4 This is a schematic diagram of the structure of a semiconductor device to be etched, provided as an embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 101-substrate;

[0036] 102 - Dielectric layer;

[0037] 103-doped polycrystalline silicon layer;

[0038] 104 - Doped polysilicon to be etched;

[0039] 105 - Residual polysilicon. Detailed Implementation

[0040] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0042] As mentioned in the background section, when etching doped polysilicon (such as phosphorus-doped polysilicon), the etching gases used in existing technologies have relatively high selectivity for polysilicon and dopant elements such as phosphorus. For example, existing technologies typically use sulfur hexafluoride (SF6), chlorine (Cl2), and hydrogen bromide (HBr) as the main etching gases for polysilicon. These etching gases react with silicon to generate volatile gases such as SiF4, SiCl4, and SiBr4, which are then removed by a vacuum system. However, as... Figure 1 As shown, for phosphorus-doped polysilicon, SF6 has a high selectivity for both polysilicon and phosphorus. When etching to the phosphorus-containing polysilicon film, SF6 tends to react with the polysilicon. As the etching time increases, phosphorus and phosphorus oxides gradually block the polysilicon underneath from being etched, eventually resulting in a large amount of polysilicon residue after etching (leaving residual polysilicon 105). That is, after etching, residual polysilicon 105 is still present on the doped polysilicon layer 103 (polysilicon film) on the dielectric layer 102 (such as the gate oxide layer) on the substrate 101 (such as the substrate silicon). This residue is a blocking defect. This polysilicon blocking etching defect causes the polysilicon to conduct electricity, causing the device to fail, significantly reducing the product yield, and may even cause the wafer to be scrapped due to the excessive number of defects.

[0043] To alleviate the aforementioned problems, related technologies employ a cleaning process to remove phosphorus precipitated on the surface of phosphorus-doped polycrystalline silicon and the resulting phosphorus-containing contaminants, thus preventing phosphorus and these contaminants from affecting subsequent etching of the doped polycrystalline silicon and causing etching residue. This approach primarily involves first immersing the wafer in an acidic solution for cleaning, and then transferring the wafer to an alkaline cleaning solution for further cleaning to remove phosphorus and the resulting phosphorus-containing contaminants from the wafer surface. This method cleans phosphorus-doped polycrystalline silicon wafers before etching to remove phosphorus and the phosphorus-containing contaminants precipitated on the polycrystalline silicon surface. However, the drawback of using cleaning processes to remove phosphorus and phosphorus-containing contaminants deposited on the surface of phosphorus-doped polycrystalline silicon is that while cleaning before etching can remove phosphorus and phosphorus-containing contaminants from the polycrystalline silicon surface, phosphorus diffused into the polycrystalline silicon is often difficult to remove, leaving residues after etching. This is because the etching gases used to etch polycrystalline silicon are generally insufficient to etch away phosphorus and phosphorus-containing oxides. As the etching reaction proceeds, phosphorus and phosphorus-containing contaminants gradually block the etching of the underlying polycrystalline silicon, resulting in residual polycrystalline silicon. Furthermore, this technology requires an additional cleaning step before etching, increasing the number of steps and lengthening the product manufacturing cycle.

[0044] Based on this, the present invention discloses an etching scheme. By adding fluorocarbon (CF) gases (such as CF4, C4F6, C4F8, etc.) in the main etching step, phosphorus and phosphorus-containing oxides can be etched away during the etching process. Compared with SF6 gas, CF gases have lower selectivity for polysilicon and phosphorus. During the etching process, polysilicon and phosphorus can be etched away simultaneously, thereby greatly reducing the blocking defects in the etching process. In other words, it can effectively improve the defects generated by the etching of phosphorus-doped polysilicon, and increase the stability and yield of mass production of products.

[0045] As an optional implementation of the disclosed content of this invention, an embodiment of this invention discloses an etching method for doped polycrystalline silicon, such as... Figure 2 As shown, the etching method includes:

[0046] S101: Pre-etching step (also known as BT step), which uses the first process gas to etch the native oxide layer on the surface of the doped polysilicon to remove the native oxide layer.

[0047] In this embodiment, the etching method for doped polysilicon is applicable to etching polysilicon containing dopants, wherein the doping element can be phosphorus. For example, the doped polysilicon can be phosphorus-doped polysilicon. By doping polysilicon with phosphorus, conductivity can be improved. Of course, the doping element is not limited to phosphorus; other similar doped polysilicon with the same or similar problems can also be etched using the etching method of this invention. The following description mainly uses phosphorus-doped polysilicon as an example.

[0048] In the embodiments of this application, a pre-etching step is performed before the main etching step. As the first step of etching, it can play a role in pre-etching. For example, a gas containing fluorocarbons can be used to remove the natural oxide layer and surface contaminants on the surface of the doped polycrystalline silicon, thereby reducing surface defects caused by contaminants that act as micro-masking layers during etching.

[0049] S102: Main etching step (also known as ME step), which uses a second process gas to etch the doped polysilicon. The second process gas includes a first reaction gas and a second reaction gas. The etching rate of the first reaction gas on polysilicon is greater than the etching rate on the dopant. The second reaction gas includes fluorocarbon gases, which are suitable for reacting with the dopant and polysilicon.

[0050] In the embodiments of this application, a second process gas is used for etching in the main etching step. The second process gas includes a first reaction gas and a second reaction gas. Using the first reaction gas as the main etching gas can achieve a faster etching rate. In this step, a second reaction gas, namely a fluorocarbon gas, is added. The addition of the fluorocarbon gas can effectively remove dopants, such as phosphorus-containing contaminants.

[0051] Of the aforementioned second process gases, the first reactant gas exhibits higher selectivity for polysilicon and dopants, while the second reactant gas, i.e., the fluorocarbon gas, shows lower selectivity. During etching, the first reactant gas preferentially reacts with polysilicon, resulting in a significantly higher etching rate for polysilicon than for dopants such as phosphorus-containing materials. In contrast, the fluorocarbon gas can react with both dopants and polysilicon; for example, during etching, it can simultaneously etch away both polysilicon and phosphorus.

[0052] Therefore, by adding fluorocarbon gas to the main etching step, this application utilizes the reaction between the fluorocarbon gas and the dopant and polysilicon to etch away the dopant during the etching process. In other words, the fluorocarbon gas can simultaneously etch away polysilicon and phosphorus during the etching process, effectively removing dopant contaminants and reducing polysilicon residue caused by dopant. This reduces barrier defects during the etching process and minimizes or avoids reliability issues caused by residual doped polysilicon or contaminants between doped polysilicon and other film layers, thereby increasing product mass production stability and yield.

[0053] like Figure 3 As shown, after the main etching step, the etching method further includes:

[0054] S103: Over-etching step (also known as OE step), the doped polysilicon is further etched using a third process gas until the target etching depth is reached.

[0055] In this embodiment, the etching method mainly includes: a pre-etching step (S101), a main etching step (S102), and an over-etching step (S103). The pre-etching step (S101) serves as the first step in the etching process, acting as a pre-etching step. For example, a gas containing fluorocarbons can be used to remove the native oxide layer and surface contaminants on the doped polysilicon surface, allowing the main etching gas (i.e., the subsequent first reaction gas) to react with the polysilicon, thus reducing surface defects caused by contaminants acting as a micro-masking layer during etching. In the main etching step (S102), most of the polysilicon film can be etched away without damaging the gate oxide layer, resulting in an ideal anisotropic sidewall profile. In the main etching step, the first reaction gas completes most of the etching, achieving a faster etching rate. Furthermore, this embodiment incorporates a fluorocarbon gas in this step, effectively removing phosphorus-containing contaminants during etching, reducing or avoiding the obstruction of polysilicon etching by phosphorus-containing substances, thereby reducing defects during the doped polysilicon etching process. In the S103 over-etching step, a third process gas can be used to continue etching the doped polysilicon to remove etching residues and remaining polysilicon, forming a doped polysilicon layer with the required depth.

[0056] It should be noted that the provided etching method for doped polysilicon can be applied in the formation process of semiconductor devices to prepare doped polysilicon layers or doped polysilicon gates. Optionally, the semiconductor device can be a memory device, such as a MOS device. As an example, the semiconductor device includes a substrate, a dielectric layer disposed on the surface of the substrate, and a doped polysilicon layer disposed on the surface of the dielectric layer. The doped polysilicon layer can be etched by the etching method for doped polysilicon provided in the embodiments of the present invention. Optionally, the dielectric layer can be a gate oxide layer.

[0057] Specifically, in some embodiments, in the S101 pre-etching step, the first process gas includes a fluorocarbon gas; the fluorocarbon gas includes at least CF4. Of course, in other embodiments, the fluorocarbon gas can also be C. x F y x and y can be integers greater than or equal to 1.

[0058] In some embodiments of the present invention, the flow rate of the first process gas, such as CF4, is in the range of 50 sccm to 150 sccm, for example, 50 sccm, 60 sccm, 80 sccm, 100 sccm, 120 sccm, 150 sccm, etc.

[0059] In some embodiments, the preparation parameters for the S101 pre-etching step are first preparation parameters, which include the aforementioned first process gas flow rate. Further, the first preparation parameters may also include a first etching time, a first chamber pressure, a first upper electrode power, and a first lower electrode power. Specifically, the first etching time may include 10s to 20s, the first chamber pressure may include 8mT to 16mT, the first upper electrode power may include 250W to 400W, and the first lower electrode power may include 20W to 100W.

[0060] That is, in the process of removing the natural oxide layer on the surface of doped polycrystalline silicon, the natural oxide layer on the surface of doped polycrystalline silicon can be etched under a chamber pressure of 8 to 16 mT, through a first process gas such as CF4 (a fluorocarbon gas) at 50 sccm to 150 sccm, and under the action of an upper electrode power of 250 to 400 W and a lower electrode power of 20 to 100 W, wherein the etching time is 10 to 20 s.

[0061] Under the aforementioned chamber pressure, upper electrode power, and lower electrode power, the etching rate of the natural oxide layer and surface contaminants is improved, production efficiency is increased, and a reaction basis is provided for the subsequent main etching step.

[0062] Thus, by setting the above pre-etching step, the natural oxide layer and surface contaminants on the polysilicon surface are removed, so that the main etching gas and the first reaction gas, such as SF6 and Cl2, can react with the polysilicon in an etching reaction.

[0063] Specifically, in some embodiments, in the main etching step S102, the proportion of the first reaction gas in the second process gas is greater than the proportion of the fluorocarbon gas.

[0064] In this embodiment of the invention, the first reactant gas can be used as the main etching gas. The first reactant gas is used to control the overall etching rate. The addition of the first reactant gas can make the etching rate relatively fast. The main etching can basically determine the morphology and critical dimensions of the polysilicon gate. At the same time, this invention also incorporates a fluorine-carbon gas, which is used to etch dopants while etching polysilicon. This fluorine-carbon gas has low selectivity for polysilicon and dopants such as phosphides, and can etch away phosphides while etching polysilicon, thereby greatly reducing defects in the polysilicon etching process.

[0065] In some embodiments, the first reacting gas includes at least a fluorine-containing gas and / or a chlorine-containing gas. For example, the first reacting gas may include a fluorine-containing gas, or it may include a chlorine-containing gas, or it may include both a fluorine-containing gas and a chlorine-containing gas.

[0066] Preferably, in some embodiments, the first reaction gas includes both a fluorine-containing gas and a chlorine-containing gas; wherein the fluorine-containing gas includes at least SF6 and / or NF3; and the chlorine-containing gas includes at least Cl2.

[0067] In this embodiment of the invention, the fluorine-containing gas can be, for example, nitrogen trifluoride (NF3) or sulfur hexafluoride (SF6). Preferably, the fluorine-containing gas is selected from SF6, which can provide more F ions and increase the etching rate.

[0068] In one specific embodiment, the first reactant gas includes SF6 and Cl2. Using SF6 and Cl2 as the main etching gases results in a higher etching rate and better etching effect for polycrystalline silicon.

[0069] In some embodiments, the second process gas includes at least one or more of CF4, C4F6, or C4F8. This fluorocarbon gas exhibits low selectivity for polysilicon and phosphides, etching away phosphides while simultaneously etching polysilicon, thereby significantly reducing defects during the polysilicon etching process.

[0070] In some embodiments, the first reactant gas in the second process gas includes a fluorine-containing gas and a chlorine-containing gas, and the second reactant gas is a fluorocarbon gas; the volume ratio of the fluorine-containing gas, the chlorine-containing gas and the fluorocarbon gas is in the range of (0.6-6):(2-15):1.

[0071] By controlling the proportions of fluorine-containing gases, chlorine-containing gases, and fluorocarbon gases in the second process gas, the etching selectivity or etching rate can be controlled. Under conditions of faster etching rate and polysilicon gate morphology and critical dimensions, dopants can be etched away, thereby reducing blocking defects during the etching process.

[0072] In some embodiments of the present invention, the flow rate of the fluorine-containing gas ranges from 30 sccm to 60 sccm, for example, 30 sccm, 40 sccm, 50 sccm, 60 sccm, etc.; the flow rate of the chlorine-containing gas ranges from 100 sccm to 150 sccm, for example, 100 sccm, 110 sccm, 120 sccm, 130 sccm, 140 sccm, 150 sccm, etc.; and the flow rate of the fluorocarbon gas ranges from 10 sccm to 50 sccm, for example, 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, etc. Of course, the present invention is not limited to these. In practical applications, the flow rates of the fluorine-containing gas, chlorine-containing gas, and fluorocarbon gas can be adjusted according to requirements, as long as their proportions are within a suitable range.

[0073] Of course, the present invention is not limited to this. In some embodiments, the second process gas mentioned above also includes a dilution gas, which is a rare gas.

[0074] In some embodiments, the rare gas includes at least helium (He). Helium can be used as a diluent gas to balance the pressure and reactant gas content within the chamber. However, it is not limited to this; the rare gas can also be other rare gases such as argon.

[0075] In some embodiments of the present invention, the volume ratio of the first reactant gas, the fluorocarbon gas, and the diluent gas in the second process gas ranges from (2-25):1:(2-20). The first reactant gas may include fluorine-containing gas and chlorine-containing gas, and the second reactant gas is a fluorocarbon gas; the volume ratio of the fluorine-containing gas, chlorine-containing gas, fluorocarbon gas, and diluent gas ranges from (0.6-6):(2-15):1:(2-20).

[0076] In some embodiments of the present invention, the flow rate of the rare gas ranges from 100 sccm to 200 sccm. For example, it can be 100 sccm, 120 sccm, 140 sccm, 150 sccm, 180 sccm, 200 sccm, etc. Of course, the present invention is not limited to this. In practical applications, the flow rate of the rare gas can be adjusted according to requirements, as long as its proportion is kept within a suitable range.

[0077] In some embodiments, the preparation parameters for the main etching step S102 are second preparation parameters. These second preparation parameters include the flow rates of the first reaction gas, the fluorocarbon gas, and the dilution gas described above. Further, these second preparation parameters may also include a second etching time, a second chamber pressure, a second upper electrode power, and a second lower electrode power. Specifically, the second etching time may include 30s to 80s, the first chamber pressure may include 10mT to 20mT, the second upper electrode power may include 800W to 1200W, and the second lower electrode power may include 50W to 100W.

[0078] That is, during the etching of doped polysilicon, the doped polysilicon can be etched under a chamber pressure of 10-20 mT by passing through 30-60 sccm of fluorine-containing gas such as SF6, 100-150 sccm of chlorine-containing gas such as Cl2, 10-50 sccm of fluorocarbon gas such as CF4, C4F6 or C4F8, and 100-200 sccm of rare gas such as He, and under the action of an upper electrode power of 800-1200 W and a lower electrode power of 50-100 W, with an etching time of 30-80 s.

[0079] Under the aforementioned chamber pressure, upper electrode power, and lower electrode power, it is helpful to improve the etching rate of doped polysilicon, increase production efficiency, and have a suitable etching selectivity.

[0080] Therefore, by setting the main etching step as described above, using SF6 and Cl2 as the main etching gases, the etching rate is relatively fast, and the morphology and critical dimensions of the polysilicon gate can be largely determined through the main etching. However, due to the high selectivity of SF6 for polysilicon and phosphides, when etching to positions containing phosphorus, SF6 tends to react with polysilicon. As the etching reaction proceeds, the phosphorus blocks the underlying polysilicon, ultimately resulting in etching residue. This application addresses this by adding fluorinated hydrocarbon gases such as CF4, C4F6, or C4F8. Fluorinated hydrocarbon gases have lower selectivity for polysilicon and phosphides, allowing phosphorus to be etched away simultaneously with the polysilicon etching, thereby significantly reducing defects during the polysilicon etching process.

[0081] Specifically, in some embodiments, in the S103 etching step, the third process gas includes at least a bromine-containing gas and a dilution gas, wherein the dilution gas is a rare gas.

[0082] In some embodiments of the present invention, the bromine-containing gas includes at least HBr; the rare gas includes at least helium (He). Of course, in other embodiments, the rare gas may also include gases of the argon type.

[0083] In some embodiments of the present invention, the flow rate of the bromine-containing gas, such as HBr, in the third process gas ranges from 20 sccm to 60 sccm, for example, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, etc. The flow rate of the rare gas, such as He, ranges from 100 sccm to 200 sccm, for example, 100 sccm, 120 sccm, 140 sccm, 150 sccm, 160 sccm, 180 sccm, 200 sccm, etc.

[0084] In some embodiments, the preparation parameters for the S103 etching step are third preparation parameters. These third preparation parameters include the aforementioned third process gas flow rate. Further, the third preparation parameters may also include a third etching time, a third chamber pressure, a third upper electrode power, and a third lower electrode power. Specifically, the third etching time may include 50s to 80s, the third chamber pressure may include 20mT to 30mT, the third upper electrode power may include 200W to 300W, and the third lower electrode power may include 30W to 100W.

[0085] That is, during the over-etching process, polycrystalline silicon can be etched under a chamber pressure of 20-30 mT, through 20-60 sccm of bromine-containing gas such as HBr and 100-200 sccm of rare gas such as He, and under the action of an upper electrode power of 200-300 W and a lower electrode power of 30-100 W, with an etching time of 50-80 s.

[0086] Therefore, by setting the above-described over-etching step, etching residues and remaining polysilicon can be removed. In this over-etching step, a mixed gas of HBr and He is used to avoid damage to the gate oxide layer caused by F-based gases. He acts as a diluent gas, and the use of HBr gas for etching ensures that the gate oxide layer is not damaged, effectively removing any remaining polysilicon. HBr has a high selectivity for the gate oxide layer, thus ensuring that the gate oxide layer is not damaged.

[0087] like Figure 4 As shown, in some embodiments, this application also provides a method for forming a semiconductor device, the method comprising:

[0088] Provide substrate 101;

[0089] A dielectric layer 102 is formed on the surface of the substrate 101;

[0090] A doped polysilicon 104 to be etched is formed on the surface of the dielectric layer 102;

[0091] Then, the aforementioned etching method for doped polysilicon is used to etch the doped polysilicon 104 to form a doped polysilicon layer 103 on the surface of the dielectric layer 102.

[0092] In some embodiments of the present invention, the substrate 101 may be a silicon substrate, the dielectric layer 102 may be a gate oxide layer, and the doped polysilicon layer 103 or the polysilicon gate may be formed by the aforementioned etching method for doped polysilicon.

[0093] The semiconductor device formation method of the present invention includes the etching method of doped polysilicon provided by the present invention, which can reduce blocking defects during the etching process, avoid polysilicon residue formed after etching, effectively improve defects generated during the etching process of phosphorus-doped polysilicon, improve mass production stability and yield, and optimize device electrical properties.

[0094] Optionally, the semiconductor device can be a memory device, such as a MOS device.

[0095] It should be noted that the present invention does not impose any special limitations on the specific type or structure of the substrate and dielectric layer, and various types or structures known in the art can be used, which will not be described in detail here.

[0096] In some embodiments, this application also provides a semiconductor device, which is prepared using the aforementioned semiconductor device formation method.

[0097] Please refer to Figure 5 The semiconductor device includes a substrate 101, a dielectric layer 102 (such as a gate oxide layer) and a doped polysilicon layer 103, wherein the dielectric layer 102 and the doped polysilicon layer 103 are sequentially formed on the substrate 101.

[0098] Therefore, the semiconductor device prepared by the semiconductor device formation method of the present invention reduces the blocking defects during the etching process, avoids the polysilicon residue formed after etching, and in particular effectively improves the defects generated during the etching process of phosphorus-doped polysilicon, improves mass production stability and yield, and optimizes the electrical properties of the device.

[0099] In some embodiments, this application also provides a semiconductor process apparatus, which includes a process chamber, an inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory. The memory stores a computer program, which, when executed by the processor, implements the aforementioned etching method for doped polysilicon or the aforementioned method for forming semiconductor devices.

[0100] In the embodiments of this application, the execution subject of the etching method for multi-doped polysilicon is a controller, which can be set in the host computer and / or slave computer of the semiconductor process equipment (such as plasma etching equipment).

[0101] For example, the aforementioned gas inlet assembly is used to introduce gas into the process chamber, including process gases such as etching gas and passivation gas. The controller can be a host computer or a slave computer. The controller can control the opening or closing of the electronic valve of the gas inlet assembly to control the start or stop of gas introduction into the process chamber. The controller can also control the opening degree of the valve of the gas inlet assembly to control the flow rate of the process gas. Optionally, the semiconductor process equipment also includes a gas extraction assembly; the gas extraction assembly is used to extract gas from the process chamber, including by-product gases generated after the etching reaction. The controller can also control the pressure inside the process chamber and discharge reaction by-products by controlling the gas extraction assembly to extract gas from the interior of the process chamber. Furthermore, the controller can also control the valve size of the electronic valve of the gas inlet assembly and the electronic valve of the gas extraction assembly to control the chamber pressure of the process chamber.

[0102] As an optional technical solution of the present invention, in this semiconductor process equipment, the upper electrode assembly includes an upper radio frequency (RF) power supply, a first matching unit electrically connected to the upper RF power supply, and an RF coil electrically connected to the first matching unit. The upper RF power supply can be electrically connected to the RF coil within the process chamber via the first matching unit, for applying RF power to the RF coil, so that the RF coil couples the RF power into the process chamber through a dielectric window, ionizing the gas within the process chamber into plasma. The controller can also be used to control the magnitude of the RF power applied by the upper RF power supply to the RF coil through the first matching unit.

[0103] As an optional technical solution of the present invention, in this semiconductor process equipment, the lower electrode assembly includes a lower radio frequency (RF) power supply, a second matching device electrically connected to the lower RF power supply, and a carrier device electrically connected to the second matching device. The carrier device includes an electrostatic chuck, etc. The lower RF power supply is electrically connected to the carrier device through the second matching device and is used to apply bias power to the carrier device to accelerate the plasma. The carrier device is used to support the substrate and to heat or cool the substrate.

[0104] As an optional implementation of the disclosure of this invention, the semiconductor process equipment can be either an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus. This application does not limit the type of semiconductor process equipment.

[0105] For other working principles and processes of the process equipment in this embodiment, please refer to the description of the doped polysilicon etching method and semiconductor device formation method in the foregoing embodiments of the present invention, which will not be repeated here.

[0106] The foregoing has provided a detailed description of the etching method for doped polycrystalline silicon, the semiconductor device and its formation method, and the semiconductor process equipment provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. It should be noted that the descriptions of each embodiment in this application have different focuses; parts not described in detail in a particular embodiment can be referred to in the relevant descriptions of other embodiments.

[0107] In the description of this invention, it should be noted that the terms "upper", "lower", "front", "horizontal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0108] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "installation" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An etching method for doped polycrystalline silicon, characterized in that, The etching method includes: In the pre-etching step, the native oxide layer on the surface of the doped polysilicon is etched using the first process gas to remove the native oxide layer. In the main etching step, the doped polysilicon is etched using a second process gas. The second process gas includes a first reactive gas and a second reactive gas. The etching rate of the polysilicon by the first reactive gas is greater than the etching rate of the dopant. The second reactive gas includes a fluorocarbon gas, which is suitable for reacting with the dopant and the polysilicon. The first reactive gas is used to regulate the overall etching rate, and the fluorocarbon gas is used to etch the dopant material while etching the polysilicon; The first reactant gas includes at least a fluorine-containing gas and a chlorine-containing gas; the fluorine-containing gas includes at least SF6 and / or NF3; the chlorine-containing gas includes at least Cl2; In the second process gas, the volume ratio of the fluorine-containing gas, the chlorine-containing gas, and the fluorocarbon gas ranges from (0.6 to 6): (2 to 15): 1; The second process gas also includes a dilution gas, which is a rare gas; In the second process gas, the volume ratio of the first reaction gas, the fluorocarbon gas, and the dilution gas is in the range of (2-25):1:(2-20).

2. The etching method for doped polycrystalline silicon according to claim 1, characterized in that, The proportion of the first reactive gas in the second process gas is greater than the proportion of the carbon-fluorine gas.

3. The etching method for doped polycrystalline silicon according to claim 1, characterized in that, The fluorocarbon gas includes at least one or more of CF4, C4F6, or C4F8.

4. The etching method for doped polycrystalline silicon according to claim 1, characterized in that, The flow rate of the fluorine-containing gas is in the range of 30 sccm to 60 sccm; The flow rate of the chlorine-containing gas is in the range of 100 sccm to 150 sccm; The flow rate of the fluorocarbon gas is in the range of 10 sccm to 50 sccm.

5. The etching method for doped polycrystalline silicon according to claim 1, characterized in that, The first process gas includes fluorocarbon gases; the fluorocarbon gases include at least CF4.

6. The etching method for doped polycrystalline silicon according to any one of claims 1 to 5, characterized in that, Following the main etching step, the etching method further includes: Following the etching step, a third process gas is used to continue etching the doped polysilicon until the target etching depth is reached.

7. The etching method for doped polycrystalline silicon according to claim 6, characterized in that, The third process gas includes at least a bromine-containing gas and a diluent gas, wherein the diluent gas is a rare gas.

8. A method for forming a semiconductor device, characterized in that, include: Provide a base; A dielectric layer is formed on the surface of the substrate; A doped polysilicon layer is formed on the surface of the dielectric layer using the etching method of any one of claims 1 to 7.

9. A semiconductor device, characterized in that, The semiconductor device is prepared using the semiconductor device formation method as described in claim 8.

10. A semiconductor process apparatus, characterized in that, The device includes a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory, in which a computer program is stored. When the computer program is executed by the processor, it implements the etching method for doped polycrystalline silicon as described in any one of claims 1 to 7, or the semiconductor device formation method as described in claim 8.

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