Method of manufacturing a metal via and semiconductor structure

Abstract

The application discloses a manufacturing method of a metal via and a semiconductor structure. The method comprises the following steps: performing a first plasma etching process with a mask to periodically and cyclically etch a substrate surface to form a first via; performing a second plasma etching process without a mask to etch the first via into a second via, wherein the second plasma etching process comprises a first etching stage, a second etching stage and a third etching stage in sequence, the first etching stage is used for forming a side wall notch at the top of the first via, the second etching stage is used for smoothing the top profile and the side wall, and the third etching stage is used for forming the second via with a larger width and a smaller side wall inclination angle than the first via; and filling the formed second via into a metal via. The application can manufacture a via with a smaller inclination angle, avoid incomplete filling defects, and meet the requirements of high-performance devices in electrical connection and heat dissipation.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and in particular to a method for manufacturing a metal through-hole and a semiconductor structure. Background Technology

[0002] With the development of electronic devices, especially in high-performance integrated circuits, microelectromechanical systems (MEMS), image sensors, and power electronic devices, the application of silicon-based materials is becoming increasingly widespread. Through-hole (via) technology plays a crucial role in these devices, enabling electrical connections between multilayer circuits, thermal management, and optical conduction. To improve device performance, especially in high-power and high-density integrated circuits, higher requirements are placed on the structure and filling effect of vias.

[0003] Currently, most traditional deep silicon etching methods for through-holes employ a vertical hole wall design. However, with the miniaturization of critical device dimensions and the increase in aspect ratio, this design may suffer from problems such as incomplete filling, poor heat dissipation, and unstable electrical connections in some applications. Therefore, it is necessary to research a new method for manufacturing metal through-holes to overcome the aforementioned shortcomings of existing technologies while meeting high-performance requirements. Summary of the Invention

[0004] The purpose of this application is to overcome the above-mentioned problems in the prior art and provide a method for manufacturing metal through-holes and a semiconductor structure that can meet the high performance requirements while overcoming the problems of incomplete filling, poor heat dissipation performance and unstable electrical connection in the prior art.

[0005] To achieve the above objectives, the technical solution of this application is as follows:

[0006] According to a first aspect of this application, embodiments of this application provide a method for manufacturing a metal through-hole, comprising:

[0007] A masked first plasma etching process is performed to periodically etch one side surface of the substrate to form a first via in the substrate. The first via has a first aperture width and a first sidewall tilt angle.

[0008] A maskless second plasma etching process is performed to etch the sidewalls of the first via into a second via. The second plasma etching process includes a first etching stage, a second etching stage, and a third etching stage connected in sequence. The first etching stage uses a first etching gas and a first pressure to form a sidewall notch at the top of the first via. The second etching stage uses a second etching gas and a second pressure to round the top morphology at the sidewall notch and smooth the sidewalls of the first via. The third etching stage uses a third etching gas and a third pressure to form a second via with a second aperture width and a second sidewall tilt angle. The second aperture width is greater than the first aperture width, and the second sidewall tilt angle is less than the first sidewall tilt angle. The first etching gas, the second etching gas, and the third etching gas are all different, and the first pressure, the second pressure, and the third pressure increase sequentially.

[0009] The second through hole is filled with metal to form a metal through hole.

[0010] In some embodiments, the sidewall notch has a third sidewall tilt angle, which is smaller than the second sidewall tilt angle.

[0011] In some embodiments, the sidewall of the first through hole has a first roughness, and the sidewall of the second through hole has a second roughness. When performing the second etching stage, the second roughness is made smaller than the first roughness by rounding the top morphology at the sidewall notch and smoothing the sidewall of the first through hole.

[0012] In some embodiments, the first etching gas includes an oxidizing gas.

[0013] In some embodiments, the second etching gas includes oxidizing gases and fluorocarbon gases.

[0014] In some embodiments, the third etching gas includes sulfur-fluorine gases and carbon-fluorine gases.

[0015] In some embodiments, the first pressure is 8 mtorr to 50 mtorr.

[0016] In some embodiments, the second pressure is 10 mtorr to 100 mtorr.

[0017] In some embodiments, the third pressure is 110 mtorr to 200 mtorr.

[0018] In some embodiments, when performing the first etching stage, the bias power is 10W to 100W and the time is 3s to 12s.

[0019] In some embodiments, when performing the second etching stage, the bias power is 0W to 90W and the time is 3s to 12s.

[0020] In some embodiments, when performing the third etching stage, the bias power is 0W to 100W and the time is 5s to 100s.

[0021] In some embodiments, the first etching gas includes O2 and has a flow rate of 1 sccm to 200 sccm.

[0022] In some embodiments, the second etching gas includes O2 and CF4, wherein the flow rate of O2 is 1 sccm to 200 sccm and the flow rate of CF4 is 1 sccm to 150 sccm.

[0023] In some embodiments, the third etching gas includes SF6 and C4F8, with the flow rate of SF6 being 1 sccm to 200 sccm and the flow rate of C4F8 being 1 sccm to 200 sccm.

[0024] In some embodiments, the tilt angle of the first sidewall is 88 to 89 degrees.

[0025] In some embodiments, the tilt angle of the second sidewall is 80 degrees to 87 degrees.

[0026] In some embodiments, the inclination angle of the third sidewall is 4 degrees to 20 degrees.

[0027] In some embodiments, the substrate material includes silicon.

[0028] In some embodiments, the metal filling the second through-hole includes copper or tungsten.

[0029] In some embodiments, the first plasma etching process includes a periodic cycle step consisting of a deposition step and an etching step, wherein the process gas used in the deposition step includes C4F8 and the process gas used in the etching step includes SF6, and the first via is formed by alternating the deposition of a passivation layer using C4F8 and the etching using SF6.

[0030] In some embodiments, the second through hole has a sidewall morphology that curves inward from top to bottom.

[0031] According to a second aspect of this application, embodiments of this application also provide a semiconductor structure containing a metal via, the metal via being obtained using a metal via manufacturing method as provided in any of the embodiments of the first aspect above.

[0032] The embodiments of this application may have, or at least have, the following advantages:

[0033] (1) This application forms a through-hole (second through-hole) structure with the required tilt angle (second sidewall tilt angle) by performing a first plasma etching process and a second plasma etching process in stages. The first plasma etching process can be used to achieve precise attainment of the through-hole depth, ensuring the stability and uniformity of the etching depth, while ensuring a reasonable balance between the etching rate and selectivity, avoiding the problem of uneven depth and width, and providing a stable benchmark for subsequent processes. On this basis, the second plasma etching process is used, and further subdivided into three interconnected stages (first... The etching process, consisting of three stages (first, second, and third), effectively improves the smoothness of the via top, ensures the absence of sharp angles at the opening, and repairs the roughness of the sidewalls to achieve ideal surface quality. It also enables the fabrication of vias with smaller tilt angles (inverted trapezoidal or flared second vias), thereby overcoming the shortcomings of traditional single etching processes in fabricating tilted vias (such as large wall roughness and top morphology defects). This provides greater flexibility and precision, thus meeting the requirements for via tilt angles in different applications and satisfying the electrical connectivity and heat dissipation needs of high-performance devices.

[0034] (2) This application provides a complete set of efficient manufacturing processes for tapered through holes with tilt angles, which solves the challenges in depth, morphology, tilt angle and other aspects. This allows for better control of the filling effect during the metal filling process through the improved second through hole etching structure, avoiding defects such as incomplete filling (e.g., voids), and significantly improving the performance and reliability of the filled metal through holes.

[0035] (3) This application not only overcomes the limitation that traditional single etching process cannot achieve high-precision control, but also provides a more refined and controllable metal through-hole etching solution for the manufacturing of high-performance devices.

[0036] Other advantages of this application will be described in the following detailed description. Attached Figure Description

[0037] Figure 1 This is a flowchart of a method for manufacturing a metal through hole according to a preferred embodiment of this application.

[0038] Figure 2 This is a schematic diagram of the structure after a mask is formed on a substrate, according to a preferred embodiment of this application.

[0039] Figure 3 This is a schematic diagram of the structure after a first through-hole is formed on a substrate, according to a preferred embodiment of this application.

[0040] Figure 4 This is a schematic diagram of the structure after removing the mask, provided as a preferred embodiment of this application.

[0041] Figure 5 This is a schematic diagram of a structure after a sidewall notch is formed at the top of the first through hole, according to a preferred embodiment of this application.

[0042] Figure 6 This is a schematic diagram of a preferred embodiment of the present application, showing the structure after the top morphology of the sidewall notch is rounded and the sidewall of the first through hole is smoothed.

[0043] Figure 7 This is a schematic diagram of the structure after a second via is formed on a substrate, according to a preferred embodiment of this application.

[0044] Figure 8 This is a schematic diagram of a structure after forming a metal via on a substrate, according to a preferred embodiment of this application.

[0045] Figure 9 This is an electron microscope schematic diagram of a second through hole provided in a preferred embodiment of this application.

[0046] Figure 10 This is an electron microscope schematic diagram of a conventional through-hole A provided for comparative example 1.

[0047] Figure 11 This is a schematic diagram of a conventional through-hole B provided for Comparative Example 2.

[0048] In the figure: 10. Substrate; 11. Mask; 12. Opening; 13. First through-hole; 14. Scallop pattern; 15. Sidewall notch; 16. Second through-hole; 17. Metal through-hole. Detailed Implementation

[0049] To address the problems of incomplete hole filling, poor heat dissipation, and unstable electrical connection in vertical through-holes manufactured using traditional processes, embodiments of this application provide a method for manufacturing metal through-holes, including:

[0050] A masked first plasma etching process is performed to periodically etch one side surface of the substrate to form a first via in the substrate. The first via has a first aperture width and a first sidewall tilt angle.

[0051] A maskless second plasma etching process is performed to etch the sidewalls of the first via into a second via. The second plasma etching process includes a first etching stage, a second etching stage, and a third etching stage connected in sequence. The first etching stage uses a first etching gas and a first pressure to form a sidewall notch at the top of the first via. The second etching stage uses a second etching gas and a second pressure to round the top morphology at the sidewall notch and smooth the sidewalls of the first via. The third etching stage uses a third etching gas and a third pressure to form a second via with a second aperture width and a second sidewall tilt angle. The second aperture width is greater than the first aperture width, and the second sidewall tilt angle is less than the first sidewall tilt angle. The first etching gas, the second etching gas, and the third etching gas are all different, and the first pressure, the second pressure, and the third pressure increase sequentially.

[0052] The second through hole is filled with metal to form a metal through hole.

[0053] The through-hole (second through-hole) manufactured through the embodiments of this application has a specific tilt angle, providing greater flexibility and precision. Furthermore, the improved etching process controls the smoothness of the top wall and the roughness of the sidewalls, enabling it to meet the electrical connection and thermal management requirements in high-performance electronic devices. The embodiments of this application not only overcome the limitations of traditional single etching processes, solving challenges related to depth, morphology, and tilt angle, but also provide a more refined and controllable etching scheme for the manufacture of high-performance devices, significantly improving the performance and reliability of metal through-holes.

[0054] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0055] refer to Figure 1 This application provides a method for manufacturing a metal through-hole, which includes the following steps:

[0056] Step S11: Provide a substrate.

[0057] refer to Figure 2 In some embodiments, the material of substrate 10 includes silicon, i.e., substrate 10 is a silicon substrate.

[0058] In some embodiments, a silicon wafer may be used as substrate 10 to further form the desired etched structure of vias on substrate 10.

[0059] In some embodiments, the silicon wafer may be doped to provide a substrate 10 that meets the required electrical properties.

[0060] In some embodiments, an integrated circuit, such as a transistor structure, may be fabricated on the substrate 10 to achieve the desired vertical interconnection by filling the metal via formed by the via (second via) with metal.

[0061] Step S12: Form multiple masks on the surface of the substrate.

[0062] refer to Figure 2 In some embodiments, a photoresist layer is spin-coated onto the upper surface of the substrate 10 as a mask layer. A photolithography process is then used to etch the photoresist layer, forming multiple photoresist patterns on the upper surface of the substrate 10, which serve as masks 11. An opening 12, acting as an etching window, is provided between any two adjacent masks 11.

[0063] It should be noted that, Figure 2 The diagram only schematically illustrates the case where three masks 11 are formed on the upper surface of the substrate 10. However, it is understood that other different numbers of masks, such as two masks, four masks, five masks, ten masks, etc., can be formed on the upper surface of the substrate 10, and are not limited to this.

[0064] Step S13: Perform the first plasma etching process and, through a mask, periodically etch the exposed surface of the substrate to form the first via in the substrate.

[0065] refer to Figure 3 In some embodiments, during the first plasma etching process, the upper surface of the substrate 10 exposed within the opening 12 is periodically etched downwards using the mask 11 formed in the previous step to form a first via 13 located in the substrate 10 on the upper surface of the substrate 10 exposed within the opening 12. That is, this step is a masked first plasma etching process that etches downwards onto the upper surface of the substrate 10 exposed within the opening 12 to form the first via 13.

[0066] In some embodiments, before performing the first plasma etching process, the substrate 10 is further pre-etched to open the upper surface of the substrate 10. That is, the bottom of the opening 12 is pre-etched downwards using the mask 11 formed in the previous step to expose the upper surface of the substrate 10 located at the bottom of the opening 12, so that when the first plasma etching process is subsequently performed, the upper surface of the substrate 10 exposed within the opening 12 can be periodically etched downwards.

[0067] In some embodiments, the first plasma etching process includes a periodic cyclic step consisting of a deposition step and an etching step. That is, each cyclic step includes a deposition step and an etching step, which are repeated to form a periodic cyclic etching. The deposition step is used to form a passivation layer (polymer) that protects the sidewalls and the mask 11. In the deposition step, the passivation layer is deposited on the inner wall of the first via 13 being formed and on the surface of the mask 11. The etching step is used to first etch open the passivation layer at the bottom of the first via 13 being formed, and then continue etching downwards into the substrate 10 to a unit depth. During the etching step, the passivation layer on the sidewall of the first via 13 and the surface of the mask 11 is also etched away. In the next deposition cycle, the passivation layer is deposited again on the inner wall of the first via 13 and the surface of the mask 11, thus providing continuous protection for the sidewall and the mask 11. The etching step in this cycle will then etch open the new passivation layer at the bottom of the first via 13 and continue etching downwards to a unit depth into the substrate 10. By repeatedly performing the above process and cyclically etching the substrate 10, a first via 13 of a predetermined depth and perpendicular (or substantially perpendicular) can be formed in the substrate 10.

[0068] It should be noted that during the first plasma etching process, the etching step in each cycle is performed isotropically on the substrate 10. Due to repeated passivation deposition, periodic ripples resembling scallops (i.e., scallop patterns 14) inevitably form on the sidewalls, increasing the roughness of the sidewalls and thus affecting the metal filling quality. Therefore, this can be improved through subsequent steps.

[0069] The first through-hole 13 formed by performing the first plasma etching process has a first roughness on its sidewalls.

[0070] The first through-hole 13 formed by performing a first plasma etching process has a first orifice width m and a first sidewall inclination angle. The first orifice width m is the width of the top orifice of the first through-hole 13. The first sidewall inclination angle is a first included angle α between the sidewall of the first through-hole 13 and the cross-sectional direction (horizontal direction) of the first through-hole 13 in the outward direction.

[0071] In some embodiments, when performing the first plasma etching process, the process gas used in the deposition step includes C4F8, and the process gas used in the etching step includes SF6. By alternately using C4F8 to deposit a passivation layer and using SF6 for etching, a first through-hole 13 having a first orifice width m, a first sidewall tilt angle, and a first sidewall roughness is formed.

[0072] In some embodiments, when performing the first plasma etching process, the flow rate of C4F8 used in the deposition step is 1 sccm to 1000 sccm. For example, the flow rate can be 1 sccm, 5 sccm, 10 sccm, 50 sccm, 100 sccm, 500 sccm, 700 sccm, or 1000 sccm, or any value between any two of the aforementioned flow rate values. Furthermore, the flow rate range is not limited to this.

[0073] In some embodiments, when performing the first plasma etching process, the flow rate of SF6 used in the etching step is 1 sccm to 1000 sccm. For example, the flow rate can be 1 sccm, 4 sccm, 8 sccm, 20 sccm, 60 sccm, 100 sccm, 500 sccm, or 1000 sccm, or any value between any two of the aforementioned flow rate values. Furthermore, the flow rate range is not limited to this.

[0074] In some embodiments, an inert gas may be used as a carrier gas when performing the first plasma etching process. For example, argon (Ar) may be used as the carrier gas at a flow rate of 1 sccm to 500 sccm. For example, the flow rate may be 1 sccm, 3 sccm, 6 sccm, 15 sccm, 40 sccm, 90 sccm, 200 sccm, or 500 sccm, or any value between any two of the aforementioned flow rates. Furthermore, the flow rate range is not limited to these values.

[0075] In some embodiments, the temperature during the first plasma etching process is between 10°C and 60°C. For example, the temperature can be 10°C, 10.1°C, 11°C, 22°C, 28°C, 35°C, 36°C, 44°C, 49°C, 59°C, or 60°C, or any value between any two of the aforementioned temperature values. The temperature range is not limited to this.

[0076] In some embodiments, the pressure during the first plasma etching process is 1 mtorr to 100 mtorr. For example, the pressure can be 1 mtorr, 1.2 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 25 mtorr, 30 mtorr, 50 mtorr, 80 mtorr, or 100 mtorr, or any value between any two of the aforementioned pressure values. Furthermore, the pressure range is not limited to this.

[0077] In some embodiments, when performing the first plasma etching process, the source power is 100W to 3000W. For example, the source power can be 100W, 200W, 500W, 800W, 1000W, 1500W, 2000W, 2500W, or 3000W, or any value between any two of the aforementioned source power values. Furthermore, the source power range is not limited to this.

[0078] In some embodiments, when performing the first plasma etching process, the bias power is 10W to 200W. For example, the bias power can be 10W, 20W, 30W, 50W, 80W, 100W, 130W, 150W, 190W, or 200W, or any value between any two of the aforementioned bias power values. Furthermore, the bias power range is not limited to this.

[0079] In some embodiments, during the first plasma etching process, while ensuring a balance between the deposition and etching steps, the lateral etching amount on the substrate 10 is gradually reduced in each cycle, resulting in an overall tapered hole shape in the etched morphology. This etching method can also reduce the protrusion of the sidewall scalloped texture 14 to some extent, making the sidewall surface relatively smooth. The amount of lateral etching can be controlled by adjusting the etching step time in each cycle.

[0080] In some embodiments, the inclination angle of the first sidewall of the first through hole 13 is 88 to 89 degrees. However, it is not limited to this (it may be slightly less than 88 degrees or slightly greater than 89 degrees).

[0081] In some embodiments, the first roughness of the sidewall of the first through hole 13 is about 30 nm to 50 nm. However, it is not limited to this.

[0082] In some embodiments, the aspect ratio of the first through hole 13 is 3:1 or more, or 5:1 or more, or 10:1 or more. However, it is not limited to these.

[0083] Step S14: Remove the mask.

[0084] refer to Figure 4 In some embodiments, a dry ashing process is used to remove the photoresist, that is, to completely remove the photoresist pattern that serves as the mask 11. After removing the photoresist pattern (mask 11), the entire upper surface of the substrate 10 will be completely exposed, that is, the upper surface of the substrate 10 on both sides of the first via 13 will no longer be protected by the mask 11.

[0085] In some embodiments, when the photoresist pattern used as mask 11 is removed by a dry ashing process, the process gas used includes at least one of O2, a mixture of H2 and N2, N2, etc., but is not limited to this.

[0086] Step S15: Perform a second plasma etching process to etch the sidewall of the first through hole, and etch the first through hole into a second through hole, so that the second through hole has a sidewall tilt angle smaller than that of the first through hole.

[0087] In some embodiments, the sidewalls of the first via 13 are etched by performing a second plasma etching process, different from the periodic cyclic etching of the first plasma etching process, to etch the first via 13 having a first sidewall tilt angle into a second via 13 having a second sidewall tilt angle, such that the second via 13 has a smaller sidewall tilt angle than the first via 13. In other words, the second via 16 has a sidewall that is more tilted relative to the vertical direction (etching direction) than the first via 13. Figure 7 As shown. The inclination angle of the second sidewall is a second included angle β between the sidewall of the second through hole 16 and the cross-sectional direction (horizontal direction) of the second through hole 16, pointing outward. In this example, both the first included angle α and the second included angle β are acute angles, and the second included angle β is smaller than the first included angle α.

[0088] Unlike the periodic cyclic etching process of the first plasma etching process, the second plasma etching process only includes its own etching steps and does not contain the deposition steps found in the first plasma etching process. In other words, the second plasma etching process is a non-periodic cyclic etching process.

[0089] In some embodiments, since the mask 11 in the previous step has been completely removed, the second plasma etching process in this step is an etching of the upper surface of the substrate 10 without any mask 11 on the upper surface of the substrate 10, that is, a second plasma etching process without mask 11 is performed.

[0090] In some embodiments, the second plasma etching process includes a first etching stage, a second etching stage, and a third etching stage connected in sequence. The first etching stage uses a first etching gas and a first pressure to... Figure 5 The top of the first through-hole 13 shown has a sidewall notch 15 (equivalent to a chamfer). The second etching stage uses a second etching gas and a second pressure to round the top morphology at the sidewall notch 15 of the first through-hole 13 and to smooth the sidewall of the first through-hole 13 (see reference). Figure 6 The third etching stage uses a third etching gas and a third pressure to form a second through-hole 16 with a second orifice width n and a second sidewall inclination angle (see reference). Figure 7 ).

[0091] In some embodiments, the second opening width n of the second through hole 16 is greater than the first opening width m of the first through hole 13, and the inclination angle of the second sidewall of the second through hole 16 is less than the inclination angle of the first sidewall of the first through hole 13 (the second included angle β is less than the first included angle α).

[0092] In some embodiments, the first etching gas, the second etching gas, and the third etching gas are different.

[0093] In some embodiments, the first pressure, the second pressure, and the third pressure increase sequentially.

[0094] refer to Figure 5 In some embodiments, when performing the first etching stage of the second plasma etching process, the first etching gas used includes an oxidizing gas. For example, the first etching gas includes O2, and an inert gas, such as Ar, can be used as a dilution and dissociation gas to etch the formed first via 13 without any mask, and to form a sidewall notch 15 with a certain tilt angle on the top of the first via 13.

[0095] In some embodiments, when performing the first etching stage, the flow rate of O2 as the first etching gas is 1 sccm to 200 sccm. For example, the flow rate can be 1 sccm, 2 sccm, 5 sccm, 10 sccm, 50 sccm, 100 sccm, 150 sccm, or 200 sccm, or any value between any two of the aforementioned flow rate values. Furthermore, the flow rate range is not limited to this.

[0096] In some embodiments, the temperature during the first etching stage is between 10°C and 60°C. For example, the temperature can be 10°C, 11°C, 15°C, 20°C, 25°C, 30°C, 40°C, 45°C, 50°C, or 60°C, or any value between any two of the aforementioned temperature values. The temperature range is not limited to this.

[0097] In some embodiments, when performing the first etching stage, the first pressure is 8 mtorr to 50 mtorr. For example, the first pressure can be 8 mtorr, 10 mtorr, 15 mtorr, 20 mtorr, 25 mtorr, 30 mtorr, 40 mtorr, or 50 mtorr, or any value between any two of the aforementioned pressure values. Furthermore, the range of the first pressure is not limited to this.

[0098] In some embodiments, when performing the first etching stage, the source power is 100W to 3000W. For example, the source power can be 100W, 200W, 500W, 800W, 1000W, 1500W, 2000W, 2500W, or 3000W, or any value between any two of the aforementioned source power values. Furthermore, the source power range is not limited to this.

[0099] In some embodiments, when performing the first etching stage, the bias power is 10W to 100W. For example, the bias power can be 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W, or 100W, or any value between any two of the aforementioned bias power values. Furthermore, the bias power range is not limited to this.

[0100] In some embodiments, the etching time for the first etching stage is 3s to 12s. For example, the time can be 3s, 4s, 5s, 6s, 7s, 8s, 9s, 10s, 11s, or 12s, or any value between any two of the aforementioned time values. The time range is not limited to this.

[0101] After the first etching stage is performed, a first through-hole 13 with a top sidewall notch 15 is formed, i.e., a first transition through-hole structure is formed, such as... Figure 5 As shown.

[0102] In some embodiments, the sidewall notch 15 has a third sidewall inclination angle, which is a third included angle θ (i.e., a downward inclination angle of the sidewall notch 15) between the sidewall (incline) at the notch and the cross-sectional direction (horizontal direction) of the first through hole 13 in the outward direction. The third included angle θ is an acute angle, and the third included angle θ is less than the second included angle β and the first included angle α, that is, the third sidewall inclination angle is less than the second sidewall inclination angle and the first sidewall inclination angle.

[0103] In some embodiments, the tilt angle of the third sidewall (the third included angle θ) is 4 degrees to 20 degrees. For example, the tilt angle of the third sidewall can be 4 degrees, 5 degrees, 6 degrees, 7 degrees, 8 degrees, 9 degrees, 10 degrees, 11 degrees, 12 degrees, 13 degrees, 14 degrees, 15 degrees, 16 degrees, 17 degrees, 18 degrees, 19 degrees, or 20 degrees, or any value between any two of the aforementioned angle values. Furthermore, the range of the tilt angle of the third sidewall is not limited to this.

[0104] In some embodiments, during the etching process of the first etching stage, the tilt angle of the third sidewall can be controlled by adjusting the magnitude of the bias power, based on the use of a first pressure. Furthermore, the magnitude of the bias power is proportional to the magnitude of the tilt angle of the third sidewall.

[0105] The purpose of forming a sidewall notch 15 at the top of the first through hole 13 is to provide a transitional basic structure for the subsequent formation of a second through hole 16 with a smaller sidewall inclination angle. That is, by pre-forming a sidewall notch 15 with a certain inclination angle at the top of the first through hole 13, the opening width at the top of the first through hole 13 is enlarged, forming an etching guide structure. This sidewall notch 15 can be used as a guide structure for subsequent etching to proceed downwards, thereby further obtaining a sidewall morphology with a certain inclination angle.

[0106] Because the formed sidewall notch 15 has a sharp chamfered step shape, in order to prevent this step shape from propagating downwards and affecting the smoothness of the sidewall, the top shape of the first through hole 13 at the sidewall notch 15 needs to be rounded. Furthermore, because the first plasma etching process forms periodic scalloped patterns 14 on the sidewall of the first through hole 13, resulting in high sidewall roughness, it also needs to be smoothed to prevent affecting the smoothness of the sidewall when forming the second through hole 16.

[0107] In some embodiments, by performing etching in the second etching stage of the second plasma etching process, and using a second etching gas and a second pressure, the top morphology at the sidewall notch 15 of the first through hole 13 is rounded, and the sidewall of the first through hole 13 is modified to make the sidewall of the first through hole 13 smooth.

[0108] refer to Figure 6 In some embodiments, when performing the second etching stage of the second plasma etching process, the second etching gas used includes oxidizing gases and fluorocarbon gases. For example, the second etching gas includes O2 and CF4, and inert gases, such as Ar, can be used as dilution and dissociation gases. Similarly, without a mask, the first through-hole 13 with the formed sidewall notch 15 is further etched to eliminate the sharp step morphology of the sidewall notch 15, making the top morphology of the sidewall notch 15 of the first through-hole 13 rounded. At the same time, the etching also modifies the sidewall of the first through-hole 13, eliminating the scalloped texture 14 on the sidewall, and smoothing the original rough sidewall of the first through-hole 13.

[0109] Compared to the first etching stage, when performing the second etching stage, CF4 is added to the O2 and the second pressure is increased to improve the isotropic etching capability of the reaction. At the same time, the sidewall damage can be reduced by correspondingly reducing the bias power.

[0110] In some embodiments, during the second etching stage, the flow rate of O2 is 1 sccm to 200 sccm, and the flow rate of CF4 is 1 sccm to 150 sccm. For example, the flow rate of O2 can be 1 sccm, 2 sccm, 5 sccm, 10 sccm, 50 sccm, 100 sccm, 150 sccm, or 200 sccm, or any value between any two of the aforementioned flow rate values ​​of O2; the flow rate of CF4 can be 1 sccm, 2 sccm, 4 sccm, 8 sccm, 10 sccm, 20 sccm, 50 sccm, 100 sccm, or 150 sccm, or any value between any two of the aforementioned flow rate values ​​of CF4. Furthermore, the flow rate ranges of O2 and CF4 are not limited to these.

[0111] In some embodiments, the temperature during the second etching stage is between 10°C and 60°C. For example, the temperature can be 10°C, 11°C, 15°C, 20°C, 25°C, 30°C, 40°C, 45°C, 50°C, or 60°C, or any value between any two of the aforementioned temperature values. The temperature range is not limited to this.

[0112] In some embodiments, when performing the second etching stage, the second pressure is 10 mtorr to 100 mtorr. For example, the second pressure can be 10 mtorr, 20 mtorr, 30 mtorr, 35 mtorr, 50 mtorr, 70 mtorr, 80 mtorr, or 100 mtorr, or any value between any two of the aforementioned pressure values. Furthermore, the range of the second pressure is not limited to this.

[0113] In some embodiments, when performing the second etching stage, the source power is 100W to 3000W. For example, the source power can be 100W, 200W, 500W, 800W, 1000W, 1500W, 2000W, 2500W, or 3000W, or any value between any two of the aforementioned source power values. Furthermore, the source power range is not limited to this.

[0114] In some embodiments, when performing the second etching stage, the bias power is 0W to 90W. For example, the bias power can be 0W, 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, or 90W, or any value between any two of the aforementioned bias power values. Furthermore, the bias power range is not limited to this.

[0115] In some embodiments, the etching time for performing the second etching stage is 3s to 12s. For example, the time can be 3s, 4s, 5s, 6s, 7s, 8s, 9s, 10s, 11s, or 12s, or any value between any two of the aforementioned time values. Moreover, the time range is not limited to this.

[0116] After the second etching stage, the surface of the sidewall notch 15 at the top of the first through-hole 13 becomes rounded, thus smoothing the entire top morphology at the sidewall notch 15. Simultaneously, the second etching stage acts on the sidewall surface of the first through-hole 13, eliminating (or essentially eliminating) the original periodic scalloped patterns 14 on the sidewall, making the sidewall smoother, thereby reducing sidewall roughness and improving sidewall smoothness. After the second etching stage, the sidewall roughness of the first through-hole 13 can be reduced to approximately 9nm to 22nm from the first roughness. Furthermore, the width of the top opening of the first through-hole 13 is further expanded based on the width formed by the sidewall notch 15.

[0117] After the second etching stage, the structure of the first through-hole 13 with a rounded top morphology and smoothed sidewalls at the sidewall notch 15 is formed, thus forming the second transition through-hole structure, as shown below. Figure 6 As shown.

[0118] By performing the second etching stage, the top morphology at the sidewall notch 15 is rounded, the sidewall of the first through hole 13 is smoothed, and the top opening width of the first through hole 13 is further enlarged, thus laying the foundation for forming the second through hole 16 with a specific inclined sidewall morphology by performing the second etching stage.

[0119] refer to Figure 7 In some embodiments, etching is performed in the third etching stage of the second plasma etching process, using a third etching gas and a third pressure to form a second through-hole 16 having a second orifice width n and a second sidewall inclination angle. The second through-hole 16 has a sidewall morphology that slopes inward from top to bottom and transitions smoothly. That is, the top orifice width (second orifice width n) of the second through-hole 16 is greater than the bottom orifice width, and the aperture gradually decreases from top to bottom, forming an approximately trumpet-shaped second through-hole 16 that is larger at the top and smaller at the bottom.

[0120] In some embodiments, the second through hole 16 has an open shape and its sidewalls bulge outwards inwards, such as... Figure 7 As shown.

[0121] In some embodiments, when performing the third etching stage of the second plasma etching process, the third etching gas used includes sulfur-fluorine gases and carbon-fluorine gases. For example, the third etching gas includes SF6 and C4F8, and inert gases, such as Ar, can be used as dilution and dissociation gases. Similarly, without a mask, the first through-hole 13 (second transition through-hole structure) after the top morphology rounding and sidewall smoothing treatment at the sidewall notch 15 is etched to further increase the top aperture width and form a more inclined sidewall, that is, to further reduce the sidewall inclination angle.

[0122] In some embodiments, when performing the third etching stage of the second plasma etching process, the third etching gas includes SF6, C4F8 and O2. By adding an appropriate amount of O2, the polymer-forming ability of C4F8 can be controlled to avoid excessive polymer production that could affect the etching effect.

[0123] Compared to the second etching stage, the third etching stage requires a higher third pressure to widen the top aperture and create a more inclined sidewall angle. This intensifies isotropic etching during the reaction, resulting in an open, curved morphology. Simultaneously, using a third etching gas reduces the etching rate, preventing over-etching. Furthermore, the bottom width of the second via 16 can be maintained by adjusting the bias power (relatively increasing the bias power reduces the tendency for the bottom width to expand).

[0124] In some embodiments, during the third etching stage, the flow rate of SF6 is 1 sccm to 200 sccm, and the flow rate of C4F8 is 1 sccm to 200 sccm. For example, the flow rate of SF6 can be 1 sccm, 2 sccm, 5 sccm, 10 sccm, 50 sccm, 100 sccm, 150 sccm, or 200 sccm, or any value between any two of the aforementioned flow rate values ​​for SF6; the flow rate of C4F8 can be 1 sccm, 2 sccm, 5 sccm, 10 sccm, 50 sccm, 100 sccm, 150 sccm, or 200 sccm, or any value between any two of the aforementioned flow rate values ​​for C4F8. Furthermore, the flow rate ranges of SF6 and C4F8 are not limited to these values.

[0125] In some embodiments, the temperature during the third etching stage is between 10°C and 60°C. For example, the temperature can be 10°C, 11°C, 15°C, 20°C, 25°C, 30°C, 40°C, 45°C, 50°C, or 60°C, or any value between any two of the aforementioned temperature values. The temperature range is not limited to this.

[0126] In some embodiments, when performing the third etching stage, the third pressure is 110 mtorr to 200 mtorr. For example, the third pressure can be 110 mtorr, 120 mtorr, 130 mtorr, 135 mtorr, 150 mtorr, 170 mtorr, 180 mtorr, or 200 mtorr, or any value between any two of the aforementioned pressure values. Furthermore, the range of the third pressure is not limited to this.

[0127] In some embodiments, when performing the third etching stage, the source power is 100W to 3000W. For example, the source power can be 100W, 200W, 500W, 800W, 1000W, 1500W, 2000W, 2500W, or 3000W, or any value between any two of the aforementioned source power values. Furthermore, the source power range is not limited to this.

[0128] In some embodiments, when performing the third etching stage, the bias power is 0W to 100W. For example, the bias power can be 0W, 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W, or 100W, or any value between any two of the aforementioned bias power values. Furthermore, the bias power range is not limited to this.

[0129] In some embodiments, the etching time for the third etching stage is 5s to 100s. For example, the time can be 5s, 10s, 15s, 20s, 30s, 40s, 50s, 65s, 80s, or 100s, or any value between any two of the aforementioned time values. The time range is not limited to this.

[0130] In some embodiments, the inclination angle of the second sidewall is 80 to 87 degrees. However, it is not limited to this.

[0131] In some embodiments, the sidewall of the second through hole 16 has a second roughness. By performing the etching in the second etching stage, the top morphology at the sidewall notch 15 is rounded and the sidewall of the first through hole 13 is smoothed, reducing the original sidewall roughness of the first through hole 13. As a result, after performing the etching in the third etching stage, the second roughness of the sidewall of the second through hole 16 is also reduced accordingly, thereby making the second roughness less than the original first roughness of the first through hole 13.

[0132] After the third etching stage, the second through-hole 16 structure is formed, as shown below. Figure 7 As shown. With Figure 4 or Figure 3As can be seen, after the third etching stage, the top opening width (second opening width n) of the second through-hole 16 is further increased. This makes the final second opening width n of the second through-hole 16 significantly larger than the first opening width m of the first through-hole 13. Furthermore, the resulting second through-hole 16 has more inclined sidewalls, and its second sidewall inclination angle is smaller than the first sidewall inclination angle of the first through-hole 13 (the second included angle β is smaller than the first included angle α). Moreover, the smooth sidewall morphology formed after the second etching stage is continued in the third etching stage, resulting in a similarly smooth sidewall morphology for the second through-hole 16. Therefore, this improves the quality of subsequent metal filling and effectively prevents the formation of voids.

[0133] Step S16: Fill the second through hole with metal to form a metal through hole.

[0134] refer to Figure 8 In some embodiments, a metal deposition process is used to fill the second via 16 with metal, and excess metal material on the upper surface of the substrate 10 is removed by a planarization process (e.g., chemical mechanical polishing) to form a metal via 17 with a flat top.

[0135] During the metal filling process, the improved etching structure of the second through-hole 16 allows for better control of the filling effect, avoids incomplete filling defects, and enables the resulting metal through-hole 17 to meet the requirements of high-performance devices for electrical connection and heat dissipation, thereby improving the stability and performance of the device.

[0136] In some embodiments, when the second through hole 16 is filled with metal, the filling metal includes copper or tungsten, etc. However, it is not limited to this.

[0137] Further steps required for chip manufacturing can then be performed, which will not be elaborated upon here.

[0138] Figure 10 The image shows the structure of a conventional via A formed in a substrate using a conventional periodic dry etching process. This conventional via A is a vertical via with a sidewall tilt angle of approximately 89 degrees. Figure 10 Marker 1 indicates a top width of 36.215 micrometers in the X direction, Marker 2 indicates a bottom width of 30.758 micrometers in the X direction, and Marker 3 indicates a depth of 102.20 micrometers in the Y direction. Figure 11This image shows the structure of a conventional via B formed in a substrate using a conventional aperiodic cyclic dry etching process. This conventional via B is a tilted via with a sidewall tilt angle of approximately 87 degrees. While conventional cyclic dry etching processes offer advantages in etching rate and selectivity, their main challenges lie in controlling the tilt angle, top smoothness, and sidewall roughness, which limits its application in fabricating complex hole shapes and demanding devices. Although conventional aperiodic cyclic dry etching can create tilted vias with a certain angle, its low etching rate and poor selectivity prevent the fabrication of vias with smaller tilt angles, thus limiting its application in high-performance devices.

[0139] Figure 9 The image shows an electron microscope schematic diagram of a second through-hole formed by a method for manufacturing a metal through-hole according to the present application. The sidewall inclination angle of the second through-hole is approximately 85 degrees. Figure 9 In the diagram, marker 1 indicates a depth of 86.568 micrometers in the Y direction, marker 2 indicates a top width of 58.415 micrometers in the X direction, and marker 3 indicates a bottom width of 35.843 micrometers in the X direction. Figure 10 The conventional through hole A shown and Figure 11 Compared to the traditional through-hole B shown Figure 9 The second through-hole shown has more inclined sidewalls, a larger overall opening, and a more inclined and rounded top angle, as well as smooth sidewalls, which facilitates the filling and formation of a high-quality metal through-hole.

[0140] This application forms a through-hole (second through-hole 16) structure with the required tilt angle (second sidewall tilt angle) by performing a first plasma etching process and a second plasma etching process in stages. The first plasma etching process ensures precise achievement of the through-hole depth, guaranteeing the stability and uniformity of the etching depth, while maintaining a reasonable balance between etching rate and selectivity, avoiding unevenness in depth and width, and providing a stable benchmark for subsequent processes. Based on this, the second plasma etching process is further subdivided into three interconnected stages (first etching...). The three etching stages (first, second, and third) can effectively improve the smoothness of the via top, ensure the absence of sharp angles at the orifice, and repair the roughness of the sidewalls to achieve ideal surface quality. It can also manufacture second vias with smaller tilt angles (inverted trapezoidal or flared vias), thereby improving the shortcomings of traditional single etching processes in manufacturing tilted vias (such as large wall roughness and top morphology defects). It provides greater flexibility and precision, thus meeting the requirements for via tilt angles in different applications, and thus meeting the needs of high-performance devices for electrical connections and heat dissipation.

[0141] This application also provides a semiconductor structure containing metal vias, which are obtained using the metal via manufacturing method described in the above embodiments.

[0142] refer to Figure 8 In some embodiments, the semiconductor structure includes a substrate 10, on which a second via 16 is provided, and the second via 16 is filled with metal to form a metal via 17. Specifically, the metal via 17 is obtained using the metal via manufacturing method of the above embodiments.

[0143] In some embodiments, the semiconductor structure is applied in the field of three-dimensional advanced packaging and utilizes metal vias formed on the substrate as a vertical interconnect structure on a 3D integrated circuit chip.

[0144] In a third aspect, embodiments of this application also provide a plasma processing apparatus for performing the first plasma etching process and the second plasma etching process corresponding to the above embodiments to create the second via corresponding to the above embodiments. The plasma processing apparatus may be, for example, an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus.

[0145] In other aspects, embodiments of this application also provide an electronic device, including a semiconductor structure obtained using the metal through-hole manufacturing method of the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0146] In summary, this application combines a first plasma etching process with a second plasma etching process, overcoming the limitations of traditional single etching processes in achieving high-precision control. It also provides a more refined and controllable metal via etching solution for the manufacture of high-performance devices. Furthermore, this application provides a complete and efficient manufacturing process for tapered vias with tilt angles, addressing challenges related to depth, morphology, and tilt angle. This allows for better control of the filling effect during metal filling, thanks to the improved etching structure of the second via 16, avoiding incomplete filling and significantly improving the performance and reliability of the filled metal via 17. This application can be widely applied in the manufacture of high-performance devices, including but not limited to integrated circuits, power electronic devices, image sensors (CIS), MEMS devices, and optoelectronic devices.

[0147] The above are merely preferred embodiments of this application. These embodiments are not intended to limit the scope of protection of this application. Therefore, any equivalent changes made based on the description and drawings of this application should also be included within the scope of protection of this application.

Claims

1. A method for manufacturing a metal through-hole, characterized in that, include: A masked first plasma etching process is performed to periodically etch one side surface of the substrate to form a first via in the substrate. The first via has a first aperture width and a first sidewall tilt angle. A maskless second plasma etching process is performed to etch the sidewalls of the first via into a second via. The second plasma etching process includes a first etching stage, a second etching stage, and a third etching stage connected in sequence. The first etching stage uses a first etching gas and a first pressure to form a sidewall notch at the top of the first via. The second etching stage uses a second etching gas and a second pressure to round the top morphology at the sidewall notch and smooth the sidewalls of the first via. The third etching stage uses a third etching gas and a third pressure to form a second via with a second aperture width and a second sidewall tilt angle. The second aperture width is greater than the first aperture width, and the second sidewall tilt angle is less than the first sidewall tilt angle. The first etching gas, the second etching gas, and the third etching gas are all different, and the first pressure, the second pressure, and the third pressure increase sequentially. The second through hole is filled with metal to form a metal through hole.

2. The method for manufacturing a metal through-hole according to claim 1, characterized in that, The sidewall notch has a third sidewall inclination angle, which is smaller than the second sidewall inclination angle.

3. The method for manufacturing a metal through-hole according to claim 1, characterized in that, The sidewall of the first through hole has a first roughness, and the sidewall of the second through hole has a second roughness. When performing the second etching stage, the top morphology at the notch of the sidewall is rounded and the sidewall of the first through hole is smoothed so that the second roughness is less than the first roughness.

4. The method for manufacturing a metal through-hole according to claim 1, characterized in that, The first etching gas includes an oxidizing gas; and / or, the second etching gas includes an oxidizing gas and a fluorocarbon gas; and / or, the third etching gas includes a sulfur-fluorine gas and a fluorocarbon gas.

5. The method for manufacturing a metal through-hole according to claim 1, characterized in that, The first pressure is 8 mtorr to 50 mtorr; and / or, the second pressure is 10 mtorr to 100 mtorr; and / or, the third pressure is 110 mtorr to 200 mtorr.

6. The method for manufacturing a metal through-hole according to claim 1, characterized in that, When performing the first etching stage, the bias power is 10W to 100W and the time is 3s to 12s; and / or, when performing the second etching stage, the bias power is 0W to 90W and the time is 3s to 12s; and / or, when performing the third etching stage, the bias power is 0W to 100W and the time is 5s to 100s.

7. The method for manufacturing a metal through-hole according to claim 1, characterized in that, The first etching gas includes O2 with a flow rate of 1 sccm to 200 sccm; and / or, the second etching gas includes O2 and CF4, with the flow rate of O2 being 1 sccm to 200 sccm and the flow rate of CF4 being 1 sccm to 150 sccm; and / or, the third etching gas includes SF6 and C4F8, with the flow rate of SF6 being 1 sccm to 200 sccm and the flow rate of C4F8 being 1 sccm to 200 sccm.

8. The method for manufacturing a metal through-hole according to claim 2, characterized in that, The first sidewall has an inclination angle of 88 to 89 degrees; and / or, the second sidewall has an inclination angle of 80 to 87 degrees; and / or, the third sidewall has an inclination angle of 4 to 20 degrees.

9. The method for manufacturing a metal through-hole according to claim 1, characterized in that, The substrate material includes silicon; and / or, the metal filling the second via includes copper or tungsten; and / or, the first plasma etching process includes a periodic cycle of deposition and etching steps, wherein the process gas used in the deposition step includes C4F8, the process gas used in the etching step includes SF6, and the first via is formed by alternating deposition of a passivation layer using C4F8 and etching using SF6; and / or, the second via has a sidewall morphology that is inclined inward from top to bottom.

10. A semiconductor structure, characterized in that, It contains a metal through-hole, which is obtained using the method for manufacturing a metal through-hole as described in any one of claims 1-9.

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