Circuit and method applied to parallel operation working condition light and heavy load dynamic response

Abstract

The invention discloses a light and heavy load dynamic response circuit and method applied to parallel operation working conditions, the light and heavy load dynamic response circuit is used for switching power supply upper tube driving in an LLC converter, the response circuit comprises an LLC driving circuit and a switching tube control circuit, the switching tube control circuit is used for sending a PWM driving signal to the LLC driving circuit, and the LLC driving circuit is connected with the switching tube control circuit. And a first bootstrap capacitor C1 of the upper tube driving unit keeps the voltage required by the operation of the upper tube driving chip. The switching tube control circuit enables the upper tube driving chip and the lower tube driving chip to maintain the voltage required by working by controlling the on-off of a first switching tube Q1 and a second switching tube Q2 of a rectifier bridge at the input end of the LLC converter, and the voltage required by the working of the upper tube driving chip and the lower tube driving chip can be maintained in any working state. The problem of insufficient voltage of the bootstrap capacitor in a light and heavy load switching test is effectively solved, a winding circuit does not need to be added, the cost can be reduced, and the power density is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a circuit and method for dynamic response to light and heavy loads in parallel operation. Background Art

[0002] In an environment of rapid technological development, server power supplies, with their high-efficiency output and stable voltage control, are able to maintain the stable operation of high-performance GPUs. As technology advances, GPU computing power is no longer limited to image processing, but is also being used in scientific computing, artificial intelligence, machine learning, and other fields. Server power supplies require not only high efficiency and stable voltage, but also rapid response capabilities with large dynamic ranges.

[0003] When parallel loads experience large dynamics between light and heavy loads, the output voltage of the power supply often overshoots when switching from heavy to light load, especially when the load is light, falling below the current sharing point. Due to voltage differences between individual power supplies in the parallel system, they fail to draw load, causing the power supply to enter burst mode for a long time. (Burst mode is an operating mode that intermittently starts and stops the operation of a device or system under specific conditions to reduce power consumption.) In power management systems, burst mode is often used under light or no-load conditions to reduce power consumption by reducing the switching frequency and number of switching cycles.

[0004] After the power supply enters burst mode for a long time, the VCC holding capacitor of the upper tube driver chip is not charged and will slowly discharge to below the undervoltage recovery point of the driver chip, causing the driver chip to stop working. At this time, if it is switched to heavy load, the control module will respond and send the corresponding drive signal, but the driver chip will still not transmit the corresponding drive signal to the MOS tube, resulting in a slow response and eventually the power supply output voltage drops to an extremely low value.

[0005] The current solution is: In the traditional LLC line, such as Figure 1 As shown in the figure, based on the VCC of the high-side tube driver chip being charged through bootstrapping, a high-side tube VCC winding is added to provide power supply to provide a hardware solution for fast parallel response. This solution increases the complexity of the circuit and the cost, which is not conducive to improving power density. Summary of the Invention

[0006] In view of this, it is necessary to provide a circuit and method for dynamic response to light and heavy loads in parallel operation, which can keep the voltage of the bootstrap capacitor in the working state of the driver chip.

[0007] A circuit for dynamic response to light and heavy loads in parallel operation is used for driving the upper tube of a switching power supply in an LLC converter. The circuit includes an LLC drive circuit and a switch tube control circuit. The LLC drive circuit includes an upper tube drive unit and a lower tube drive unit, wherein the output ends of the upper tube drive unit and the lower tube drive unit are respectively connected to the gate of the first switch tube Q1 and the gate of the second switch tube Q2 of the switching power supply; the LLC drive circuit is used to drive the first switch tube Q1 and the second switch tube Q2 of the input-end rectifier bridge of the LLC converter on and off; The switch tube control circuit includes an output voltage sampling circuit, a voltage loop control circuit, a burst wave detection circuit, a bootstrap capacitor C1 voltage maintenance control circuit, and a PWM drive signal output circuit, which are connected in sequence; the switch tube control circuit is used to send a PWM drive signal to the LLC drive circuit, so that the first bootstrap capacitor C1 of the upper tube drive unit maintains the voltage required for the upper tube drive chip to operate.

[0008] Preferably, the lower tube driving unit includes a lower tube driving chip, a second bootstrap capacitor C2, and a power supply winding, wherein the second bootstrap capacitor C2 and the power supply winding are connected in parallel to the VCC power supply terminal and the ground terminal GND of the lower tube driving chip; the signal output terminal VOUT of the lower tube driving chip is connected to the gate of the second switch tube Q2, and the ground terminal GND of the lower tube driving chip is connected to the source of the second switch tube Q2; The upper tube driving unit includes the upper tube driving chip and the first bootstrap capacitor C1, wherein the two ends of the first bootstrap capacitor C1 are respectively connected to the VCC power supply terminal and the ground terminal GND of the upper tube driving chip; the signal output terminal VOUT of the upper tube driving chip is connected to the gate of the first switch tube Q1, and the ground terminal GND of the upper tube driving chip is connected to the source of the first switch tube Q1; The power supply voltage pin VCC of the lower tube driver chip is connected to the power supply voltage pin VCC of the upper tube driver chip; the signal input terminal VIN of the upper tube driver chip and the signal input terminal VIN of the lower tube driver chip are respectively connected to the output terminal of the PWM drive signal output circuit of the switch tube control circuit.

[0009] Preferably, the input end of the output voltage sampling circuit is connected to the output end of the LLC converter, and the output voltage sampling circuit is used to collect the output voltage of the LLC converter; the output end of the output voltage sampling circuit is connected to the input end of the voltage loop control circuit, and the voltage loop control circuit is used to compare the actual output voltage with the reference voltage to obtain an error signal; the output end of the voltage loop control circuit is connected to the input end of the Burst wave detection circuit, and the Burst wave detection circuit is used to detect whether the output of the LLC converter enters the Burst mode.

[0010] Preferably, the bootstrap capacitor C1 voltage maintenance control circuit includes a burst wave accumulator circuit, an accumulator delay judgment circuit, and a specific pulse output circuit connected in sequence; the burst wave accumulator circuit is used to accumulate and calculate the duration of time the output of the LLC converter enters the burst mode; the accumulator delay judgment circuit is used to judge whether the cumulative duration of time the output of the LLC converter enters the burst mode reaches a predetermined value; the specific pulse output circuit is used to send a specific pulse width modulation signal to the PWM drive signal output circuit when the cumulative duration of time the output of the LLC converter enters the burst mode reaches a predetermined value.

[0011] Preferably, the switch tube control circuit further includes a voltage loop output circuit, the input end of the voltage loop output circuit being connected to the output end of the Burst wave detection circuit, and the output end of the voltage loop output circuit being connected to the PWM drive signal output circuit, and the voltage loop output circuit being configured to send a MOS tube drive pulse signal to the PWM drive signal output circuit when the output of the LLC converter does not enter the Burst mode.

[0012] A method for dynamic response to light and heavy loads in parallel operation is also provided. The circuit for dynamic response to light and heavy loads in parallel operation is used to drive the upper tube of the switching power supply in the LLC converter so that the upper tube is always in an operating state. The method includes the following steps: Step 1: Circuit configuration: Set up an LLC drive circuit at the input end of the LLC converter, connect the output voltage sampling circuit of the switch tube control circuit to the output end of the LLC converter, and connect the PWM drive signal output circuit of the switch tube control circuit to the LLC drive circuit; Step 2: sampling the output voltage signal of the LLC converter; Step 3: Compare the sampled voltage with the reference voltage to obtain a comparison value between the output voltage of the LLC converter and the reference voltage; Step 4: Determine whether the LLC converter enters the Burst mode; if the LLC converter does not enter the Burst mode, proceed to step 6; if the LLC converter enters the Burst mode, proceed to step 5; Step 5: Calculate the cumulative duration of the LLC converter entering the Burst mode; if the cumulative duration is less than the predetermined duration t, proceed to step 8; if the cumulative duration is greater than the predetermined duration t, proceed to step 9; Step 6: The accumulated duration of the Burst wave accumulator circuit is reset to zero, and the Burst wave accumulator circuit is turned off; Step 7: The voltage loop output circuit sends a MOS tube drive pulse signal to the PWM drive signal output circuit; then the process goes to step 2. Step 8: Turn off the PWM drive signal output circuit, so that the PWM drive signal output circuit does not send a drive pulse signal to the LLC drive circuit and the LLC converter; go to step 2; Step nine, the accumulated duration of the Burst wave accumulator circuit is reset to zero, and the specific pulse output circuit sends a specific drive signal to the PWM drive signal output circuit; Step 10: The PWM drive signal output circuit sends a specific pulse width modulation signal to the LLC drive circuit; then go to step 2.

[0013] Preferably, the predetermined value t of the cumulative time length is the time interval for sending a specific pulse width modulation signal when the LLC converter enters the Burst mode.

[0014] Preferably, the predetermined value t of the cumulative time length in step five is the time length during which the first bootstrap capacitor C1 maintains the VCC voltage of the upper tube driver chip in the Burst mode; the predetermined value t of the cumulative time length is proportional to the capacitance value of the first bootstrap capacitor C1 in the upper tube driver unit.

[0015] Preferably, the specific pulse width modulation signal in step 10 is a driving signal of two specific pulse widths forcibly issued by a specific pulse output circuit at an interval of a predetermined time t when the LLC converter enters the Burst mode.

[0016] Preferably, the specific pulse width modulation signal in step 10 is: turning off the first switch tube Q1 and turning on the second switch tube Q2 at the same time, so as to charge the first bootstrap capacitor C1.

[0017] In the aforementioned circuit and method for dynamic response to light and heavy loads in parallel operation, the switch control circuit controls the on / off switching of the first switch Q1 and the second switch Q2 of the input rectifier bridge of the LLC converter to maintain the required operating voltage for the upper and lower tube driver chips. This effectively resolves the issue of insufficient bootstrap capacitor voltage during light and heavy load switching testing under any operating state, eliminating the need for additional winding circuits, reducing costs, and increasing power density. The method of the present invention is simple, easy to implement, and inexpensive, making it easy to promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the circuit structure of adding a driving circuit to a traditional LLC top tube in the prior art.

[0019] Figure 2 The figure is a schematic diagram of the circuit structure of a light and heavy load dynamic response circuit applied to parallel operation conditions according to an embodiment of the present invention.

[0020] Figure 31 is a schematic diagram of a circuit structure for charging a first bootstrap capacitor C1 of an upper tube driving unit of a circuit for dynamic response to light and heavy loads in parallel operation according to an embodiment of the present invention.

[0021] Figure 4 This is a flow chart of a method for dynamic response to light and heavy loads in parallel operation conditions applied in an embodiment of the present invention.

[0022] Figure 5 This is a timing diagram comparing whether a specific pulse width modulation signal is sent by an LLC drive module in a method for dynamic response to light and heavy loads in parallel operation according to an embodiment of the present invention (the upper half shows the specific pulse width modulation signal being sent, and the lower half shows the specific pulse width modulation signal not being sent).

[0023] Figure 6 This is a comparison diagram of the output voltage before and after adding the driving strategy to the light and heavy load dynamic response method for parallel operation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] This embodiment takes a multi-dimensional vocabulary expansion query method, system, and computer-readable storage medium for trademark registration risk assessment as an example, and the present invention will be described in detail below in conjunction with specific embodiments and drawings.

[0025] See also Figure 2 , shows a circuit for dynamic response to light and heavy loads in parallel operation provided by an embodiment of the present invention, which is used to drive the upper tube of the switching power supply in the LLC converter. The circuit includes an LLC drive circuit and a switch tube control circuit, wherein, The LLC drive circuit includes an upper tube drive unit and a lower tube drive unit, wherein the output ends of the upper tube drive unit and the lower tube drive unit are respectively connected to the gate of the first switch tube Q1 and the gate of the second switch tube Q2 of the switching power supply; the LLC drive circuit is used to drive the first switch tube Q1 and the second switch tube Q2 of the input-end rectifier bridge of the LLC converter on and off; The switch tube control circuit includes an output voltage sampling circuit, a voltage loop control circuit, a burst wave detection circuit, a bootstrap capacitor C1 voltage maintenance control circuit, and a PWM drive signal output circuit, which are connected in sequence; the switch tube control circuit is used to send a PWM drive signal to the LLC drive circuit, so that the first bootstrap capacitor C1 of the upper tube drive unit maintains the voltage required for the upper tube drive chip to operate.

[0026] Specifically, the circuit state when the first bootstrap capacitor C1 is charged is as follows: Figure 3As shown, wherein the first switch tube Q1 is disconnected, the second switch tube Q2 is connected, and the first bootstrap capacitor C1 is charged to provide the voltage required for the upper tube drive chip to work, so that when the LLC converter is switched to heavy load, the upper tube drive chip cannot respond in time, resulting in an excessively low output voltage.

[0027] Specifically, in the present embodiment, when the power supply is in burst mode, the driving pulses of the first switch tube Q1 and the second switch tube Q2 are in discontinuous mode, and the pulse width is 300 ns; when the LLC converter is working normally, the driving pulses of the power supply circuit are in continuous mode, and the driving pulse width is ≥ 300 ns.

[0028] Preferably, the lower tube drive unit comprises a lower tube drive chip, a second bootstrap capacitor C2, and a power supply winding, the second bootstrap capacitor C2 and the power supply winding are connected in parallel to the VCC power supply end and the ground end GND of the lower tube drive chip; the signal output end VOUT of the lower tube drive chip is connected to the gate of the second switch tube Q2, and the ground end GND of the lower tube drive chip is connected to the source of the second switch tube Q2. The upper tube drive unit comprises the upper tube drive chip and the first bootstrap capacitor C1, and the two ends of the first bootstrap capacitor C1 are connected to the VCC power supply end and the ground end GND of the upper tube drive chip, respectively; the signal output end VOUT of the upper tube drive chip is connected to the gate of the first switch tube Q1, and the ground end GND of the upper tube drive chip is connected to the source of the first switch tube Q1. The power supply voltage pin VCC of the lower tube drive chip is connected to the power supply voltage pin VCC of the upper tube drive chip; the signal input end VIN of the upper tube drive chip and the signal input end VIN of the lower tube drive chip are respectively connected to the output end of the PWM driving signal output circuit of the switch tube control circuit.

[0029] Preferably, the input end of the output voltage sampling circuit is connected to the output end of the LLC converter, and the output voltage sampling circuit is used to collect the output voltage of the LLC converter; the output end of the output voltage sampling circuit is connected to the input end of the voltage loop control circuit, and the voltage loop control circuit is used to compare the actual output voltage with the reference voltage to obtain an error signal; the output end of the voltage loop control circuit is connected to the input end of the burst wave detection circuit, and the burst wave detection circuit is used to detect whether the output of the LLC converter enters burst mode.

[0030] Preferably, the bootstrap capacitor C1 voltage maintenance control circuit includes a burst wave accumulator circuit, an accumulator delay judgment circuit, and a specific pulse output circuit connected in sequence; the burst wave accumulator circuit is used to accumulate and calculate the duration of time the output of the LLC converter enters the burst mode; the accumulator delay judgment circuit is used to judge whether the cumulative duration of time the output of the LLC converter enters the burst mode reaches a predetermined value; the specific pulse output circuit is used to send a specific pulse width modulation signal to the PWM drive signal output circuit when the cumulative duration of time the output of the LLC converter enters the burst mode reaches a predetermined value.

[0031] Preferably, the switch tube control circuit further includes a voltage loop output circuit, the input end of the voltage loop output circuit being connected to the output end of the Burst wave detection circuit, and the output end of the voltage loop output circuit being connected to the PWM drive signal output circuit, and the voltage loop output circuit being configured to send a MOS tube drive pulse signal to the PWM drive signal output circuit when the output of the LLC converter does not enter the Burst mode.

[0032] Also, see Figure 4 , a method for dynamic response to light and heavy loads in parallel operation is shown. The circuit for dynamic response to light and heavy loads in parallel operation is used to drive the upper tube of the switching power supply in the LLC converter so that the upper tube is always in an operating state. The method includes the following steps: Step S10, circuit configuration: setting an LLC drive circuit at the input end of the LLC converter, connecting the output voltage sampling circuit of the switch tube control circuit to the output end of the LLC converter, and connecting the PWM drive signal output circuit of the switch tube control circuit to the LLC drive circuit; Step S20, sampling the output voltage signal of the LLC converter; Step S30, comparing the sampled voltage with the reference voltage to obtain a comparison value between the output voltage of the LLC converter and the reference voltage; Step S40, determining whether the LLC converter enters the Burst mode; if the LLC converter does not enter the Burst mode, proceeding to step S60; if the LLC converter enters the Burst mode, proceeding to step S50; Step S50, calculating the cumulative time that the LLC converter enters the Burst mode; if the cumulative time is less than the predetermined time t, proceeding to step S80; if the cumulative time is greater than the predetermined time t, proceeding to step S90; Step S60: the accumulated duration of the Burst wave accumulator circuit is reset to zero, and the Burst wave accumulator circuit is turned off; Step S70: The voltage loop output circuit sends a MOS transistor drive pulse signal to the PWM drive signal output circuit; then the process goes to step S20; Step S80, turning off the PWM drive signal output circuit, so that the PWM drive signal output circuit does not send a drive pulse signal to the LLC drive circuit and the LLC converter; turning to step S20; Step S90: the accumulated duration of the Burst wave accumulator circuit is reset to zero, and the specific pulse output circuit sends a specific drive signal to the PWM drive signal output circuit; In step S100 , the PWM driving signal output circuit sends a specific pulse width modulation signal to the LLC driving circuit; and the process proceeds to step S20 .

[0033] Preferably, the predetermined value t of the cumulative time length is the time interval for sending a specific pulse width modulation signal when the LLC converter enters the Burst mode.

[0034] Preferably, the predetermined value t of the cumulative time length in step five is the time length during which the first bootstrap capacitor C1 maintains the VCC voltage of the upper tube driver chip in the Burst mode; the predetermined value t of the cumulative time length is proportional to the capacitance value of the first bootstrap capacitor C1 in the upper tube driver unit.

[0035] Specifically, the larger the capacitance of the first bootstrap capacitor C1 is, the larger the predetermined value t of the cumulative time length for the accumulator delay judgment circuit to perform judgment is.

[0036] Preferably, the specific pulse width modulation signal in step 10 is a driving signal of two specific pulse widths forcibly issued by a specific pulse output circuit at an interval of a predetermined time t when the LLC converter enters the Burst mode.

[0037] Specifically, the pulse width and interval duration t of the driving signal of a specific pulse width are obtained through circuit testing. It is necessary to satisfy that within the interval duration t, the driving pulse width ensures that the voltage of the bootstrap capacitor does not fall out of the power supply range, and when the pulse width drive is output for the interval duration t, the no-load voltage of the power supply output is stable and does not overshoot.

[0038] Preferably, the specific pulse width modulation signal in step 10 is: turning off the first switch tube Q1 and turning on the second switch tube Q2 at the same time, so as to charge the first bootstrap capacitor C1.

[0039] Specifically, in this embodiment, the circuit configuration includes a main control unit MCU, which performs loop calculations and updates the calculation results for the driver; a high-speed ADC sampling module is also configured, using an LLC bridge topology circuit, including LLC upper and lower tube drive circuits.

[0040] The ADC module samples the output voltage and combines it with the voltage loop control to form a voltage closed-loop control structure. The loop calculation results determine whether to enter the burst mode. If so, the PWM drive will stop generating waves.

[0041] The power supply stops sending drive waves in burst mode. Once the driving time exceeds time t, the voltage of the upper tube bootstrap capacitor C1 will be lower than the undervoltage recovery point of the driver IC, causing the upper tube driver chip to stop working. Therefore, when it is detected that the duration of the burst mode is greater than time t, two minimum pulse width drives are sent to charge the upper tube driver bootstrap capacitor and maintain the required VCC voltage to ensure that the upper tube driver chip continues to work.

[0042] See also Figure 5 , shows a timing diagram of the driving signal in the circuit of this embodiment, including a timing comparison when a specific pulse width modulation signal is sent and when no specific pulse width modulation signal is sent.

[0043] See also Figure 6 , showing the comparison results of the output voltage before and after the drive strategy is added to the circuit of this embodiment. As can be seen from the figure, the software method of paralleling light and heavy load switching and the traditional method of adding winding circuit hardware have the same effect, and both can effectively prevent the undervoltage of the driver IC from affecting the dynamic response.

[0044] In the aforementioned circuit and method for dynamic response to light and heavy loads in parallel operation, the switch control circuit controls the on / off switching of the first switch Q1 and the second switch Q2 of the input rectifier bridge of the LLC converter to maintain the required operating voltage for the upper and lower tube driver chips. This effectively resolves the issue of insufficient bootstrap capacitor voltage during light and heavy load switching testing under any operating state, eliminating the need for additional winding circuits, reducing costs, and increasing power density. The method of the present invention is simple, easy to implement, and inexpensive, making it easy to promote.

[0045] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A circuit for dynamic response to light and heavy loads in parallel operation, used for driving the upper tube of the switching power supply in the LLC converter, characterized by: It includes LLC drive circuit and switch tube control circuit, among which, The LLC drive circuit includes an upper tube drive unit and a lower tube drive unit, wherein the output ends of the upper tube drive unit and the lower tube drive unit are respectively connected to the gate of the first switch tube Q1 and the gate of the second switch tube Q2 of the switching power supply; the LLC drive circuit is used to drive the first switch tube Q1 and the second switch tube Q2 of the input-end rectifier bridge of the LLC converter on and off; The switch tube control circuit includes an output voltage sampling circuit, a voltage loop control circuit, a burst wave detection circuit, a bootstrap capacitor C1 voltage maintenance control circuit, and a PWM drive signal output circuit, which are connected in sequence; the switch tube control circuit is used to send a PWM drive signal to the LLC drive circuit, so that the first bootstrap capacitor C1 of the upper tube drive unit maintains the voltage required for the upper tube drive chip to operate.

2. The circuit for dynamic response to light and heavy loads in parallel operation as claimed in claim 1, characterized in that: The lower tube driving unit includes a lower tube driving chip, a second bootstrap capacitor C2 and a power supply winding, wherein the second bootstrap capacitor C2 and the power supply winding are connected in parallel to the VCC power supply terminal and the ground terminal GND of the lower tube driving chip; the signal output terminal VOUT of the lower tube driving chip is connected to the gate of the second switch tube Q2, and the ground terminal GND of the lower tube driving chip is connected to the source of the second switch tube Q2; The upper tube driving unit includes the upper tube driving chip and the first bootstrap capacitor C1, wherein the two ends of the first bootstrap capacitor C1 are respectively connected to the VCC power supply terminal and the ground terminal GND of the upper tube driving chip; the signal output terminal VOUT of the upper tube driving chip is connected to the gate of the first switch tube Q1, and the ground terminal GND of the upper tube driving chip is connected to the source of the first switch tube Q1; The power supply voltage pin VCC of the lower tube driver chip is connected to the power supply voltage pin VCC of the upper tube driver chip; the signal input terminal VIN of the upper tube driver chip and the signal input terminal VIN of the lower tube driver chip are respectively connected to the output terminal of the PWM drive signal output circuit of the switch tube control circuit.

3. The circuit for dynamic response to light and heavy loads in parallel operation as claimed in claim 1, characterized in that: The input end of the output voltage sampling circuit is connected to the output end of the LLC converter, and the output voltage sampling circuit is used to collect the output voltage of the LLC converter; the output end of the output voltage sampling circuit is connected to the input end of the voltage loop control circuit, and the voltage loop control circuit is used to compare the actual output voltage with the reference voltage to obtain an error signal; the output end of the voltage loop control circuit is connected to the input end of the burst wave detection circuit, and the burst wave detection circuit is used to detect whether the output of the LLC converter enters the burst mode.

4. The circuit for dynamic response to light and heavy loads in parallel operation as claimed in claim 1, characterized in that: The bootstrap capacitor C1 voltage maintenance control circuit includes a burst wave accumulator circuit, an accumulator delay judgment circuit, and a specific pulse output circuit connected in sequence; the burst wave accumulator circuit is used to accumulate and calculate the duration of time the LLC converter output enters the burst mode; the accumulator delay judgment circuit is used to determine whether the accumulated duration of time the LLC converter output enters the burst mode reaches a predetermined value; and the specific pulse output circuit is used to send a specific pulse width modulation signal to the PWM drive signal output circuit when the accumulated duration of time the LLC converter output enters the burst mode reaches a predetermined value.

5. The circuit for dynamic response to light and heavy loads in parallel operation as claimed in claim 1, characterized in that: The switch tube control circuit also includes a voltage loop output circuit, the input end of the voltage loop output circuit is connected to the output end of the burst wave detection circuit, and the output end of the voltage loop output circuit is connected to the PWM drive signal output circuit. The voltage loop output circuit is used to send a MOS tube drive pulse signal to the PWM drive signal output circuit when the output of the LLC converter does not enter the burst mode.

6. A method for dynamic response to light and heavy loads in parallel operation, wherein the circuit for dynamic response to light and heavy loads in parallel operation as claimed in any one of claims 1 to 5 is used to drive the upper tube of the switching power supply in the LLC converter, so that the upper tube is always in an operating state, characterized in that: The method comprises the following steps: Step 1: Circuit configuration: Set up an LLC drive circuit at the input end of the LLC converter, connect the output voltage sampling circuit of the switch tube control circuit to the output end of the LLC converter, and connect the PWM drive signal output circuit of the switch tube control circuit to the LLC drive circuit; Step 2: sampling the output voltage signal of the LLC converter; Step 3: Compare the sampled voltage with the reference voltage to obtain a comparison value between the output voltage of the LLC converter and the reference voltage; Step 4: Determine whether the LLC converter enters the Burst mode; if the LLC converter does not enter the Burst mode, proceed to step 6; if the LLC converter enters the Burst mode, proceed to step 5; Step 5: Calculate the cumulative duration of the LLC converter entering the Burst mode; if the cumulative duration is less than the predetermined duration t, proceed to step 8; if the cumulative duration is greater than the predetermined duration t, proceed to step 9; Step 6: The accumulated duration of the Burst wave accumulator circuit is reset to zero, and the Burst wave accumulator circuit is turned off; Step 7: The voltage loop output circuit sends a MOS tube drive pulse signal to the PWM drive signal output circuit; then the process goes to step 2. Step 8: Turn off the PWM drive signal output circuit, so that the PWM drive signal output circuit does not send a drive pulse signal to the LLC drive circuit and the LLC converter; go to step 2; Step nine, the accumulated duration of the Burst wave accumulator circuit is reset to zero, and the specific pulse output circuit sends a specific drive signal to the PWM drive signal output circuit; Step 10: The PWM drive signal output circuit sends a specific pulse width modulation signal to the LLC drive circuit; then go to step 2.

7. The method for dynamic response to light and heavy loads in parallel operation as claimed in claim 6, characterized in that: The predetermined value t of the cumulative time length is the time interval for sending a specific pulse width modulation signal when the LLC converter enters the Burst mode.

8. The method for dynamic response to light and heavy loads in parallel operation as claimed in claim 6, characterized in that: The predetermined value t of the cumulative time length in step five is the time length during which the first bootstrap capacitor C1 maintains the VCC voltage of the upper tube driver chip in the Burst mode; the predetermined value t of the cumulative time length is proportional to the capacitance value of the first bootstrap capacitor C1 in the upper tube driver unit.

9. The method for dynamic response to light and heavy loads in parallel operation as claimed in claim 6, characterized in that: The specific pulse width modulation signal in step 10 is a driving signal of two specific pulse widths forcibly issued by the specific pulse output circuit at an interval of a predetermined time t when the LLC converter enters the Burst mode.

10. The method for dynamic response to light and heavy loads in parallel operation as claimed in claim 6, characterized in that: The specific pulse width modulation signal in step 10 is: turning off the first switch tube Q1 and closing the second switch tube Q2 at the same time, so as to charge the first bootstrap capacitor C1.

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