K-band low phase noise class-c voltage controlled oscillator, phase-locked loop and chip

Abstract

The application relates to a K-band low-phase-noise class-C voltage-controlled oscillator, a phase-locked loop and a chip. The K-band low-phase-noise class-C voltage-controlled oscillator comprises an oscillation circuit, a switched-capacitor array circuit and a dynamic starting circuit. The oscillation circuit is used for providing an oscillation signal. The switched-capacitor array circuit is used for changing a self-capacitance value according to a control signal group sel to adjust the frequency of the oscillation signal. The dynamic starting circuit is used for dynamically controlling the voltage of a cross-coupled pair circuit according to a reference voltage V ref to adjust the amplitude of the oscillation signal. The application introduces a dynamic starting circuit in the class-C inductance-capacitance voltage-controlled oscillator, which is composed of an operational amplifier with extremely low static power consumption. The high gain of the operational amplifier can effectively ensure the rapid stable starting of the oscillator. In addition, the extremely low static current can effectively reduce the influence of the low-frequency noise of the amplifier on the phase noise of the oscillator, and the power consumption and phase noise performance of the voltage-controlled oscillator are improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and in particular to a K-band low phase noise Class C voltage-controlled oscillator, a phase-locked loop, and a K-band low phase noise chip. Background Technology

[0002] With the rapid development of millimeter-wave communication, satellite navigation, and radar detection technologies, K-band (18-27GHz) wireless systems are placing more stringent demands on core frequency sources. As the core module of the frequency synthesizer, the voltage-controlled oscillator (VCO) directly determines the signal-to-noise ratio and anti-interference capability of the phase-locked loop (PLL) system due to its phase noise performance. While traditional Class C VCOs offer high efficiency, transistor nonlinearity intensifies at high frequencies in the K-band, leading to significant deterioration of phase noise. Existing technologies often suppress noise by increasing the quality factor (Q value) of the resonant circuit or sacrificing the tuning range, but these methods struggle to meet the combined requirements of wide tuning range and ultra-low phase noise for 5G millimeter-wave and high-speed frequency-hopping systems. Furthermore, the influence of high-frequency parasitic parameters on the resonant network further limits the performance boundaries of existing Class C VCOs, becoming a bottleneck in the design of high-precision frequency sources.

[0003] In K-band Class C VCOs, the amplifier quiescent current setting in the startup circuit has a decisive impact on the phase noise performance of the oscillator core module. Traditional startup circuits, to meet the requirement of rapid oscillation, typically employ a high quiescent current design to provide sufficient initial transconductance. However, this directly results in amplifier thermal noise and 1 / f noise components being injected into the oscillator core through power supply paths or substrate coupling, leading to near-end phase noise degradation. Furthermore, the narrow conduction angle characteristic of Class C VCOs requires strict matching between the quiescent current and the resonant circuit impedance. However, high-frequency parasitic parameters introduce additional nonlinear modulation effects, reducing the accuracy of quiescent current control and increasing the sensitivity of phase noise to process deviations. While existing dynamic biasing techniques can alleviate noise problems by adjusting the quiescent current in stages (e.g., switching to a low-power mode after oscillation), the current step caused by its transient switching process disturbs the stability of the resonant network, leading to far-end phase noise degradation (>1MHz offset). This strong coupling contradiction between quiescent current and phase noise in the startup circuit has become a key obstacle limiting the application of K-band Class C VCOs in high-precision scenarios. Summary of the Invention

[0004] Therefore, it is necessary to address the problem of strong coupling between static current and phase noise in existing VCO startup circuits, which leads to phase noise degradation, by providing a K-band low-phase-noise Class C voltage-controlled oscillator, phase-locked loop, and chip.

[0005] In a first aspect, the present invention proposes a K-band low phase noise Class C voltage-controlled oscillator, which includes: an oscillation circuit, a switched capacitor array circuit, and a dynamic start-up circuit.

[0006] The oscillation circuit provides the oscillation signal and includes two output nodes, VP and VN, and one cross-coupled pair circuit. The input of the switched capacitor array circuit is connected to the control signal group sel, and the output is connected to VP and VN; it is used to adjust the frequency of the oscillation signal by changing its capacitance value according to sel.

[0007] The dynamic start-up circuit is used based on the reference voltage V ref This circuit dynamically controls the voltage across the cross-coupled transistors to adjust the amplitude of the oscillation signal. It includes: five NMOS transistors M10-M14, five PMOS transistors MP1-MP5, and two resistors R5-R6. The gates of MP3-MP5 are connected to the drain of MP3, and their sources are connected to the power supply VDD. The drain of MP4 is connected to the sources of MP1 and MP2. The drain of MP3 is connected to the drain of M11. One end of R6 is connected to the source of M11, and the other end is grounded. The gates of M10 and M11 are connected, and their sources are grounded. One end of R5 is connected to VDD, and the other end is connected to the drain and gate of M10. The gates of MP1 and MP2 are respectively connected to VDD. ref The source and drain of the cross-coupled circuit are connected to the drains of M12 and M13 respectively; the sources of M12 and M13 are grounded; the drain and gate of M12 are connected; the drain of MP5 is connected to the source of M14 and is also connected to the gate of the cross-coupled circuit; the gate of M14 is connected to the drain of M13 and the drain is grounded.

[0008] In a second aspect, the present invention also proposes a phase-locked loop comprising a Class C voltage-controlled oscillator with low phase noise in the K-band as described in the first aspect.

[0009] Thirdly, the present invention also proposes a K-band low phase noise chip, which is packaged from the K-band low phase noise Class C voltage-controlled oscillator described in the first aspect. The pins of the K-band low phase noise chip include:

[0010] One power supply pin for connecting to VDD; one ground pin for grounding; one pin for connecting to I... bias Tail current pin; 1 for connecting V ctrl One control pin; one bias pin for connecting to Vb; one bias pin for connecting to Vb. ref The system includes: a reference pin; a first output pin for connecting to VP; a second output pin for connecting to VN; and K signal pins connected to the switched capacitor array circuit, which are used to receive K control signals sel1 to sel2 respectively. K .

[0011] The beneficial effects of this invention are as follows:

[0012] 1. This invention introduces a dynamic startup circuit into a Class C inductor-capacitor voltage-controlled oscillator. This circuit consists of an operational amplifier with extremely low quiescent power consumption. Its high gain can effectively ensure the rapid and stable startup of the oscillator. In addition, the extremely low quiescent current can effectively reduce the impact of low-frequency noise of the amplifier on the phase noise of the oscillator, thereby improving the power consumption and phase noise performance of the voltage-controlled oscillator of this invention.

[0013] 2. This invention introduces an NMOS stacked switched capacitor array into the resonant cavity of a Class C inductor-capacitor voltage-controlled oscillator. This array is controlled by a 4-bit digital control signal. Compared with the traditional structure, it can effectively improve the Q value of the resonant cavity, reduce the layout area, and expand the tuning range of the voltage-controlled oscillator. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a Class C voltage-controlled oscillator with low phase noise in the K-band, as shown in the embodiment.

[0016] Figure 2 This is a schematic diagram of the switched capacitor array circuit in the embodiment;

[0017] Figure 3 This is a schematic diagram of the dynamic startup circuit in the embodiment;

[0018] Figure 4 VP and V during the start-up process of the oscillator of this invention bias V S Simulation results over time;

[0019] Figure 5 This is a schematic diagram showing the results of the examples and comparative examples;

[0020] Figure 6 The figure shows the simulation results of the frequency modulation curve of the oscillator of this invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] This embodiment provides a K-band low-phase-noise Class C voltage-controlled oscillator, comprising: an oscillation circuit, a switched-capacitor array circuit, and a dynamic startup circuit. The oscillation circuit further includes: an LC resonant unit, a cross-coupled pair, and a bias circuit. The LC resonant unit constitutes the main body of the oscillator, providing the start-up signal required by the VCO. The cross-coupled pair circuit is cascaded with the LC resonant unit, generating negative resistance to compensate for the energy loss of the LC resonant unit and maintain oscillation. The switched-capacitor array circuit, through digital signal control of the circuit's on / off state, changes the capacitance value of the switched-capacitor array circuit with binary weights, thereby changing the oscillator's output frequency and achieving a wide range of frequency adjustment for the voltage-controlled oscillator. The dynamic startup circuit is connected to the oscillator in the form of negative feedback to adjust the amplitude, enhancing the stability of the circuit's startup. The bias circuit is connected to the cross-coupled pair circuit, mirroring and amplifying the current source to provide current to the oscillator.

[0024] The following provides a detailed explanation of each part. Please refer to... Figure 1 The LC resonant unit includes an inductor L, a capacitor C1, and a differential varactor resonant circuit. L can be a center-tapped inductor, with its first port (tap end) connected to the external power supply VDD, its second port connected to the first output node VP, and its third port connected to the second output node VN. C1 can be a fixed-value capacitor, with its first port connected to VP and its second port connected to VN. The combination of L and C1 generates an equivalent resistance in parallel with the differential varactor resonant circuit, providing the conditions for oscillation. The differential varactor resonant circuit group consists of two differential varactor resonant circuits connected in parallel. Each differential varactor resonant circuit includes two varactor transistors C1, C2, C3, C4, C5, C6, C7, C8, C9, C1, C1, C1, C1, C2 ... var1 ~C var2 There are two resistors, R3 and R4, and two capacitors, C4 and C5. Among them, C... var1 One end is connected to VP via C4 and to the bias voltage Vb via R3. var2One end is connected to VN via C5 and to Vb via R4. C var1 C var2 The other end is connected to V ctrl Through V ctrl Change C var1 C var2 The voltage difference between the two ends is used to change the capacitance value of the differential varactor resonant circuit, thereby changing the output frequency of the oscillator and achieving fine adjustment of the voltage-controlled oscillator frequency.

[0025] In this embodiment, the cross-coupled circuit includes two NMOS transistors M1 and M2, two resistors R1 and R2, and two capacitors C2 and C3. The drains of M1 and M2 are connected to VP and VN, respectively. The gate of M1 is connected to the drain of M2 through C3, the drain of M1 is connected to the gate of M2 through C2, and the source of M1 is connected to the source of M2. One end of R1 and R2 is connected to the gate of M1 and M2, respectively. The other end of R1 and R2 is connected to the output of the dynamic startup circuit. In another embodiment, M1 and M2 can be MOS transistors based on CMOS RF technology, which can have good high-frequency characteristics at an operating frequency of 20GHz.

[0026] Take a 4-bit switched capacitor array circuit as an example. Please refer to... Figure 2 The switched capacitor array circuit includes: a K-stage capacitor array and one inverter INV. The output of INV is connected to the input of the K-stage capacitor array. The output of the K-stage capacitor array is connected to VP and VN. The k-th stage capacitor array includes 2... k-1 One capacitor layer, and it receives one external control signal sel from INV. k k∈[1,K]. sel1~sel K The capacitor array is configured as a 4-stage array. Each sel consists of 4-bit digital control signals sel1 to sel4. One sel... k This is used to control the connection or disconnection of a capacitor array, thereby adjusting the total capacitance. The four-stage capacitor array consists of capacitor layers 1, 2, 4, and 8 in sequence. Each capacitor layer has the same structure, including: five NMOS transistors M5-M9 and two capacitors C6-C7. The gates of M5-M9 are connected and receive sel... k The drains of M7 and M9 are connected to the output of INV, and their sources are connected to the drains of M6 and M8, respectively. The input of INV also receives sel. kOne end of C6 is connected to the source of M6 and the drain of M5, and the other end is connected to VP. One end of C7 is connected to the source of M5 and M8, and the other end is connected to VN. SEL1 to SEL4 control the switching on and off of circuits with 1, 2, 4, and 8 identical capacitor layers, respectively. The capacitance values ​​of the switched capacitor array circuit are changed by binary weighting, thereby changing the output frequency of the oscillator and achieving coarse adjustment of the voltage-controlled oscillator frequency. Furthermore, in the on mode, SEL... k When control M5 is turned on, the capacitor array connected to VP and VN has the maximum capacitance value. In turn-off mode, sel k When control M5 is turned off, the capacitor array connected to VP and VN has the minimum capacitance value.

[0027] In this embodiment, the dynamic startup circuit employs a two-stage operational amplifier with sufficiently high gain. It includes components for connecting to the reference voltage V. ref The positive input terminal V in + Connect the negative input terminal V of the source stages M1 and M2. in - The output port V connects to R1 and R2. out The source voltage V of M1 and M2 S Enter to V in - V out Output bias voltage V bias Used to pass V ref Dynamic control of the gate voltages of M1 and M2 ensures the stability of the oscillator startup process. Simultaneously, its self-biased current mirror power supply results in extremely low static power consumption, effectively reducing the degradation of oscillator noise. Specifically, such as... Figure 3 As shown, the dynamic startup circuit includes: five NMOS transistors M10-M14, five PMOS transistors MP1-MP5, and two resistors R5-R6. The gates of MP3-MP5 are connected to the drain of MP3, and their sources are connected to VDD. The drain of MP4 is connected to the sources of MP1 and MP2. The drain of MP3 is connected to the drain of M11. One end of R6 is connected to the source of M11, and the other end is grounded. The gates of M10 and M11 are connected, and their sources are grounded. One end of R5 is connected to VDD, and the other end is connected to the drain and gate of M10. The gates of MP1 and MP2 are respectively connected to VDD. in + and V in - The drains of M12 and M13 are connected to each other, respectively. The sources of M12 and M13 are grounded. The drain and gate of M12 are connected. The drain of MP5 is connected to the source of M14, and a Vi is formed between them. outThe gate of M14 is connected to the drain of M13, and the drain is grounded. This dynamic startup circuit utilizes its high-gain virtual short characteristic to control V. S and V bias The oscillator is clamped to a preset value, thereby controlling the oscillator's startup process, increasing startup stability, and reducing the oscillator's phase noise.

[0028] In this embodiment, the bias circuit includes: two NMOS transistors M3 to M41 and one tail capacitor C. tail 1 filter capacitor C L In this case, the drain and gate of M3 are connected to the current source I. bias Source grounded. Gate of M4 connected to I. bias The drain is connected to the source of M1, and the source is grounded to provide the tail current I. tail C tail C L One end of each transistor is connected to the source of M1 and R2, while the other end is grounded. In another embodiment, M3 and M4 can be NMOS transistors with a width-to-length ratio of 1:4, allowing M4 to better utilize I... bias The oscillator is then powered by the current method.

[0029] The beneficial effects of this invention will be further illustrated below through simulation experiments. Please refer to... Figure 4 It refers to VP and V during the oscillator startup process in this invention. bias V S The simulation results change over time. (From...) Figure 4 It can be seen that the oscillation state of this voltage-controlled oscillator can be divided into three stages: in the pre-oscillation stage, the Vo of the dynamic start-up circuit... bias The source voltage V of M1 and M2 in the cross-coupled pair is stable at 770mV. S The voltage stabilizes at 250mV, therefore the cross-coupling results in a relatively large overdrive voltage for transistors M1 and M2 in the circuit, making it easier for the voltage-controlled oscillator to start oscillating. During the start-up phase, due to the high gain and virtual short effect of the operational amplifier in the dynamic startup circuit, V... S It was pulled up, and at the same time V bias It was pulled down. During the stable phase, V... S Stabilized to 350mV, compared to the preset V bias. ref At the same time, the output voltage is pulled down to 620mV, and the oscillator enters Class C operation mode, completing the oscillation start-up. At this point, the power consumption and phase noise performance of the voltage-controlled oscillator reach their optimal state.

[0030] Using a Class C voltage-controlled oscillator with a fixed voltage bias as a comparative example, its phase noise performance is compared with that of this embodiment, and the results are as follows: Figure 5As shown, with an oscillator center frequency of 19.8 GHz, the voltage-controlled oscillator with dynamic start-up circuit bias of this invention achieves a phase noise performance of -106.8 dBc / Hz at a 1 MHz bias frequency, while the voltage-controlled oscillator with fixed voltage bias has a phase noise of -104.7 dBc / Hz at the same 1 MHz bias frequency. This demonstrates that the voltage-controlled oscillator of this invention has superior phase noise performance.

[0031] Please refer to Figure 6 This is a simulation result of the frequency modulation curve of the oscillator in this invention. From... Figure 6 It can be seen that the voltage-controlled oscillator of the present invention controls the voltage V. ctrl It exhibits a wide frequency tuning range of 18.8 to 21.4 GHz when varying from 0 to 0.9 V; and at V ctrl Under the joint control of Sel, it has the functions of coarse frequency modulation and fine frequency modulation, indicating that the present invention has good frequency modulation characteristics.

[0032] In another embodiment, a phase-locked loop is also proposed, which includes a Class C voltage-controlled oscillator with low phase noise in the K-band as described in the above embodiment, which can effectively improve the signal-to-noise ratio and anti-interference capability of the phase-locked loop.

[0033] In another embodiment, a K-band low phase noise chip is also proposed, which is packaged from the K-band low phase noise Class C voltage-controlled oscillator as described in the above embodiment. The pins of the K-band low phase noise chip include:

[0034] One power supply pin for connecting to VDD. One ground pin for connecting to ground. One pin for connecting to I. bias The tail current pin. One for connecting V. ctrl One control pin. One bias pin for connecting to Vb. One bias pin for connecting to V. ref The reference pin. One first output pin for connecting to VP. One second output pin for connecting to VN. K signal pins, which connect to the switched capacitor array circuit, are used to receive K external control signals sel1 to sel2 respectively. K .

[0035] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A Class C voltage-controlled oscillator with low phase noise in the K-band, characterized in that, include: An oscillating circuit, used to provide an oscillation signal; It includes two output nodes VP and VN and one cross-coupled pair circuit; A switched capacitor array circuit, whose input terminal is connected to the control signal group sel and whose output terminal is connected to VP and VN; It is used to adjust the frequency of the oscillation signal by changing its own capacitance value according to sel; Dynamic start-up circuit, which is used to start based on reference voltage V ref To dynamically control the voltage of the cross-coupled circuit, thereby adjusting the amplitude of the oscillation signal; It includes: 5 NMOS transistors M10-M14, 5 PMOS transistors MP1-MP5, and 2 resistors R5-R6; the gates of MP3-MP5 are connected to the drain of MP3, and their sources are connected to the power supply VDD; the drain of MP4 is connected to the source of MP1 and MP2; the drain of MP3 is connected to the drain of M11; one end of R6 is connected to the source of M11, and the other end is grounded; the gates of M10 and M11 are connected, and their sources are grounded; one end of R5 is connected to VDD, and the other end is connected to the drain and gate of M10; the gates of MP1 and MP2 are respectively connected to VDD. ref The source and drain of the cross-coupled circuit are connected to the drains of M12 and M13 respectively; the sources of M12 and M13 are grounded; the drain and gate of M12 are connected; the drain of MP5 is connected to the source of M14 and is also connected to the gate of the cross-coupled circuit; the gate of M14 is connected to the drain of M13 and the drain is grounded.

2. The K-band low-phase-noise Class C voltage-controlled oscillator according to claim 1, characterized in that, The cross-coupled circuit includes two NMOS transistors M1 to M2, two resistors R1 to R2, and two capacitors C2 to C3; The drains of M1 and M2 are connected to VP and VN respectively; the gate of M1 is connected to the drain of M2 through C3, the drain is connected to the gate of M2 through C2, and the source is connected to the source of M2; the source of M1 and M2 is connected to the gate of MP2; one end of R1 and R2 is connected to the gate of M1 and M2 respectively, and the other end is connected to the drain of MP5.

3. The K-band low-phase-noise Class C voltage-controlled oscillator according to claim 2, characterized in that, The oscillation circuit also includes: an LC resonant unit and a bias circuit; The LC resonant unit includes: an inductor L, a capacitor C1, and a differential varactor resonant circuit group; the first end of L is connected to VDD, the second end is connected to one end of C1 to form VP, and the third end is connected to the other end of C1 to form VN; the differential varactor resonant circuit group is connected in parallel between VP and VN, and is connected to an external control voltage V. ctrl ; The bias circuit is connected to the source of M1 to provide the tail current I. tail .

4. The K-band low phase noise Class C voltage-controlled oscillator according to claim 3, characterized in that, The differential varactor resonant circuit group consists of two differential varactor resonant circuits connected in parallel; the differential varactor resonant circuit includes: two varactor transistors C var1 ~C var2 1. Two resistors R3 to R4; 2. Two capacitors C4 to C5; C var1 One end is connected to VP via C4 and to the bias voltage Vb via R3; C var2 One end is connected to VN via C5 and to Vb via R4; C var1 C var2 The other end is connected to V ctrl .

5. The K-band low-phase-noise Class C voltage-controlled oscillator according to claim 3, characterized in that, The bias circuit includes: two NMOS transistors M3 to M4, and one tail capacitor C. tail 1 filter capacitor C L ; Among them, the drain and gate of M3 are connected to current source I. bias Source grounded; gate of M4 connected to I. bias The drain is connected to the source of M1, and the source is grounded; C tail C L One end is connected to the source of M1 and R2 respectively, and the other end is grounded.

6. The K-band low-phase-noise Class C voltage-controlled oscillator according to claim 1, characterized in that, The switched capacitor array circuit includes: a K-level capacitor array and one inverter INV; The output of INV is connected to the input of the K-stage capacitor array; the output of the K-stage capacitor array is connected to VP and VN; the k-th stage capacitor array includes 2 k-1 One capacitor layer, and it receives one external control signal sel from INV. k ;k∈[1,K];sel1~sel K Composed of sel.

7. The K-band low-phase-noise Class C voltage-controlled oscillator according to claim 6, characterized in that, The capacitor layer in the k-th level capacitor array includes: 5 NMOS transistors M5 to M9 and 2 capacitors C6 to C7; The gates of M5 to M9 are connected, and sel is received. k The drains of M7 and M9 are connected to the output terminal of INV, and the sources are connected to the drains of M6 and M8 respectively; one end of C6 is connected to the source of M6 and the drain of M5, and the other end is connected to VP; one end of C7 is connected to the source of M5 and M8, and the other end is connected to VN.

8. The K-band low phase noise Class C voltage-controlled oscillator according to claim 7, characterized in that, When sel k When control M5 is turned on, the k-th stage capacitor array has the maximum capacitance value; when sel k When control M5 is turned off, the k-th stage capacitor array has the minimum capacitance value.

9. A phase-locked loop, characterized in that, It includes a Class C voltage-controlled oscillator with low phase noise in the K-band as described in any one of claims 1 to 8.

10. A K-band low phase noise chip, characterized in that, It is packaged as a K-band low phase noise Class C voltage-controlled oscillator as described in any one of claims 1 to 8; the pins of the K-band low phase noise chip include: One power supply pin for connecting to VDD; one ground pin for grounding; one pin for connecting to I... bias Tail current pin; 1 for connecting V ctrl One control pin; one bias pin for connecting to Vb; one bias pin for connecting to Vb. ref The system includes: a reference pin; a first output pin for connecting to VP; a second output pin for connecting to VN; and K signal pins connected to the switched capacitor array circuit, which are used to receive K control signals sel1 to sel2 respectively. K .

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