Buffer-in-loop-based novel error feedback noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) circuit structure

Abstract

The invention provides a Buffer-i n-loop-based novel error feedback noise shaping SAR ADC circuit structure, which comprises a noise feedback connector connected to the input end of a CDAC capacitor and one side of an input signal sampling capacitor, and is characterized in that the noise feedback connector comprises a gain amplifier and a residual voltage sampling capacitor; the residual voltage sampling capacitor is connected with the output of the gain amplifier through a switch; the CDAC capacitor is connected in parallel with the residual voltage sampling capacitor through a switch; and the CDAC capacitor is connected in series with the input end of the unity gain buffer through a switch. Through decoupling of a CDAC and a sampling capacitor in an NS-SAR ADC loop, noise shaping and fusion with other shaping modes are realized by adopting noise feedback connection.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, and in particular to a novel error feedback noise shaping SAR ADC circuit structure based on buffer-in-loop. Background Art

[0002] The noise-shaping SAR analog-to-digital converter (ADC) combines the advantages of delta-sigma and SAR ADCs, trading oversampling for reduced quantization noise and comparator noise. It features a simple structure, a high degree of digitization, low power consumption, and high energy efficiency. To further enhance the noise-shaping SAR's ability to drive the CDAC, a buffer-in-loop noise-shaping SAR was proposed.

[0003] Like noise-shaping SAR, there are two buffer-in-loop noise shaping methods. One is feedforward noise shaping, where the feedforward integrator circuit is L(z). By increasing the number of comparator input differential pairs or stacking capacitors carrying the integrated signal between the input signal sampling capacitor Cs and the comparator, the feedforward integrated signal and the input signal can be superimposed, thus achieving noise shaping. However, the disadvantages are that if multiple comparators are stacked, the number of comparator input pairs is large, leading to matching accuracy and noise issues. If capacitor stacking is used, parasitic capacitance in the signal path can be introduced, resulting in signal attenuation and a reduced signal-to-noise ratio. These issues are particularly prominent in high-order noise shaping.

[0004] The other type of noise shaping is feedback noise shaping, where a capacitor collects the residual voltage from the previous cycle and feeds it back to the input of the current cycle to achieve noise shaping. Like the feedforward method, the feedback type has two superposition methods: one is to feed back the residual voltage to the CDAC and superimpose it with the input voltage after sampling, and the other is to stack capacitors between the sampling capacitor and the comparator. The disadvantage of this method is the instability of the zero point of the quantization noise transfer function. Furthermore, if the residual voltage and input voltage are superimposed, the input voltage will be attenuated. If the capacitor stacking method is used, the same parasitic capacitance and signal attenuation issues as the feedforward method exist. Summary of the Invention

[0005] In view of the above-mentioned shortcomings, the present invention provides a novel error feedback noise shaping circuit structure based on buffer-in-loop. By utilizing the decoupling characteristics of CDAC and sampling capacitor, the residual voltage is collected and fed back to the CDAC, thereby reducing the circuit hardware cost without causing input voltage attenuation.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] A novel error feedback noise shaping circuit structure based on buffer-in-loop includes a noise feedback connection connected to the CDAC capacitor input and one side of the input signal sampling capacitor. The noise feedback connection includes a gain amplifier and a residual voltage sampling capacitor, and the residual voltage sampling capacitor is connected to the gain amplifier output through a switch.

[0008] The CDAC capacitor is connected in parallel with the margin voltage sampling capacitor through a switch; and the CDAC capacitor is connected in series with the unity gain buffer input terminal through a switch.

[0009] Furthermore, the margin voltage sampling capacitor is configured by the gain amplifier to store the margin voltage after sampling is completed.

[0010] Furthermore, when the residual voltage sampling capacitor or the CDAC capacitor is configured to be reset, the charges on the upper and lower plates of the residual voltage sampling capacitor or the CDAC capacitor are cleared.

[0011] Furthermore, the CDAC capacitor at the P terminal is configured to share charge with the CDAC capacitor at the N terminal when connected in parallel, and the CDAC capacitor at the N terminal is configured to obtain half of the margin voltage.

[0012] Furthermore, the residual voltage sampling capacitor is configured to perform charge sharing when connected in parallel with the CDAC capacitor at the P terminal through a switch.

[0013] The beneficial effects of this application are as follows:

[0014] (1) Enhance the driving capability of the NS-SAR analog-to-digital converter and reduce the difficulty of ADC AFE design.

[0015] (2) Eliminate the input signal attenuation problem caused by traditional EF NS-SAR.

[0016] (3) Reduce the number of capacitors required by traditional EF NS-SAR and reduce the area.

[0017] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0019] Figure 1 This is a schematic diagram of a signal flow graph of a feedback noise shaping SAR provided by the present invention.

[0020] Figure 2 This is a schematic diagram of the overall structure of a buffer-in-loop noise shaping SAR provided by the present invention.

[0021] Figure 3 This is a schematic diagram of specific implementation steps of the feedback noise shaping provided by the present invention.

[0022] Figure 4 This is a structural timing diagram corresponding to a feedback noise shaping circuit provided by the present invention.

[0023] Figure 5 This is a schematic diagram of a non-unit gain margin extraction amplifier provided by the present invention.

[0024] Figure 6 This is a schematic diagram of a SAR structure block diagram extended to high-order noise shaping provided by the present invention. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of this application more clearly understood, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] The present application provides a novel EF NS-SAR ADC structure based on buffer-in-loop. By utilizing the decoupling characteristics of CDAC and sampling capacitor, the residual voltage is collected and fed back to the CDAC. This reduces the circuit hardware cost without causing input voltage attenuation, while greatly enhancing the driving capability of the SAR ADC.

[0027] The following is a brief introduction to the design concept of the embodiments of this application.

[0028] like Figure 1As shown, a novel error feedback noise shaping circuit structure based on buffer-in-loop includes a noise feedback connection connected to the CDAC capacitor input end and one side of the input signal sampling capacitor. It is characterized in that the noise feedback connection includes a gain amplifier and a residual voltage sampling capacitor, and the residual voltage sampling capacitor is connected to the gain amplifier output through a switch.

[0029] The CDAC capacitor is connected in parallel with the margin voltage sampling capacitor through a switch; and the CDAC capacitor is connected in series with the unity gain buffer input terminal through a switch.

[0030] In specific implementation, Figure 2 The noise shaping circuit structure shown (single-ended example, actual operation is differential, H EF The residual extraction part is Figure 3 As shown, it includes a unity gain buffer and a margin sampling capacitor C ef , Figure 4 is the corresponding timing diagram.

[0031] The margin voltage sampling capacitor is configured by the gain amplifier to store the margin voltage after sampling is completed.

[0032] In specific implementation, Figure 3 The figure shows the steps for implementing the noise feedback shaping path. This invention utilizes the decoupling characteristics of the buffer-in-loop structure between the CDAC and the sampling capacitor. After sampling, the input voltage is no longer present on the CDAC, but is instead latched onto the input signal sampling capacitor, Cs. After the conversion phase, the gain amplifier removes the residual voltage from the previous cycle and feeds it back to the P-terminal of the CDAC, allowing the conversion of the current cycle to begin. Then, in the next cycle, the residual voltage stored on the P-terminal capacitor is transferred to the N-terminal for quantization, thus achieving second-order feedback noise shaping.

[0033] The margin voltage sampling capacitor or the CDAC capacitor connected to the P / N terminal is configured to clear the charges on its upper and lower plates when reset; the CDAC capacitor at the P terminal is configured to be connected in parallel with the CDAC capacitor at the N terminal and share charge, and the CDAC capacitor at the N terminal is configured to obtain half of the margin voltage; the margin voltage sampling capacitor is configured to be connected to the CDAC capacitor at the P terminal for charge sharing.

[0034] In specific implementation, Figure 3 As shown in (a), after sampling is completed, the residual voltage is stored in the residual voltage sampling capacitor C by a unity gain amplifier (such as a source follower). ef in; such as Figure 3 (b) and then reset the capacitors at the N-terminal to V cm, clear the stored charge on it; Figure 3 As shown in (c), the CDAC capacitor at the P end and the CDAC capacitor at the N end share charge, so that the residual voltage of the previous cycle is divided by two and transferred to the CDAC at the N end; Figure 3 As shown in (d), reset the upper and lower plates of the CDAC at the P end to V cm The two ends clear the stored charge; the capacitor C of the residual voltage of the previous cycle ef The charge is shared with the CDAC capacitor at the P end to realize the transfer of the residual voltage of the previous cycle. At this point, the second-order feedback noise shaping process is realized. Figure 3 (a) Corresponding timing Figure 4 ΦINT in, Figure 3 (b)-(e) Corresponding time series Figure 4 ΦEF in.

[0035] This structure can be adjusted or expanded. For example, it can only implement first-order noise shaping or second-order noise shaping, or it can be combined with a feedforward noise shaping method to achieve higher-order (such as third-order, fourth-order) noise shaping capabilities.

[0036] like Figure 5 As shown, the amplifier for margin extraction can provide a gain of A instead of unity gain, because the subsequent C ef When sharing charge with the P-side CDAC, there will be voltage attenuation. This improvement can offset the attenuation, thereby optimizing the pole position of the quantization noise transfer function and achieving a better shaping effect. Assuming C ef The capacitance is half of the capacitance of the P-terminal CDAC, and the residual extraction voltage provides a 6-fold gain. The quantization noise transfer function can be expressed as (1-z -1 ) 2 , to achieve ideal second-order noise shaping. Of course, in actual circuits, due to the existence of non-ideal factors, the ideal situation will not be achieved. The amplification factor can be adjusted appropriately.

[0037] like Figure 6 As shown, a higher-order expansion is performed on the basis of the feedback second-order noise shaping structure, such as adding a feedforward structure and connecting it in parallel with the feedback structure circuit. Since the headroom voltage extraction in the present invention is active extraction, it will not affect the headroom voltage, and the headroom voltage can be integrated with the feedforward noise shaping. Since the feedback noise shaping of the present invention uses fewer hardware structures and does not add redundant structures (such as capacitors) to the input signal path of the overall circuit, after combining it with the low-order feedforward architecture, high-order noise shaping can be achieved with less hardware expenditure, thereby achieving better energy efficiency.

[0038] Compared with the prior art, the novel error feedback noise shaping circuit of the present application has the following technical effects:

[0039] (1) Noise shaping is introduced into the buffer-in-loop architecture to enhance the circuit driving capability and reduce the capacitor array area.

[0040] (2) The CDAC capacitor in this structure does not participate in the input signal sampling, so when it participates in the feedback and shaping of the margin voltage, it avoids the attenuation of the input signal.

[0041] (3) No additional capacitors are required for capacitor stacking between the sampling capacitor and the comparator, which reduces parasitic effects and thus reduces signal attenuation in the signal path.

[0042] (4) The structure is simple, the hardware overhead is small, and it is easy to achieve second-order shaping effects and expand to higher orders.

[0043] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A novel error feedback noise shaping SAR ADC circuit structure based on buffer-in-loop, including a noise feedback connection connected to the CDAC capacitor input terminal and one side of the input signal sampling capacitor, characterized in that: The noise feedback connection includes a gain amplifier and a residual voltage sampling capacitor, and the residual voltage sampling capacitor is connected to the output of the gain amplifier through a switch; The CDAC capacitor is connected in parallel with the margin voltage sampling capacitor through a switch; and the CDAC capacitor is connected in series with the unity gain buffer input terminal through a switch.

2. The novel error feedback noise shaping SAR ADC circuit structure based on buffer-in-loop according to claim 1, characterized in that: The margin voltage sampling capacitor is configured by the gain amplifier to store the margin voltage after sampling is completed.

3. The novel error feedback noise shaping SAR ADC circuit structure based on buffer-in-loop according to claim 1, characterized in that: When the residual voltage sampling capacitor or the CDAC capacitor is configured to be reset, the charges on the upper and lower plates of the residual voltage sampling capacitor or the CDAC capacitor are cleared.

4. The novel error feedback noise shaping SAR ADC circuit structure based on buffer-in-loop according to claim 3, characterized in that: The CDAC capacitor at the P-terminal is configured to share charge when connected in parallel with the CDAC capacitor at the N-terminal, and the CDAC capacitor at the N-terminal is configured to obtain half of the margin voltage.

5. The novel error feedback noise shaping SAR ADC circuit structure based on buffer-in-loop according to claim 3, characterized in that: The residual voltage sampling capacitor is configured to perform charge sharing when connected in parallel with the CDAC capacitor at the P terminal through a switch.

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