A new error feedback noise shaping SAR ADC circuit structure based on buffer-in-loop
By introducing a buffer-in-loop structure into the SAR ADC circuit and using a gain amplifier and a margin voltage sampling capacitor to feed back noise, the problems of input signal attenuation and high hardware overhead in noise shaping are solved, achieving efficient noise shaping and enhanced driving capability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-27
- Publication Date
- 2026-04-10
AI Technical Summary
Existing noise-shaping SAR ADC circuits suffer from input signal attenuation and parasitic capacitance issues in high-order noise shaping, and have high hardware overhead, making it difficult to achieve efficient noise shaping.
A novel error feedback noise shaping circuit structure based on buffer-in-loop is adopted. By designing a gain amplifier and a margin voltage sampling capacitor, the margin voltage is fed back to the CDAC to achieve noise shaping, reduce the number of capacitors, and avoid input signal attenuation.
It enhances the driving capability of SAR ADC, reduces the number of capacitors and hardware costs, and achieves efficient noise shaping, making it suitable for high-order noise shaping.
Smart Images
Figure CN120768366B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of analog integrated circuits, in particular to a new error feedback noise shaping SAR ADC circuit structure based on Buffer-in-loop. BACKGROUND
[0002] Noise shaping SAR ADC combines the advantages of delta-sigma ADC and SAR ADC, reduces quantization noise and comparator noise in exchange for oversampling, has the characteristics of simple structure, high digitization, low power consumption and high energy efficiency, etc. In order to further enhance the driving ability of noise shaping SAR to CDAC, buffer-in-loop noise shaping SAR is proposed.
[0003] Like noise shaping SAR, there are two ways of noise shaping of buffer-in-loop. One is feedforward noise shaping, the feedforward integration circuit is L(z), by increasing the number of input differential pairs of the comparator, or stacking the capacitor with the integration signal between the input signal sampling capacitor Cs and the comparator, both can achieve the purpose of superimposing the feedforward integration signal and the input signal, thereby realizing the noise shaping function, the disadvantage is that if the multi-input comparator is superimposed, the number of input pairs of the comparator is large, which will bring the matching accuracy and noise problem, if the capacitor stacking method is used, the parasitic capacitance problem on the signal path will be brought, thereby causing signal attenuation and signal-to-noise ratio reduction, these problems are more prominent in high-order noise shaping.
[0004] The other is a feedback type noise shaping method, which feeds back the residual voltage of the last period to the input end of the current period after being collected by a capacitor, to achieve the purpose of noise shaping. Like feedforward, feedback has two superimposition methods, one is to feedback to CDAC and input voltage after sampling, and the other is to use capacitor stacking method to superimpose before sampling capacitor and comparator, the disadvantage is that the zero point of the quantization noise transfer function is unstable, at the same time, if the residual voltage and input voltage superimposition method is used, the input voltage attenuation is caused, if the capacitor stacking method is used, the parasitic capacitance and signal attenuation problem exists as the feedforward. SUMMARY
[0005] In view of the above-mentioned deficiencies existing at present, the present application provides a new error feedback noise shaping circuit structure based on Buffer-in-loop, which utilizes the decoupling characteristics of CDAC and sampling capacitor to feed back the residual voltage to CDAC, thereby reducing the circuit hardware expenditure without causing input voltage attenuation.
[0006] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:
[0007] The application discloses a new error feedback noise shaping circuit structure based on a buffer-in-loop, which comprises a noise feedback connection connected to a CDAC capacitor input end and an input signal sampling capacitor output end, and is characterized in that the noise feedback connection comprises a gain amplifier and a residual voltage sampling capacitor, and the residual voltage sampling capacitor is connected with the gain amplifier output through a switch.
[0008] The CDAC capacitor is connected with the residual voltage sampling capacitor through a switch; the input end of the gain amplifier is connected with the output end of the input signal sampling capacitor.
[0009] The voltage input end is connected with the input end of a unit gain buffer, and the output end of the unit gain buffer is connected with the input signal sampling capacitor.
[0010] The output end of the CDAC capacitor is connected with the input end of the unit gain buffer through a switch.
[0011] Further, the residual voltage sampling capacitor is configured to store the residual voltage after sampling by the gain amplifier.
[0012] Further, when the residual voltage sampling capacitor or the CDAC capacitor is configured to be reset, the residual voltage sampling capacitor or the CDAC capacitor is configured to clear the charges of the upper and lower plates.
[0013] Further, when the CDAC capacitor at the P end is configured to share charges with the CDAC capacitor at the N end, the CDAC capacitor at the N end is configured to obtain half of the residual voltage.
[0014] Further, when the residual voltage sampling capacitor is configured to share charges with the CDAC capacitor at the P end through a switch, the residual voltage sampling capacitor is configured to share charges with the CDAC capacitor at the P end.
[0015] The application has the following beneficial effects:
[0016] (1) The driving capability of the NS-SAR analog-to-digital converter is enhanced, and the AFE design difficulty of the ADC is reduced.
[0017] (2) The input signal attenuation problem caused by the traditional EF NS-SAR is eliminated.
[0018] (3) The number of capacitors required by the traditional EF NS-SAR is reduced, and the area is reduced.
[0019] Other features and advantages of the application will be set forth in the specification, and in part will become apparent to those skilled in the art upon reference to the specification, or can be learned by practice of the application. The objectives and other advantages of the application can be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.
[0021] Figure 1 The signal flow diagram of the basic feedback noise shaping SAR provided by the present application is shown in the figure.
[0022] Figure 2 The overall structure diagram of the buffer-in-loop noise shaping SAR provided by the present application is shown in the figure.
[0023] Figure 3 The specific implementation step diagram of the feedback noise shaping provided by the present application is shown in the figure.
[0024] Figure 4 The structure timing diagram corresponding to the feedback noise shaping circuit provided by the present application is shown in the figure.
[0025] Figure 5 The excess margin extraction amplifier with non-unit gain provided by the present application is shown in the figure.
[0026] Figure 6 The SAR structure block diagram of the new error feedback noise shaping SAR ADC circuit provided by the present application is shown in the figure. DETAILED DESCRIPTION
[0027] In order to make the purpose, technical solutions and advantages of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0028] The present application provides a new EF NS-SAR ADC structure based on Buffer-in-loop, which utilizes the characteristics of CDAC and sampling capacitor decoupling, and feeds back the excess voltage to CDAC. Without causing input voltage attenuation, the circuit hardware expenditure is reduced, and the driving capability of SAR ADC is greatly enhanced.
[0029] The design idea of the embodiments of the present application will be briefly introduced below.
[0030] As Figure 1 shown, is a basic error feedback noise shaping circuit structure diagram. The excess voltage is connected to the input Vin end through a feedback connection .
[0031] As Figure 2 shown, a new error feedback noise shaping circuit structure based on Buffer-in-loop, including a noise feedback connection connected to the CDAC capacitor input end and the input signal sampling capacitor output end , the noise feedback connection includes a gain amplifier and an excess voltage sampling capacitor (for Figure 3 (a)), and the excess voltage sampling capacitor is connected with the gain amplifier output through a switch;
[0032] The CDAC capacitor is connected with the excess voltage sampling capacitor through a switch; the input end of the gain amplifier and the output end of the input signal sampling capacitor are connected;
[0033] The voltage input end is connected to the input end of the unit gain buffer, and the output end of the unit gain buffer is connected to the input signal sampling capacitor;
[0034] The output end of the CDAC capacitor is connected with the unit gain buffer input end in series through a switch.
[0035] The single-ended example shown in the figure is actually differential, Figure 4 and the corresponding timing diagram is shown.
[0036] In the specific implementation, as Figure 3 shown, the corresponding is the implementation step of the noise feedback shaping path, and the application utilizes the decoupling characteristics of the buffer-in-loop structure for the CDAC and the sampling capacitor. After the sampling is completed, the input voltage does not exist on the CDAC, but is locked on the input signal sampling capacitor Cs. After the conversion phase is completed, the excess voltage of the last period is taken down by the gain amplifier, and then is fed back to the P end of the CDAC, enters the conversion of the current period, and then in the next period, the excess voltage stored on the capacitor of the P end is transferred to the N end for quantization, so as to realize the second-order feedback type noise shaping.
[0037] When the margin voltage sampling capacitor or the CDAC capacitor connected to the P / N terminal is configured to be reset, the charge on its upper and lower plates is cleared; when one of the CDAC capacitors DACP in the differential circuit is configured to be connected in parallel with the other CDAC capacitor DACN in the differential circuit, that is, the CDAC capacitor at the P terminal is configured to be connected in parallel with the CDAC capacitor at the N terminal and share charge, and the CDAC capacitor at the N terminal is configured to obtain half of the margin voltage; the margin voltage sampling capacitor is configured to share charge with the CDAC capacitor connected to the P terminal.
[0038] In specific implementation, such as Figure 3 As shown in (a), after sampling, the residual voltage is stored in the residual voltage sampling capacitor by a unity-gain amplifier (such as a source follower). In; as Figure 3 As shown in (b), the capacitor at terminal N is then reset to its original state. Clear the charge stored on it; such as Figure 3 As shown in (c), the CDAC capacitor at the P terminal and the CDAC capacitor at the N terminal share charge, thereby transferring the residual voltage of the previous cycle by dividing it by two to the CDAC at the N terminal; as Figure 3 As shown in (d), reset the upper and lower plates of the CDAC at the P terminal to... At both ends, clear the stored charge; the capacitor with the residual voltage from the previous cycle. By sharing charge with the CDAC capacitor at the P terminal, the residual voltage from the previous cycle is transferred, thus realizing the second-order feedback noise shaping process. Figure 3 (a) Corresponding timing Figure 3 ΦINT in Figure 4 (b)-(e) Corresponding timing Figure 3 ΦEF in.
[0039] This structure can be adjusted or extended. For example, it can be used to implement only first-order noise shaping or second-order noise shaping, or it can be combined with feedforward noise shaping methods to achieve higher-order (such as third-order and fourth-order) noise shaping capabilities.
[0040] like Figure 4 As shown, the amplifier with margin extraction can provide gain A instead of unity gain, due to subsequent... When sharing charge with the P-terminal CDAC, there will be voltage attenuation. This improvement can offset the attenuation, thereby optimizing the pole positions of the quantization noise transfer function and achieving better shaping results. Assuming... The capacitor is half the capacitance of the CDAC at the P-end, and the margin is used to extract voltage to provide a 6x gain. Therefore, the quantization noise transfer function can be expressed as: , to achieve the ideal second-order noise shaping, of course, in the actual circuit due to the presence of non-ideal factors, thus will not reach the ideal case, can be adjusted appropriately amplification.
[0041] As shown in Figure 5 Figure 6 The feedback type second-order noise shaping structure is expanded to a higher order, such as adding a feedforward structure in parallel with the feedback structure circuit. Since the residual voltage extraction in the application is active extraction, it will not affect the residual voltage, and the residual voltage can be combined with the feedforward noise shaping. Since the hardware structure used for feedback noise shaping in the application is less, and no additional structure (such as a capacitor) is added to the input signal path of the overall circuit, the combination of the low-order feedforward architecture can achieve high-order noise shaping with less hardware expenditure, thereby achieving a better energy efficiency ratio.
[0042] Compared with the prior art, the technical effects of the novel error feedback noise shaping circuit are:
[0043] Noise shaping is introduced in the buffer-in-loop architecture to enhance the circuit driving capability and reduce the capacitor array area.
[0044] The CDAC capacitor in the structure does not participate in the sampling of the input signal, so when participating in the feedback and shaping of the residual voltage, the attenuation of the input signal is avoided.
[0045] No additional capacitors are needed to stack the sampling capacitors and the capacitors between the comparators, reducing the parasitic effect and thus reducing the signal attenuation on the signal path.
[0046] The structure is simple, the hardware expenditure is small, and the second-order shaping effect can be easily achieved and expanded to a higher order.
[0047] The above is only a specific embodiment of the application, but the protection scope of the application is not limited thereto, any changes or replacements within the scope of the disclosed technology can be easily thought of by those skilled in the art, which should be covered within the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.
Claims
1. A novel error feedback noise shaping SAR ADC circuit structure based on Buffer-in-loop, comprising a noise feedback connection connected to a CDAC capacitor input and an input signal sampling capacitor output, characterized in that, The noise feedback connection includes a gain amplifier and a residual voltage sampling capacitor, and the residual voltage sampling capacitor is connected with the gain amplifier output through a switch; the CDAC capacitor is connected with the residual voltage sampling capacitor through a switch; the input of the gain amplifier is connected with the output of the input signal sampling capacitor; The voltage input is connected with the input of a unit gain buffer, and the output of the unit gain buffer is connected with the input signal sampling capacitor; The output of the CDAC capacitor is connected with the input of a unit gain buffer through a switch.
2. The novel error feedback noise shaping SAR ADC circuit structure based on Buffer-in-loop as claimed in claim 1, wherein, The residual voltage sampling capacitor is configured to store the residual voltage after sampling by the gain amplifier.
3. The new error feedback noise shaping SAR ADC circuit structure based on Buffer-in-loop as claimed in claim 1, wherein, When the residual voltage sampling capacitor or the CDAC capacitor is configured to reset, the upper and lower plates of the residual voltage sampling capacitor or the CDAC capacitor are charged.
4. The new error feedback noise shaping SAR ADC circuit structure based on Buffer-in-loop as claimed in claim 3, wherein, One of the DACP ends of the CDAC capacitor is configured to share the charge with the other DACN end of the CDAC capacitor when the two ends are connected, and the DACN end of the CDAC capacitor is configured to obtain half of the residual voltage.
5. The new error feedback noise shaping SAR ADC circuit structure based on Buffer-in-loop as claimed in claim 3, wherein, The residual voltage sampling capacitor is configured to share the charge with the DACP end of the CDAC capacitor when the two ends are connected through a switch.