Semiconductor process methods

Abstract

This invention provides a semiconductor process method, relating to the field of semiconductor manufacturing technology, to solve the problem of the contradiction between increasing the etching depth of fins within a trench and maintaining the protective layer on the trench sidewalls. The semiconductor process method includes: providing a film structure with trenches; a first etching step, etching a first SiN layer covering the top surface of the fins in a first process gas atmosphere; a second etching step, etching the top surface of the fins in a second process gas atmosphere to expose the first Si layer of the fins; and a third etching step, etching the first Si layer in a third process gas atmosphere such that the upper surface of the first Si layer is lower than the top surface of a first insulating layer, and the second SiN layers on both sides of the fins are higher than the third SiN layer covering the top surface of the first insulating layer. This method can alleviate the technical problem of the contradiction between increasing the etching depth of fins within a trench and maintaining the protective layer on the trench sidewalls.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor manufacturing process method. Background Technology

[0002] Plasma etching technology is widely used in large-scale integrated circuits to transfer design patterns from photoresist to wafers, completing the construction of semiconductor devices. With the continuous pursuit of processing performance and computing power, device dimensions are constantly shrinking. In integrated circuits with processes of 14nm and below, to solve the leakage problem caused by the short-channel effect, the transistor structure has changed from planar junction field-effect transistors to Fin-FETs (Fin-FETs) with three-dimensional gate structures. In the Fin-FET process, the fins need to be cut to achieve structural isolation, and the etching of part of the fins needs to be done within the laid trenches. When the trench size shrinks to below 20nm, the small space within the trench increases the difficulty of etching the fins within the trench, making it difficult to guarantee the etching depth of the fins. However, if we focus solely on improving the etching effect on the fins to ensure the etching depth, it may consume the protective layer on the sidewalls of the trench, resulting in excessively large critical dimensions (such as the trench width). Excessively large critical dimensions can lead to the failure of the surrounding structure. Therefore, there is a contradiction between increasing the etching depth of the fins in the trench and maintaining the protective layer on the sidewalls of the trench. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor process method to solve the technical problem of the contradiction between increasing the etching depth of the fins in the trench and maintaining the protective layer on the trench sidewalls.

[0004] The semiconductor process method provided by this invention includes:

[0005] A film structure is provided, the film structure including a trench, the trench having a fin and a first insulating layer located on both sides of the fin, the fin being higher than the first insulating layer, and the top surface and side surface of the fin and the top surface of the first insulating layer being covered with a SiN layer;

[0006] The first etching step involves etching the first SiN layer covering the top surface of the fin in a first process gas atmosphere.

[0007] In the second etching step, the top surface of the fin is etched in a second process gas atmosphere to expose the first Si layer of the fin.

[0008] In the third etching step, the first Si layer of the fin is etched in a third process gas atmosphere so that the upper surface of the first Si layer of the fin is lower than the top surface of the first insulating layer, and the second SiN layers on both sides of the fin are higher than the third SiN layer covered by the top surface of the first insulating layer.

[0009] Among them, the etching selectivity of the third process gas for Si and SiN is greater than that of the second process gas for Si and SiN, which is greater than that of the first process gas for Si and SiN.

[0010] The beneficial effects of the semiconductor process method of this invention are:

[0011] In the first etching step, a first process gas is used to strip the first SiN layer at the top of the fin. In the second etching step, a second process gas with a Si and SiN selectivity greater than that of the first process gas but less than that of the third process gas is used. This allows for the continued stripping of both the first Si and first SiN layers at the top of the fin, ensuring complete exposure of Si and facilitating continuous etching of the first Si layer in the fin in the third etching step. Simultaneously, by utilizing the moderate selectivity of the second process gas, the etching depth of the SiN layer on the trench sidewall can be controlled while the first Si and first SiN layers are being stripped, preventing excessive etching that could result in an oversized critical trench dimension.

[0012] In an optional technical solution, the first process gas includes CHF3 and CF4, wherein the flow rate of CHF3 is greater than the flow rate of CF4.

[0013] In an optional technical solution, the sidewalls of the trench and the top surface of the non-trench region are covered with a SiN layer; in the first etching step, the bias power adopts a pulse mode, and when the bias power is turned off, a carbon-containing polymer can be deposited on the SiN layer covering the sidewalls of the trench, the top surface of the non-trench region, the top surface of the first insulating layer, and the side surface of the fin.

[0014] In the optional technical solution, in the first etching step: the flow rate of CF4 is 25 sccm~100 sccm, the flow rate of CHF3 is 50 sccm~200 sccm; the first process gas also includes Ar, and the flow rate of Ar is 25 sccm~200 sccm;

[0015] And / or, the bias power is 100W~350W; the pulse frequency is 100Hz~500Hz; the pulse ratio is 15%~50%; and the etching time is 5s~25s.

[0016] And / or, the process pressure is 5mT~30mT; the etching temperature is 30℃~70℃; and the excitation power is 250w~600w.

[0017] In the optional technical solution, the bias power in the second etching step adopts a pulse mode.

[0018] In an optional technical solution, the second process gas includes HBr and O2, with the O2 flow rate being less than the HBr flow rate.

[0019] In an optional technical solution, in the second etching step: the flow rate of HBr is 100 sccm to 500 sccm, the flow rate of O2 is 0 sccm to 30 sccm; the second process gas also includes He, and the flow rate of He is 50 sccm to 400 sccm;

[0020] And / or, the bias power is 400W~800W; the pulse frequency is 100Hz~500Hz; the pulse ratio is 20%~60%; and the etching time is 20s~50s.

[0021] And / or, the process pressure is 5mT~30mT; the etching temperature is 30℃~70℃; and the excitation power is 700w~1200w.

[0022] In an optional technical solution, the third process gas includes HBr, O2, and Cl2, with the flow rates of O2 and Cl2 both being lower than the flow rate of HBr.

[0023] In an optional technical solution, in the third etching step: the flow rate of HBr is 300 sccm to 700 sccm, the flow rate of O2 is 10 sccm to 50 sccm, and the flow rate of Cl2 is 10 sccm to 60 sccm; the third process gas also includes He, and the flow rate of He is 30 sccm to 800 sccm.

[0024] And / or, the process pressure is 20mT~100mT; the etching temperature is 30℃~85℃; the excitation power is 800w~1600w; and the bias power is 400w~800w.

[0025] And / or, the pulse frequency is 100Hz~500Hz; the pulse ratio is 20%~60%; and the etching duration is 30s~120s. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments or background art of the present invention, the drawings used in the description of the embodiments or background art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0027] Figure 1This is a schematic flowchart of a semiconductor process method provided in an embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of the film structure etched by the semiconductor process method provided in the embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of the film structure etched by the semiconductor process method provided in the embodiment of the present invention at the end of the first etching step.

[0030] Figure 4 This is a schematic diagram of the film structure etched by the semiconductor process method provided in the embodiment of the present invention at the end of the second etching step.

[0031] Figure 5 This is a schematic diagram of the film structure etched by the semiconductor process method provided in the embodiment of the present invention at the end of the third etching step.

[0032] Explanation of reference numerals in the attached figures:

[0033] 10 - Trench; 11 - Fifth SiN layer;

[0034] 20 - Fin; 21 - First SiN layer; 22 - First Si layer; 23 - Second SiN layer;

[0035] 30 - Non-trench region; 31 - Fourth SiN layer; 32 - Second insulating layer; 33 - Second Si layer;

[0036] 40 - First insulating layer; 41 - Third SiN layer. Detailed Implementation

[0037] In related technologies, a breakthrough (BT) step with continuous power output is typically used to remove the SiN film layer on the fin tip and sidewalls. Then, HBr and high-flow-rate O2 are used as process gases in the main etching (ME) step. In the BT step, ensuring effective SiN film removal is crucial. Related technologies employ strong etching intensity to guarantee this, for example, by increasing bias power, increasing process gas flow rate, increasing process pressure, and extending etching time. While this preserves the SiN film layer on the fin tip and sidewalls, the process gases also etch the SiN layer on the trench sidewalls during this step, consuming some of the SiN layer and increasing the critical dimensions of the trench. Therefore, this step is suitable for situations where critical dimensions are not critical, but cannot meet high-standard requirements. However, if the etching intensity in the BT step is reduced or limited in order to meet the high standard requirements for the critical dimensions of the trench, the SiN film on the top and sidewalls of the fin will not be completely peeled off and will remain. As a result, in the subsequent ME step, the SiN film remaining on the top and sidewalls of the fin is likely to cause etching termination, resulting in the etching depth of the fin failing to meet the standard.

[0038] This invention provides a semiconductor process method that optimizes process steps and parameters to ensure both fin etching effect and critical trench dimensions. To make the objectives, features, and advantages of this invention more apparent and understandable, specific embodiments are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0039] Figure 1 This is a schematic flowchart of a semiconductor process method provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the film structure etched by the semiconductor process method provided in the embodiment of the present invention. Figure 3 This is a schematic diagram of the film structure etched by the semiconductor process method provided in the embodiment of the present invention at the end of the first etching step. Figure 4 This is a schematic diagram of the film structure etched by the semiconductor process method provided in the embodiment of the present invention at the end of the second etching step. Figure 5 This is a schematic diagram of the film structure etched by the semiconductor process method provided in this embodiment of the invention at the end of the third etching step. Figures 1-5 As shown, the semiconductor process method provided in Embodiment 1 of the present invention includes:

[0040] S102, a film structure is provided, the film structure includes a trench 10, the trench 10 has a fin 20 and a first insulating layer 40 located on both sides of the fin 20, the fin 20 is higher than the first insulating layer 40, and the top surface and side surface of the fin 20 and the top surface of the first insulating layer 40 are all covered with a SiN layer.

[0041] S104, First etching step, etching the first SiN layer 21 covering the top surface of the fin 20 in a first process gas atmosphere;

[0042] S106, Second etching step, etching the top surface of fin 20 in a second process gas atmosphere to expose the first Si layer 22 of fin 20;

[0043] S108, third etching step, etching the first Si layer 22 of the fin 20 in the third process gas atmosphere, so that the upper surface of the first Si layer 22 of the fin 20 is lower than the top surface of the first insulating layer 40, and the second SiN layer 23 on both sides of the fin 20 is higher than the third SiN layer 41 covered by the top surface of the first insulating layer 40.

[0044] Among them, the etching selectivity of the third process gas for Si and SiN is greater than that of the second process gas for Si and SiN, which is greater than that of the first process gas for Si and SiN.

[0045] In the first etching step S104, a first process gas is used to peel off the first SiN layer 21 at the top of the fin 20. In the second etching step S106, a second process gas with a Si and SiN selectivity greater than that of the first process gas but less than that of the third process gas is used. This allows for continued peeling of the first Si layer 22 at the top of the fin 20 and the first SiN layer 21 on the sidewall of the fin 20, ensuring complete exposure of Si. This facilitates continuous etching of the first Si layer of the fin 20 in the third etching step S108. Simultaneously, by utilizing the moderate selectivity of the second process gas, while continuing to peel off the first Si layer 22 and the first SiN layer 21 of the fin, the etching depth of the SiN layer on the sidewall of the trench 10—the fifth SiN layer 11—can be controlled, preventing excessive etching of the fifth SiN layer 11 and thus avoiding an excessively large critical dimension of the trench 10.

[0046] In the first etching step S104, the first SiN layer 21 at the top of the fin 20 is opened by taking advantage of the relatively small selectivity of the first process gas for Si and SiN, so that the first Si layer 22 of the fin 20 can be etched in the future. Although in the first etching step S104, while opening the first SiN layer 21 on the top of the fin 20, the fourth SiN layer 31 at the top of the non-trench region 30 is also etched, the fourth SiN layer 31 in the non-trench region 30 is thicker than the first SiN layer 21 at the top of the fin 20 because the area of ​​the non-trench region 30 is larger and it is easier to deposit and form a SiN layer in the previous steps. Even if the etching depth of the first SiN layer 21 and the fourth SiN layer 31 is the same, the loss of the fourth SiN layer 31 in the non-trench region 30 is smaller in the first etching step S104 and the second etching step S106. Even if the first SiN layer 21 is completely peeled off, a part of the fourth SiN layer 31 can still be retained in the thickness direction, so that the second insulating layer 32 is not directly exposed.

[0047] In the film structure, the SiN layer covering the top surface of the fin 20 is the first SiN layer 21; the SiN layer covering the side surface of the fin 20 is the second SiN layer 23; the SiN layer covering above the first insulating layer is the third SiN layer 41; the SiN layer covering the non-trench region is the fourth SiN layer 31; and the SiN layer covering the side surface of the trench 10 is the fifth SiN layer 11. The Si layer of the fin 20 is the first Si layer 22; and the Si layer in the non-trench region is the second Si layer 33. Furthermore, in this embodiment, a second insulating layer 32, i.e., an oxide layer—OX layer—is also provided on top of the second Si layer 33 in the non-trench region 30, and the fourth SiN layer 31 is located above the OX layer.

[0048] In this embodiment of the invention, the first process gas includes CHF3 and CF4, with the flow rate of CHF3 being greater than that of CF4. This configuration ensures effective stripping of the first SiN layer 21 at the tip of the fin 20 when the bias power is on. Furthermore, CHF3, with its higher C / F ratio than CF4, is more conducive to deposition. When the bias power is off, CHF3 facilitates the deposition of carbon-containing polymers on the sidewall surface of the trench 10 and the surface of the non-trench region 30, thus protecting the fifth SiN layer 11 on the sidewall surface of the trench 10 and the fourth SiN layer 31 on the surface of the non-trench region 30.

[0049] In this embodiment of the invention, the sidewalls of the trench 10 are covered with a SiN layer—the fifth SiN layer 11, and the top surface of the non-trench region 30 is covered with a SiN layer—the fourth SiN layer 31. In the first etching step S104, the bias power adopts a pulse mode. When the bias power is turned off, carbon-containing polymers can be deposited on the SiN layers covering the sidewalls of the trench 10, the top surface of the non-trench region 30, the top surface of the first insulating layer 40, and the side surface of the fin 20.

[0050] Since the bias power adopts a pulsed mode, when the bias power is turned off, the bombardment effect of the first process gas on the top of the film structure is significantly reduced, and the deposition tendency is significantly enhanced. Therefore, carbon-containing polymers can be deposited on the sidewalls of the trench 10 and in the non-trench region 30 to protect the corresponding surfaces in subsequent etching steps and reduce the consumption of these surfaces.

[0051] It should be noted that although carbon-containing polymers may also be deposited at the tip of fin 20, the critical dimensions at the tip of fin 20 are smaller, making it less likely for carbon-containing polymers to deposit compared to the non-trench region 30. Therefore, the amount of carbon-containing polymer deposited at the tip of fin 20 will be much less than that in the non-trench region 30, and will not have a significant impact on subsequent etching steps.

[0052] In this embodiment of the invention, in the first etching step S104: the flow rate of CF4 is 25 sccm to 100 sccm, the flow rate of CHF3 is 50 sccm to 200 sccm; the first process gas also includes Ar, with an Ar flow rate of 25 sccm to 200 sccm; the bias power is 100 W to 350 W; the pulse frequency is 100 Hz to 500 Hz; the pulse ratio is 15% to 50%; the etching time is 5 s to 25 s; the process pressure is 5 mT to 30 mT; the etching temperature is 30 °C to 70 °C; and the excitation power is 250 W to 600 W.

[0053] Because the first process gas has relatively low selectivity for etching Si and SiN, the etching time in the first etching step S104 is controlled to be 5s~25s. This short etching time prevents excessive consumption of the fifth SiN layer 11 on the sidewalls of the trench 10. Controlling the pulse ratio to the above proportion allows for the deposition of a carbon-containing polymer protective layer on the sidewalls of the trench 10, the top surface of the non-trench region 30, the top surface of the first insulating layer 40, and the sides of the fin 20 during the pulse power off-time of the etching time. Selecting the Ar flow rate within the above range controls the concentration of active particles, thereby appropriately controlling the etching rate and avoiding excessive consumption of the fifth SiN layer 11 on the sidewalls of the trench 10. Furthermore, this Ar flow rate can remove etching product particles, preventing them from contaminating the cavity and affecting the etching quality. Controlling the process pressure within the above range appropriately reduces the etching rate, thus preventing excessive consumption of the fifth SiN layer 11. By selecting the etching temperature within the above range, the reaction rate can be controlled to prevent excessive etching of the fifth SiN layer 11, and side reactions can be suppressed. Selecting the pulse frequency within the above range improves etching uniformity. Selecting the excitation power within the above range, compared to the subsequent second and third etching steps, results in a lower excitation power, thus controlling the plasma generation rate to be relatively low. This prevents the etching rate of the first SiN layer 21 in the first etching step from being too high, avoiding excessive plasma generation and over-etching of the remaining SiN layers.

[0054] In this embodiment of the invention, the bias power in the second etching step S106 adopts a pulse mode. This setting allows the carbon-containing polymer to be removed by the second process gas when the bias power is not turned on, which helps to prevent etching termination.

[0055] In this embodiment of the invention, the second process gas includes HBr and O2, with the O2 flow rate being lower than the HBr flow rate. This helps to control the etching selectivity of the second process gas for Si and SiN to prevent it from becoming too high. Therefore, while etching the first Si layer 22 of the fin 20, the second SiN layer 23 on the sidewall of the fin 20 can still be stripped, thereby reducing the height of the second SiN layer 23 on the sidewall of the fin 20. This prevents the remaining second SiN layer 23 on the sidewall of the fin 20 from being too high, which would prevent the first Si layer 22 of the fin 20 from being completely removed in subsequent etching steps, ultimately leading to etching termination. Because the spacing between adjacent second SiN layers 23 is too small, it is difficult for the third process gas to enter between adjacent second SiN layers 23, especially at the bottom of the space formed by adjacent second SiN layers 23.

[0056] Specifically, such as Figure 4As shown, after the second etching step S106, the second SiN layer 23 and the first Si layer 22 of the fin 20 are visible on the sidewall, and both are significantly reduced compared to after the first etching step S104. This facilitates the subsequent third etching step S108, where the Si of the fin 20 can be etched using a third process gas with higher selectivity for Si and SiN.

[0057] In this embodiment of the invention, in the second etching step S106: the flow rate of HBr is 100 sccm~500 sccm, the flow rate of O2 is 0 sccm~30 sccm; the second process gas also includes He, with a flow rate of 50 sccm~400 sccm; the bias power is 400 W~800 W; the pulse frequency is 100 Hz~500 Hz; the pulse ratio is 20%~60%; the etching time is 20 s~50 s; the process pressure is 5 mT~30 mT; the etching temperature is 30 ℃~70 ℃; and the excitation power is 700 W~1200 W.

[0058] The O2 flow rate is 0 sccm to 30 sccm, which does not mean the O2 flow rate can be zero. In fact, O2 is required in the second etching step S106, but the O2 flow rate is very low. By setting the HBr and O2 flow rates to these values, the etching rate can be increased, and the gas composition of the second process gas can be controlled to prevent the etching selectivity of the second process gas for Si and SiN from becoming too high. Compared to the first etching step S104, the bias power and excitation power in the second etching step S106 are increased, which can increase the etching rate of the second etching step S106 and reduce the time taken in the second etching step S106. Using He as the protective gas in the second process gas and selecting the flow rate within the above range can, on the one hand, adjust the etching rate and improve the etching uniformity, and on the other hand, suppress the regeneration of side reactions and remove etching product particles. Selecting the pulse frequency within the above range can improve etching uniformity. Furthermore, increasing the pulse ratio improves etching selectivity, allowing for a greater increase in the etching depth of the first Si layer 22 compared to the etching of the SiN layer. This reduces the loss of the fifth SiN layer 11 while ensuring the etching of the first Si layer 22. The significantly longer etching time compared to the first etching step is beneficial for etching the first Si layer 22 to reduce its height, while simultaneously etching the second SiN layer 23, reducing its height to facilitate deeper etching of the first Si layer 22 later. Controlling the process pressure within the above range reduces surface damage and suppresses side reactions. Selecting the etching temperature within the above range prevents excessively high reaction rates, avoiding the etching of too much of the fifth SiN layer 11 and suppressing side reactions.

[0059] In this embodiment of the invention, the third process gas includes HBr, O2, and Cl2, with the flow rates of O2 and Cl2 both lower than that of HBr. Adding O2 to the third process gas improves the etching selectivity of Si for SiN and OX, while using Cl2 increases the etching rate for Si. This shortens the etching time of the third etching step S108 while achieving the target etching depth in the fin 20. Furthermore, the combination of Cl2 and the high etching selectivity of the third process gas minimizes the impact on SiN and OX on the sidewalls of the trench 10 and the top of the non-trench region 30, protecting the SiN and OX at these locations.

[0060] It should be noted that although the third process gas has relatively high selectivity for etching Si and SiN, it does not completely prevent SiN from being etched. It simply means that SiN is etched more slowly compared to Si. Figure 5 and Figure 4 The comparison shows that after the third etching step S108, the SiN on the sidewall of fin 20 is significantly reduced compared to after the second etching step S106.

[0061] In this embodiment of the invention, in the third etching step S108: the flow rate of HBr is 300 sccm~700 sccm, the flow rate of O2 is 10 sccm~50 sccm, and the flow rate of Cl2 is 10 sccm~60 sccm; the third process gas also includes He, with a flow rate of 30 sccm~800 sccm; the process pressure is 20 mT~100 mT; the etching temperature is 30℃~85℃; the excitation power is 800 W~1600 W; the bias power is 400 W~800 W; the pulse frequency is 100 Hz~500 Hz; the pulse ratio is 20%~60%; and the etching duration is 30 s~120 s.

[0062] By using the above gas flow rate in the third etching step S108, compared to the second etching step S106, the gas flow rate is increased, thereby increasing the etching rate. Simultaneously, the increased He flow rate further improves etching uniformity and suppresses the regeneration of side reactions, while also removing etching product particles. Increasing the process pressure also increases plasma density and etching rate. Setting the etching temperature within the above range further increases the etching rate. Furthermore, increasing the excitation power improves the directionality of the process gas. Combined with the high etching selectivity of the third process gas for Si to SiN and Si to OX, this facilitates deeper etching of the Si in the fin 20 while reducing etching of the fifth SiN layer 11 on the sidewall of the trench 10, the fourth SiN layer 31 in the non-trench region 30, and the OX in the non-trench region 30, thus protecting the critical lateral dimensions of the trench 10. Selecting the pulse frequency within the above range improves etching uniformity. Furthermore, compared to the first etching step S102, the increased pulse ratio improves etching selectivity and allows for a greater increase in the etching depth of the first Si layer 22 compared to the etching of the SiN layer. This reduces the loss of the fifth SiN layer 11 while ensuring the etching of the first Si layer 22. By selecting the above etching duration and combining it with other parameters, the first SiN layer 22 of the fin can be etched more thoroughly, achieving the effect expected in the third etching step S108 of etching the upper surface of the first Si layer 22 to be lower than the top surface of the first insulating layer 40.

[0063] In this embodiment of the invention, the first SiN layer 21 at the top of the fin 20 is opened by using a bias power pulse mode in the first etching step S104; then, a second etching step S106 is performed using a second process gas with a high Si / SiN etching selectivity ratio as a follow-up to the first etching step S104 to etch the fin 20 and the SiN covering the sidewalls of the fin 20; finally, a third etching step S108 is performed using a third process gas with an even higher Si / SiN etching selectivity ratio to perform a rapid / deep etching of the fin 20. Therefore, it can be seen that in the semiconductor process method provided by the embodiments of the present invention, by optimizing the process formula, controlling different process gases, and timely changing the etching selectivity of process gases between different film layers, the consumption of the fourth SiN layer 31 in the non-trench region 30 is reduced. This achieves both ensuring sufficient etching depth for the first Si layer 22 of the fin 20 and limiting the etching of the fifth SiN layer on the sidewall of the trench 10, thereby ultimately ensuring the critical dimensions of the trench 10 and achieving etching mainly of the fin 20 within the trench 10, thus meeting the high requirements for etching of semiconductor devices.

[0064] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0065] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0066] In the above embodiments, descriptions of directions such as "up" and "down" are based on the accompanying drawings.

[0067] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.

[0068] Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of semiconductor processing, characterized by, The application relates to a film layer structure and a manufacturing method thereof. The film layer structure comprises a groove (10) with a fin (20) and a first insulating layer (40) on both sides of the fin (20), the fin (20) is higher than the first insulating layer (40), and the top surface of the fin (20), the side surface of the fin (20) and the top surface of the first insulating layer (40) are covered with SiN layers; A first etching step is adopted to etch the first SiN layer (21) covering the top surface of the fin (20) in a first process gas atmosphere; A second etching step is adopted to etch the top surface of the fin (20) in a second process gas atmosphere, so that the first Si layer (22) of the fin (20) is exposed; A third etching step is adopted to etch the first Si layer (22) of the fin (20) in a third process gas atmosphere, so that the upper end surface of the first Si layer (22) of the fin (20) is lower than the top surface of the first insulating layer (40), and the second SiN layer (23) on both sides of the fin (20) is higher than the third SiN layer (41) covering the top surface of the first insulating layer (40). The etching selectivity ratio of the third process gas to Si and SiN is greater than the etching selectivity ratio of the second process gas to Si and SiN, which is greater than the etching selectivity ratio of the first process gas to Si and SiN.

2. The semiconductor process method of claim 1, wherein, The first process gas comprises CHF3 and CF4, and the flow rate of the CHF3 is greater than that of the CF4.

3. The semiconductor process method of claim 2, wherein, The side wall of the groove (10) and the top surface of the non-groove area (30) are covered with SiN layers; In the first etching step, the bias power adopts a pulse mode, and when the bias power is turned off, carbon-containing polymers can be deposited on the SiN layers covering the side wall of the groove (10), the top surface of the non-groove area (30), the top surface of the first insulating layer (40) and the side surface of the fin (20).

4. The semiconductor process method of claim 3, wherein, In the first etching step, the flow rate of the CF4 is 25sccm-100sccm, the flow rate of the CHF3 is 50sccm-200sccm, the first process gas further comprises Ar, and the flow rate of the Ar is 25sccm-200sccm. And / or, the bias power is 100w-350w, the pulse frequency is 100Hz-500Hz, the pulse proportion is 15%-50%, and the etching time is 5s-25s. And / or, the process pressure is 5mT-30mT, the etching temperature is 30 DEG C-70 DEG C, and the excitation power is 250w-600w.

5. The semiconductor process method of any one of claims 1-4, wherein, In the second etching step, the bias power adopts a pulse mode.

6. The semiconductor process method of any one of claims 1-4, wherein, The second process gas comprises HBr and O2, and the flow rate of the O2 is less than that of the HBr.

7. The semiconductor process method of claim 6, wherein, In the second etching step, the flow rate of the HBr is 100sccm-500sccm, the flow rate of the O2 is 0sccm-30sccm, the second process gas further comprises He, and the flow rate of the He is 50sccm-400sccm. And / or, the bias power is 400w-800w, the pulse frequency is 100Hz-500Hz, the pulse proportion is 20%-60%, and the etching time is 20s-50s. And / or, the process pressure is 5mT~30mT; the etching temperature is 30℃~70℃; the excitation power is 700w~1200w.

8. The semiconductor process method of any one of claims 1-4, wherein, The third process gas comprises HBr, O2 and Cl2, and the flow rates of O2 and Cl2 are both less than the flow rate of HBr.

9. The semiconductor process method of claim 8, wherein, In the third etching step, the flow rate of HBr is 300sccm~700sccm, the flow rate of O2 is 10sccm~50sccm, and the flow rate of Cl2 is 10sccm~60sccm; the third process gas further comprises He, and the flow rate of He is 30sccm~800sccm. And / or, the process pressure is 20mT~100mT; the etching temperature is 30℃~85℃; the excitation power is 800w~1600w; and the bias power is 400w~800w.

10. The semiconductor process method of claim 8, wherein, In the third etching step, the pulse frequency is 100Hz~500Hz; the pulse duty cycle is 20%~60%; and the etching duration is 30s~120s.

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