An etching method of a semiconductor device

Abstract

The application provides an etching method of a semiconductor device, which comprises the following steps: providing a preset substrate; the preset substrate comprises a plurality of stack structures formed by a channel layer and a sacrifice layer, and a groove formed between the stack structures; a diffusion layer etching step, a first etching gas is introduced into a chamber to etch both sides of the stack structure, so that a diffusion layer formed by Ge components in the sacrifice layer diffused to the sidewall of both sides of the stack structure is etched and removed; the first etching gas comprises a hydrogen-containing gas and a bromine-containing gas; a sacrifice layer etching step, a second etching gas and a third etching gas are alternately introduced into the chamber to selectively etch the sacrifice layer on both sides of the stack structure, so that a groove is formed on both sides of the sacrifice layer; the second etching gas comprises a protective gas of the channel layer, and the third etching gas comprises a fluorocarbon-based gas for etching the sacrifice layer. The application can effectively reduce the rounding amount of the sacrifice layer, avoid affecting the size of the stack structure and the isolation depth, and improve the product yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an etching method for semiconductor devices. Background Technology

[0002] One of the key processes in manufacturing gate-all-around field-effect transistors (GAA-FETs) is the selective etching of portions of the SiGe sacrificial layer to form an inner spacer. This separates the channel from the source / drain regions and defines the gate length. Before the formation of the inner spacer, due to the wafer bias power Vpp being greater than 1000V during anisotropic etching of the SiGe / Si stack, ions transfer energy to Ge atoms, providing sufficient energy for Ge diffusion. The diffusion of Ge atoms on the Si surface is accelerated by ion bombardment, resulting in a gradient distribution of Ge composition near the Si / SiGe stack interface. (See Figure...) Figure 1a The diagram shows the diffusion of Ge composition in the SiGe sacrificial layer. Because the Si-Ge bond energy is lower than the Si-Si bond energy, in related SiGe sacrificial layer etching techniques using fluorine-containing plasma, the SiGe etching rate decreases as the Ge composition decreases. Therefore, the SiGe etching rate near the SiGe / Si interface is lower than the etching rate at the center of the SiGe sacrificial layer, as shown in the figure. Figure 1b The diagram shown illustrates the crescent shape and rounding amount formed before the etching of the SiGe sacrificial layer. The resulting difference in etching rate causes the sidewalls of the SiGe layer to become rounded, which in turn causes the subsequently grown internal spacer layer to also have a crescent shape. This worsens the physical isolation between the gate and the source / drain epitaxial layer, making it easier to expose the source / drain epitaxial layer during the downstream channel release process, thus affecting the isolation depth and reducing product yield. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide an etching method for semiconductor devices that can effectively reduce the rounding amount of the sacrificial layer, avoid affecting the size and isolation depth of the stacked structure, and improve product yield.

[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0005] In a first aspect, embodiments of the present invention provide an etching method for a semiconductor device, comprising:

[0006] A preset substrate is provided; wherein the preset substrate includes multiple stacked structures formed by a channel layer and a sacrificial layer, and trenches formed between the stacked structures;

[0007] A diffusion layer etching step, a first etching gas is introduced into the chamber to etch both sides of the stack structure, so as to etch and remove the diffusion layer formed on the sidewalls of the stack structure on both sides by diffusing Ge component in the sacrificial layer to the channel layer; wherein the first etching gas comprises hydrogen-containing gas and bromine-containing gas;

[0008] A sacrificial layer etching step, a second etching gas and a third etching gas are alternately introduced into the chamber to selectively etch the sacrificial layer on both sides of the stack structure, so as to form a groove on both sides of the sacrificial layer; wherein the second etching gas comprises a protective gas of the channel layer, and the third etching gas comprises a fluorocarbon-based gas for etching the sacrificial layer.

[0009] Further, the embodiment of the present application provides a first possible implementation manner of the first aspect, wherein the first etching gas comprises hydrogen bromide and nitrogen, and the process time of the diffusion layer etching step is 5-10s.

[0010] Further, the embodiment of the present application provides a second possible implementation manner of the first aspect, wherein the flow rate ratio of the hydrogen bromide and the nitrogen ranges from 20:1 to 50:1.

[0011] Further, the embodiment of the present application provides a third possible implementation manner of the first aspect, wherein the protective gas comprises oxygen.

[0012] Further, the embodiment of the present application provides a fourth possible implementation manner of the first aspect, wherein the fluorocarbon-based gas comprises C4F6 and CF4.

[0013] Further, the embodiment of the present application provides a fifth possible implementation manner of the first aspect, wherein the flow rate ratio of the C4F6 and the CF4 is 1:6-1:10.

[0014] Further, the embodiment of the present application provides a sixth possible implementation manner of the first aspect, wherein in each cycle, the second etching gas is introduced for 5-10s, and the third etching gas is introduced for 5-8s.

[0015] Further, the embodiment of the present application provides a seventh possible implementation manner of the first aspect, wherein the etching mode of the diffusion layer etching step adopts plasma etching, the upper electrode radio frequency power in the diffusion layer etching step ranges from 600 to 1000W, and the lower electrode radio frequency power is 0.

[0016] Further, the embodiment of the present application provides an eighth possible implementation manner of the first aspect, wherein the forming step of the preset substrate comprises:

[0017] alternately epitaxially growing the sacrificial layer and the channel layer on the substrate;

[0018] forming a hard mask layer on the sacrificial layer and the channel layer, and patterning the hard mask layer;

[0019] introducing a fourth etching gas into the chamber, taking the patterned hard mask layer as a mask to etch the channel layer, the sacrificial layer and the substrate, so as to form a plurality of the stack structures and form a groove between adjacent stack structures; wherein the depth of the groove is greater than the thickness of the stack structure.

[0020] Further, the embodiment of the present application provides a ninth possible implementation manner of the first aspect, wherein before the diffusion layer etching step, the method further comprises:

[0021] a cleaning step of cleaning the preset substrate by using a preset cleaning liquid in a cleaning device to remove the polymer and the oxide layer on the surface.

[0022] The embodiment of the present application provides an etching method of a semiconductor device, which comprises: providing a preset substrate; wherein the preset substrate comprises a plurality of stack structures formed by a channel layer and a sacrificial layer, and a groove formed between the stack structures; a diffusion layer etching step of introducing a first etching gas into a chamber to etch both sides of the stack structure, so as to etch and remove a diffusion layer formed by Ge components in the sacrificial layer diffusing to the sidewall of both sides of the stack structure; wherein the first etching gas comprises a hydrogen-containing gas and a bromine-containing gas; a sacrificial layer etching step of alternately introducing a second etching gas and a third etching gas into the chamber to selectively etch the sacrificial layer on both sides of the stack structure, so as to form a groove on both sides of the sacrificial layer; wherein the second etching gas comprises a protective gas of the channel layer, and the third etching gas comprises a fluorocarbon-based gas for etching the sacrificial layer. By using the hydrogen-containing gas and the bromine-containing gas etching gas to etch the diffusion layer formed by the Ge components in the sacrificial layer diffusing to the sidewall of both sides of the stack structure before selectively etching the sacrificial layer in the stack structure, the rounding amount of the sacrificial layer can be effectively reduced. Since the diffusion layer formed by the Ge components diffusing in the stack structure is usually only an atomic level thickness, the size of the stack structure and the isolation depth can be avoided from being affected, and the product yield is improved.

[0023] Other features and advantages of the embodiments of the present application will be described in the following description, or can be learned from the description, or can be determined without any doubt from the description, or can be known by implementing the above-mentioned technologies of the embodiments of the present application.

[0024] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0026] Figure 1a A SiGe sacrificial layer Ge composition diffusion schematic diagram is shown.

[0027] Figure 1b A SiGe sacrificial layer etching pre-formation of crescent shape and rounding amount schematic diagram is shown.

[0028] Figure 2 An etching method flow chart of a semiconductor device provided by the embodiment of the present application is shown.

[0029] Figure 3 A preset substrate structure schematic diagram provided by the embodiment of the present application is shown.

[0030] Figure 4a An amplification schematic diagram of diffusion layer formed by the sidewall of the two sides of the stack structure provided by the embodiment of the present application is shown.

[0031] Figure 4b A preset substrate structure schematic diagram after the diffusion layer etching step provided by the embodiment of the present application is shown.

[0032] Figure 5 A preset substrate structure schematic diagram after the sacrificial layer etching step provided by the embodiment of the present application is shown.

[0033] Figure 6 A preset substrate formation schematic diagram provided by the embodiment of the present application is shown. Specific embodiments

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the present application will be described below in combination with the drawings. Obviously, the described embodiments are some embodiments of the present application, not all embodiments.

[0035] At present, with the continuous advancement of Moore's law, the integrated circuit (IC) manufacturing process enters the 5nm technology node, and the fin field effect transistor (Fin-FET) is difficult to continue to improve the performance of semiconductor devices, and the technology faces major innovation. The gate-all-around field effect transistor (GAA-FET) structure can achieve better control of the field effect transistor channel because the contact area of the gate and the channel is larger, increasing from three-side contact of FinFET structure to four-side contact of GAA structure, which will greatly reduce the gate length or device feature size, and is considered as the main candidate technology for 3-5nm node transistors.

[0036] The related gate-all-around field effect transistor etching technology generally uses SiO2 as a hard mask after epitaxially growing a stack layer formed by a SiGe layer and a Si layer, performs anisotropic etching on the stack layer by Cl-based plasma, then performs "post-etching treatment", uses a cleaning solution to clean the surface oxide, and finally performs SiGe selective isotropic etching by using a plasma etching machine. By performing "post-etching treatment" after anisotropic etching of the Si / SiGe stack layer, the improvement of the SiGe rounding amount is limited, and the separate "post-etching treatment" step makes the process flow more complicated, which is not conducive to improving the process efficiency. To improve the above problems, the embodiment of the present application provides an etching method of a semiconductor device, which will be described in detail below.

[0037] The embodiment provides an etching method of a semiconductor device, which can be applied to a semiconductor process equipment, referring to the flow chart of the etching method of the semiconductor device shown in the figure, Figure 2 The method mainly comprises the following steps:

[0038] Step S202, providing a preset substrate;

[0039] Referring to the preset substrate structure schematic diagram as shown in the figure, Figure 3 The preset substrate comprises a plurality of stack structures 30 formed by a channel layer 31 and a sacrificial layer 32, and a groove 33 formed between the stack structures 30; as shown in the figure, Figure 3 The stack structure 30 is located above the substrate 20, the depth of the groove 33 is greater than the thickness of the stack structure 30, and the bottom of the groove 33 is located below the interface between the stack structure 30 and the substrate 20.

[0040] Step S204, diffusion layer etching step, introducing a first etching gas into the chamber to etch both sides of the stack structure, so as to etch and remove the Ge component in the sacrificial layer diffused to the diffusion layer formed on the sidewall of the stack structure on both sides;

[0041] The aforementioned pre-defined substrate is introduced into the reaction chamber. Before selectively etching the sacrificial layer, a first etching gas, comprising hydrogen-containing gas and bromine-containing gas, is introduced into the chamber to etch the non-uniform Ge diffusion layers on both sides of the stacked structure. In the aforementioned stacked structure, the channel layer is a Si layer, and the sacrificial layer is a SiGe layer.

[0042] The stacked structure (also known as a Si / SiGe stack) provides sufficient energy for Ge diffusion during anisotropic etching, resulting in a gradient distribution of Ge composition near the interface between the channel layer and the sacrificial layer of the Si / SiGe stack. (See example...) Figure 4a The diagram shows an enlarged view of the diffusion layers formed on both sidewalls of the stacked structure. The Ge component in the sacrificial layer diffuses into the channel layer, forming diffusion layers 40 on both sidewalls of the stacked structure. Since the Si-Si bond energy (2.31 eV) is greater than the Si-Ge bond energy (2.12 eV), the Si-Ge bonds are more easily opened during etching than the Si-Si bonds. By using hydrogen-containing and bromine-containing gases for plasma etching of the diffusion layer 40, compared to other etching gases (such as F-based and Cl-based gases), it does not cause significant lateral damage to the channel layer and can remove the diffusion layer formed by the non-uniform Ge component. The reactions generated during the etching process are as follows:

[0043] HBr(g) → H· + Br·

[0044] Ge·+H·+ Br·→GeH x Bry (g)

[0045] Si· + H· + Br· → SiH x Bry (g)

[0046] In one embodiment, the first etching gas provided in this embodiment includes hydrogen bromide and nitrogen, and the process time of the diffusion layer etching step is 5 to 10 seconds.

[0047] The Ge component in the sacrificial layer diffuses into the channel layer. The diffusion layer formed on both sidewalls of the stacked structure is typically only atomically thick, see example... Figure 4b The schematic diagram of the preset substrate structure after the diffusion layer etching step shows that etching the diffusion layer for a short time does not significantly change the sidewall morphology of the stacked structure. Adding nitrogen to the etching gas can improve the selectivity of the sacrificial layer for the upper hard mask layer.

[0048] In one embodiment, during the diffusion layer etching step, the flow rate ratio of hydrogen bromide to nitrogen ranges from 20:1 to 50:1. The process parameters during etching can be set as follows: process chamber vacuum range of 4–10 mT, upper electrode RF power range of 600–1000 W, lower electrode RF power of 0 (i.e., no bias power), as the absence of bias power reduces the impact on the shallow trench isolation depth; etching temperature range of 40°C–70°C; and HBr and N2 as the main etching gases, with HBr flow rate ranging from 200–500 sccm and N2 flow rate ranging from 10–30 sccm.

[0049] Step S206, sacrificial layer etching step, alternately introducing a second etching gas and a third etching gas into the chamber to selectively etch the sacrificial layer on both sides of the stacked structure to form grooves on both sides of the sacrificial layer.

[0050] The second etching gas includes a protective gas for the channel layer, and the third etching gas includes a fluorocarbon-based gas for etching the sacrificial layer. The number of alternating cycles of the second and third etching gases can be determined according to the size requirements of the sacrificial layer. See also... Figure 5 The schematic diagram of the preset substrate structure after the sacrificial layer etching step is shown. The atomic layer etching (ALE) method is used to selectively etch both sides of the sacrificial layer in the stacked structure. The sacrificial layer 32 is oxidized and protected based on the second etching gas and etched based on the third etching gas in an alternating cycle to form grooves 50 on both sides of the sacrificial layer 32.

[0051] The protective gas can be an oxidizing gas, such as oxygen, to achieve the purpose of oxidizing and protecting the channel layer. In a specific embodiment, the protective gas provided in this embodiment includes oxygen. The main function of O2 plasma treatment is to oxidize and protect the Si layer and oxidize the SiGe layer. The preferred range of process parameters for this step is: process chamber vacuum degree range of 15-30 mT, upper electrode RF power range of 300-600 W, no bias power, oxidation temperature range of 40℃-60℃, O2 as the main gas in the oxidation step, O2 gas flow rate range of 100-300 sccm, and the introduction time of the second etching gas is 5-10 s. The oxidation protection process is self-limiting, that is, the oxidation protection will reach saturation after a certain time. If the introduction time of the second etching gas is further increased, the oxidation process will no longer continue. The oxidation time is related to the Si and Ge composition ratio of the SiGe material and is affected by the process parameters. SiGe is oxidized to SiGe under O2 plasma. x O y Si is oxidized to SiO2. Since the oxide needs to break its original covalent bonds before forming an oxide, SiGe is more easily oxidized than Si. The reaction between oxygen and the sacrificial layer is as follows:

[0052] SiGe(s) + O2(g) → SiOy(s) + Ge(s) x O y (s)

[0053] Since the Si-O bond energy (9.0 eV) is greater than the Ge-O bond energy (5.0 eV), the Si-O-Ge bond energy is between the two, and the carbon-fluorine-based gas etching oxide can form volatile SiF x , GeF x and CO or CO2, and the reaction is as follows:

[0054] SiGe x Oy(s) + F· + C· → SiF x (g) + GeF x (g) + CO / CO2(g)

[0055] The carbon-fluorine-based gas can include C4F6, CF4, CF4, and C4F8, and in an embodiment, the carbon-fluorine-based gas provided in the present embodiment includes C4F6 and CF4.

[0056] The flow ratio of C4F6 and CF4 provided in the present embodiment is 1:6-1:10. The gas flow ratio range of C4F6 and CF4 cannot be too high, because the lack of O in SiGe cannot make the rich C produce volatile CO or CO2, and increasing the C / F ratio will inhibit the etching of the SiGe surface. By setting the flow ratio of C4F6 and CF4 to 1:6-1:10, the etching rate of SiGe can be much higher than that of Si, and selective etching of SiGe is achieved.

[0057] When the third etching gas is introduced to selectively etch the sacrificial layer, the process parameters are preferably in the following ranges: the process chamber vacuum degree is 40-70 mT, the upper electrode RF power is 300-700 W, there is no bias power, the etching temperature is 40-60°C, the total flow rate of C4F6 and CF4 is 200-300 sccm, and the introduction time of the third etching gas is 5-8 s.

[0058] By using the atomic layer etching method to selectively etch the sacrificial layer, and based on the alternating circulation of oxygen plasma treatment and carbon-fluorine-based gas selective etching of the SiGe layer, the purpose of quantitatively etching the sacrificial layer on both sides can be achieved.

[0059] The etching method of the semiconductor device provided by the embodiment can effectively reduce the rounding amount of the sacrificial layer by etching the diffusion layer formed on the sidewalls of the stack structure on both sides by diffusing the Ge component in the sacrificial layer to the diffusion layer before etching the sacrificial layer in the stack structure, and the diffusion layer formed by diffusing the Ge component in the stack structure is usually only atomic thickness, so that the size of the stack structure and the isolation depth can be avoided from being affected, and the product yield is improved.

[0060] In one embodiment, the method provided by the embodiment includes the following steps of forming a preset substrate:

[0061] Referring to a preset substrate formation schematic diagram as shown in Figure 6 The sacrificial layer 32 and the channel layer 31 are alternately epitaxially grown on the substrate 20.

[0062] The hard mask layer 60 is formed on the stack of the sacrificial layer 32 and the channel layer 31, and the hard mask layer 60 is patterned.

[0063] The fourth etching gas is introduced into the chamber, and the channel layer 31, the sacrificial layer 32 and the substrate 20 are etched by taking the patterned hard mask layer 60 as a mask, as shown in Figure 3 to form a plurality of stack structures 30 and form a groove 33 between adjacent stack structures; and the depth of the groove 33 is greater than the thickness of the stack structure 30.

[0064] The Si / SiGe (1%≤Ge≤25%) stack is epitaxially grown on the substrate, and the pattern transfer is realized by a self-aligned double exposure pattern (SADP) or a self-aligned quadruple exposure pattern (SAQP) technology to pattern the hard mask layer.

[0065] The fourth etching gas can include HBr, O2 and N2. By using HBr and O2, the hard mask pattern can be accurately transmitted, and the etching morphology is optimized. By adding nitrogen in the etching gas, the selectivity of the stack structure to the hard mask layer can be improved. In one embodiment, during the etching process, the chamber pressure can be controlled in the range of 5-10 mT, 200-400 sccm of HBr gas is introduced into the chamber, 5-15 sccm of O2 is introduced into the chamber, the upper electrode radio frequency power is controlled in the range of 800-1200 W, the bias power is controlled in the range of 150-300 W, and the etching time is controlled in the range of 20-50 s.

[0066] In one embodiment, before the diffusion layer etching step, the method provided by the embodiment further includes:

[0067] The cleaning step involves using a pre-set cleaning solution in a cleaning device to clean a pre-set substrate in order to remove the polymer and oxide layer on the surface.

[0068] The pre-set cleaning solution used in this cleaning step can be a 1% concentration hydrofluoric acid solution, the cleaning device can be a tank cleaning machine, the cleaning time can be 15-35 seconds, and the temperature can be kept at room temperature. This can clean and remove polymer and oxide layers from the wafer surface.

[0069] The etching method for the semiconductor device provided in this embodiment, by using hydrogen bromide and nitrogen as the main etching gases before selectively etching the sacrificial layer, can effectively reduce the SiGe rounding amount in a short time without affecting the stack-up structure size and isolation depth.

[0070] Based on the foregoing embodiments, this embodiment provides an example of using the aforementioned semiconductor device etching method to improve the morphology of the SiGe sacrificial layer in the etching of a ring gate structure. The specific steps are as follows:

[0071] Step 1, as follows Figure 6 As shown, a sacrificial layer 32 and a channel layer 31 are alternately epitaxially grown on a substrate, and a hard mask layer 60 is formed on the sacrificial layer 32 and the channel layer 31. Pattern transfer is achieved by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) techniques to pattern the hard mask layer 60.

[0072] Step 2: HBr, O2, and N2 are introduced into the chamber. Using the patterned hard mask layer 60 as a mask, the channel layer 31, sacrificial layer 32, and substrate 20 are etched, as shown below. Figure 3 As shown, multiple stacked structures 30 are formed and grooves 33 are formed between adjacent stacked structures;

[0073] During the etching process, the chamber pressure is controlled within the range of 5–10 mT, 200–400 sccm of HBr gas is introduced into the chamber, 5–15 sccm of O2 is introduced into the chamber, the upper electrode RF power is controlled within the range of 800–1200 W, the bias power is controlled within the range of 150–300 W, and the etching time is controlled within the range of 20–50 s.

[0074] Step 3, cleaning step: Use a 1% concentration of hydrofluoric acid solution to clean the wafer containing the preset substrate to remove the polymer and oxide layer on the surface.

[0075] The cleaning device can be a tank cleaning machine, the cleaning time can be 15-35s, the temperature can be kept at room temperature, and the polymer and oxide layer on the wafer surface can be cleaned and removed.

[0076] Step 4, diffusion layer etching step (BT (break through) step), HBr and N2 are introduced into the chamber to etch the two sides of the stack structure, so as to etch and remove the Ge component in the SiGe sacrificial layer to diffuse into the diffusion layer formed on the sidewall of the stack structure on both sides;

[0077] The diffusion layer etching step is added before the selective etching of the sacrificial layer, which is mainly used to etch the uneven Ge component diffusion layer on both sides of the stack structure. The stack structure (also known as Si / SiGe stack) provides sufficient energy for Ge diffusion during anisotropic etching, forming a gradient distribution of Ge components near the interface between the channel layer and the sacrificial layer of the Si / SiGe stack. Since the Si-Si bond energy (2.31eV) > Si-Ge bond energy (2.12eV), Si-Ge bond is more likely to open during etching than Si-Si bond. Compared with other etching gases (such as F-based and Cl-based gases), short-time HBr plasma etching will not cause significant lateral damage to the channel layer, and the uneven Ge component diffusion layer can be removed.

[0078] The diffusion layer formed by the diffusion of Ge components in the sacrificial layer to the sidewall of the stack structure on both sides is usually only atomic level thickness, and a short-time etching of the diffusion layer will not cause obvious changes to the sidewall morphology of the stack structure. By adding nitrogen in the etching gas, the selectivity of the sacrificial layer to the upper hard mask layer can be improved.

[0079] During etching, the process chamber has a vacuum degree of 4-10mT, the upper electrode has a radio frequency power of 600-1000W, and the lower electrode has a radio frequency power of 0 (i.e. no bias power). The application of no bias power can reduce the impact on the depth of shallow trench isolation, and the etching temperature is 40-70℃. HBr and N2 are used as the main etching gas, the flow rate of HBr gas can be 200-500sccm, and the flow rate of N2 can be 10-30sccm.

[0080] Step 5, the sacrificial layer in the stack structure is selectively etched by atomic layer etching, and the second etching gas and the third etching gas are alternately introduced into the chamber to selectively etch the sacrificial layer on both sides of the stack structure, so as to form grooves on both sides of the sacrificial layer;

[0081] The following oxidation protection step and sacrificial layer selective etching step are alternately performed:

[0082] The O2 plasma treatment is mainly used for oxidizing and protecting the Si layer and the SiGe layer. The process parameters are preferably in the following ranges: the process chamber vacuum degree is 15-30 mT, the upper electrode radio frequency power is 300-600 W, there is no bias power, the oxidation temperature is 40-60 DEG C, the O2 gas flow is 100-300 sccm, the O2 input time is 5-10 s, and the oxidation protection process is self-limited, that is, the oxidation protection will reach saturation in a certain time, and the oxidation process will not continue if the second etching gas input time is continuously increased. The oxidation time is related to the Si and Ge component ratio of the SiGe material and is affected by the process parameters. The SiGe is oxidized to SiGeO2 under the O2 plasma, and the Si is oxidized to SiO2. Since the oxide needs to open the original covalent bond before forming, the SiGe is more easily oxidized than the Si. x O y

[0083] The sacrificial layer selective etching step is performed by inputting C4F6 and CF4 into the chamber. The process parameters are preferably in the following ranges: the process chamber vacuum degree is 40-70 mT, the upper electrode radio frequency power is 300-700 W, there is no bias power, the etching temperature is 40-60 DEG C, the total flow of the C4F6 and CF4 gas is 200-300 sccm, the flow ratio of the C4F6 and CF4 is 1:6-1:10, and the C4F6 and CF4 gas input time is 5-8 s.

[0084] The number of alternating cycles of the O2 plasma treatment and the C4F6 and CF4 selective etching of the sacrificial layer is determined according to the size requirement of the SiGe sacrificial layer. Since the Si-O bond energy (9.0 eV) is greater than the Ge-O bond energy (5.0 eV), and the Si-O-Ge bond energy is between the two, the use of fluorocarbon-based gas etching of the oxide will form volatile SiF x and GeF x and CO or CO2. The C4F6 and CF4 gas flow range cannot be too high, because the lack of O in the SiGe cannot make the rich C produce volatile CO or CO2. Therefore, increasing the C / F ratio will inhibit the etching of the SiGe surface. When the flow ratio of the C4F6 and CF4 is 1:6-1:10, the etching rate of the SiGe is much higher than that of the Si, and the selective etching of the SiGe is realized.

[0085] The etching method of the semiconductor device provided in the embodiment can effectively reduce the SiGe rounding amount without increasing the depth of the anisotropic etching of the stacked structure by adding the diffusion layer etching step before the selective etching of the SiGe sacrificial layer, thereby improving the product yield.

[0086] ​In addition, in the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be direct connection, can also be indirect connection through intervening medium, can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0087] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the prior art or the part of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and various program code storage media.

[0088] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0089] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the same. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that any person skilled in the art can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features, within the technical scope disclosed by the present application. The modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An etching method of a semiconductor device, characterized by, The application relates to a method for forming a trench structure on a substrate. The method comprises the following steps: a preset substrate is provided; wherein the preset substrate comprises a plurality of stack structures formed by a channel layer and a sacrificial layer, and a groove formed between the stack structures; a diffusion layer etching step is performed, a first etching gas is introduced into a chamber to etch both sides of the stack structure, so that a diffusion layer formed by Ge components in the sacrificial layer diffusing to the sidewall of the stack structure on both sides is etched and removed; wherein the first etching gas comprises hydrogen bromide and nitrogen, and the flow ratio of the hydrogen bromide and the nitrogen ranges from 20:1 to 50:1; 2. The method of claim 1, wherein, a sacrificial layer etching step is performed, a second etching gas and a third etching gas are alternately introduced into the chamber to selectively etch the sacrificial layer on both sides of the stack structure, so that grooves are formed on both sides of the sacrificial layer; wherein the second etching gas comprises a protective gas of the channel layer, and the third etching gas comprises a fluorocarbon-based gas for etching the sacrificial layer.

3. The method of claim 1, wherein, The process time of the diffusion layer etching step is 5-10 s.

4. The method of claim 1, wherein, The protective gas comprises oxygen.

5. The method of claim 4, wherein, The fluorocarbon-based gas comprises C4F6 and CF4.

6. The method of claim 1, wherein, The flow ratio of the C4F6 and the CF4 is 1:6-1:

10.

7. The method of claim 1, wherein, In each cycle, the second etching gas is introduced for 5-10 s, and the third etching gas is introduced for 5-8 s.

8. The method of claim 1, wherein, The etching mode of the diffusion layer etching step adopts plasma etching, the upper electrode radio frequency power ranges from 600 W to 1000 W in the diffusion layer etching step, and the lower electrode radio frequency power is 0. The forming step of the preset substrate comprises the following steps: The sacrificial layer and the channel layer are alternately epitaxially grown on a substrate; A hard mask layer is formed on the sacrificial layer and the channel layer, and the hard mask layer is patterned; 9. The method of claim 1, wherein, A fourth etching gas is introduced into a chamber, the channel layer, the sacrificial layer and the substrate are etched by taking the patterned hard mask layer as a mask, so that a plurality of stack structures are formed and a groove is formed between adjacent stack structures; wherein the depth of the groove is greater than the thickness of the stack structure. Before the diffusion layer etching step, the method further comprises the following steps: A cleaning step is performed, a preset cleaning liquid is used in a cleaning device to clean the preset substrate, so that the surface polymer and the oxide layer are removed.

Images