A method for manufacturing a semiconductor device hard mask

Abstract

The application provides a preparation method of a semiconductor device hard mask, and relates to the technical field of semiconductors.The preparation method comprises the following steps: providing a laminated structure, wherein the laminated structure comprises a magnetic tunnel junction film layer, a first hard mask layer and a second hard mask layer which are sequentially stacked from bottom to top, and the first hard mask layer is a metal nitride material; performing main etching, taking the patterned second hard mask layer as a mask layer, and etching the first hard mask layer to make it patterned, wherein the process gas comprises chlorine-containing gas and boron-containing gas.The preparation method can improve the steepness and precision of the second pattern opening formed by etching, and ensure the effective height of the hard mask, thereby ensuring the precision of the target pattern transferred to the magnetic tunnel junction film layer, improving the topography precision of the MTJ, and being conducive to the further miniaturization of the MTJ and improving the integration degree of the MTJ.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a hard mask for semiconductor devices. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a semiconductor device that stores data by means of magnetic field polarization. It combines the high-speed read / write capability of Static Random Access Memory (SRAM) with the high integration density of Dynamic Random Access Memory (DRAM). It can be rewritten almost infinitely and can be used in systems that require fast and large-scale data storage, data retention after power failure, and rapid recovery.

[0003] The basic structure of an MRAM memory cell is a magnetic tunnel junction (MTJ), consisting of a free layer, a tunnel insulating gate layer, and a fixed layer from top to bottom. The magnetic field polarization direction of the free layer is variable, while the magnetic field direction of the fixed layer is fixed. The morphological accuracy of the MTJ directly affects the storage performance of the MRAM. In related technologies, a double-layer film structure of heavy metal and dielectric layers is generally used as the hard mask for etching the MTJ. However, the hard mask patterning process generates a large amount of deposits, resulting in poor steepness of the pattern openings. This not only affects the performance and lifespan of the MTJ's tunnel magnetic resistance (TMR), hindering subsequent process fabrication and leading to a low survival rate of the semiconductor device, but also significantly impedes the etching rate, resulting in longer etching times and excessive consumption of the hard mask. This poses a short-circuit risk to the subsequent MRAM circuit bit lines and the MTJ. Furthermore, further etching of the pattern openings is difficult, hindering the miniaturization of the MTJ and its integration density. Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing a hard mask for a semiconductor device, so as to solve the technical problems in the related art where the steepness of the pattern opening formed by the hard mask is poor and the further etching of the pattern opening is difficult.

[0005] To address the above problems, the present invention provides a method for fabricating a hard mask for a semiconductor device, the method comprising:

[0006] A stacked structure is provided, the stacked structure comprising a magnetic tunneling membrane layer, a first hard mask layer and a second hard mask layer stacked sequentially from bottom to top, wherein the first hard mask layer is a metal nitride material;

[0007] The main etching step uses a patterned second hard mask layer as a mask layer to etch the first hard mask layer to pattern it, wherein the process gas includes chlorine-containing gas and boron-containing gas.

[0008] Optionally, in the main etching step, the chlorine-containing gas includes Cl2, and the boron-containing gas includes BCl3, wherein the flow rate ratio of BCl3 to Cl2 is 1:10 to 1:1.

[0009] Optionally, in the main etching step, the flow rate of BCl3 is 20-100 sccm, the flow rate of Cl2 is 100-180 sccm, the chamber pressure is 5-10 mT, the upper electrode power is 400-1000 W, and the lower electrode power is 30-70 W.

[0010] Optionally, the material of the first hard mask layer is TaN or TiN, and the thickness of the first hard mask layer is 100-200 nm.

[0011] Optionally, prior to the main etching step, the following steps are included:

[0012] In the first etching step, the second hard mask layer is patterned by etching with a fluorocarbon process gas, wherein the fluorocarbon process gas includes CF4 and CHF3, and the flow rate ratio of CF4 to CHF3 is 1:0.4 to 1:0.05.

[0013] Optionally, in the first etching step, the flow rate of CF4 is 150-200 sccm, the flow rate of CHF3 is 10-60 sccm, the chamber pressure is 5-10 mT, the upper electrode power is 500-800 W, and the lower electrode power is 50-100 W.

[0014] Optionally, after the first etching step, the following steps are included:

[0015] The second etching step removes byproducts deposited on the second hard mask layer, wherein the process gas includes an oxygen-containing gas.

[0016] Optionally, in the second etching step, the oxygen-containing gas includes O2, the flow rate of O2 is 150-200 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 1000-1200 W; and the lower electrode power is 0-50 W.

[0017] Optionally, the stacked structure further includes a planarization layer, an anti-reflection coating, and a photoresist layer stacked sequentially from bottom to top, wherein the planarization layer is located on the second hard mask layer; before the first etching step, a patterned second hard mask layer is included.

[0018] Using a patterned photoresist layer as a mask layer, the anti-reflective coating is etched to pattern it;

[0019] Using a patterned anti-reflective coating as a mask layer, the planarization layer is etched to pattern it;

[0020] Using a patterned anti-reflective coating and planarization layer as a mask layer, the second hard mask layer is etched to pattern it.

[0021] Optionally, the stacked structure further includes an etch stop layer located between the magnetic tunneling film layer and the first hard mask layer, and the etch stop layer is a metallic conductive material.

[0022] In the semiconductor device hard mask fabrication method provided by this invention, a patterned second hard mask layer is used as the mask layer. A process gas including chlorine-containing gas and boron-containing gas is used to etch the first hard mask layer. During the etching process, the chlorine-containing gas and boron-containing gas react with the first hard mask layer containing metal nitride material, producing only a single, small amount of boron nitride deposit. Part of the boron nitride is deposited on the sidewall of the second pattern opening, forming a passivation layer of relatively small thickness. This passivation layer can protect the sidewall of the second pattern opening, reducing lateral etching loss during the etching process. Furthermore, as etching continues, the rate of lateral etching loss of the passivation layer is approximately balanced with the rate of new passivation layer formation, thereby ensuring the continuous protection of the sidewall by the passivation layer and ensuring the perpendicularity of the sidewall. This correspondingly improves the steepness and accuracy of the etching to form the second pattern opening, thereby ensuring the accuracy of the target pattern transfer to the magnetic tunnel junction layer, improving the morphological accuracy of the obtained MTJ, and ensuring the tunnel magnetic reluctance (MTJ). The performance and lifespan of TMR (Total Resistance Ratio), as well as the survival rate of subsequent process technology and semiconductor devices.

[0023] During the etching process, in addition to the boron nitride deposited on the sidewall of the second pattern opening, another portion of boron nitride is deposited on the bottom wall of the second pattern opening to form a barrier layer of relatively thin thickness. The anisotropic process gas can quickly and effectively bombard and remove this barrier layer, and continue etching downwards to continuously deepen the depth of the second pattern opening. The relatively thin barrier layer has little hindrance to the etching rate, thus ensuring efficient etching. This allows the second pattern opening to quickly reach the bottom of the first hard mask layer, correspondingly shortening the etching time of the first hard mask layer, reducing excessive consumption of the second hard mask layer and the entire hard mask, thereby increasing the effective height of the hard mask. This ensures the effectiveness of the hard mask during the subsequent etching of the magnetic tunnel junction layer, improves the morphological accuracy of the MTJ, and reduces the risk of short circuits in the subsequent MRAM circuit bit lines and MTJ. At the same time, the target pattern can be smoothly and accurately etched and transferred to the first hard mask layer, which is also conducive to further miniaturization of the MTJ and improves its integration density. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the device structure obtained by the method for fabricating a magnetic tunnel junction hard mask according to related technologies provided in an embodiment of the present invention;

[0026] Figure 2A-2C This is a schematic diagram of the device structure for three steps of a method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention.

[0027] Figure 3 Electron micrograph of the etching morphology of a hard mask obtained by the method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention;

[0028] Figure 4 This is a first flowchart of a method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention;

[0029] Figure 5 This is a second flowchart of a method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures:

[0031] 10 - Layered structure; 100 - Magnetic tunneling film layer; 200 - Etching stop layer; 300 - First hard mask layer; 310 - Second pattern opening; 400 - Second hard mask layer; 410 - First pattern opening; 500 - Planarization layer; 600 - Anti-reflective coating; 700 - Ta-FO byproduct. Detailed Implementation

[0032] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] Figure 1 This is a schematic diagram of the device structure obtained by the fabrication method of the magnetic tunnel junction hard mask provided by related technologies.

[0036] In related technologies, a magnetic tunnel junction film layer 100, a first hard mask layer 300, and a second hard mask layer 400 are sequentially formed on a substrate. The first hard mask layer 300 is a Ta film layer, and the second hard mask layer 400 is a SiN film layer. The dual-film structure composed of the Ta film layer and the SiN film layer serves as the hard mask for the magnetic tunnel junction film layer 100. The patterning process of the hard mask is as follows: the target pattern required for the magnetic tunnel junction is transferred to the SiN film layer by etching. Then, using the SiN film layer as a mask layer, the Ta film layer is etched with a mixed gas of CHF3 and O2, thereby transferring the target pattern to the Ta film layer to form the hard mask required for etching the MTJ.

[0037] However, in related technologies, during the etching of Ta films using CHF3 and O2 to form target patterns, the reaction of CHF3, O2, and Ta produces a significant amount of Ta-FO byproducts 700 and carbon polymers. Simultaneously, O2 oxidizes the sidewalls of the pattern openings, forming a passivation layer. As the etching depth increases, the deposition of Ta-FO byproducts, carbon polymers, and the passivation layer on the sidewalls of the pattern openings becomes increasingly abundant, resulting in a sloping extension of the sidewalls from top to bottom. Consequently, the steepness of the final pattern openings formed by the Ta film is relatively poor. The MTJ obtained by etching the magnetic tunnel junction layer 100 using a hard mask composed of SiN and Ta films has poor precision. This not only affects the performance and lifespan of the tunnel magnetoresistive layer, which is detrimental to subsequent process technology and leads to a low survival rate of semiconductor devices, but also results in a large amount of deposits that significantly hinder the etching rate, leading to a longer etching time and excessive consumption of the hard mask. This poses a risk of short circuits between the circuit bit lines of the subsequent MRAM and the MTJ. At the same time, further etching of the Ta film pattern openings is difficult, which is not conducive to the miniaturization of the MTJ and the improvement of its integration density.

[0038] This embodiment provides a method for fabricating a hard mask for a semiconductor device. A first hard mask layer 300 and a second hard mask layer 400 made of metal nitride material are used as hard masks for a magnetic tunnel junction layer 100. The process gases used when etching the first hard mask layer 300 to form pattern openings include chlorine-containing gas and boron-containing gas. During etching, only a single, small amount of deposit is generated. This not only improves the steepness and accuracy of the pattern openings, ensuring the accuracy of the pattern openings transferred to the magnetic tunnel junction layer 100, thus improving the accuracy of the obtained MTJ, ensuring the performance and lifespan of the tunnel magnetoresistive field, and the survival rate of subsequent processes and semiconductor devices; but also, the small amount of deposit has a minimal impact on the etching rate, shortening the etching time of the first hard mask layer 300, reducing etching loss on the effective height of the hard mask, and thus reducing the risk of short circuits in subsequent MRAM circuit bit lines and MTJs. Simultaneously, the smooth and high-precision transfer of the target pattern is also beneficial for further miniaturization of the MTJ, improving its integration density. The method for fabricating a hard mask for a semiconductor device provided by this embodiment will be further described in detail below with reference to the accompanying drawings.

[0039] Figure 2A-2C This is a schematic diagram of the device structure for three steps of a method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention. Figure 3 Electron micrograph of the etching morphology of a hard mask obtained by the method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention. Figure 4 This is a first flowchart of a method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention.

[0040] like Figure 4As shown, an embodiment of the present invention provides a method for fabricating a hard mask for a semiconductor device, comprising:

[0041] S402 provides a stacked structure 10, which includes a magnetic tunneling membrane layer 100, a first hard mask layer 300 and a second hard mask layer 400 stacked sequentially from bottom to top, wherein the first hard mask layer 300 is a metal nitride material.

[0042] The stacked structure 10 is specifically formed on a substrate (not shown in the figure), or the stacked structure 10 includes a substrate located at the bottom of the magnetic tunneling membrane layer 100; the magnetic tunneling membrane layer 100 specifically includes a free layer, a tunnel insulating grid layer and a fixed layer stacked sequentially from bottom to top, and a double film layer composed of a first hard mask layer 300 and a second hard mask layer 400 serves as the hard mask of the magnetic tunneling membrane layer 100, and the first hard mask layer 300 is a metal nitride material.

[0043] In the S404 main etching step, the first hard mask layer 300 is etched to pattern the patterned second hard mask layer 400 using the patterned second hard mask layer 400 as the mask layer. The process gases include chlorine-containing gases and boron-containing gases.

[0044] like Figure 2B As shown, after the target pattern required for MTJ etching is transferred to the second hard mask layer 400 to form the first pattern opening 410, as... Figure 2C As shown, the main etching step is performed to transfer the target pattern to the first hard mask layer 300 to form the second pattern opening 310, thereby obtaining the hard mask required for etching the magnetic tunnel junction film layer 100. Specifically, using the patterned second hard mask layer 400 as the mask layer, the first hard mask layer 300 is etched using process gases including chlorine-containing gas and boron-containing gas. During the etching process, the chlorine-containing gas and boron-containing gas react with the first hard mask layer 300 of the metal nitride material, producing only a single, small amount of boron nitride deposit. Among them, some boron nitride is deposited on the sidewall of the second pattern opening 310 to form a passivation layer of relatively small thickness. The passivation layer can protect the sidewalls of the second pattern opening 310, thereby reducing the lateral etching loss of the sidewalls during the etching process. As the etching continues, the rate at which the passivation layer is laterally etched away is approximately balanced with the rate at which a new passivation layer is generated. This ensures the continuous protection of the sidewalls by the passivation layer and ensures the verticality of the sidewalls. Consequently, it improves the steepness and accuracy of the second pattern opening 310 formed by etching, thereby ensuring the accuracy of the target pattern transfer to the magnetic tunnel junction layer 100, improving the morphological accuracy of the obtained MTJ, ensuring the performance and lifespan of the tunnel magnetoresistive material, as well as the survival rate of subsequent processes and semiconductor devices.

[0045] During the etching process, in addition to the boron nitride deposited on the sidewall of the second pattern opening 310, another portion of boron nitride is deposited on the bottom wall of the second pattern opening 310 to form a barrier layer of relatively small thickness. The anisotropic process gas can quickly and effectively bombard and remove this barrier layer, and continue etching downwards to continuously deepen the depth of the second pattern opening 310. The relatively small thickness of the barrier layer has little hindrance to the etching rate, thereby ensuring efficient etching. This allows the second pattern opening 310 to quickly reach the bottom of the first hard mask layer 300, correspondingly shortening the etching time of the first hard mask layer 300, reducing excessive consumption of the second hard mask layer 400 and the entire hard mask, thereby increasing the effective height of the hard mask. This ensures the effectiveness of the hard mask during the subsequent etching of the magnetic tunnel junction layer 100, improves the morphological accuracy of the MTJ, and reduces the risk of short circuits in the subsequent MRAM circuit bit lines and MTJ. At the same time, the target pattern can be smoothly and accurately etched and transferred to the first hard mask layer 300, which is also conducive to the further miniaturization of the MTJ and improves its integration density.

[0046] This fabrication method is suitable for fabricating MRAM circuits below 60nm and can achieve precise transfer of target patterns.

[0047] In this embodiment of the invention, in the main etching step S404, the chlorine-containing gas includes Cl2, and the boron-containing gas includes BCl3, wherein the flow rate ratio of BCl3 to Cl2 is 1:10 to 1:1. Cl2 and BCl3 contain a relatively high Cl content. During the etching process, Cl2 and BCl3 can dissociate to release sufficient reactive gas Cl to bombard the first hard mask layer 300 and generate gaseous byproducts. These gaseous byproducts can be extracted during the etching process. Simultaneously, the B in BCl3 can react with the N in the first hard mask layer 300 to generate a single, small amount of BN deposits. Some of these BN deposits form a passivation layer with a relatively thin thickness that maintains dynamic equilibrium on the sidewall of the second pattern opening 310, thereby ensuring continuous and effective protection of the sidewall of the second pattern opening 310, reducing lateral etching loss on the sidewall, and improving the steepness and morphological accuracy of the sidewall. Another portion of the BN deposits forms a relatively thin barrier layer on the bottom wall of the second pattern opening 310. This barrier layer can be quickly removed by bombardment with reactive gas Cl, with minimal obstruction to the etching rate, ensuring efficient etching of the bottom wall, thus ensuring smooth etching, effectively shortening the etching time, and reducing excessive consumption of the hard mask.

[0048] In this embodiment of the invention, the process parameters of the main etching step can be as follows: the flow rate of BCl3 is 20-100 sccm, the flow rate of Cl2 is 100-180 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 400-1000 W, and the lower electrode power is 30-70 W.

[0049] In this embodiment of the invention, the first hard mask layer 300 is made of TaN or TiN, and its thickness is 100–200 nm. On one hand, by using TaN or TiN as the material for the first hard mask layer 300, it serves not only as a mask for etching the magnetic tunnel junction layer 100 but also as an electrode layer for the subsequently formed MTJ. On the other hand, the second hard mask layer 400 is made of SiN, while the first hard mask layer 300 is made of TaN or TiN. The process gases used to etch the first hard mask layer 300 are Cl2 and BCl3. The process gases affect both the second hard mask layer 400 and the first hard mask layer 300. The etching selectivity can reach 3 to 7. During the etching of the first hard mask layer 300, the first hard mask layer 300 can be etched quickly while consuming less of the effective height of the second hard mask layer 400. This reduces the excessive consumption of the hard mask composed of the first hard mask layer 300 and the second hard mask layer 400, ensuring the effectiveness of the hard mask in the subsequent etching of the magnetic tunnel junction layer 100, improving the topographic accuracy of the target pattern transferred to the MTJ, and reducing the risk of short circuits in the subsequent MRAM circuit bit lines and MTJ.

[0050] In this process, when the first hard mask layer 300 is made of TaN material and Cl2 and BCl3 are used as process gases in the main etching step, the etching reaction formula is as follows:

[0051] BCl3 + Cl2 + TaN → BCl x ↑+TaCl4↑+BN.

[0052] The thickness of the magnetic tunneling membrane layer 100 can be 10–14 nm, and the thickness of the second hard mask layer 400 can be 10–15 nm.

[0053] In embodiments of the present invention, such as Figure 2A-2C As shown, the stacked structure 10 also includes an etch stop layer 200, which is located between the magnetic tunneling film layer 100 and the first hard mask layer 300, and the etch stop layer 200 is made of a metallic conductive material. On the one hand, the etch stop layer 200 serves as a stop layer for the main etching step in forming the second patterned opening 310, so that the second patterned opening 310 stops at the etch stop layer 200, thereby controlling the depth of the second patterned opening 310 and reducing uncontrollable damage to the magnetic tunneling film layer 100 caused by the main etching step. On the other hand, the etch stop layer 200 is made of a metallic conductive material, and the etch stop layer 200 can serve as the electrode layer for the subsequently formed MTJ, thereby reducing the conductivity requirements of the first hard mask layer 300 and correspondingly reducing the requirements for the N content in the first hard mask layer 300.

[0054] Specifically, the material of the etch stop layer 200 can be Ru or Ir, and the first hard mask layer 300 of the metal nitride material has a high etch selectivity with the etch stop layer 200; the thickness of the etch stop layer 200 can be 5 to 6 nm.

[0055] In this embodiment of the invention, before the main etching step S404, the process includes: a first etching step, in which a second hard mask layer 400 is etched and patterned using a fluorocarbon process gas, wherein the fluorocarbon process gas includes CF4 and CHF3, and the flow rate ratio of CF4 to CHF3 is 1:0.4 to 1:0.05. Before executing the main etching step to etch the first hard mask layer 300, the second hard mask layer 400 is first etched to transfer the target pattern to the second hard mask layer 400. A mixed gas of CF4 and CHF3 with a low carbon-fluorine ratio is used as the process gas to etch the second hard mask layer 400. CF4 is used as the main etching gas. CF4 and CHF3 have high reactivity. During the etching process, sufficient active gas F can be dissociated to etch and bombard the second hard mask layer 400, thereby achieving efficient and high-precision etching of the second hard mask layer 400 and accurately transferring the target pattern to the second hard mask layer 400, making it efficiently and accurately patterned. This reduces the etching consumption of the effective height of the second hard mask layer 400 and ensures the accuracy of transferring the target pattern to the first hard mask layer 300 in the subsequent main etching step.

[0056] Specifically, when the second hard mask layer 400 is made of SiN material, and the process gases for the first etching step are CF4 and CHF3, the etching reaction formula is as follows:

[0057] SiN+CF4+CHF3→SiF4↑+CNF+NH↑.

[0058] The SiF4 and NH generated in the reaction are in a gaseous state and can be extracted during the etching process; the CNF generated in the reaction can be deposited on the sidewall of the second pattern opening 310 to form a passivation layer to protect it, thereby reducing the lateral etching of the sidewall during the etching process and improving the verticality of the second pattern opening 310; the addition of CHF3 allows N to form NH free radicals without polymer formation, which can promote the etching of SiN.

[0059] In this embodiment of the invention, the process parameters for the first etching step can be as follows: the flow rate of CF4 is 150-200 sccm, the flow rate of CHF3 is 10-60 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 500-800 W, and the lower electrode power is 50-100 W.

[0060] In this embodiment of the invention, after the first etching step and before the main etching step, a second etching step is included to remove byproducts deposited on the second hard mask layer 400, wherein the process gas includes oxygen-containing gas. After the first etching step etches the second hard mask layer 400 and transfers the target pattern to the second hard mask layer 400, the second etching step continues. Specifically, a process gas including oxygen-containing gas is used to remove the deposits formed in the first etching step, thereby improving the morphological accuracy of the first pattern opening 410 formed on the second hard mask layer 400. This improves the morphological accuracy of the second pattern opening 310 transferred to the first hard mask layer 300 using the second hard mask layer 400 as a mask layer in the main etching step, and further improves the morphological accuracy of the target pattern transferred to the MTJ.

[0061] In this embodiment of the invention, the process parameters for the second etching step can be as follows: the oxygen-containing gas includes O2, the flow rate of O2 is 150-200 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 1000-1200 W, and the lower electrode power is 0-50 W.

[0062] The reaction formula for removing CNF deposits in the first etching step using O2 is as follows:

[0063] CNF + O2 → CO x ↑+COF2↑+NO x ↑.

[0064] In embodiments of the present invention, such as Figure 2A-2B As shown, before the first etching step, the second hard mask layer 400 is patterned through the following process steps: The stacked structure 10 also includes a planarization layer 500, an anti-reflection coating 600, and a photoresist layer (not shown) stacked sequentially from bottom to top, wherein the planarization layer 500 is located on the second hard mask layer 400; Before the first etching step, the second hard mask layer 400 is patterned as follows: using the patterned photoresist layer as a mask layer, the anti-reflection coating 600 is etched to pattern it; using the patterned anti-reflection coating 600 as a mask layer, the planarization layer 500 is etched to pattern it; using the patterned anti-reflection coating 600 and the planarization layer 500 as mask layers, the second hard mask layer 400 is etched to pattern it.

[0065] Specifically, the anti-reflective coating 600 is a Siarc coating with a thickness of 20–40 nm; the planarization layer 500 is a spin-on carbon (SOC) layer with a thickness of 100–300 nm; a target pattern is formed on the photoresist layer. First, using the patterned photoresist layer as a mask, a mixed gas of CF4 and CHF3 is used as the process gas to etch the anti-reflective coating 600 to transfer the target pattern to the anti-reflective coating 600 and pattern it; then, using the anti-reflective coating 600 as a mask, the planarization layer 500 is etched. The specific etching process parameters are: a mixed gas of O2 and Cl2 is used as the process gas, wherein the flow rate of O2 is 80–120 sccm and the flow rate of Cl2 is 20–60 sccm; the chamber pressure is 5–10 mT; the upper electrode power is 300–500 W and the lower electrode power is 100–200 W; the etching time can be determined by the endpoint etching capture method. Continuing, using the remaining anti-reflective coating 600 and planarization layer 500 as mask layers, the first etching step is performed to etch the second hard mask layer 400 to pattern it.

[0066] Among them, such as Figure 2B As shown, in addition to removing the byproducts formed in the first etching step, the remaining SOC layer can also be removed in the second etching step.

[0067] Figure 5 This is a second flowchart of a method for fabricating a hard mask for a semiconductor device according to an embodiment of the present invention.

[0068] like Figure 5 As shown, the preparation method includes:

[0069] S502 provides a magnetic tunnel junction layer 100 as a substrate, on which an etch stop layer 200, a first hard mask layer 300, a second hard mask layer 400, a planarization layer 500, an anti-reflection coating 600, and a patterned photoresist layer are sequentially formed.

[0070] S504 uses a patterned photoresist layer as a mask layer and etches an anti-reflective coating 600 to pattern it; it also uses the patterned anti-reflective coating 600 as a mask layer and etches a planarization layer 500 to pattern it.

[0071] S506 performs the first etching step: using the patterned anti-reflective coating 600 and planarization layer 500 as mask layers, the second hard mask layer 400 is etched using a carbon-fluorine based process gas to pattern it.

[0072] S508 performs the second etching step: using oxygen-containing gas as the process gas to etch away the remaining SOC layer and the byproducts deposited in the second etching step.

[0073] S510 performs the main etching step: using the patterned second hard mask layer 400 as a mask layer, the first hard mask layer 300 of the nitride metal material is etched with chlorine-containing gas and boron-containing gas to pattern it.

[0074] Thus, we can obtain the following: Figure 2C and Figure 3 The hard mask shown.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a hard mask for a semiconductor device, characterized in that, The preparation method includes: A stacked structure (10) is provided, the stacked structure (10) including a magnetic tunneling membrane layer (100), a first hard mask layer (300) and a second hard mask layer (400) stacked sequentially from bottom to top, wherein the material of the first hard mask layer (300) is TaN or TiN; In the main etching step, the first hard mask layer (300) is etched to pattern the patterned second hard mask layer (400) using the patterned second hard mask layer (400) as the mask layer, and the formed second patterned opening (310) reaches the bottom of the first hard mask layer (300). The process gas includes chlorine-containing gas and boron-containing gas. The chlorine-containing gas includes Cl2, and the boron-containing gas includes BCl3. The flow ratio of BCl3 and Cl2 is 1:10 to 1:

1. During the etching process, gaseous byproducts and a single BN deposit are generated. The generated gaseous byproducts can be extracted, and the BN deposit forms a passivation layer with a thickness that can maintain dynamic balance on the sidewall of the second patterned opening (310).

2. The preparation method according to claim 1, characterized in that, In the main etching step, the flow rate of BCl3 is 20~100 sccm, the flow rate of Cl2 is 100~180 sccm, the chamber pressure is 5~10 mT, the upper electrode power is 400~1000 W, and the lower electrode power is 30~70 W.

3. The preparation method according to claim 1, characterized in that, The thickness of the first hard mask layer (300) is 100~200nm.

4. The preparation method according to any one of claims 1-3, characterized in that, Prior to the main etching step, the following steps are included: In the first etching step, the second hard mask layer (400) is etched using a fluorocarbon process gas to pattern it. The fluorocarbon process gas includes CF4 and CHF3, and the flow rate ratio of CF4 to CHF3 is 1:0.4 to 1:0.

05.

5. The preparation method according to claim 4, characterized in that, In the first etching step, the flow rate of CF4 is 150~200 sccm, the flow rate of CHF3 is 10~60 sccm, the chamber pressure is 5~10 mT, the upper electrode power is 500~800 W, and the lower electrode power is 50~100 W.

6. The preparation method according to claim 4, characterized in that, Following the first etching step, the process includes: The second etching step removes byproducts deposited on the second hard mask layer (400), wherein the process gas includes an oxygen-containing gas.

7. The preparation method according to claim 6, characterized in that, In the second etching step, the oxygen-containing gas includes O2, the flow rate of O2 is 150~200 sccm; the chamber pressure is 5~10 mT; the upper electrode power is 1000~1200 W; and the lower electrode power is 0~50 W.

8. The preparation method according to claim 4, characterized in that, The stacked structure (10) further includes a planarization layer (500), an anti-reflection coating (600), and a photoresist layer stacked sequentially from bottom to top, wherein the planarization layer (500) is located on the second hard mask layer (400); before the first etching step, a patterned second hard mask layer (400) is included: Using a patterned photoresist layer as a mask layer, the anti-reflective coating (600) is etched to pattern it; Using a patterned anti-reflective coating (600) as a mask layer, the planarization layer (500) is etched to pattern it; Using a patterned anti-reflective coating (600) and a planarization layer (500) as mask layers, the second hard mask layer (400) is etched to pattern it.

9. The preparation method according to any one of claims 1-3, characterized in that, The stacked structure (10) further includes an etch stop layer (200), which is located between the magnetic tunneling film layer (100) and the first hard mask layer (300), and the etch stop layer (200) is a metallic conductive material.

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