Photonic integrated circuit package and method of manufacturing same

Abstract

Photonic integrated circuit packages and methods of manufacture are disclosed. An example integrated circuit package includes: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate including a glass core including a through glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through glass via, a recess defined by a third surface of the glass core, the recess having a different shape than the through glass via; and a reflective metal disposed on the third surface to define a mirror, the reflective metal further disposed between a wall of the through glass via and a conductive material disposed in the through glass via.

Description

[0001] Related applications

[0002] This patent claims priority to U.S. Patent Application No. 18 / 189,782, filed on March 24, 2023. U.S. Patent Application No. 18 / 189,782 is hereby incorporated by reference in its entirety. Priority to U.S. Patent Application No. 18 / 189,782 is hereby claimed. Technical Field

[0003] The present disclosure relates generally to integrated circuits and, more particularly, to photonic integrated circuit packages and methods of fabricating the same. Background Art

[0004] In many integrated circuit packages, one or more semiconductor dies are mechanically and electrically coupled to an underlying package substrate. Some package substrates include a glass core. This glass core provides stability to the package and can also be used to propagate light in photonic applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example integrated circuit (IC) package is shown that includes two example semiconductor dies electrically coupled to a package substrate that is electrically coupled to a circuit board.

[0006] Figure 2 Yes, you can Figure 1 sectional view of an example package substrate implemented in an IC package.

[0007] Figure 3 Yes, you can Figure 1 and / or Figure 2 Cross-sectional view of an example glass core assembly implemented in a packaging substrate.

[0008] Figures 4 to 8 Shows the manufacturing Figure 3 Example glass core assemblies at different stages of the example process.

[0009] Figure 9 Yes, you can Figure 1 and / or Figure 2 sectional view of another example glass core assembly implemented in a packaging substrate of FIG.

[0010] Figures 10 to 14 Shows the manufacturing Figure 9 Example glass core assemblies at different stages of the example process.

[0011] Figures 15 to 19 Different stages in another example process of making another example glass core assembly are shown.

[0012] Figure 20 It means manufacturing Figure 3 and Figure 9 A flow chart of an example method of an example glass core assembly.

[0013] Figure 21 It means manufacturing Figure 19 A flow chart of an example method of an example glass core assembly.

[0014] Figure 22 is a top view of a wafer including dies that may be included in an IC package constructed according to the teachings disclosed herein.

[0015] Figure 23 is a cross-sectional side view of an IC device that may be included in an IC package constructed according to the teachings disclosed herein.

[0016] Figure 24 is a cross-sectional side view of an IC device assembly that may include an IC package constructed according to the teachings disclosed herein.

[0017] Figure 25 is a block diagram of an example electrical device that may include an IC package constructed according to the teachings disclosed herein.

[0018] Generally, the same reference numerals will be used throughout the drawings and the accompanying written description to refer to the same or similar parts. The drawings are not necessarily drawn to scale. Rather, the thickness of layers or regions may be exaggerated in the drawings. Although the figures illustrate layers and regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0019] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one portion between the Earth and the first part. Similarly, as used herein, a first part is "below" a second part when the first part is closer to the Earth than the second part. As described above, a first part can be above or below a second part and satisfy one or more of the following: there are other parts between them, there are no other parts between them, the first part and the second part are in contact, or the first part and the second part are not in direct contact with each other.

[0020] Notwithstanding the foregoing, "above" with reference to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die during manufacture or fabrication is not with reference to the Earth, but rather with reference to the underlying substrate on which the associated components are manufactured, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is "above" a second component when, during manufacture / fabrication, the first component is further away from the substrate (e.g., a semiconductor wafer) on which the two components are manufactured or otherwise provided than the second component within the semiconductor die. Similarly, a first component within an IC package (e.g., a semiconductor die) is "above" a second component within the IC package when, during manufacture, the first component is further away from a printed circuit board (PCB) to which the IC package is mounted or attached, unless otherwise stated or implied from the context. It should be understood that semiconductor devices are typically used in an orientation different from their orientation during manufacture. Thus, when reference is made during use to a semiconductor device (e.g., a transistor), a semiconductor die comprising a semiconductor device, and / or an integrated circuit (IC) package comprising a semiconductor die, the definition of “above” in the preceding paragraph (i.e., the term “above” describing the relationship of two parts relative to the earth) will likely be governed based on the context of use.

[0021] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any way on another part (e.g., positioned on another part, located on another part, disposed on another part, or formed on another part, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part and that one or more intermediate parts are located therebetween.

[0022] As used herein, unless otherwise specified, connection references (e.g., attachment, coupling, connection, and engagement) may include intermediate members between the elements referred to by the connection reference and / or relative movement between these elements. Thus, a connection reference does not necessarily infer that two elements are directly connected to each other and / or are in a fixed relationship. As used herein, stating that any part is "in contact with" another part is defined to mean that there is no intermediate part between the two parts.

[0023] Unless otherwise specifically stated, the use of descriptors such as "first," "second," "third," etc. herein does not imply or otherwise indicate any meaning of priority, physical order, arrangement in a list, and / or ordering in any manner, but is merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to in the claims with different descriptors such as "second" or "third." In such instances, it should be understood that such descriptors are only used to clearly identify those elements that may, for example, share the same name in other contexts.

[0024] As used herein, "approximately" and "about" modify their subject / values ​​to recognize the potential for variations that occur in real-world applications. For example, as will be understood by one of ordinary skill in the art, "approximately" and "approximately" may modify a dimension that may be inaccurate due to manufacturing tolerances and / or other real-world imperfections. For example, unless otherwise indicated in the following description, "approximately" and "approximately" may indicate that such a dimension may be within a tolerance of + / - 10%. As used herein, "substantially real time" means occurring in a near-instantaneous manner, recognizing that there may be real-world delays for computation times, transmissions, and the like. Thus, unless otherwise indicated, "substantially real time" means real time + / - 1 second.

[0025] As used herein, the phrase "communication" includes variations thereof, encompassing direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but instead includes selective communication at periodic intervals, pre-scheduled intervals, non-periodic intervals, and / or one-time events.

[0026] As used herein, “processor circuitry” is defined as including (i) one or more special purpose circuitries that are configured as specific machines to perform particular operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented with one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that are programmed to perform particular operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented with one or more transistors). Examples of processor circuitry include programmable microprocessors, field-programmable gate arrays (FPGAs) that can instantiate instructions, central processing unit(s) (CPU(s)), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), XPU(s), or microcontrollers, as well as integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and / or combinations thereof) and an application programming interface (API) that can assign computing tasks to the processor circuitry of the multiple types that is best suited to perform the computing task. DETAILED DESCRIPTION

[0027] Figure 1 An example integrated circuit (IC) package (e.g., semiconductor package) 100 constructed in accordance with the teachings disclosed herein is shown. In the illustrated example, the IC package 100 is electrically coupled to a circuit board 102 via an array of contact pads or lands 104 on a mounting surface (e.g., a bottom surface) of the package. In some examples, in addition to or instead of the contact pads 104, the IC package 100 can include balls, pins, and / or pads to enable electrical coupling of the package 100 to the circuit board 102. In this example, the package 100 includes two semiconductor (e.g., silicon) dies 106, 108 (also sometimes referred to as chips or cores) mounted to a package substrate 110 and encapsulated by a package cap or molding compound 112. Although the package 100 is shown as a flip-chip package in which the dies 106, 108 are mounted face down on the substrate 110, in other examples the package 100 can be a wire-bond package in which the dies 106, 108 are mounted face up on the substrate 110. Figure 1 The example IC package 100 includes two dies 106, 108, but in other examples the package 100 can have only one die or have more than two dies. In some examples, one of the dies 106, 108 (or a separate die) is embedded in the package substrate 110. The dies 106, 108 can provide any suitable type of functionality (e.g., data processing, memory storage, etc.).

[0028] In the illustrated example, each of the dies 106, 108 is electrically and mechanically coupled to the substrate 110 via a corresponding array of interconnects 114. In this example, the interconnects 114 are solder balls, but in other examples the interconnects 114 can be wire bonds, conductive adhesive, or other suitable electrical connections. Figure 1, the interconnects are shown as bumps. However, in addition to or in place of the bumps shown (e.g., balls, pins, pads, wire bonds, etc.), interconnects 114 can be any other type of electrical connection. The electrical connection between die 106, 108 and substrate 110 (e.g., interconnect 114) is sometimes referred to as a first-level interconnect. In contrast, the electrical connection between IC package 100 and circuit board 102 (e.g., pads 104) is sometimes referred to as a second-level interconnect. In some examples, one or both of die 106, 108 can be stacked on top of one or more other dies and / or interposers. In such examples, die 106, 108 are coupled to the lower die and / or interposer via a first set of first-level interconnects, and the lower die and / or interposer can be connected to package substrate 110 via a separate set of first-level interconnects associated with the lower die and / or interposer. Thus, as used herein, first level interconnects refer to interconnects (eg, balls, bumps, pins, pads, wire bonds, etc.) between a die and a package substrate or between a die and an underlying die and / or an interposer.

[0029] like Figure 1 As shown in FIG, the interconnect 114 of the first level interconnect includes two different types of bumps, namely, core bumps 116 and bridge bumps 118. As used herein, a core bump is a bump on a die through which electrical signals are passed between the die and other components within the IC package containing the die (e.g., a different die) or external to the IC package. Thus, as shown in the illustrated example, when the dies 106, 108 are mounted to the package substrate 110, the core bumps 116 are physically connected and electrically coupled to contact pads 120 on an inner surface 122 of the substrate 110. The contact pads 120 on the inner surface 122 of the package substrate 110 are electrically coupled to the landing pads 104 on the bottom (external) surface 124 (e.g., the surface opposite the inner surface 122) of the substrate 110 via internal interconnects 126 within the substrate 110. As a result, a complete signal path exists between the bumps 116 of the dies 106 , 108 and the landing pads 104 mounted to the circuit board 102 , through the contact pads 120 and the interconnects 126 disposed therebetween.

[0030] As used herein, a bridge bump is a bump on a die through which electrical signals are passed between different ones of the dies within an IC package. More specifically, a bridge bump is different from a core bump in that the bridge bump is connected to the die via an interconnect bridge (e.g., a substrate 110) embedded in the underlying substrate (e.g., the package substrate 110). Figure 1 The interconnect bridge 128) electrically connects two or more different dies. Figure 1 As shown, core bumps 116 are typically larger than bridge bumps 118. In some examples, interconnect bridges 128 and associated bridge bumps 118 are omitted.

[0031] Figure 1 The example IC package 100 is a photonic package that includes at least one optical component 130 integrated with and / or carried by a substrate 110. More specifically, in some examples, the substrate 110 includes a glass substrate, layer, or core 202 (in the embodiment of FIG. 1 ) to which the optical component 130 is coupled. Figure 2 In some examples, light is directed through and / or along glass core 202 toward optical component 130 .

[0032] Figure 2 It is for Figure 1 , further details are provided in cross-sectional views of example embodiments of an example packaging substrate 110. The packaging substrate 110 of the illustrated example includes a glass substrate or core 202 between two separate build layers or regions 204. In this example, the build regions 204 are disposed on a first surface 206 of the glass core 202 and a second surface 208 of the glass core 202 opposite the first surface 206. The build regions 204 of the illustrated example are defined by alternating insulating patterns of dielectric layers 210 and patterned conductive (e.g., metal) layers 212. In this example, there are three dielectric layers 210 and three conductive layers 212 (excluding the outermost layer of conductive material) in the build region 204. However, in other examples, any other suitable number of dielectric layers 210 and conductive layers 212 may be employed. In some examples, the build region 204 on at least one side of the glass core 202 may be omitted such that the glass core defines the outer surface of the packaging substrate 110.

[0033] The conductive layer 212 in the build area 204 is patterned to define electrical wiring or conductive traces that serve as signal routing or transmission lines for use in an associated IC package (e.g., Figure 1 The conductive (e.g., metal) vias 214 extend through the dielectric layer 210 to electrically couple different conductive layers in the conductive layers 212 in different build areas 204. Figure 2 As shown, the glass core 202 of the illustrated example includes one or more through-glass vias (TGVs) 216 (e.g., copper-plated vias) extending between opposing surfaces 206, 208 of the glass core 202 to communicatively and / or electrically couple the conductive layer 212 and associated metal vias 214 within the build-up areas 204 on either side of the glass core 202. Thus, in this example, the electrical wiring or traces defined by the patterning of the conductive layer 212, the conductive vias 214, and the TGVs 216 collectively define electrical interconnects (e.g., Figure 1 interconnect 126).

[0034] In the example shown, the package substrate 110 includes a first plurality of connectors 218 (e.g., solder balls, bumps, contact pads, pins, etc.) on the inner surface 122 of the substrate 110 to electrically couple the package substrate 110 to one or more semiconductor dies (e.g., Figure 1 In addition, the example package substrate 110 includes a second plurality of solder connections 220 (e.g., solder balls, bumps, contact pads, pins, etc.) to electrically couple the package substrate 110 to a printed circuit board (e.g., Figure 1 circuit board 102), interposer and / or any other substrate.

[0035] Although the glass core 202 of the example package substrate 110 is shown as the central core of the substrate 110, in some examples, the glass core 202 can be an interposer and / or any other layer of the package substrate 110. For example, the glass core 202 can be used in place of one or more of the dielectric layers 210 of the package substrate 110. In some examples, the package substrate 110 can include different materials, including organic materials, silicon, and / or other conventional materials used to manufacture package substrates. In some examples, the package substrate 110 includes an embedded multi-die interconnect bridge (EMIB) (e.g., Figure 1 Bridge 128).

[0036] High density substrate packaging technologies often use organic cores (e.g., epoxy-based prepreg layers with glass cloth) as the starting material in next generation computing applications. These next generation computing applications have increased scaling requirements that specify (e.g., stipulate, require, etc.) a reduction in warpage and thickness variation as multi-chip architectures proliferate. As a result, the starting organic core material becomes thicker and thicker in subsequent generations to provide an effectively lower coefficient of thermal expansion (CTE). The thicker starting organic core material shortens the life of the silicon die (e.g., silicon die) mounted on such substrates. Figure 1 The difference (e.g., delta) in the CTE of the dies 106, 108 is reduced. However, increasing the core thickness is not a universal solution because some applications have an overall core thickness that is limited by customer demand (e.g., portable machines, mobile devices, etc.). In addition, increasing the core thickness may be detrimental to the electrical performance of the product.

[0037] Using glass as the starting core material (e.g. Figure 2The glass core 202 of the present invention has mechanical benefits, electrical benefits and design flexibility benefits over the use of traditional organic core materials (for example, epoxy-based prepregs). In addition, the glass core can be used as a waveguide to define an optical signal path that can transmit light. As a result, the optical component 130 can be directly incorporated or integrated into the packaging substrate adjacent to the surface of the glass core. Typically, in the manufacture of integrated circuit packages, it is necessary to metallize the surface on the glass core 202. Typically, the process of metallizing the surface is completed in multiple photolithography steps. Due to the reduction in tube core size, substrate size and packaging complexity, the multiple photolithography steps increase the possibility of damage to the integrated circuit package and increase production time. The examples disclosed herein include a process for metallizing the surface of the glass core in fewer photolithography steps than other known methods.

[0038] exist Figure 2 In the example shown, the optical component 130 is embedded in a cavity in the glass core 202. In other examples, the optical component 130 is on the first surface 206 or the second surface 208 of the glass core 202. In some examples, the optical component 130 includes Figure 3 The reflecting surface or reflector is described in further detail in Figures 3 to 19 Example constructions of metallized optical components 130 within a substrate including a glass core are described in further detail in .

[0039] Figure 3 Yes, you can Figure 1 and / or Figure 2 FIG. 3 is a cross-sectional view of an example glass core assembly 300 implemented in a packaging substrate 110 of FIG. Figure 3 An example glass core assembly 300 is Figure 2 Example configuration of glass core 202. Example glass core assembly 300 includes a glass substrate or core 302 (with Figure 2 In some examples, the optical component 304 is embedded in the glass substrate or core 302. Figure 3 The optical component 304 corresponds to Figure 1 and Figure 2 130 of the example glass core assembly 300. In this example, the optical component 304 corresponds to and / or includes a reflector or light reflecting surface. In some examples, the reflector or light reflecting surface of the optical component 304 includes a non-planar or multi-dimensional surface. In the example shown, the optical component 304 is adjacent to a first surface 306 of the example glass core assembly 300 that is opposite to a second surface 308. In some examples, the first surface 306 and the second surface 308 correspond to Figure 2 The corresponding first surface 206 and second surface 208.

[0040] In the example shown, optical component 304 is disposed in and / or has a shape defined by a cavity, void, or recess 309 in glass core 302. In this example, cavity 309 is located along second surface 306 of glass core 302 and is defined by third surface 310 of glass core 302. In some examples, such as Figure 3 As shown, third surface 310 includes a plurality of discrete facets that can be angled relative to one another and / or shaped in any suitable manner. In some cases, at least one facet of third surface 310 is arcuate or curved. In some examples, the reflective or light-reflecting surface of optical component 304 is defined by a reflective metal 311 (also referred to herein as a mirror metal) disposed on third surface 310 of glass core 302. In some examples, reflective metal 311 includes at least one of aluminum (Al), gold (Au), silver (Ag), or ruthenium (Ru). In the example shown, optical component 304 includes a filler material 312 to fill cavity 309. In some examples, filler material 312 includes at least one of a polymer, copper (Cu), aluminum, gold, silver, or ruthenium (Ru). Although only one optical component 304 is shown in the example shown, any suitable number of optical components 304 can be implemented in glass core 302. Furthermore, different optical components within optical components 304 can vary in shape, size, location, and / or function.

[0041] like Figure 3 As shown, the example glass core 300 assembly includes through-glass vias 314. In some examples, Figure 3 The through-glass via 314 corresponds to Figure 2The through-glass vias 314 are defined by holes extending between the first surface 306 and the opposing second surface 308 and filled with a conductive material 320. In some examples, the conductive material 320 includes at least one of copper. In the illustrated example, the example glass core assembly 300 includes three through-glass vias 314. However, any suitable number of through-glass vias 314 can be included. In some examples, the glass core assembly 300 includes a single or two through-glass vias 314. In other examples, the glass core assembly 300 includes more than three through-glass vias 314. In the illustrated example, the through-glass vias 314 include walls 316, 318 between the glass substrate or core 302 and the conductive material 320 disposed in the through-glass vias 314. In some examples, a reflective metal 311 is disposed between the walls 316 of the through-glass vias 314 and the conductive material 320 disposed in the through-glass vias 314. That is, in some examples, the same material used for the reflective or light reflecting surface of the optical component 304 (e.g., reflective metal 311) rests directly against the wall 316 of the hole defining the through-glass via 314. In some cases, the thickness or depth of the reflective metal 311 disposed on the third surface 310 is approximately equal to the reflective metal 311 disposed on the wall 316. In some examples, the thickness of the reflective metal 311 is consistent between the optical component 304 and the through-glass via 314 because the reflective metal 311 is deposited at both locations at the same time (e.g., during the same manufacturing process). In the example shown, the reflective metal 311 is disposed across the entire wall 316 of the through-glass via 314. In other examples, the reflective metal extends a portion of the length of the walls 316, 318 (e.g., less than the full length), such as Figure 9 、 Figure 14 and Figure 19 described in further detail in .

[0042] Furthermore, in this example, the example glass core assembly 300 includes solder pads 322 located on the first surface 306 and the second surface 308 at the first end 324 and the second end 326 of the through-glass via 314. The solder pads 322 are composed of the same conductive material 320 that extends through the through-glass via 314. In some examples, a reflective metal 311 is disposed between the solder pads 322 and the first surface 306 and the second surface 308 of the glass core 302. In some cases, the reflective metal 311 adjacent to the solder pads 322 is an extension or continuation of (e.g., continuous with) the reflective metal 311 along the wall 316 of the through-glass via 314. Thus, in some examples, the thickness or depth of the reflective metal 311 disposed adjacent to the solder pads 322 is approximately equal to and / or consistent with the thickness or depth of the reflective metal 311 disposed on the third surface 310 and the wall 316.

[0043] In some examples, reflective metal 311 serves as a seed layer for conductive material 320 that penetrates glass via 314 and pad 322. Thus, in some examples, reflective metal 311 is the only material between glass core 302 and conductive material 320. In other words, in some examples, reflective metal 311 is in direct contact with glass core 302. Similarly, in some examples, conductive material 320 is in direct contact with reflective metal 311.

[0044] Figures 4 to 8 Shown in the manufacturing Figure 3 Different manufacturing stages 400, 500, 600, 700, 800 during an example process of an example glass core assembly 300. Figure 4 At manufacturing stage 400 shown in FIG, glass core 302 is provided with a cavity (e.g., a void, a recess, etc.) 309 and a through-glass via 314. In some examples, cavity 309 is defined by a third surface 310 that is non-planar or multi-dimensional. In other words, cavity 309 is not confined to a single plane of glass core 302. In some cases, cavity 309 is arched or curved, or at least includes an arched or curved portion. In some examples, facets or portions of third surface 310 of cavity 309 are angled relative to first surface 306 and second surface 308. In some examples, facets or portions of third surface 310 of cavity 309 are also angled relative to walls 316 of through-glass via 314 (which are substantially perpendicular to first surface 306 and second surface 308). In some examples, cavity 309 and through-glass via 314 are provided in glass core 302 using an etching process and / or a drilling process (e.g., laser drilling).

[0045] Figure 5 The manufacturing stage 500 is shown after a thin metal film of reflective metal 311 has been metallized (e.g., coated, disposed, etc.) over the entirety (e.g., all exposed surfaces) of the glass core 302. As a result of the metallization of the entirety of the glass core 302, the third surface 310 (associated with the cavity 309 for the optical component 304), the walls 316 of the through-glass via 314, and the first and second surfaces 306, 308 of the glass core 302 all share or are covered by a common reflective metal 311 provided in a single manufacturing process. In some examples, the reflective metal 311 is added to all exposed surfaces of the glass core 302 using a non-directional conformal coating process such as atomic layer deposition (ALD). In some examples, chemical vapor deposition (CVD) is used. Both ALD and CVD produce thin films having a relatively uniform thickness across all surfaces, such that the reflective metal 311 will have a relatively uniform thickness lining the walls 316 of the through-glass via 314 and the third surface 310 defining the cavity 309.

[0046] Rather than a single deposition process to add reflective metal 311 at all locations, as disclosed herein, existing methods typically use multiple separate manufacturing processes to add metal to different areas of the glass core 302. For example, a first deposition process may be performed to coat the walls 316 of the through-glass via 314 (to provide a seed layer for subsequent plating of the conductive material 320), and a second separate deposition process may be performed to add metal to the third surface 310 in the cavity 309 (to define a mirror or light reflecting surface for the optical component 304). Performing multiple deposition processes in this manner typically requires multiple lithographic operations (e.g., seeding, plating, and / or etching) to expose the target areas where metal will be applied during a given deposition process, while covering other areas during a given deposition process. In the disclosed examples, a common deposition or single deposition is performed to add reflective metal 311 at all locations where a thin metal film is desired. Thus, the disclosed examples not only reduce the number of deposition processes, but also reduce the number of deposition processes that are generated. Figure 3 The number of photolithographic operations required for the example glass core assembly 300 shown in FIG.

[0047] Figure 6 The manufacturing stage 600 is shown after depositing fill material 312 to fill cavity 309. In some cases, filler 312 is used to prevent conductive material 320 from being electrodeposited on reflective metal 311 during subsequent processing. Specifically, Figure 7 The manufacturing stage 700 is shown after a layer of conductive material 320 is deposited (e.g., plated) onto the glass core 302. In this example, the reflective metal 311 is used as a seed to facilitate the electroplating process. Thus, as shown in the illustrated example, the conductive material 320 is plated to fill the through-hole via 314 and cover the first surface 306 and the second surface 308 of the glass core 302 at the end of the through-glass via 314 (serving as the basis for the subsequently defined pad 320). Figure 8 Manufacturing stage 800 is shown after excess portions of conductive material are removed from glass core 302. In this example, the remaining portions of conductive material 320 include through-glass vias 314 and metal pads 322 located on first surface 306 and second surface 308 at the ends of through-glass vias 314. In some examples, selective etching (using a photolithographic process) and / or planarization are used to remove excess material from glass core 302.

[0048] Figure 9 Yes, you can Figure 1 and / or Figure 2 FIG. 1 is a cross-sectional view of another example glass core assembly 900 implemented in a packaging substrate 110 of FIG. Figure 9 An example glass core assembly 900 is Figure 2 For the purpose of explanation, Figure 9Example glass core assembly 900 with Figure 3 Components that are identical or similar to those in the example glass core assembly 300 are identified by the same reference numerals. Figure 9 As shown in FIG, the example glass core assembly 900 includes a glass substrate or core 302 in which an optical component 304 is embedded, as described above in Figure 3 In the example shown, the optical component 304 is adjacent to a first surface 306 of the example glass core assembly 900 that is opposite a second surface 308 .

[0049] In some examples, the reflective mirror or light reflecting surface of the optical component 304 is defined by a reflective metal 311 disposed on the third surface 310 of the glass core 302 (eg, the surface defining the cavity 309). Figure 3 described in and again in Figure 9 As shown in FIG, the optical component 304 includes a filling material 312 to fill the cavity 309. As previously mentioned, the shape, size, position and / or function of different optical components in the optical component 304 may be different. Figure 9 As shown, the example glass core assembly 900 includes through-glass vias 314. In the example shown, the example glass core assembly 900 includes three through-glass vias 314. However, any suitable number of through-glass vias 314 can be included. In some examples, the glass core assembly 900 includes a single or two through-glass vias 314. In other examples, the glass core assembly 900 includes more than three through-glass vias 314. In some examples, reflective metal 311 is disposed between walls 316 of the through-glass vias 314 and conductive material 320 disposed in the through-glass vias 314. However, unlike Figure 3 As shown in Figure 9 In the illustrated example of FIG, the reflective metal 311 extends only a portion (e.g., less than the entire) of the length 902 through the glass via 314. In some examples, the portion of the length 902 extends at least halfway through the glass via 314. In other examples, the portion of the length 902 extends less than halfway through the glass via 314, such as Figure 9. In addition, the example glass core assembly 900 includes solder pads 322 located on the first surface 306 and the second surface 308 at the first end 324 and the second end 326 of the through-glass via 314. Although the entire length of the through-glass via 314 is not lined with reflective metal 311, in this example, the two solder pads 322 are still separated from the glass core 302 by a thin layer of reflective metal 311. In other examples, the solder pads 322 on at least one of the surfaces 306, 308 of the glass core 302 are in direct contact with the glass core 302. That is, in some examples, there is no reflective metal 311 between some of the solder pads 322 and the glass core 302. In some such examples, the solder pads 322 that are in direct contact with the glass core 302 are the solder pads 322 located at the end of the through-glass via 314 opposite the portion of the length 902 of the via 314 on which the reflective metal 311 is disposed.

[0050] Figures 10 to 14 Shown in the manufacturing Figure 9 Different manufacturing stages 1000, 1100, 1200, 1300, 1400 during an example process of an example glass core assembly 900. Figure 10 At the manufacturing stage 1000 shown in FIG, the glass core 302 is provided with a cavity (eg, void, recess, etc.) 309 and a through-glass via 314 .

[0051] Figure 11 The manufacturing stage 1100 is shown after metallizing (eg, coating, disposing, etc.) a thin metal film of reflective metal 311 on the glass core 302. Figure 5 CVD and ALD are used to provide a conformal coating of reflective metal, using a directional deposition process. Figure 11 . An example deposition process that can be used is physical vapor deposition (PVD). However, any other suitable deposition process may be used in addition or alternatively. Due to the directional nature of the deposition process, the reflective metal 311 does not coat all surfaces, but is deposited on facing surfaces (e.g., in the example shown, on the side associated with the first surface 306 of the glass core 302). In some examples, the portion 902 of the through-glass via 314 coated with the reflective metal 311 corresponds to the distance within the via 314 that the metal 311 can reach during the deposition process. In some cases, the thickness of the reflective metal 311 tapers from the end of the through-glass via 314 toward the middle of the through-glass via 314. As a result of the directional deposition process, the first surface 306 of the glass core 302, the third surface 310 (associated with the cavity 309 for the optical component 304), and the portion 902 of the through-glass via 314 all share or are covered by a common reflective metal 311 provided in a single manufacturing process.

[0052] Figure 12 Manufacturing stage 1200 is shown after depositing fill material 312 to fill cavity 309 . Figure 13 The manufacturing stage 1300 is shown after a layer of conductive material 320 is deposited (e.g., plated) onto the glass core 302. In some examples, the reflective metal 311 is used as a seed to facilitate the electroplating process. Thus, as shown in the illustrated example, the conductive material 320 is plated to fill the through-hole via 314 and cover the first surface 306 of the glass core 302 (serving as a substrate) at the end of the through-glass via 314. Figure 14 322). Figure 14 The manufacturing stage 1400 is shown after additional conductive material 320 is added to the second surface of the glass core and then excess portions of conductive material 320 are removed from the glass core 302 to define metal pads 322. In some cases, Figure 13 After the manufacturing stage 1300 shown in Figure 14 Prior to manufacturing stage 1400 represented in , a separate layer of reflective metal 311 is deposited (in a separate directional deposition process) on the second surface 308 of the glass core. In such examples, the separate layer of reflective metal 311 is used to seed the pads 322 on the second surface 308. In other examples, the pads 322 on the second surface 308 are plated without the reflective metal 311. Because the separate layer of reflective metal 311 is deposited in a separate deposition process, any suitable material may be used in addition to or in place of the reflective metal 311 used in the process. For example, in some examples, titanium (Ti) and / or copper (Cu) are used to seed the pads 322 on the second surface 308. In some examples, selective etching and / or planarization is used to remove excess material from the glass core 302, such as Figure 14 shown.

[0053] Figures 15 to 19 Shown in the manufacturing Figure 19 Different manufacturing stages 1500 , 1600 , 1700 , 1800 , 1900 during an example process for another example glass core assembly 1902 . Figure 15 The manufacturing stages 1500 shown in FIG. Figure 4 and Figure 10 The manufacturing stages 400, 1000 shown in FIG are identical. Figure 16Manufacturing stage 1600 is shown after a thin metal film of reflective metal 311 is metallized on second surface 308 of glass core 302. In some examples, any suitable metal (whether reflective or not) can be used in addition to or in place of reflective metal 311 on second surface 308, as it is not associated with optical components and therefore does not need to be reflective. In this example, a directional deposition technique (e.g., CVD) is employed such that only second surface 308 is coated. However, at least some of reflective metal 311, or any other suitable metal, will be deposited on walls 316 of through-glass via 314 along a portion of length 1602 of through-glass via 314. Additionally, manufacturing stage 1600 shows that a layer of conductive material 320 is deposited onto glass core 302 after depositing reflective metal 311. In this example, reflective metal 311 serves as a seed layer to facilitate deposition (e.g., plating) of conductive material 320. As shown in the illustrated example, conductive material 320 is plated to fill the through-hole via 314 and to cover the second surface 308 of the glass core 302 (serving as a substrate) at the end of the through-glass via 314. Figure 19 322).

[0054] Figure 17 1. The manufacturing stage 1700 is shown after metallizing a second thin metal film of reflective metal 311 on the first surface 306 of the glass core 302. In some examples, the second film of reflective metal 311 is provided using a second directional deposition (e.g., CVD) process. As a result of the metallization process, the first surface 306 of the glass core 302 and the third surface 310 (associated with the cavity 309 for the optical component 304) both share or are covered by a common reflective metal 311 provided in a single manufacturing process. In this example, the first end 324 of the through-glass via 314 is covered by the thin metal film of reflective metal 311. Additionally, Figure 17 The manufacturing stage 1700 represented in FIG. 1 is after depositing fill material 312 to fill cavity 309 after depositing the second film of reflective metal 311.

[0055] Figure 18 Fabrication stage 1800 is shown after depositing a second layer 1802 of conductive material 320 onto glass core 302. As shown in the illustrated example, conductive material 320 is electroplated to cover first surface 306 of glass core 302 using a second thin film of reflective metal 311 as a seed layer. Figure 191 shows a manufacturing stage 1900 after excess portions of conductive material 320 are removed from glass core 302 to produce an example glass core assembly 1902. In this example, the remaining portions of conductive material 320 include through-glass vias 314 and metal pads 322 located on first surface 306 and second surface 308 at the ends of through-glass vias 314. In some examples, selective etching and / or planarization are used to remove excess material from glass core 302, such as Figure 19 shown.

[0056] Figure 20 is a diagram showing the manufacture of a glass core assembly (e.g., Figure 3 and Figure 9 Flowchart of an example method 2000 for producing a glass core assembly 300, 900) that utilizes a fewer number of deposition processes and a fewer number of photolithographic operations than the known manufacturing techniques described above. Figure 20 The flowchart shown describes an example manufacturing method, but many other methods may be used instead. For example, the order of execution of the blocks may be changed, and / or some blocks may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0057] Figure 20 The example process 2000 begins at block 2002 where a glass core is provided. In some examples, the glass core corresponds to Figures 3 to 19 At block 2004, a through-glass via is provided in the glass core 302. In some examples, the through-glass via corresponds to the through-glass via described above in conjunction with Figures 3 to 19 At block 2006, a recess is provided in the glass core 302. In some examples, the recess corresponds to the through-glass via 314 described above. Figures 3 to 19 309 as described in the figure. In some examples, the cavity 309 and the through-glass via 314 are provided in the glass core 302 using an etching process and / or a drilling process (e.g., laser drilling). At block 2008, a reflective metal and / or mirror metal (e.g., reflective metal 311) is simultaneously deposited (e.g., deposited during the same process) on the surface of the recess and on the surface of the glass core 302 associated with the through-glass via 314. In some examples, the surface of the glass core 302 covered by the reflective metal 311 depends on the nature of the deposition process used. For example, if a non-directional deposition technique (e.g., PVD, ALD) is used, all surfaces of the glass core 302 will be coated, including the full length of the through-glass via 314, as shown in FIG. Figure 5 On the other hand, if a directional deposition technique (eg, CVD) is used, only one side of the glass core 302 will be covered, and a portion of the length 902 of the through-glass via 314 will be covered by the reflective metal 311, as shown. Figure 11shown.

[0058] At block 2010, the recess is filled with a fill material. In some examples, the fill material corresponds to the fill material described above in Figure 3 At block 2012, a metal layer is plated using the exposed reflective metal as a seed. In some examples, the metal layer corresponds to Figure 3 In some cases, the process at block 2012 produces a metal layer 320 as described in Figure 7 In other examples, the process at block 2012 produces Figure 13 1300. In some examples, plating of the metal layer 320 continues beyond Figure 13 , to provide sufficient material to define metal pad 322. Finally, at block 2014, excess material is removed from glass core 302. In some examples, the excess material removed at block 2014 corresponds to metal layer 320 to leave only portions of conductive material 320 on the surface of glass core 302 corresponding to metal pad 322, as determined by Figure 8 and Figure 14 800, 1400. Thereafter, Figure 20 The example method ends and the glass core assembly can be used for further processing.

[0059] Figure 21 is a diagram showing the manufacture of a glass core assembly (e.g., Figure 19 Flowchart of an example method of manufacturing a glass core assembly 1902) that utilizes a fewer number of deposition processes and a fewer number of photolithography operations than required by known manufacturing techniques. Figure 21 The flowchart shown describes an example manufacturing method, but many other methods may be used instead. For example, the order of execution of the blocks may be changed, and / or some blocks may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0060] Figure 21 The example process 2100 is mirrored for the first three boxes. Figure 20 Example process 2000. In other words, Figure 21 Boxes 2102, 2104, and 2106 correspond to Figure 20 At block 2108, a seed metal is deposited on the first surface of the glass core 302. In some examples, the seed metal is a reflective metal 311, and in other examples, any other suitable metal may be used. At block 2110, a metal layer is deposited on the seed metal. In some examples, the deposition of the metal layer continues long enough to allow the metal to fill the through-glass via 314. In some examples, completion of block 2110 corresponds to Figure 16 16. In other examples, plating of the metal layer (e.g., block 2110) is not included until further along in the process. At block 2112, reflective metal 311 is deposited on a second surface of the glass core, the second surface opposite the first surface including cavity 309. In some examples, reflective metal 311 spans or covers exposed portions of the metal layer (e.g., conductive material 320) at the ends of through-glass vias 314 adjacent to the second surface of glass core 302. In some examples, completion of block 2112 corresponds to Figure 17 Manufacturing stage 1700 is shown in FIG. Figure 21 The example process 2100 is mirrored for the last three boxes. Figure 20 Example process 2000. In other words, Figure 21 Boxes 2114, 2116, and 2118 correspond to Figure 20 2010, 2012 and 2014. However, in Figure 21 In the embodiment of the present invention, the plating of the metal (block 2116) can only occur on the second surface of the glass core because the metal has already been deposited on the reflective metal 311 on the first surface at block 2110 as described above. Figure 21 The example method ends and the glass core assembly can be used for further processing.

[0061] The example glass core assemblies 300 , 900 , 1902 disclosed herein may be included in any suitable electronic component. Figures 22 to 25 Various examples of devices that may include, be included in, or otherwise coupled to the glass core assemblies 300, 900, 1902 disclosed herein are shown.

[0062] Figure 22 can be included in Figure 1 108) in an IC package 100 that includes any of the example glass core assemblies 300, 900, 1902. Wafer 2200 may be composed of semiconductor material and may include one or more die 2202 having circuitry. Each of the die 2202 may be a repeating unit of a semiconductor product. After fabrication of the semiconductor product is complete, wafer 2200 may undergo a singulation process in which the die 2202 are separated from one another to provide discrete "chips." The die 2202 may include one or more transistors (e.g., transistors discussed below). Figure 23Some of the transistors 2340), support circuitry for routing electrical signals to the transistors, passive components (e.g., traces, resistors, capacitors, inductors, and / or other circuitry), and / or any other components. In some examples, die 2202 can include and / or implement memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuitry. Multiple of these devices can be combined on a single die 2202. For example, a memory array formed of multiple memory circuits can be formed on a die with programmable circuitry (e.g., Figure 25 2502) or other logic circuitry on the same die 2202. Such memory may store information used by the programmable circuitry.

[0063] Figure 23 is a cross-sectional side view of an IC device 2300 that may be included in an example IC package 100 (e.g., in any of the dies 106, 108) that includes any of the example glass core assemblies 300, 900, 1902. One or more of the IC devices 2300 may be included in one or more of the dies 2202 ( Figure 22 ). The IC device 2300 may be formed on a die substrate 2302 (eg, Figure 22 2200) and may be included in a die (e.g., Figure 22 The die substrate 2302 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 2302 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 2302 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as groups II-VI, III-V, or IV may also be used to form the die substrate 2302. Although several examples of materials that may form the die substrate 2302 are described herein, any material that may serve as the basis for the IC device 2300 may be used. The die substrate 2302 may be a singulated die (e.g., Figure 22 of die 2202) or wafer (e.g., Figure 22 portion of wafer 2200).

[0064] The IC device 2300 may include one or more device layers 2304 disposed on or above a die substrate 2302. The device layer 2304 may include features of one or more transistors 2340 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 2302. The device layer 2304 may include, for example, one or more source and / or drain (S / D) regions 2320, a gate 2322 for controlling the flow of current between the S / D regions 2320, and one or more S / D contacts 2324 for routing electrical signals to / from the S / D regions 2320. The transistor 2340 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 2340 is not limited to Figure 23 The types and configurations depicted in the drawings may include a variety of other types and / or configurations, such as, for example, planar transistors, non-planar transistors, or a combination of the two. Non-planar transistors may include FinFET transistors such as double-gate transistors or tri-gate transistors, and all-around gate or gate-all-around transistors such as nanoribbon and nanowire transistors.

[0065] Each transistor 2340 may include a gate 2322 formed from at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one or more layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be performed on the gate dielectric to improve its quality when using high-k materials.

[0066] Depending on whether transistor 2340 will be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor, a gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. For other purposes, additional metal layers, such as barrier layers, may be included. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0067] In some examples, when a cross section of transistor 2340 is viewed along the source-channel-drain direction, the gate electrode may be comprised of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 2302 and two sidewall portions substantially perpendicular to the top surface of die substrate 2302. In other examples, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 2302 and may not include a sidewall portion substantially perpendicular to the top surface of die substrate 2302. In other examples, the gate electrode may be comprised of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

[0068] In some examples, a pair of sidewall spacers can be formed on opposite sides of the gate stack to encase the gate stack. The sidewall spacers can be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process steps. In some examples, multiple pairs of spacers can be used; for example, two, three, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

[0069] The S / D regions 2320 can be formed within the die substrate 2302 adjacent to the gate 2322 of each transistor 2340. For example, the S / D regions 2320 can be formed using an implantation / diffusion process or an etching / deposition process. In the implantation process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the die substrate 2302 to form the S / D regions 2320. An annealing process to activate the dopants and diffuse them further into the die substrate 2302 can follow the implantation process. In the etching process, the die substrate 2302 can first be etched to form recesses at the locations of the S / D regions 2320. An epitaxial deposition process can then be performed to fill the recesses with the material used to form the S / D regions 2320. In some embodiments, the S / D regions 2320 can be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy can be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some examples, one or more alternative semiconductor materials such as germanium or a III-V material or alloy can be used to form the S / D region 2320. In other examples, the S / D region 2320 can be formed using one or more layers of metal and / or metal alloys.

[0070] By providing one or more interconnect layers (on the Figure 23 2306-2310) to and / or from devices (e.g., transistors 2340) of device layer 2304. For example, conductive features (e.g., gates 2322 and S / D contacts 2324) of device layer 2304 can be electrically coupled to interconnect structures 2328 of interconnect layers 2306-2310. One or more interconnect layers 2306-2310 can form a metallization stack (also referred to as an "ILD stack") 2319 of IC device 2300.

[0071] Interconnect structures 2328 may be arranged within interconnect layers 2306-2310 to route electrical signals according to a variety of designs (particularly, the arrangement is not limited to Figure 23 ). Although Figure 23 A specific number of interconnect layers 2306 - 2310 are depicted in FIG, but examples of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0072] In some examples, the interconnect structure 2328 may include wires 2328a and / or vias 2328b filled with a conductive material such as metal. The wires 2328a may be arranged to route electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 2302 on which the device layer 2304 is formed. For example, the wires 2328a may be arranged to route electrical signals in a direction substantially parallel to a plane of the die substrate 2302 on which the device layer 2304 is formed. Figure 23 The vias 2328b can be arranged to route electrical signals in a direction substantially perpendicular to the plane of the surface of the die substrate 2302 on which the device layer 2304 is formed. In some examples, the vias 2328b can electrically couple together the lines 2328a of different interconnect layers 2306-2310.

[0073] The interconnect layers 2306-2310 may include a dielectric material 2326 disposed between interconnect structures 2328, such as Figure 23 In some examples, the dielectric material 2326 disposed between the interconnect structures 2328 in different ones of the interconnect layers 2306 - 2310 can have different compositions; in other examples, the composition of the dielectric material 2326 between different interconnect layers 2306 - 2310 can be the same.

[0074] A first interconnect layer 2306 (referred to as metal 1 or "M1") can be formed directly on the device layer 2304. In some examples, as shown, the first interconnect layer 2306 can include lines 2328a and / or vias 2328b. The lines 2328a of the first interconnect layer 2306 can be coupled to contacts of the device layer 2304 (e.g., S / D contacts 2324).

[0075] A second interconnect layer 2308 (referred to as metal 2 or "M2") can be formed directly on the first interconnect layer 2306. In some examples, the second interconnect layer 2308 can include vias 2328b to couple the lines 2328a of the second interconnect layer 2308 with the lines 2328a of the first interconnect layer 2306. Although the lines 2328a and vias 2328b are structurally outlined with lines within each interconnect layer (e.g., within the second interconnect layer 2308) for clarity, in some examples, the lines 2328a and vias 2328b can be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0076] A third interconnect layer 2310 (referred to as Metal 3 or "M3") (and additional interconnect layers, as needed) can be formed continuously on the second interconnect layer 2308 according to similar techniques and configurations as described in connection with the second interconnect layer 2308 or the first interconnect layer 2306. In some examples, the interconnect layers in the IC device 2300 that are "higher" in the metallization stack 2319 (i.e., further away from the device layer 2304) can be thicker.

[0077] IC device 2300 may include a solder resist material 2334 (e.g., polyimide or similar material) and one or more conductive contacts 2336 formed on interconnect layers 2306-2310. Figure 23In some examples, the conductive contacts 2336 are shown taking the form of bond pads. The conductive contacts 2336 can be electrically coupled with the interconnect structures 2328 and configured to route electrical signals of the transistor 2340 to other external devices. For example, solder bonds can be formed on one or more of the conductive contacts 2336 to mechanically and / or electrically couple a chip including the IC device 2300 with another component (e.g., a circuit board). The IC device 2300 can include additional or alternative structures to route electrical signals from the interconnect layers 2306-2310; for example, the conductive contacts 2336 can include other similar features (e.g., pillars) to route electrical signals to external components.

[0078] Figure 24 is a cross-sectional side view of an IC device assembly 2400 that can include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100, which can include any of the example glass core assemblies 300, 900, 1902. The IC device assembly 2400 includes several components disposed on a circuit board 2402, which can for example be a motherboard. The IC device assembly 2400 includes components disposed on a first face 2440 of the circuit board 2402 and an opposing second face 2442 of the circuit board 2402; generally, components can be disposed on one or both of the faces 2440 and 2442. Any of the IC packages discussed below with respect to the IC device assembly 2400 can take the form of the example IC package 100. Figure 1

[0079] In some examples, the circuit board 2402 can be a printed circuit board (PCB) that includes a plurality of metal layers separated from one another by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers can be formed in a desired circuit pattern to route electrical signals between components coupled to the circuit board 2402 (optionally in combination with other metal layers). In other examples, the circuit board 2402 can be a non-PCB substrate. In some examples, the circuit board 2402 can be, for example, the circuit board 102 of Figure 1

[0080] Figure 24 The IC device assembly 2400 shown in FIG. 24 includes a package-on- interposer structure 2436 coupled to the first face 2440 of the circuit board 2402 by coupling components 2416. The coupling components 2416 can electrically and mechanically couple the package-on-interposer structure 2436 to the circuit board 2402 and can include solder balls (as shown in FIG. 24), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure. Figure 24

[0081] ​​​The interposer-on-package structure 2436 can include an IC package 2420 coupled to the interposer 2404 by coupling components 2418. The coupling components 2418 can take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2416. Although Figure 24 A single IC package 2420 is shown, but multiple IC packages can be coupled to the interposer 2404; indeed, additional interposers can be coupled to the interposer 2404. The interposer 2404 can provide an intervening substrate for bridging the circuit board 2402 and the IC package 2420. The IC package 2420 can be or include, for example, a die (e.g., the die 2202), an IC device (e.g., the IC device 2300), or any other suitable component. In general, the interposer 2404 can extend connections to a wider pitch or re-route connections to different connections. For example, the interposer 2404 can couple the IC package 2420 (e.g., a die) to a set of BGA conductive contacts of the coupling components 2416 to couple to the circuit board 2402. In Figure 22 the example shown, the IC package 2420 and the circuit board 2402 are attached to opposite sides of the interposer 2404; in other examples, the IC package 2420 and the circuit board 2402 can be attached to the same side of the interposer 2404. In some examples, three or more components can be interconnected through the interposer 2404. Figure 23 Figure 24 In some examples, the interposer 1704 can be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 1704 can be formed of epoxy, fiberglass-reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some examples, the interposer 2404 can be formed of alternative rigid or flexible materials, which can include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2404 can include metal interconnects 2408 and vias 2410, including but not limited to through-silicon vias (TSVs) 2406. The interposer 2404 can also include embedded devices 2414, including passive and active devices. Such devices can include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices can also be formed on the interposer 2404, such as radio-frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices. The interposer-on-package structure 2436 can take the form of any interposer-on-package structure known in the art.

[0082] In some examples, the interposer 1704 can be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 1704 can be formed of epoxy, fiberglass-reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some examples, the interposer 2404 can be formed of alternative rigid or flexible materials, which can include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2404 can include metal interconnects 2408 and vias 2410, including but not limited to through-silicon vias (TSVs) 2406. The interposer 2404 can also include embedded devices 2414, including passive and active devices. Such devices can include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices can also be formed on the interposer 2404, such as radio-frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices. The interposer-on-package structure 2436 can take the form of any interposer-on-package structure known in the art.

[0083] ​IC device assembly 2400 may include an IC package 2424 coupled to first side 2440 of circuit board 2402 via coupling component 2422. Coupling component 2422 may take the form of any of the examples discussed above with reference to coupling component 2416, and IC package 2424 may take the form of any of the examples discussed above with reference to IC package 2420.

[0084] Figure 24 The IC device assembly 2400 shown in FIG4 includes a package-on-package structure 2434 coupled to the second side 2442 of the circuit board 2402 via a coupling component 2428. The package-on-package structure 2434 may include a first IC package 2426 and a second IC package 2432 coupled together via a coupling component 2430, such that the first IC package 2426 is disposed between the circuit board 2402 and the second IC package 2432. The coupling components 2428, 2430 may take the form of any of the examples of the coupling component 2416 discussed above, and the IC packages 2426, 2432 may take the form of any of the examples of the IC package 2420 discussed above. The package-on-package structure 2434 may be configured according to any package-on-package structure known in the art.

[0085] Figure 25 Yes, it can include Figure 1 100, which includes one or more of the example glass core assemblies 300, 900, 1902. For example, any suitable component of the components of the electrical device 2500 may include one or more of the device assembly 2400, IC device 2300, or die 2202 disclosed herein and may be arranged in the example IC package 100. Figure 25 Several components are shown as included in electrical device 2500, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some examples, some or all of the components included in electrical device 2500 may be attached to one or more motherboards. In some examples, some or all of these components are fabricated onto a single system-on-chip (SoC) die.

[0086] Additionally, in various examples, the electrical device 2500 may not include Figure 252500, but may include interface circuitry for coupling to one or more of the components. For example, the electrical device 2500 may not include the display 2506, but may include display interface circuitry (e.g., a connector and driver circuitry) to which the display 2506 may be coupled. In another set of examples, the electrical device 2500 may not include an audio input device 2524 (e.g., a microphone) or an audio output device 2508 (e.g., a speaker, headphones, earbuds, etc.), but may include audio input or output device interface circuitry (e.g., a connector and supporting circuitry) to which the audio input device 2524 or audio output device 2508 may be coupled.

[0087] The electrical device 2500 may include a programmable circuit system 2502 (e.g., one or more processing devices). The programmable circuit system 2502 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 2500 may include a memory 2504, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some examples, the memory 2504 may include a memory that shares a die with the programmable circuit system 2502. The memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0088] In some examples, the electrical device 2500 may include a communication chip 2512 (e.g., one or more communication chips). For example, the communication chip 2512 may be configured to manage wireless communications for transmitting data to and from the electrical device 2500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some examples they may not.

[0089] The communication chips 2512 can implement any of a number of wireless standards or protocols, including but not limited to IEEE 802.11 standards (including IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ah, IEEE 802.1 lad, and / or IEEE 802.1 lax), Bluetooth, Bluetooth Low Energy, IEEE 802.16 (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project

[0090] In some examples, the communication chips 2512 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chips 2512 can include multiple communication chips. For example, a first communication chip 2512 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 2512 can be dedicated to longer-range wireless communication, such as a global

[0091] The electrical device 2500 may include a battery / power circuitry 2514. The battery / power circuitry 2514 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 2500 to an energy source separate from the electrical device 2500 (e.g., AC line power).

[0092] The electrical device 2500 may include a display 2506 (or corresponding interface circuitry, as described above). The display 2506 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0093] The electrical device 2500 may include an audio output device 2508 (or corresponding interface circuitry, as described above). The audio output device 2508 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0094] The electronic device 2500 may include an audio input device 2524 (or corresponding interface circuitry, as described above). The audio input device 2524 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0095] The electrical device 2500 may include GPS circuitry 2518. The GPS circuitry 2518 may communicate with a satellite-based system and may receive the location of the electrical device 2500, as is known in the art.

[0096] The electrical device 2500 may include any other output devices 2510 (or corresponding interface circuitry, as described above). Examples of other output devices 2510 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0097] The electronic device 2500 may include any other input device 2520 (or corresponding interface circuitry, as described above). Examples of other input devices 2520 may include an accelerometer, a gyroscope, a compass, an image acquisition device, a keyboard, a cursor control device such as a mouse, a stylus, or a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0098] The electronic device 2500 can have any desired form factor, such as a handheld or mobile electronic device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electronic device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electronic device. In some examples, the electronic device 2500 can be any other electronic device that processes data.

[0099] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., includes, contains, has, etc.) as a preamble or is used within any type of claim reference, it should be understood that additional elements, items, etc. may be present without falling outside the scope of the corresponding claim or reference. As used herein, when the phrase "at least" is used as a transition term, such as in the preamble of a claim, it is open-ended in the same manner as the terms "comprising" and "including" are open-ended. The term "and / or" when used, for example, in a form such as A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or execution of a process, instruction, action, activity, and / or step, the phrase "at least one of A or B" is intended to refer to an embodiment that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0100] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. In addition, although listed separately, multiple modules, elements, or method actions can be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and including in different examples or claims does not imply that the combination of features is not feasible and / or advantageous.

[0101] From the foregoing, it can be appreciated that example systems, methods, apparatus, and articles have been disclosed that produce glass core assemblies using fewer deposition processes and fewer photolithography operations than known methods by depositing reflective metal on surfaces of cavities in a glass core and on other surfaces of the glass core associated with metal interconnects (e.g., through-glass vias and associated conductive pads) in a single deposition process. The reflective metal in the cavity serves the purpose of a reflective surface of an optical component (e.g., a mirror), and the reflective metal on the other surfaces serves the purpose of seed metal for subsequent deposition of conductive material (e.g., copper) for the metal interconnects. In effect, reducing the number of process operations required for the glass core assembly reduces the amount of defects in the glass core assembly. Apparatus and manufacturing methods are disclosed that save time and cost in producing the glass core assemblies described herein. Accordingly, the disclosed systems, methods, apparatus, and articles are accordingly directed to one or more improvements in the operation of machines (such as computers or other electronic and / or mechanical devices).

[0102] Disclosed herein are example methods, apparatus, systems, and articles for photonic integrated circuit packaging. Further examples and combinations thereof include the following:

[0103] Example 1 includes an integrated circuit (IC) package comprising: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate comprising a glass core, the glass core comprising a through-glass via extending between opposing first and second surfaces of the glass core, the glass core comprising a recess spaced apart from the through-glass via, the recess being defined by a third surface of the glass core, the recess having a different shape than the through-glass via; and a reflective metal disposed on the third surface to define a reflector, the reflective metal also being disposed between a wall of the through-glass via and a conductive material disposed in the through-glass via.

[0104] Example 2 includes the device defined in Example 1, wherein the third surface is a non-planar surface.

[0105] Example 3 includes the device defined in Example 1, wherein the reflective metal on the third surface is a first thickness and the reflective metal on the wall of the through-glass via is a second thickness, the first thickness being approximately equal to the second thickness.

[0106] Example 4 includes the apparatus defined in Example 1, wherein the third surface is angled relative to a wall of the through-glass via and angled relative to the first and second surfaces of the glass core.

[0107] Example 5 includes the apparatus defined in Example 1, wherein the third surface is arcuate.

[0108] Example 6 includes the apparatus defined in Example 1, wherein the reflective metal on the wall of the through-glass via extends between the first and second surfaces of the glass core throughout the entire length of the glass via.

[0109] Example 7 includes the apparatus defined in Example 1, wherein the reflective metal on the wall of the through-glass via extends a portion of the length of the through-glass via between the first and second surfaces of the glass core.

[0110] Example 8 includes the apparatus of Example 7, wherein the portion of the length of the through-glass via comprising the reflective metal is at a first end of the via adjacent the first surface of the glass core, the recess being in the first surface of the glass core.

[0111] Example 9 includes the apparatus of Example 7, wherein the portion of the length of the through-glass via comprising the reflective metal is at a first end of the via adjacent the first surface of the glass core, and the recess is in the second surface of the glass core.

[0112] Example 10 includes the apparatus of Example 1, wherein the conductive material defines a pad on the first surface of the glass core, the recess is in the first surface of the glass core, the pad is electrically coupled to the conductive material in the through-glass via, and the reflective metal is disposed between the pad and the first surface of the glass core.

[0113] Example 11 includes the device defined in Example 1, wherein the reflective metal includes aluminum.

[0114] Example 12 includes the device defined in Example 1, wherein the reflective metal includes gold.

[0115] Example 13 includes the device defined in Example 1, wherein the reflective metal includes silver.

[0116] Example 14 includes the device defined in Example 1, wherein the reflective metal comprises ruthenium.

[0117] Example 15 includes the device defined in Example 1, wherein the reflective metal is in direct contact with the third surface and in direct contact with a wall of the through-glass via.

[0118] Example 16 includes an integrated circuit (IC) package comprising: a package substrate; a semiconductor die mounted on the package substrate; and a glass core within the package substrate, the glass core comprising a through-glass via extending through the glass core, the glass core comprising a void spaced apart from the through-glass via, the void having a different shape than the through-glass via, the surfaces of both the through-glass via and the void being lined with a common reflective metal that reflects light that would otherwise pass through the glass core.

[0119] Example 17 includes the device defined in Example 16, wherein the surface of the void is a multi-dimensional surface.

[0120] Example 18 includes the apparatus defined in Example 16, wherein the reflective metal on the surface of the void has a first depth and the reflective metal on the surface of the through-glass via is a second depth, the first depth coinciding with the second depth.

[0121] Example 19 includes the apparatus defined in Example 16, wherein the glass core has opposing first and second sides, and a surface of the void is inclined relative to the first and second sides of the glass core.

[0122] Example 20 includes the device defined in Example 16, wherein the surface of the void is curved.

[0123] Example 21 includes the device defined in Example 16, wherein the reflective metal covers the entire length of the surface of the through-glass via from the first side of the glass core to the second side of the glass core.

[0124] Example 22 includes the apparatus as defined in Example 16, wherein the reflective metal on the surface of the through-glass via extends a portion of the length of the through-glass via from the first side of the glass core to the second side of the glass core.

[0125] Example 23 includes the apparatus of Example 22, wherein the portion of the length of the through-glass via comprising the reflective metal is at a first end of the via adjacent to the first side of the glass core, the void being in the first side of the glass core.

[0126] Example 24 includes the apparatus of Example 22, wherein the portion of the length of the through-glass via comprising the reflective metal is at a first end of the via adjacent to the first side of the glass core, and the recess is in the second side of the glass core.

[0127] Example 25 includes the device of Example 16, wherein the reflective metal is disposed on the first surface at a first partial length and a second partial length and on the second surface at a third partial length and a fourth partial length, the first surface and the second surface being adjacent to the first end and the second end of the via, respectively, and the conductive material is disposed on the first partial length and the second partial length and the third partial length and the fourth partial length to define the first contact portion and the second contact portion.

[0128] Example 26 includes the device defined in Example 16, wherein the reflective metal comprises at least one of aluminum, gold, or silver.

[0129] Example 27 includes a method of manufacturing an integrated circuit package, the method comprising: providing a through-glass via in a glass core; providing a recess in the glass core that is spaced apart from the through-glass via; and depositing a metal film on surfaces of both the through-glass via and the recess at the same point in time.

[0130] Example 28 includes the method of Example 27, comprising depositing the conductive material on the glass core using the metal film as a seed.

[0131] Example 29 includes the method defined in Example 28, comprising removing a portion of at least one of the metal film or the conductive metal from the glass core.

[0132] Example 30 includes the method defined in Example 27, wherein depositing the metal film involves at least one of atomic layer deposition or physical vapor deposition.

[0133] Example 31 includes the method defined in Example 27, wherein depositing the metal film involves physical vapor deposition.

[0134] Example 32 includes the method defined in Example 27, wherein depositing the metal film involves a conformal coating process such that a thickness of the metal film is substantially uniform on surfaces of both the through-glass via and the recess.

[0135] The following claims are hereby incorporated into this detailed description by this reference. Although certain example systems, methods, devices, and articles have been disclosed herein, the scope of coverage of this patent is not limited thereto. Rather, this patent covers all systems, methods, devices, and articles that fully fall within the scope of the claims of this patent.

Claims

1. An integrated circuit (IC) package, comprising: semiconductor die; a package substrate supporting the semiconductor die, the package substrate comprising a glass core, the glass core including a through-glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through-glass via, the recess defined by a third surface of the glass core, the recess having a different shape than the through-glass via; as well as A reflective metal is disposed on the third surface to define a reflector, the reflective metal also being disposed between a wall of the through-glass via and a conductive material disposed in the through-glass via.

2. The device according to claim 1, wherein The third surface is a non-planar surface.

3. The device according to claim 1, wherein The reflective metal on the third surface is a first thickness and the reflective metal on the wall of the through-glass via is a second thickness, the first thickness being approximately equal to the second thickness.

4. The apparatus according to claim 1, wherein The third surface is angled relative to the wall of the through-glass via and angled relative to the first and second surfaces of the glass core.

5. The device according to any one of claims 1 to 4, wherein: The reflective metal on the wall of the through-glass via extends the entire length of the through-glass via between the first and second surfaces of the glass core.

6. The device according to any one of claims 1 to 4, wherein: The reflective metal on the wall of the through-glass via extends a portion of the length of the through-glass via between the first and second surfaces of the glass core.

7. The apparatus according to claim 6, wherein The portion of the through-glass via length including the reflective metal is at a first end of the via adjacent the first surface of the glass core in which the recess is located.

8. The apparatus according to any one of claims 1 to 4, wherein: The conductive material defines a pad on the first surface of the glass core, the recess is in the first surface of the glass core, the pad is electrically coupled to the conductive material in the through-glass via, and the reflective metal is disposed between the pad and the first surface of the glass core.

9. The apparatus according to any one of claims 1 to 4, wherein: The reflective metal includes ruthenium.

10. The apparatus according to any one of claims 1 to 4, wherein: The reflective metal includes aluminum.

11. The apparatus according to any one of claims 1 to 4, wherein: The reflective metal includes gold.

12. The apparatus according to any one of claims 1 to 4, wherein: The reflective metal includes silver.

13. The apparatus according to any one of claims 1 to 4, wherein: The reflective metal is in direct contact with the third surface and in direct contact with the wall of the through-glass via.

14. An integrated circuit (IC) package, comprising: Package substrate; a semiconductor die mounted on the package substrate; as well as A glass core is provided within the package substrate, the glass core including a through-glass via extending through the glass core, the glass core including a void spaced apart from the through-glass via, the void having a different shape from the through-glass via, and surfaces of both the through-glass via and the void being lined with a common reflective metal configured to reflect light that is about to pass through the glass core.

15. The apparatus according to claim 14, wherein The surface of the void is a multi-dimensional surface.

16. The apparatus according to claim 14, wherein The reflective metal on the surface of the void has a first depth, and the reflective metal on the surface of the through-glass via is a second depth, the first depth being consistent with the second depth.

17. The apparatus according to claim 14, wherein The glass core has opposing first and second sides, and a surface of the void is inclined relative to the first side and inclined relative to the second side of the glass core.

18. The apparatus according to claim 14, wherein The surface of the void is curved.

19. The apparatus according to any one of claims 14 to 18, wherein The reflective metal on the surface of the through-glass via extends a portion of the length of the through-glass via from a first side of the glass core to a second side of the glass core.

20. The apparatus according to claim 19, wherein The portion of the through-glass via length including the reflective metal is at a first end of the via adjacent a first side of the glass core, and the recess is in a second side of the glass core.

21. The apparatus according to any one of claims 14 to 18, wherein The reflective metal is arranged on the first surface to have a first partial length and a second partial length and on the second surface to have a third partial length and a fourth partial length, the first surface and the second surface are adjacent to the first end and the second end of the via, respectively, and a conductive material is arranged on the first partial length and the second partial length and the third partial length and the fourth partial length to define a first contact portion and a second contact portion.

22. A method of manufacturing an integrated circuit package, the method comprising: providing a through-glass via in the glass core; providing a recess in the glass core spaced apart from the through-glass via; as well as A metal film is deposited on surfaces of both the through-glass via and the recess at the same time.

23. The method of claim 22, comprising depositing a conductive material on the glass core using the metal film as a seed.

24. The method according to any one of claims 22-23, wherein Depositing the metal film involves at least one of atomic layer deposition or physical vapor deposition.

25. The method according to any one of claims 22-23, wherein Depositing the metal film involves a conformal coating process such that the thickness of the metal film is substantially uniform across the surfaces of both the through-glass via and the recess.

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