Deposition mask and electronic device

Abstract

The invention relates to a deposition mask and an electronic device. The deposition mask includes: a mask substrate including a plurality of cell regions and a cell peripheral region surrounding the plurality of cell regions; a mask diaphragm disposed in the plurality of cell regions of the mask substrate and including a mask shield defining a pixel opening; a mask frame disposed in the cell peripheral region of the mask substrate and including a first upper inorganic layer on the mask substrate and a second upper inorganic layer on the first upper inorganic layer; and a mask conductive layer including a first portion on the mask frame and a second portion on the mask shield, where the first portion and the second portion are spaced apart from each other and the pixel opening is between the first portion and the second portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2024-0047871, filed on April 9, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a deposition mask and an electronic device. Background Art

[0004] Wearable devices in the form of glasses or helmets that focus near the user's eyes are being developed recently. For example, the wearable device can be a head-mounted display (HMD) device or augmented reality (AR) glasses. Such wearable devices provide the user with an AR screen or a virtual reality (VR) screen.

[0005] Wearable devices such as HMDs and AR glasses require display specifications of at least 2,000 pixels per inch (PPI) to allow users to use the wearable devices for a long time without feeling dizzy. Therefore, organic light-emitting diode on silicon (OLEDoS) technology, which is a high-resolution, small-sized organic light-emitting element display device, can be used for such wearable devices. OLEDoS is a technology for disposing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed. Summary of the Invention

[0006] Embodiments of the present disclosure provide a silicon deposition mask capable of manufacturing a high-resolution display panel.

[0007] Embodiments of the present disclosure also provide a deposition mask that can prevent the mask from being damaged during use.

[0008] It should be noted that the embodiments of the present disclosure are not limited to the embodiments described herein; and other embodiments of the present disclosure will be apparent to those skilled in the art from the following description.

[0009] In an embodiment of the present disclosure, a deposition mask includes: a mask substrate, including a plurality of unit areas and a unit peripheral area surrounding the plurality of unit areas; a mask diaphragm, arranged in the plurality of unit areas of the mask substrate and including a mask shield defining a pixel opening; a mask frame, arranged in the unit peripheral area of ​​the mask substrate and including a first upper inorganic layer located on the mask substrate and a second upper inorganic layer located on the first upper inorganic layer; and a mask conductive layer, including a first portion located on the mask frame and a second portion located on the mask shield, wherein the first portion and the second portion are spaced apart from each other, and the pixel opening is between the first portion and the second portion.

[0010] In an embodiment, the height of the mask conductive layer may be equal to or greater than about 20 nanometers and equal to or less than about 300 nanometers.

[0011] In an embodiment, the mask conductive layer may include a conductive metal material.

[0012] In an embodiment, the first portion may completely surround the mask frame, and the second portion of the mask conductive layer completely surrounds the mask shield.

[0013] In embodiments, the second upper inorganic layer may include a protrusion protruding toward the plurality of unit regions than a side surface of the first upper inorganic layer, and the first portion may overlap the protrusion of the second upper inorganic layer in a thickness direction of the mask substrate.

[0014] In embodiments, the side surface of the first upper inorganic layer and the protrusion of the second upper inorganic layer may collectively form an undercut.

[0015] In an embodiment, the first portion may completely cover the undercut.

[0016] In embodiments, the first portion may contact the mask substrate, the first upper inorganic layer, and the second upper inorganic layer.

[0017] In an embodiment, the second portion may be in full contact with the mask shield.

[0018] In an embodiment, the mask frame may further include: a first lower inorganic layer located on a side of the mask substrate opposite to the first upper inorganic layer; and a second lower inorganic layer located on the first lower inorganic layer, and the mask conductive layer may contact the first lower inorganic layer and the second lower inorganic layer.

[0019] In an embodiment, the first upper inorganic layer and the first lower inorganic layer may include the same material as each other, and the second upper inorganic layer and the second lower inorganic layer may include the same material as each other.

[0020] In embodiments, the mask shield may include the same material as the second upper inorganic layer.

[0021] In an embodiment, the height of the mask shield may be equal to or greater than approximately 0.5 micrometers and equal to or less than approximately 2.5 micrometers.

[0022] In an embodiment, the mask substrate may further include an edge surface including an edge of the mask substrate, and the mask conductive layer may further include a third portion overlapping the edge surface.

[0023] In an embodiment, the third portion may be spaced apart from the second portion, with the pixel opening being between the third portion and the second portion.

[0024] In an embodiment, the mask cover may completely surround the pixel opening in plan view, and the mask frame may completely surround the mask membrane in plan view.

[0025] In an embodiment, the mask substrate may include silicon, and the mask substrate has a circular shape in a plan view.

[0026] In embodiments, the second upper inorganic layer may include a first surface at an opposite side opposite to a side of the second upper inorganic layer facing the first upper inorganic layer, and the first portion may completely contact the first surface of the second upper inorganic layer.

[0027] In embodiments, the first portion may be in contact with neither the first upper inorganic layer nor the mask substrate.

[0028] In an embodiment, the mask shield may include a second surface facing the mask conductive layer, wherein the second portion may fully contact the second surface of the mask shield and may not contact a side surface of the mask shield facing the pixel opening.

[0029] In an embodiment, an electronic device includes: a display device including a display panel formed using a deposition mask; a mask substrate including a plurality of unit areas and a unit peripheral area surrounding the plurality of unit areas; a mask diaphragm disposed in the plurality of unit areas of the mask substrate and including a mask shield defining a pixel opening; a mask frame disposed in the unit peripheral area of ​​the mask substrate and including a first upper inorganic layer located on the mask substrate and a second upper inorganic layer located on the first upper inorganic layer; and a mask conductive layer including a first portion located on the mask frame and a second portion located on the mask shield, wherein the first portion and the second portion are spaced apart from each other and the pixel opening is between the first portion and the second portion.

[0030] According to an embodiment of the present disclosure, a deposition mask can be used to manufacture a high-resolution display panel. In such an embodiment, the deposition mask according to the embodiment includes a mask conductive layer covering a mask substrate and a mask diaphragm, so that mask damage defects that may occur during use can be effectively prevented.

[0031] It will be understood that the effects of the embodiments of the present disclosure are not limited to the above-mentioned effects, and other effects of the embodiments of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0033] Figure 1 is a perspective view illustrating a head mounted electronic device according to an embodiment of the present disclosure.

[0034] Figure 2 It shows Figure 1 An exploded perspective view of an example of a head-mounted electronic device.

[0035] Figure 3 is a perspective view illustrating a head mounted electronic device according to an embodiment of the present disclosure.

[0036] Figure 4 is an exploded perspective view illustrating a display device according to an embodiment of the present disclosure.

[0037] Figure 5 is a cross-sectional view illustrating an example of a portion of a display panel according to an embodiment of the present disclosure.

[0038] Figure 6 is a plan view of a mask according to an embodiment of the present disclosure.

[0039] Figure 7 yes Figure 6 An enlarged plan view of area A.

[0040] Figure 8 It is along Figure 7 A cross-sectional view taken along line X1-X1'.

[0041] Figure 9 yes Figure 8 An enlarged cross-sectional view of region T.

[0042] Figure 10 It is along Figure 7 A cross-sectional view of another example taken along line X1-X1'.

[0043] Figure 11 yes Figure 10 An enlarged cross-sectional view of region Q. DETAILED DESCRIPTION

[0044] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

[0045] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0046] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section. Thus, the "first element," "first component," "first area," "first layer," or "first section" discussed below may be referred to as the "second element," "second component," "second area," "second layer," or "second section" without departing from the teachings herein.

[0047] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit. As used herein, unless the context clearly indicates otherwise, the singular form "one", "one (kind / person)" and "described (the)" are intended to include the plural form comprising "at least one (kind / person)". Therefore, in the claims, after the reference to "one (one)" element, the reference to "described (the)" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the terms “comprises and / or comprising” or “includes and / or including” specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in a drawing is turned over, an element described as being "under" the other elements will subsequently be oriented "over" the other elements. Thus, depending on the specific orientation of the drawing, the term "lower" can cover both "lower" and "over" orientations. Similarly, if the device in a drawing is turned over, an element described as being "under" or "beneath" the other elements will subsequently be oriented "over" the other elements. Thus, the terms "under" or "under" can cover both "over" and "under" orientations.

[0049] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0051] The embodiments are described herein with reference to cross-sectional views which are schematic diagrams of idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a perspective view showing the head-mounted electronic device 1 according to the embodiment. Figure 2 yes Figure 1 An exploded perspective view of an example of the head-mounted electronic device 1.

[0054] Referring to Figure 1 and Figure 2 , the head-mounted electronic device 1 according to an embodiment includes a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a head strap 140, a first display device 10_1, a second display device 10_2, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170, and a connector.

[0055] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described with reference to Figure 4 and Figure 5 . Thus, detailed features of the first display device 10_1 and the second display device 10_2 will be described later with reference to Figure 4 and Figure 5 .

[0056] In an embodiment, as shown in Figure 2 , the first optical member 151 can be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 can be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 can include at least one convex lens.

[0057] The intermediate frame 160 can be disposed between the first display device 10_1 and the control circuit board 170, and can be disposed between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 can support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0058] The control circuit board 170 can be disposed between the intermediate frame 160 and the display device housing 110. The control circuit board 170 can be connected to the first display device 10_1 and the second display device 10_2 through the connector. The control circuit board 170 can convert an image source input from the outside into digital video data, and can transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0059] In an embodiment, the control circuit board 170 may transmit digital video data associated with a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data associated with a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data to both the first display device 10_1 and the second display device 10_2.

[0060] The display device housing 110 houses the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is provided to cover the open surface of the housing 110. The housing cover 120 may include a first eyepiece 131 where the user's left eye is placed and a second eyepiece 132 where the user's right eye is placed. In an embodiment, the first eyepiece 131 and the second eyepiece 132 may be as shown in FIG. Figure 1 and Figure 2 , but the embodiments of the present disclosure are not limited thereto. In another embodiment, the first eyepiece 131 and the second eyepiece 132 may be combined into a single element.

[0061] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Thus, the user may see a virtual image of the image in the first display device 10_1 magnified by the first optical member 151 through the first eyepiece 131, and see a virtual image of the image in the second display device 10_2 magnified by the second optical member 152 through the second eyepiece 132.

[0062] In an embodiment, the head strap 140 fixes the housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are kept in a straight line with the user's left eye and the right eye, respectively (corresponding to or overlapping the user's left eye and the right eye). In an embodiment, by realizing a light and small display device housing 110, the head-mounted electronic device 1 can include, for example Figure 3 Instead of the head strap 140, the eyeglass frame is shown in FIG.

[0063] In an embodiment, the head-mounted electronic device 1 may further include a battery for supplying power, an external memory slot for inserting an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0064] Figure 3 1 is a perspective view showing a head mounted electronic device 1_1 according to the embodiment.

[0065] Reference Figure 3 The head-mounted electronic device 1_1 according to an embodiment may be a glasses-type display device having a light and small display device housing 120_1. The head-mounted electronic device 1_1 according to an embodiment may include a display device 10_3, a left-eye lens 311, a right-eye lens 312, a support frame 350, temples 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 120_1.

[0066] Figure 3 The display device 10_3 shown in FIG. Figure 4 and Figure 5 The display devices 10 described are substantially the same. Therefore, any repeated detailed description of the display device 10_3 will be omitted or simplified.

[0067] In an embodiment, the display device housing 120_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. The image displayed on the display device 10_3 may be magnified by the optical member 320, and the optical path of the image may be converted by the optical path conversion member 330 to be provided to the user's right eye through the right-eye lens 312. As a result, the user may view an augmented reality image with the right eye that combines a virtual image displayed on the display device 10_3 and a real-world image viewed through the right-eye lens 312.

[0068] In an embodiment, the display device housing 120_1 may be as follows Figure 3 3 is shown as being disposed at the right end of the support frame 350, but embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the display device housing 120_1 may be disposed at the left end of the support frame 350. In such an embodiment, the image displayed on the display device 10_3 may be provided to the user's left eye. Alternatively, the display device housing 120_1 may be disposed at the left and right ends of the support frame 350, respectively. In such an embodiment, the user can view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0069] Figure 4 is an exploded perspective view showing the display device 10 according to an embodiment of the present disclosure.

[0070] Reference Figure 4, the display device 10 according to the embodiment displays a moving image or a still image. The display device 10 according to the embodiment can be adopted by portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit of a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0071] According to an embodiment, the display device 10 includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driver circuit 440 , and a power supply circuit 450 .

[0072] The display panel 410 may have a shape similar to a rectangular shape when viewed in a plan view or in the thickness direction of the display panel 410. In an embodiment, for example, the display panel 410 may have a shape similar to a rectangle in a plan view having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). Here, the third direction (Z-axis direction) may be a direction perpendicular to the first and second directions, or may be the thickness direction of the display panel 410. In the display panel 410, each of the corners where the short side in the first direction (X-axis direction) intersects the long side in the second direction (Y-axis direction) may be rounded with a predetermined curvature or may be a right angle. The shape of the display panel 410 in a plan view is not limited to a rectangular shape, but may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. In a plan view, the shape of the display device 10 may follow the shape of the display panel 410, but the embodiments of the present disclosure are not limited thereto.

[0073] The display panel 410 includes a display area where an image is displayed and a non-display area where no image is displayed.

[0074] The display area includes a plurality of pixels, and each of the plurality of pixels includes a plurality of sub-pixels SP1, SP2, and SP3 (see Figure 5 ). The sub-pixels SP1, SP2 and SP3 include a plurality of pixel transistors. The pixel transistors are formed by a semiconductor process and may be disposed on a semiconductor substrate SSUB (see Figure 5 In an embodiment, for example, the pixel transistor may be implemented as a complementary metal oxide semiconductor (CMOS) transistor.

[0075] The heat dissipation layer 420 may overlap the display panel 410 in a third direction (Z-axis direction), which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be provided on one surface of the display panel 410, for example, on the rear surface. The heat dissipation layer 420 is used to release heat generated in the display panel 410. The heat dissipation layer 420 may include graphite, or may be a metal layer having high thermal conductivity including silver (Ag), copper (Cu), and aluminum (Al).

[0076] The circuit board 430 may be electrically connected to the plurality of pads in the pad region of the display panel 410 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board made of a flexible material or a flexible film. In an embodiment, the circuit board 430 may be a flexible printed circuit board such as a Figure 4 , or the circuit board 430 may be bent. In an embodiment where the circuit board 430 is bent, one end of the circuit board 430 may be disposed on the rear surface of the display panel 410. The one end of the circuit board 430 may be opposite to an opposite end of the circuit board 430 that is connected to a pad in a pad area of ​​the display panel 410 using a conductive adhesive member.

[0077] The driver circuit 440 may receive digital video data and a timing signal from the outside, and may generate a scan timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 in response to the timing signal.

[0078] The power supply circuit 450 may generate a plurality of panel driving voltages in response to a supply voltage from the outside.

[0079] Each of the driver circuit 440 and the power supply circuit 450 may be implemented as an integrated circuit (IC) and attached to a surface of the circuit board 430 .

[0080] Figure 5 is a cross-sectional view showing an example of a portion of the display panel 410 according to an embodiment of the present disclosure. For example, Figure 5 A cross-sectional structure of a portion of a display area including a plurality of sub-pixels SP1 , SP2 , and SP3 is shown.

[0081] Reference Figure 5 , an embodiment of the display panel 410 includes a semiconductor backplane SBP, an emission material backplane EBP, an emission material layer EML, an encapsulation layer TFE and a cover layer CVL.

[0082] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the pixel transistors PTR, respectively.

[0083] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be located in the upper surface of the semiconductor substrate SSUB. The well regions WA may be doped with second-type impurities. The second-type impurities may be different from the first-type impurities. In an embodiment, for example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0084] In another embodiment, the semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In such an embodiment, the thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0085] Each of the plurality of well areas WA includes a source region SA associated with a source electrode of the pixel transistor PTR, a drain region DA associated with a drain electrode of the pixel transistor PTR, and a channel region CH between the source region SA and the drain region DA.

[0086] Each of the source region SA and the drain region DA may be doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap with the well region WA in the third direction (Z-axis direction). The channel region CH may overlap with the gate electrode GE in the third direction (Z-axis direction). The source region SA may be located on one side of the gate electrode GE, and the drain region DA may be located on the opposite side of the gate electrode GE.

[0087] The first semiconductor insulating film SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may include a silicon carbonitride (SiCN)-based or silicon oxide (SiO x )-based inorganic film or silicon carbonitride (SiCN)-based or silicon oxide (SiO x )-based inorganic film formation, but not limited thereto.

[0088] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may include silicon oxide (SiO x )-based inorganic film or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0089] A plurality of contact terminals CTE may be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source area SA, and the drain area DA of each of the pixel transistors PTR through a hole defined or formed through the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The contact terminal CTE may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Alternatively, the contact terminal CTE may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0090] The third semiconductor insulating film SINS3 may be provided on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may not be covered by the third semiconductor insulating film SINS3 but may be exposed. In an embodiment, the third semiconductor insulating film SINS3 may include silicon oxide (SiO x )-based inorganic film or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0091] The emission material back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the emission material back plate EBP includes a plurality of interlayer dielectric films INS1 to INS10.

[0092] The first to eighth metal layers ML1 to ML8 are used to implement circuits of the sub-pixels SP by connecting a plurality of contact terminals CTE exposed from the semiconductor backplane SBP.

[0093] A first interlayer dielectric film INS1 may be provided on the semiconductor backplane SBP. Each of a plurality of first vias VA1 may penetrate or extend through the first interlayer dielectric film INS1 and may be connected to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of a plurality of first metal layers ML1 may be provided on the first interlayer insulating film INS1 and may be connected to the first vias VA1.

[0094] A second interlayer dielectric film INS2 may be disposed on the first interlayer dielectric film INS1 and the first metal layer ML1. Each of the plurality of second vias VA2 may penetrate or extend through the second interlayer dielectric film INS2 to connect to the exposed first metal layer ML1. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second vias VA2.

[0095] A third interlayer dielectric film INS3 may be disposed on the second interlayer dielectric film INS2 and the second metal layer ML2. Each of the plurality of third vias VA3 may penetrate or extend through the third interlayer dielectric film INS3 to connect to the exposed second metal layer ML2. Each of the plurality of third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third vias VA3.

[0096] A fourth interlayer dielectric film INS4 may be disposed on the third interlayer dielectric film INS3 and the third metal layer ML3. Each of the plurality of fourth vias VA2 may penetrate or extend through the fourth interlayer dielectric film INS4 to connect to the exposed third metal layer ML3. Each of the plurality of fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth via VA4.

[0097] A fifth interlayer dielectric film INS5 may be disposed on the fourth interlayer dielectric film INS4 and the fourth metal layer ML4. Each of a plurality of fifth vias VA5 may penetrate or extend through the fifth interlayer dielectric film INS5 to connect to the exposed fourth metal layer ML4. Each of a plurality of fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the fifth vias VA5.

[0098] A sixth interlayer dielectric film INS6 may be disposed on the fifth interlayer dielectric film INS5 and the fifth metal layer ML5. Each of a plurality of sixth vias VA6 may penetrate or extend through the sixth interlayer dielectric film INS6 to connect to the exposed fifth metal layer ML5. Each of a plurality of sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may be connected to the sixth via VA6.

[0099] A seventh interlayer dielectric film INS7 may be disposed on the sixth interlayer dielectric film INS6 and the sixth metal layer ML6. Each of a plurality of seventh vias VA7 may penetrate or extend through the seventh interlayer dielectric film INS7 to connect to the exposed sixth metal layer ML6. Each of a plurality of seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the seventh via VA7.

[0100] An eighth interlayer dielectric film INS8 may be disposed on the seventh interlayer dielectric film INS7 and the seventh metal layer ML7. Each of a plurality of eighth vias VA8 may penetrate or extend through the eighth interlayer dielectric film INS8 to connect to the exposed seventh metal layer ML7. Each of a plurality of eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth via VA8.

[0101] The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may include substantially the same material as each other or be made of substantially the same material as each other. In an embodiment, the first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these, or be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. The first to eighth vias VA1 to VA8 may include substantially the same material as each other or be made of substantially the same material as each other. In an embodiment, the first to eighth interlayer dielectric films INS1 to INS8 may include silicon oxide (SiO x )-based inorganic film or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of this specification are not limited thereto.

[0102] The thickness of the first metal layer ML1 (i.e., the height in the third direction (Z-axis direction)), the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially all equal.

[0103] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 may be substantially equal to the thickness of the eighth metal layer ML8.

[0104] The ninth interlayer dielectric film INS9 may be disposed on the eighth interlayer dielectric film INS8 and the eighth metal layer ML8. In an embodiment, the ninth interlayer dielectric film INS9 may include silicon oxide (SiO x )-based inorganic film or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0105] Each of the plurality of ninth via holes VA9 may penetrate or extend through the ninth interlayer dielectric film INS9 to connect to the exposed eighth metal layer ML8. In an embodiment, the ninth via hole VA9 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Or made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0106] The first reflective electrode RL1 may be disposed on the ninth interlayer dielectric film INS9 and may be connected to the ninth via hole VA9. In embodiments, the first reflective electrode RL1 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Alternatively, the first reflective electrode RL1 may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0107] The second reflective electrode RL2 may be disposed on the first reflective electrode RL1. In an embodiment, the second reflective electrode RL2 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Alternatively, the second reflective electrode RL2 may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. In an embodiment, for example, the second reflective electrode RL2 may include or be formed of titanium nitride (TiN).

[0108] In the first sub-pixel SP1, a step layer STPL may be provided on the second reflective electrode RL2. In each of the second sub-pixel SP2 and the third sub-pixel SP3, no step layer STPL may be provided. The step layer STPL may include a silicon carbonitride (SiCN)-based or silicon oxide (SiO x )-based inorganic film, or silicon carbonitride (SiCN)-based or silicon oxide (SiO x )-based inorganic film formation, but not limited thereto.

[0109] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the stepped layer STPL. In the second and third subpixels SP2 and SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Alternatively, the third reflective electrode RL3 may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. In another embodiment, at least one of the first, second, and third reflective electrodes RL1, RL2, and RL3 may be omitted.

[0110] The fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may include a metal with high reflectivity for light reflection. The fourth reflective electrode RL4 may include aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy (an alloy of silver (Ag), palladium (Pd), and copper (Cu), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), or may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy (an alloy of silver (Ag), palladium (Pd), and copper (Cu), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but is not limited thereto.

[0111] The tenth interlayer dielectric film INS10 may be disposed on the ninth interlayer dielectric film INS9 and the fourth reflective electrode RL4. In an embodiment, the tenth interlayer dielectric film INS10 may include silicon oxide (SiO x )-based inorganic film or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0112] Each of the plurality of tenth via holes VA10 may penetrate or extend through the tenth interlayer dielectric film INS10 to connect to the fourth reflective electrode RL4. The tenth via hole VA10 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Due to the stepped layer STPL, the thickness of the tenth via hole VA10 in the first subpixel SP1 may be smaller than the thickness of the tenth via hole VA10 in each of the second subpixel SP2 and the third subpixel SP3.

[0113] The emission material layer EML may be disposed on the emission material back plate EBP. The emission material layer EML may include light emitting elements LE and a pixel defining layer PDL, each of the light emitting elements LE including a first electrode AND, an emission layer IL, and a second electrode CAT.

[0114] The first electrode AND may be disposed on the tenth interlayer dielectric film INS10 and may be connected to the tenth via VA10. The first electrode AND may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. In embodiments, the first electrode AND may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Alternatively, the first electrode AND may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. For example, the first electrode AND may be titanium nitride (TiN).

[0115] The pixel defining layer PDL may be partially disposed on the first electrode AND. The pixel defining layer PDL may be disposed on an edge of the first electrode AND. The pixel defining layer PDL is used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0116] The first emission area EA1 may be defined as a region in the first sub-pixel SP1 where the first electrode AND, the first emission layer IL1, and the second electrode CAT are sequentially stacked on each other to emit light. The second emission area EA2 may be defined as a region in the second sub-pixel SP2 where the first electrode AND, the second emission layer IL2, and the second electrode CAT are sequentially stacked on each other to emit light. The third emission area EA3 may be defined as a region in the third sub-pixel SP3 where the first electrode AND, the third emission layer IL3, and the second electrode CAT are sequentially stacked on each other to emit light.

[0117] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on an edge of the first electrode AND, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. In an embodiment, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may include silicon oxide (SiO x )-based inorganic film or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0118] The emission layer IL may include a first emission layer IL1, a second emission layer IL2, and a third emission layer IL3. The first emission layer IL1, the second emission layer IL2, and the third emission layer IL3 may emit light of different colors or wavelengths. In an embodiment, for example, the first emission layer IL1 may emit red light, the second emission layer IL2 may emit green light, and the third emission layer IL3 may emit blue light, but the present disclosure is not limited thereto.

[0119] In the first direction (X-axis direction (see Figure 1 The plurality of emission layers IL1, IL2, and IL3 adjacently arranged on the display panel 410 may be disconnected by the pixel defining layer PDL. In the display panel 410 according to the embodiment, by disconnecting the first emission layer IL1, the second emission layer IL2, and the third emission layer IL3 adjacently arranged, leakage current between adjacent sub-pixels SP1, SP2, and SP3 can be effectively prevented and color crosstalk can be effectively prevented.

[0120] The second electrode CAT may be disposed on the emission layer IL. The second electrode CAT may be a common electrode. The second electrode CAT may include a transparent conductive material (TCP) such as ITO and indium zinc oxide (IZO) that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag), or be formed of a transparent conductive material (TCP) such as ITO and indium zinc oxide (IZO) that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). In an embodiment in which the second electrode CAT is formed of a semi-transmissive conductive material, light extraction efficiency can be increased by using a microcavity in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0121] The encapsulation layer TFE may be disposed on the emission material layer EML. The encapsulation layer TFE may include at least one inorganic film to prevent oxygen or moisture from penetrating into the emission material layer EML. In an embodiment, for example, the encapsulation layer TFE may include a first encapsulation layer TFE1 and a second encapsulation layer TFE2.

[0122] The first encapsulation layer TFE1 may be disposed on the second electrode CAT, and the second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1. In an embodiment, the first encapsulation layer TFE1 and the second encapsulation layer TFE2 may include silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x) layer or multiple layers in which one or more inorganic layers are alternately stacked on each other, or a layer in which silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layers are made of a multilayer in which one or more inorganic layers are alternately stacked with each other.

[0123] The adhesive layer APL may be a layer provided to increase the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. The adhesive layer APL may include or be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0124] The cover layer CVL may be disposed on the adhesive layer APL. The cover layer CVL may be a glass substrate or include a polymer resin. In embodiments where the cover layer CVL is a glass substrate, the cover layer CVL may serve as a package substrate. In embodiments where the cover layer CVL includes a polymer resin, the cover layer CVL may be applied or formed directly on the adhesive layer APL.

[0125] The polarizer POL may be provided on the surface of the cover layer CVL. The polarizer POL may be a structure for preventing degradation of visibility due to reflection of external light. The polarizer POL may include a linear polarizer and a phase delay film. In an embodiment, for example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the embodiments of the present disclosure are not limited thereto.

[0126] Figure 6 is a plan view of a mask (or deposition mask) MK according to an embodiment of the present disclosure. Figure 7 yes Figure 6 An enlarged plan view of area A. Figure 6 The mask MK shown in FIG can be deposited above with reference to Figure 5 At least some of the emission layers IL of the display panel 410 are used in the described processes.

[0127] Reference Figure 6 and Figure 7 The mask MK according to the embodiment may be a mask for making an ultra-high-resolution display. In the embodiment, for example, the mask MK may be a mask for making a display included in an extended reality device (XR device) such as a VR device, an AR device, and a mixed reality (MR) device.

[0128] The mask MK according to the embodiment can be used to perform sub-pixel ( Figure 5 For a display included in an extended reality device, the screen is positioned directly in front of the user's eyes, and thus such a display can have a small screen rather than a large screen. In addition, because the display included in the extended reality device is positioned close to the user's eyes, an ultra-high resolution can be expected. In an embodiment, for example, the desired resolution of the display included in the extended reality device may be approximately 1,000 pixels per inch (PPI) or greater, for example, an ultra-high resolution of 2,000PPI or greater. Therefore, the deposition mask MK according to the embodiment may be a mask for making such an ultra-high resolution display. The mask MK according to the embodiment of the present disclosure may include the mask to be described later. Figure 8 The embodiment of the mask MK1 shown in Figure 10 Another embodiment of the mask MK3 is shown in FIG.

[0129] The mask MK according to an embodiment may include a mask base MSUB.

[0130] The mask substrate MSUB according to an embodiment may include a silicon wafer. Because silicon wafers allow for finer and more precise processing compared to large-area substrates by utilizing technologies developed in semiconductor processing, silicon wafers can be used as substrates for ultra-high-resolution displays. The mask MK according to an embodiment can be used in the same manner as a silicon wafer to form pixels on the silicon wafer for such ultra-high-resolution displays.

[0131] According to an embodiment, the shape of the mask substrate MSUB can conform to the silicon wafer of the ultra-high-resolution display. In an embodiment, for example, the mask substrate MSUB can have the same size or shape as the silicon wafer of the ultra-high-resolution display. However, it will be understood that the embodiments of the present disclosure are not limited thereto. The mask substrate MSUB can be a large-area substrate. In an embodiment, for example, the mask substrate MSUB can include materials such as glass, quartz, and polymer resin.

[0132] The mask substrate MSUB according to embodiments may include a plurality of cell areas CA, a cell peripheral area CRA, and an edge area EDA.

[0133] According to an embodiment, the cell peripheral area CRA may surround a plurality of cell areas CA. In a plan view or when viewed in the thickness direction of the mask MK, the cell peripheral area CRA may correspond to the mask frame MF. The mask frame MF may be a region that supports the mask MK. The mask frame MF may define a mask opening COP in a plan view and may surround the mask opening COP. The mask opening COP may be positioned to correspond to the cell area CA or overlap with the cell area CA.

[0134] According to an embodiment of the present disclosure, a plurality of unit areas CA may be formed, and the unit areas CA may be spaced apart from each other. The unit area CA may overlap with the mask diaphragm MM. The mask diaphragm MM may include a pixel opening SOP and a mask shielding member MS. In a plan view, the mask shielding member MS may completely surround the pixel opening SOP and may be integrally formed into a single, integral, indivisible body.

[0135] In a plan view, the mask frame MF may completely surround the mask shield MS and may be integrally formed as a single, integral, indivisible body. In other words, the mask shield MS may be in the form of an integrated pattern exposing the pixel openings SOP in a plan view, and the mask frame MF may be in the form of an integrated pattern exposing the mask openings COP in a plan view.

[0136] The edge area EDA according to an embodiment may refer to an edge of the mask substrate MSUB and an area near the edge. In other words, the edge area EDA may mean a boundary area of ​​the mask substrate MSUB.

[0137] Figure 8 It is along Figure 7 A cross-sectional view taken along line X1-X1'.

[0138] exist Figure 8 In the cross-sectional view of FIG, the mask frame MF according to an embodiment of the present disclosure may be positioned to correspond to or overlap the cell peripheral area CRA. The mask frame MF may include a mask substrate MSUB, a first upper inorganic layer U1, a second upper inorganic layer U2, a first lower inorganic layer L1, and a second lower inorganic layer L2.

[0139] In some embodiments, the mask substrate MSUB may include a top surface s1, a bottom surface s2, and a side surface s3. The top surface s1 may face the first upper inorganic layer U1, the bottom surface s2 may be opposite the top surface s1, and the side surface s3 may connect the top surface s1 and the bottom surface s2. The side surface s3 of the mask substrate MSUB may be an inclined surface. Such a structure can be formed by removing a portion of the mask substrate MSUB through an etching process during the process of manufacturing the mask MK.

[0140] In some embodiments, the mask substrate MSUB may further include an edge surface e1 in the edge area EDA. The edge surface e1 may refer to a surface including an edge of the mask substrate MSUB.

[0141] According to an embodiment of the present disclosure, the first upper inorganic layer U1 may be located on the mask substrate MSUB. The first upper inorganic layer U1 may contact the top surface s1 of the mask substrate MSUB and may completely cover the top surface s1. The first upper inorganic layer U1 may define a mask opening COP. In a cross-section, the mask opening COP may be aligned with (correspond to or overlap with) the cell area CA.

[0142] The first upper inorganic layer U1 may include an inorganic insulating material. In an embodiment, for example, the first upper inorganic layer U1 may include, but is not limited to, silicon oxide.

[0143] According to an embodiment of the present disclosure, the second upper inorganic layer U2 may be located on the first upper inorganic layer U1. The second upper inorganic layer U2 may be in contact with the first upper inorganic layer U1 and may completely cover the first upper inorganic layer U1.

[0144] According to an embodiment of the present disclosure, the second upper inorganic layer U2 may include a protrusion P protruding from the side surface s3 of the mask substrate MSUB toward the unit area CA. The protrusion P of the second upper inorganic layer U2 may protrude further than the side surface s3 of the mask substrate MSUB in the first direction (X-axis direction).

[0145] The second upper inorganic layer U2 may include an inorganic insulating material. In an embodiment, for example, the second upper inorganic layer U2 may include, but is not limited to, silicon nitride.

[0146] According to embodiments of the present disclosure, the first upper inorganic layer U1 and the second upper inorganic layer U2 may have different stress properties. In embodiments, for example, if the first upper inorganic layer U1 includes an inorganic insulating material having compressive stress, the second upper inorganic layer U2 may include an inorganic insulating material having tensile stress. According to embodiments of the present disclosure, since the first upper inorganic layer U1 and the second upper inorganic layer U2 may have different stress properties, the stress of the mask MK can be adjusted.

[0147] The second upper inorganic layer U2 may include the same material as the mask shield MS to be described later, and a more detailed description thereof will be given below.

[0148] According to an embodiment of the present disclosure, the first lower inorganic layer L1 may be positioned on the bottom surface s2 of the mask substrate MSUB. The first lower inorganic layer L1 may be in contact with the bottom surface s2 and may completely cover the bottom surface s2.

[0149] During the process of manufacturing the mask MK, the first mask inorganic layer IOL1 may be formed to completely cover the top surface s1, the bottom surface s2, and the edge surface e1 of the mask base MSUB. A portion of the first mask inorganic layer IOL1 may then be removed through a subsequent etching process, thereby forming the first upper inorganic layer U1 and the first lower inorganic layer L1 as shown in the drawings.

[0150] During this process, portions of the first mask inorganic layer IOL1 that are not removed from the edge area EDA and the area surrounding the edge area EDA may remain to cover the top surface s1, bottom surface s2, and edge surface e1 of the mask base MSUB. However, it will be understood that the embodiments of the present disclosure are not limited thereto. In another embodiment, depending on the fabrication process, the first mask inorganic layer IOL1 located in the edge area EDA may be removed. In other words, the first lower inorganic layer L1 and the first upper inorganic layer U1 may be part of the first mask inorganic layer IOL1 during the fabrication process and then formed as shown in the accompanying drawings.

[0151] Therefore, the first lower inorganic layer L1 located in the cell peripheral area CRA may include the same material as the first upper inorganic layer U1. Depending on the embodiment, the first mask inorganic layer IOL1 may be described as the first lower inorganic layer L1 or the first upper inorganic layer U1.

[0152] According to an embodiment of the present disclosure, the alignment mark AM may be located on the first mask inorganic layer IOL1 in the edge area EDA and an area near the edge area EDA. The alignment mark AM may be formed to Figure 5 The display panel 410 shown in FIG is aligned with the mask MK. The shape of the alignment mark AM is not limited to the shape shown in the drawings, but the alignment mark AM may have various shapes and arrangements.

[0153] According to an embodiment of the present disclosure, the second lower inorganic layer L2 may be located on the first lower inorganic layer L1. The second lower inorganic layer L2 may be in contact with the first lower inorganic layer L1.

[0154] During the process of making the mask MK, the second mask inorganic layer 10L2 may be formed to completely cover the top surface s1, the bottom surface s2, and the edge surface e1 of the mask base MSUB. A portion of the second mask inorganic layer 10L2 may then be removed through a subsequent etching process, thereby forming a second upper inorganic layer U2 and a second lower inorganic layer L2 as shown in the drawings.

[0155] During this process, portions of the second mask inorganic layer IOL2 that are not removed from the edge area EDA and the area surrounding the edge area EDA may remain to cover the top surface s1, bottom surface s2, and edge surface e1 of the mask base MSUB. However, it will be understood that the embodiments of the present disclosure are not limited thereto. In another embodiment, depending on the manufacturing process, the second mask inorganic layer IOL2 located in the edge area EDA may be removed. In other words, the second lower inorganic layer L2 and the second upper inorganic layer U2 may be part of the second mask inorganic layer IOL2 during the manufacturing process and then formed as shown in the drawings.

[0156] Therefore, the second lower inorganic layer L2 located in the cell peripheral area CRA may include the same material as the second upper inorganic layer U2. Depending on the embodiment, the second mask inorganic layer IOL2 may be described as the second lower inorganic layer L2 or the second upper inorganic layer U2.

[0157] According to an embodiment, the mask membrane MM may be positioned in line with (corresponding to or overlapping) the cell area CA. The mask membrane MM may include a plurality of mask shields MS and a plurality of pixel openings SOP.

[0158] Pixel opening SOP can be located between adjacent mask shielding members MS in the mask shielding member MS. Pixel opening SOP can be referred to as a hole or mask hole. A plurality of pixel opening SOPs can be defined or formed to pass through the mask frame MF along the thickness direction (e.g., the third direction (Z-axis direction)) of the mask MK. During the manufacturing process, a plurality of pixel opening SOPs can be formed by etching portions of the mask base MSUB, the first mask inorganic layer 101, and the second mask inorganic layer 102 from the bottom surface s2 of the mask base MSUB.

[0159] The mask shield MS may surround the pixel opening SOP. The mask shield MS may have, but is not limited to, a reverse tapered shape.

[0160] When the deposition material evaporates from the deposition source inside the deposition apparatus, the mask shield MS may be used to mask the substrate (eg, the display panel 410 (see FIG. 4 )) undergoing deposition. Figure 4 ) or a blocking unit of a backplane substrate). Therefore, the deposition material generated from the deposition source can be deposited on the surface of the substrate subjected to deposition (eg, the display panel 410 or the backplane substrate) through the pixel opening SOP.

[0161] According to an embodiment of the present disclosure, the mask shield MS may include the same material as the second upper inorganic layer U2. In the process of manufacturing the mask MK, the mask shield MS and the second upper inorganic layer U2 may be integrally formed into a single, integral, indivisible body, and then formed into the shape shown in the drawings through a subsequent etching process.

[0162] The mask conductive layer CL of the mask MK1 may completely surround the mask frame MF and the mask shield MS.

[0163] The mask conductive layer CL may be provided to effectively prevent the occurrence of mask defects that may be caused by static electricity and physical pressure generated during contact and separation processes between the mask MK1 and the display panel 410 .

[0164] The mask conductive layer CL may include a conductive metal material. In an embodiment, for example, the mask conductive layer CL may include, but is not limited to, at least one selected from copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). In addition to the metals listed above, the mask conductive layer CL may also include any metal having conductive properties.

[0165] In some embodiments, the mask conductive layer CL may include a first portion CL1, a second portion CL2, and a third portion CL3. The first portion CL1 may be located in the cell peripheral area CRA and may surround (or completely cover) the mask frame MF. The second portion CL2 may be located in the cell area CA and may surround (or completely cover) the mask shield MS. The third portion CL3 may be located in the cell peripheral area CRA and the edge area EDA and may surround (or completely cover) the first mask inorganic layer IOL1, the second mask inorganic layer IOL2, and the mask base MSUB. The first portion CL1, the second portion CL2, and the third portion CL3 may be spaced apart from each other, and the mask opening COP may be between the first portion CL1, the second portion CL2, and the third portion CL3. In other words, the first portion CL1, the second portion CL2, and the third portion CL3 may be spaced apart from each other, and the pixel opening SOP may be between the first portion CL1, the second portion CL2, and the third portion CL3.

[0166] In an embodiment, the mask conductive layer CL is formed using deposition techniques such as ALD and CVD, so that the mask conductive layer CL can be formed with a uniform thickness along the contour of the underlying structure. In such an embodiment, the first portion CL1 can completely surround the mask frame MF with a uniform thickness along the contour of the mask frame MF. In addition, the second portion CL2 can completely surround the mask shield MS with a uniform thickness along the contour of the mask shield MS. In addition, the third portion CL3 can completely surround the first mask inorganic layer IOL1, the second mask inorganic layer IOL2, and the mask base MSUB along the contours of the first mask inorganic layer IOL1, the second mask inorganic layer IOL2, and the mask base MSUB. A more detailed description of this will be given below.

[0167] Figure 9 yes Figure 8 An enlarged cross-sectional view of region T.

[0168] Reference Figure 9 , the first upper inorganic layer U1 according to an embodiment of the present disclosure may include a side surface u1c. The side surface u1c of the first upper inorganic layer U1 may be located on the same plane as the side surface s3 of the mask substrate MSUB.

[0169] According to an embodiment of the present disclosure, the protrusion P of the second upper inorganic layer U2 may protrude toward the cell area CA more than the side surface u1c of the first upper inorganic layer U1. Therefore, an undercut (or undercut structure) may be formed or defined by the protrusion P of the second upper inorganic layer U2 and the side surface u1c of the first upper inorganic layer U1.

[0170] According to an embodiment of the present disclosure, the height HU1 of the first upper inorganic layer U1 can be equal to the height HL1 of the first lower inorganic layer L1. Here, the height of a layer can refer to the thickness of the layer. In addition, the height HU2 of the second upper inorganic layer U2 can be equal to the height HL2 of the second lower inorganic layer L2. As described above, in the process of manufacturing the mask MK1, the first upper inorganic layer U1 and the first lower inorganic layer L1 can be integrally formed into a single, integral, indivisible body, and can then be formed into the shape shown in the drawings through subsequent processes. Therefore, the first upper inorganic layer U1 and the first lower inorganic layer L1 can include or be made of the same material as each other and have the same height as each other. In addition, in the process of manufacturing the mask MK1, the second upper inorganic layer U2 and the second lower inorganic layer L2 can be integrally formed into a single, integral, indivisible body, and can then be formed into the shape shown in the drawings through subsequent processes. Therefore, the second upper inorganic layer U2 and the second lower inorganic layer L2 can include or be made of the same material as each other and have the same height as each other.

[0171] According to an embodiment of the present disclosure, the height HU2 of the second upper inorganic layer U2 can be equal to the height HMS of the mask shield MS. As described above, during the process of manufacturing the mask MK1, the second upper inorganic layer U2 and the mask shield MS can be integrally formed into a single, indivisible body, and can then be formed into the shape shown in the accompanying drawings through subsequent processes. Therefore, the second upper inorganic layer U2 and the mask shield MS can include or be made of the same material and have the same height.

[0172] In some embodiments, the height HMS of the mask cover MS may be, but is not limited to, about 0.5 micrometers or more and about 2.5 micrometers or less. Any repeated detailed description of features identical or similar to those described above will be omitted.

[0173] The first portion CL1 of the mask conductive layer CL included in the mask MK1 may completely cover the protrusion P of the second upper inorganic layer U2, and may also completely cover the undercut formed by the protrusion P of the second upper inorganic layer U2 and the side surface u1c of the first upper inorganic layer U1. The first portion CL1 of the mask conductive layer CL may be in contact with the first upper inorganic layer U1, the second upper inorganic layer U2, the mask substrate MSUB, the first lower inorganic layer L1, and the second lower inorganic layer L2.

[0174] The second portion CL2 of the mask conductive layer CL included in the mask MK1 may entirely cover the mask shield MS and may be in complete contact with the mask shield MS (ie, in contact with the entire outer surface of the mask shield MS).

[0175] In some embodiments, since the second portion CL2 covers the outline of the mask cover MS with a uniform thickness, the second portion CL2 may have, but is not limited to, a reverse tapered shape.

[0176] The first portion CL1 and the second portion CL2 of the mask conductive layer CL may have the same height as each other. In an embodiment, for example, the height HCL of the mask conductive layer CL may be, but is not limited to, about 20 nanometers or more and about 300 nanometers or less.

[0177] In such an embodiment, since the mask MK1 includes the mask conductive layer CL completely covering the mask frame MF and the mask shield MS, mask defects that may be caused by static electricity and physical pressure generated during contact and separation processes between the mask MK1 and the display panel 410 can be effectively prevented from occurring.

[0178] Figure 10 It is along Figure 7 A cross-sectional view of another example taken along line X1-X1'. Figure 11 yes Figure 10An enlarged cross-sectional view of region Q.

[0179] Reference Figure 10 and Figure 11 The mask conductive layer CL of the embodiment of the mask MK3 can be the same as that of the embodiment of the mask MK3. Figure 8 and Figure 9 The mask conductive layer CL of the embodiment of the described mask MK1 has a different structure. The following description will focus on the differences between the mask MK1 and the mask MK3.

[0180] In an embodiment, the mask conductive layer CL included in the mask MK3 may include a first portion CL5, a second portion CL6, and a third portion CL7. The first portion CL5 may be located in the cell peripheral area CRA and may be located on the mask frame MF. The second portion CL6 may be located in the cell area CA and may be located on the mask shield MS. The third portion CL7 may be located in the cell peripheral area CRA and the edge area EDA, and may be located on the second mask inorganic layer IOL2. The first portion CL5, the second portion CL6, and the third portion CL7 may be spaced apart from each other, and the mask opening COP may be between the first portion CL5, the second portion CL6, and the third portion CL7. In other words, the first portion CL5, the second portion CL6, and the third portion CL7 may be spaced apart from each other, and the pixel opening SOP may be between the first portion CL5, the second portion CL6, and the third portion CL7.

[0181] In some embodiments, the second upper inorganic layer U2 of the mask MK3 may have a top surface u2a and a side surface u2c. The top surface u2a may face the mask conductive layer CL, and the side surface u2c may face the mask shield MS. The side surface u2c of the second upper inorganic layer U2 may protrude toward the cell area CA more than the side surface u1c of the first upper inorganic layer U1. In other words, the side surface u2c of the second upper inorganic layer U2 may overlap with the protrusion P of the second upper inorganic layer U2. The side surface u2c of the second mask inorganic layer U2 may be spaced apart from the mask shield MS, and the pixel opening SOP is between the side surface u2c and the mask shield MS.

[0182] The first portion CL5 of the mask conductive layer CL may be located on and in contact with the top surface u2a of the second upper inorganic layer U2. The first portion CL5 may completely cover the top surface u2a of the second upper inorganic layer U2. The first portion CL5 may overlap with the protrusion P of the second upper inorganic layer U2 in the third direction (Z-axis direction).

[0183] In some embodiments, the first portion CL5 of the mask MK3 can not be in contact with the first upper inorganic layer U1, the mask substrate MSUB, the first lower inorganic layer L1, and the second lower inorganic layer L2. In addition, the first portion CL5 can not be in contact with the side surface u2c of the second upper inorganic layer U2, but the disclosure is not limited thereto.

[0184] In some embodiments, the mask shield MS of the mask MK3 can have a top surface m1 and a side surface m3. The top surface m1 of the mask shield MS can face the mask conductive layer CL, and the side surface m3 can face the pixel opening SOP.

[0185] The second portion CL6 of the mask conductive layer CL can be located on and can be in contact with the top surface m1 of the mask shield MS. The second portion CL6 can completely cover the top surface m1 of the mask shield MS.

[0186] In some embodiments, the second portion CL6 of the mask MK3 can not be in contact with the side surface u2c of the mask shield MS, but the disclosure is not limited thereto.

[0187] According to some embodiments, the height HU2 of the second upper inorganic layer U2 can be equal to the height HMS of the mask shield MS. The height HMS of the mask shield MS can be, but is not limited to, about 0.5 micrometers or more and about 2.5 micrometers or less.

[0188] In the cell peripheral area CRA and the edge area EDA, the third portion CL7 of the mask conductive layer CL can be in contact with the second mask inorganic layer IOL2, and can completely cover the upper surface of the second mask inorganic layer IOL2.

[0189] The first portion CL5, the second portion CL6, and the third portion CL7 of the mask conductive layer CL can have the same height as each other. In an embodiment, for example, the height HCL of the mask conductive layer CL can be, but is not limited to, about 20 nanometers or more and about 300 nanometers or less. Any repetitive detailed description of features identical or similar to the above-described features will be omitted.

[0190] In an embodiment, since the mask MK3 includes the mask conductive layer CL on the second upper inorganic layer U2 as well as the mask shield MS, it can be effectively prevented from occurring the mask defect that can be caused by static electricity and physical pressure generated during a contact and separation process between the mask MK3 and the display panel 410.

[0191] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications and variations may be made without departing from the technical ideas or essential features of the present disclosure. Therefore, it should be understood that the above-mentioned embodiments are not restrictive in all aspects, but illustrative.

[0192] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0193] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A deposition mask, wherein: The deposition mask comprises: a mask substrate comprising a plurality of unit regions and a unit peripheral region surrounding the plurality of unit regions; a mask membrane disposed in the plurality of unit regions of the mask substrate and comprising a mask shield defining a pixel opening; a mask frame disposed in the cell peripheral region of the mask substrate and including a first upper inorganic layer on the mask substrate and a second upper inorganic layer on the first upper inorganic layer; and a mask conductive layer, comprising a first portion located on the mask frame and a second portion located on the mask shielding member, The first portion and the second portion are spaced apart from each other, and the pixel opening is between the first portion and the second portion.

2. The deposition mask according to claim 1, wherein The height of the mask conductive layer is equal to or greater than 20 nanometers and equal to or less than 300 nanometers.

3. The deposition mask according to claim 2, wherein: The mask conductive layer includes a conductive metal material.

4. The deposition mask according to claim 1, wherein The first portion completely surrounds the mask frame, and The second portion of the mask conductive layer completely surrounds the mask shielding member.

5. The deposition mask according to claim 4, wherein The second upper inorganic layer includes a protrusion protruding toward the plurality of unit regions from a side surface of the first upper inorganic layer, and The first portion overlaps with the protrusion of the second upper inorganic layer in a thickness direction of the mask substrate.

6. The deposition mask according to claim 5, wherein The side surface of the first upper inorganic layer and the protrusion of the second upper inorganic layer collectively form an undercut.

7. The deposition mask according to claim 6, wherein: The first portion completely covers the undercut.

8. The deposition mask according to claim 4, wherein The first portion contacts the mask substrate, the first upper inorganic layer, and the second upper inorganic layer.

9. The deposition mask according to claim 8, wherein The second portion is in full contact with the mask shield.

10. The deposition mask according to claim 4, wherein The mask frame further includes: a first lower inorganic layer located on a side of the mask substrate opposite to the first upper inorganic layer; and a second lower inorganic layer, located on the first lower inorganic layer, and The mask conductive layer is in contact with the first lower inorganic layer and the second lower inorganic layer.

11. The deposition mask according to claim 10, wherein The first upper inorganic layer and the first lower inorganic layer include the same material as each other, and The second upper inorganic layer and the second lower inorganic layer include the same material.

12. The deposition mask according to claim 1, wherein The mask shield and the second upper inorganic layer include the same material.

13. The deposition mask according to claim 12, wherein: The height of the mask shield is equal to or greater than 0.5 micrometers and equal to or less than 2.5 micrometers.

14. The deposition mask according to claim 1, wherein The mask substrate further includes an edge surface including an edge of the mask substrate, and Wherein, the mask conductive layer further includes a third portion overlapping with the edge surface.

15. The deposition mask according to claim 14, wherein The third portion is spaced apart from the second portion, and the pixel opening is between the third portion and the second portion.

16. The deposition mask according to claim 1, wherein The mask shield completely surrounds the pixel opening in plan view, and The mask frame completely surrounds the mask membrane in the plan view.

17. The deposition mask according to claim 1, wherein The mask substrate comprises silicon, and The mask substrate has a circular shape in a plan view.

18. The deposition mask according to claim 1, wherein The second upper inorganic layer includes a first surface located on an opposite side opposite to a side of the second upper inorganic layer facing the first upper inorganic layer, and The first portion is in complete contact with the first surface of the second upper inorganic layer.

19. The deposition mask according to claim 18, wherein The first portion is in contact with neither the first upper inorganic layer nor the mask substrate.

20. The deposition mask according to claim 19, wherein The mask shield comprises a second surface facing the mask conductive layer, wherein the second portion is in complete contact with the second surface of the mask shield, and The second portion does not contact the side surface of the mask shielding member facing the pixel opening.

21. An electronic device, wherein: The electronic device comprises: A display device including a display panel formed using a deposition mask, Wherein, the deposition mask comprises: a mask substrate comprising a plurality of unit regions and a unit peripheral region surrounding the plurality of unit regions; a mask membrane disposed in the plurality of unit regions of the mask substrate and comprising a mask shield defining a pixel opening; a mask frame disposed in the cell peripheral region of the mask substrate and including a first upper inorganic layer on the mask substrate and a second upper inorganic layer on the first upper inorganic layer; and a mask conductive layer, comprising a first portion located on the mask frame and a second portion located on the mask shielding member, The first portion and the second portion are spaced apart from each other, and the pixel opening is between the first portion and the second portion.

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