Semiconductor aging test circuit and method

By designing a semiconductor burn-in test circuit suitable for SIP packaging, the problem that existing test circuits cannot meet the testing requirements of SIP packaged chips is solved, full-resource testing and reliability screening are achieved, and chip stability is ensured.

CN120779216APending Publication Date: 2025-10-14SHANGHAI SHENCI INTEGRATED CIRCUIT CO LTD
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Patent Information

Application Number
CN202511191983.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-08-25
Publication Date
2025-10-14

AI Technical Summary

Technical Problem

Existing single-chip integrated circuit burn-in test circuits are not fully applicable to finished system-in-package (SIP) chips and cannot meet their stringent testing requirements.

Method used

A semiconductor burn-in test circuit was designed, including a three-temperature test area, a configuration interface circuit, a burn-in system, and an excitation board. It is used for aging tests in the temperature range of -55°C to 125°C. The circuit integrates FPGA, Flash, and functional burn-in modules. The FPGA controls the internal Flash to implement the storage and configuration of the burn-in bitstream, and performs ATPG burn-in and functional burn-in.

Benefits of technology

It realizes full-resource testing of SIP packaged chips, ensuring the stability and reliability of the chips during their life cycle, and can quickly expose potential defects to meet the stringent testing requirements of SIP packaging.

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Abstract

The invention discloses a semiconductor aging test circuit and method, and belongs to the technical field of integrated circuits, the semiconductor aging test circuit comprises a three-temperature test area, an FPGA (Field Programmable Gate Array), a Flash and a DDR (Double Data Rate) device which are interconnected are packaged in an SIP (Session Initiation Protocol) in a to-be-tested chip, and a function aging module is integrated in the to-be-tested chip and is used for a function aging test. The configuration interface circuit is connected with the to-be-tested chip and is used for providing a JTAG interface for the to-be-tested chip; a chip to be tested is connected with a JTAG interface of the aging system through a JTAG interface provided by the configuration interface circuit, the aging system applies electric stress, thermal stress and dynamic signals to the chip to be tested, and the excitation board provides two paths of excitation clock signals to clock pins of a PL end and a PS end of the chip to be tested. The burn-in test circuit matched with the SIP packaged chip to be tested is provided for burn-in test, and the chip to be tested is arranged in the three-temperature test area, so that the test influence of extreme temperature on related circuits is reduced.
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