Multi-axis nanoscale real-time synchronous control system and method based on heterogeneous computing cooperation

Abstract

The application relates to the technical field of high-precision motion control and discloses a multi-axis nanometer real-time synchronous control system and method based on heterogeneous computing cooperation. The system adopts a space-time separation architecture of an AM5728 processor and an FPGA; the FPGA serves as a time-sensitive layer, multi-axis sensor data nanosecond-level synchronous collection and strict synchronous output of a control signal are realized through a global clock network; double-DSP kernels of the AM5728 serve as a calculation-intensive layer, and parallel calculation of multi-axis control algorithms is performed. The double-DSP kernels realize low-delay interaction of instructions and data through an optimized PCIe / GPMC interface. Under a clock taming mechanism, the synchronous error of multi-axis control signals is obviously reduced, and positioning precision is obviously improved. The scheme solves the real-time cooperative control problem of multi-axis systems in the fields of semiconductor manufacturing and the like, and the cost is greatly reduced compared with a traditional architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of precision motion control, and particularly relates to a multi-axis nanoscale real-time synchronous control system based on heterogeneous computing cooperation. BACKGROUND

[0002] In the field of high-end equipment such as semiconductor manufacturing and precision optical processing, the performance of the multi-axis motion control system directly affects the product precision and production efficiency. For example, the worktable of a lithography machine needs to control 4-6 precision motion axes to achieve nanoscale positioning, and the control signals of each axis must be strictly synchronized. The traditional microcontroller-based scheme has a fundamental defect: the sequential execution of the control cycle by the microcontroller results in a millisecond-level time difference in the multi-axis signal output. For example, a certain type of lithography machine has a positioning error of up to 120 nanometers due to a delay of more than 100 microseconds between axes, which cannot meet the requirements of 3-nanometer process technology.

[0003] With the increasing complexity of control algorithms, the calculation time of advanced algorithms such as model predictive control on microcontrollers exceeds 200 microseconds, far exceeding the control cycle requirement of 50 microseconds. This forces the system to reduce the control frequency or simplify the algorithm, thereby sacrificing the dynamic response performance. More seriously, control signal jitter (typical value ±50 microseconds) can excite mechanical resonance, which accumulates to form a trajectory deviation of more than 100 nanometers in high-speed motion scenarios.

[0004] Existing improvement schemes attempt to break through the bottleneck by two paths: one is to use a dedicated motion control chip, which can increase the calculation speed but increases the hardware cost by more than 40%; the other is to use a field programmable gate array plus microcontroller architecture, but the microcontroller computing power still cannot support real-time solution of 16-axis model predictive control. More importantly, the software layer has a stop response time of more than 1 millisecond, which cannot block the over-limit motion in time in the nanoscale positioning scenario, and there is a risk of equipment collision.

[0005] The above problems are essentially that the traditional architecture cannot simultaneously meet the three requirements of nanosecond-level synchronization, real-time complexity of algorithms, and high reliability. The current industry urgently needs a new system architecture that can coordinate timing control and computing load, which is the core research direction of the present application. SUMMARY

[0006] To solve the above technical problems, the present application provides a multi-axis nanoscale real-time synchronous control system based on heterogeneous computing cooperation, characterized in that the system comprises the following modules:

[0007] A space-time separation architecture module: the dual-DSP kernel of the AM5728 processor constitutes a calculation-intensive layer, and the FPGA constitutes a time-sensitive layer;

[0008] Global synchronization mechanism module: OCXO clock source is distributed to FPGA and AM5728 through LVDS network, reducing phase deviation;

[0009] Collaborative workflow module:

[0010] (a) FPGA synchronously collects multi-axis data at the clock rising edge and adds a timestamp;

[0011] (b) Data is transmitted to DSP through PCIe or GPMC interface to optimize communication;

[0012] (c) DSP completes control algorithm calculation within a specified time;

[0013] (d) The calculation result is returned to FPGA and synchronously updates the multi-axis output at the next clock rising edge.

[0014] Further, the FPGA comprises:

[0015] 24-channel ADC synchronous sampling unit, wherein the sampling jitter of the sampling unit is less than a first threshold;

[0016] 16-axis PWM synchronous output unit, triggered and updated by the same clock edge;

[0017] Emergency stop protection circuit, wherein the response time of the emergency stop protection circuit is less than a second threshold.

[0018] Further, the DSP core runs TI-RTOS real-time operating system; through parallel calculation by using vectorization instructions, operation acceleration is realized; a watchdog timer is integrated to monitor whether the task period is overdue.

[0019] Further, the PCIe or GPMC has the following specific structure:

[0020] The PCIe protocol frame structure is a 12-byte header and a 256-byte payload, and the bandwidth utilization rate is 95%;

[0021] Or

[0022] The GPMC interface timing parameters are address line setup time 4ns and data line hold time 2ns.

[0023] Further, FPGA performs nanoscale interpolation on the original encoder signal to improve signal resolution, and real-time monitoring of axis offset is realized through a hardware position comparator; DSP dynamically identifies mechanical resonance frequency and injects an anti-phase compensation signal, combined with an adaptive proportional-integral-derivative control algorithm, gain parameters are adjusted in real time according to load inertia changes to improve multi-axis positioning accuracy.

[0024] The application also provides a multi-axis synchronous control method of a multi-axis nanoscale real-time synchronous control system based on heterogeneous computing cooperation, characterized by comprising the following steps.

[0025] Step S1: configuring an OCXO master clock to trigger system synchronization;

[0026] Step S2: using vectorized instructions to perform parallel calculation of 16-axis control variables:

[0027]

[0028] wherein U is an axis control variable output, E is an axis error vector, is a proportional gain matrix, is an integral gain matrix, is a differential gain matrix;

[0029] Step S3: synchronously updating all axis output signals at the rising edge of the next clock cycle.

[0030] The embodiment of the application has the following technical effects:

[0031] The multi-axis synchronous control system of the application realizes all-round performance breakthrough in the field of semiconductor manufacturing. Relying on the hardware-level global clock triggering mechanism and high-precision clock taming network of a field programmable gate array, the multi-axis control signal output synchronous error stable control is within nanoseconds, which is several times higher than the microsecond-level error of a traditional microcontroller architecture, completely eliminates the trajectory distortion problem of a lithography machine workpiece table caused by inter-axis delay, and realizes hundreds of times improvement in synchronization performance. By integrating the nanoscale signal interpolation technology of a field programmable gate array and the dynamic resonance suppression algorithm of a digital signal processor, the system positioning accuracy reaches ±7.2 nanometers, and the positioning accuracy meets the 3-nanometer tip process demand. Application tests show that the workpiece table positioning error is compressed from the 100-nanometer level to the 10-nanometer level, reaching the ±10-nanometer tolerance requirement of the current most advanced process technology. The single instruction multiple data instruction set of the digital signal processor layer realizes parallel solution of 16-axis control variables, the model predictive control calculation time is greatly compressed compared with the traditional scheme, the efficiency is obviously improved, and the calculation efficiency real-time bottleneck is broken through. Combined with the reduced frame protocol of a peripheral component interconnect standard, the stability of the system under the rated time control cycle is greatly improved, providing algorithm guarantee for high-speed nanometer positioning. The time-space separation architecture significantly reduces the hardware cost compared with a special motion controller, significantly reduces the printed circuit board area, and significantly reduces power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0033] Figure 1 It is a system architecture diagram provided by the embodiment of the present application.

[0034] Figure 2 It is a clock taming network topology diagram provided by the embodiment of the present application.

[0035] Figure 3 It is a multi-stage closed-loop control block diagram provided by the embodiment of the present application.

[0036] Figure 4 It is a safety protection mechanism schematic diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the present application more clear, the technical scheme of the present application will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the present application. DETAILED DESCRIPTION

[0039] In the space-time separation heterogeneous computing architecture constructed by the present application, the time-sensitive layer constructed by the field programmable gate array (FPGA) realizes the global clock rising edge synchronous trigger of the multi-axis analog-to-digital converter sampling through hardware logic, ensures that the phase deviation of 24-axis sensor data acquisition meets the requirements, and at the same time drives the multi-axis pulse width modulation signal to be strictly aligned and updated in the next clock cycle, so that the phase difference is obviously reduced. The emergency stop protection circuit directly connects the actuator enable end, the response time is compressed to the level of 100 nanoseconds, and a hardware level safety barrier is formed. The calculation intensive layer constructed by the AM5728 processor is composed of double digital signal processor cores, adopts single instruction multiple data instruction set parallel processing of 16-axis control quantity, and compresses the model predictive control calculation time to 38 microseconds; combined with online mechanical resonance frequency identification and inverse sine compensation technology, mechanical resonance is effectively suppressed, and the algorithm bandwidth is obviously improved.

[0040] The present application also provides a multi-axis synchronous control method of a multi-axis nanometer real-time synchronous control system based on heterogeneous computing cooperation, characterized by comprising the following steps:

[0041] Step S1: configure OCXO master clock to trigger full system synchronization;

[0042] Step S2: Calculate 16-axis control quantities in parallel using vectorized instructions:

[0043]

[0044] Where U is the axis control output, E is the axis error vector, and K... p K is the proportional gain matrix. i K is the integral gain matrix. d It is the differential gain matrix;

[0045] Step S3: The calculation results are sent back to the FPGA and all axis output signals are updated synchronously on the rising edge of the next clock cycle. Figure 1 For system architecture diagrams, such as Figure 1 As shown, the master clock of the temperature-controlled crystal oscillator (OCXO) is distributed to 24 ADCs via an LVDS network. Synchronous sampling is triggered by the rising edge of the global clock, with a wiring length error of ≤1mm (time delay difference ≤5ps), ensuring that the data acquisition phase deviation is ≤200ps and embedding a ±1ns precision timestamp. The 16-axis PWM output achieves parallel loading of the duty cycle through a shared register group and a global reset signal, and the control signal is updated synchronously on the next rising edge of the clock. A 50Ω impedance matching circuit is deployed at the output to suppress jitter, and the output phase difference is ≤10ns. The emergency stop protection adopts a physical direct connection mechanism, with the signal directly reaching the FPGA hardware interrupt pin. After triggering, the PWM enable terminal is forcibly turned off within 80ns and the mechanical brake is activated.

[0046] The AM5728 dual-DSP core, based on a single-instruction multiple-data instruction set, completes four 32-bit floating-point multiply-accumulate operations in a single cycle. The TI-RTOS system divides the dual-core tasks: DSP1 executes position loop PID calculations, while DSP2 handles model predictive control optimization. Data is exchanged via shared memory, and a watchdog timer monitors task cycle timeouts and switches to backup algorithms. Mechanical resonance suppression involves real-time analysis of the encoder signal at a 1MHz sampling rate, extraction of the resonant frequency via FFT, and generation of an inverse compensation signal when the resonant energy exceeds a threshold. This is superimposed on the PID output and increases the derivative gain K. d ,in To compensate for the signal amplitude, f res φ is the mechanical resonant main frequency, t is the precise time reference, and φ is the phase correction amount. Model predictive control transforms the 16-axis state-space model into a block diagonal sparse matrix, and accelerates the inversion based on hot-start iteration and hardware divider, which greatly reduces the computation time.

[0047] The PCIe protocol adopts a simplified frame structure of 12-byte packet header and 256-byte payload, and zero-copy transmission is realized by directly writing the memory mapping area of the DSP by the FPGA. The dynamic delay compensation is realized by loopback test, the FPGA records time T1 when sending the test frame, records T2 after the DSP returns, calculates the transmission delay, dynamically adjusts the data sending time of the next period to realize the whole system timing alignment, and finally realizes the closed loop of "synchronous sampling → real-time calculation → accurate output" in 50 μs period, reduces the synchronization error of multi-axis control, and improves the positioning accuracy.

[0048] The system synchronization is based on clock taming network, and the oven-controlled crystal oscillator integrated in the FPGA is precisely driven by three paths through low-voltage differential signal network. The first path is transmitted to the global clock of the FPGA, and the timing of the analog-to-digital conversion and the pulse width modulation is uniformly scheduled; the second path is connected to the phase-locked loop input of the AM5728, so that the timing of the processor core and the execution layer is locked; and the third path is directly connected to the encoder sampling clock, so that the signal acquisition deviation is controlled within a predetermined range. The FPGA embeds a high-precision timestamp for each frame of data, and the whole system timing jitter is obviously reduced by combining the loopback delay dynamic compensation technology. As shown in Figure 2 The oven-controlled crystal oscillator outputs a 100 MHz base frequency signal, which is precisely driven by three paths through low-voltage differential signal (LVDS) network: the first path is connected to the global clock pin of the FPGA through a clock buffer, the serpentine wiring controls the equal length of the PCB wiring, and the timing of the ADC / PWM is uniformly scheduled; the second path is input to the phase-locked loop of the AM5728 processor, which generates a 3 GHz core clock in integer-N frequency division mode, and the dynamic phase detection realizes the timing locking of the processor and the execution layer; and the third path is directly connected to the sampling clock end of the optical encoder, the twisted shielded wire is transmitted and an RC filter network is deployed to ensure that the encoder acquisition deviation meets the actual demand.

[0049] The FPGA integrated time-to-digital converter module is driven by the OCXO clock to cooperate with a 32-bit counter and a fine interpolation circuit to capture the time point at the moment when the ADC sampling is completed and generate a high-precision timestamp, which is written into the fixed position of the data frame header; temperature-voltage compensation is automatically performed every 24 hours, the non-linear error is corrected based on the lookup table, and the precision drift is reduced.

[0050] The FPGA sends a 128-byte loopback test frame at the starting point of the control period, which contains a local timestamp T1, and the DSP returns the frame in the specified time; the FPGA records T2 when receiving the returned frame, and calculates the one-way transmission delay according to the formula , wherein t proc is the fixed processing delay of the DSP; the data sending time of the next period is dynamically adjusted as follows: , wherein is the predicted value of the DSP calculation time, and T0 is the reference time.

[0051] LVDS driver deploys spread spectrum modulation to compress clock jitter caused by power supply noise within the rated range; FPGA built-in eye diagram monitoring module measures the deviation of ADC sampling edge from clock rising edge in real time, feedback to OCXO control DAC for dynamic calibration, combined with three-way clock cooperation and delay compensation closed loop, to realize the reduction of timing jitter in the whole system, and keep the multi-axis signal synchronization error small in a large temperature range.

[0052] As shown in Figure 3 , signal processing and algorithm control together realize precision guarantee. At the signal processing level, FPGA performs nanoscale interpolation on the encoder original signal, improves the 1 pm resolution to 0.1 nm, forms a position loop, and monitors the axis deviation in real time through a hardware position comparator; at the algorithm control level, the digital signal processor dynamically identifies the mechanical resonance frequency and injects a reverse compensation signal, forms a speed loop, and combines with an adaptive proportional-integral-derivative control algorithm to adjust the gain parameters in real time according to the load inertia changes, finally realizes high precision of multi-axis positioning, and forms a current loop.

[0053] FPGA realizes nanoscale signal interpolation, uses dual-channel quadrature encoder signals, and generates high-resolution position data through sine and cosine lookup table and CORDIC algorithm. The original 1 pm period signal is subdivided by 4096 times, combined with noise shaping technology, and the effective resolution is improved to 0.1 nm. The hardware position comparator monitors the axis deviation in real time: the built-in 32-bit subtracter runs at a frequency of 400 MHz, compares the set position and feedback position difference, triggers the emergency stop signal within 50 ns when it exceeds the limit, and the accuracy is guaranteed by the temperature compensation circuit.

[0054] DSP performs three dynamic optimizations to realize precision control, captures the encoder vibration signal in real time at a sampling rate of 1 MHz, extracts the dominant mechanical resonance frequency through 1024-point FFT analysis , and generates a reverse compensation signal when the energy of a specific frequency band > 10 nm; simultaneously estimates the load inertia J in real time, where , is the motor torque, and a is the acceleration, to realize adaptive PID control, and adjust the PID gain in proportion when J changes > 10%: K p is updated to , K i is updated to , K d is updated to , where J new is the current load inertia, and J old is the load inertia before updating; a resonance suppression-inertia adaptive combined control strategy is formed.

[0055] Signal processing and algorithm control depth synergy build nanometer precision closed loop, FPGA 0.1 nm interpolation data every 50 μs upload to DSP, as PID algorithm error vector E; inverse compensation signal Real-time superimposed to PID output U.

[0056] Peripheral component interconnect standard protocol uses 12-byte simplified header and 256-byte axis data payload innovative frame structure, significantly improves the effective payload rate, 16-axis data transmission time consumption significantly shortens. Security protection is achieved through FPGA hardware layer and digital signal processor software layer synergy - hardware layer deployment emergency stop signal direct connection pulse width modulation enable end and overrun position real-time comparison; software layer running watchdog timer monitoring control cycle, and feedback to FPGA security state at 100 μs period, build from physical layer to logical layer complete protection system, communication optimization and security mechanism form closed loop protection.

[0057] PCIe protocol uses 12-byte simplified header and 256-byte payload (16-byte storage position / speed / state per axis) innovative frame structure, including 4-byte timestamp, 2-byte axis ID mask, 2-byte CRC, 4-byte control instruction, 256-byte payload including 16-byte storage position / speed / state per axis, effective payload rate significantly improved; based on PCIe Gen2 x4 interface to realize DSP memory mapping area direct writing and DMA burst transmission, combined with data packet prefetch mechanism, 16-axis data transmission time compression to 1.5 μs, header deployment Reed-Solomon error correction code, error rate significantly reduced.

[0058] As shown in Figure 4 Emergency stop signal straight through FPGA dedicated hardware interrupt pin, trigger fast pull-down PWM enable end and cut off the motor power, where MOSFET metal oxide semiconductor field effect transistor off <30 ns, total response time <100 ns; 400 MHz hardware position comparator real-time comparison of encoder feedback position and preset safety threshold, overrun instant freeze PWM output, synchronous activation brake relay, form physical level protection.

[0059] Independent hardware watchdog timer monitoring control cycle, automatically switch to simple PID backup algorithm when timeout; generate 32-bit security word every 100 μs, where byte 0-7 is task cycle state flag; byte 8-15 is memory CRC32 checksum; byte 16-23 is overload / over temperature alarm flag; byte 24-31 is reserved bit, optimized PCIe frame transmission to FPGA, immediately trigger safety shutdown sequence when verification fails.

[0060] The FPGA cross-verification hardware position monitoring result is compared with the position estimation value in the DSP security word, which is generated by a linear extrapolation algorithm, and when the deviation is too large, a secondary emergency stop is started; at the moment of triggering an emergency event, the last 128 frames of communication data, including 64-bit time stamps and shaft states, are frozen and written into a ferroelectric memory to build a complete fault tracing chain. Specific Implementation Two

[0062] The core hardware of the four-axis control system of the lithography machine workpiece table is based on an AM5728 processor and a field programmable gate array (FPGA). The AM5728 processor provides dual digital signal processor (DSP) core support, with a main frequency of 750 MHZ, responsible for core control algorithm operation. The FPGA undertakes high-speed real-time signal acquisition, synchronization and output driving tasks. The system uses an ultra-precision clock source to provide a global clock signal, with a frequency stability of ±25 ppb, ensuring a high-precision reference for the timing of the entire system. High-speed data exchange between the processor and the FPGA is realized through a peripheral component interconnect express second generation four-channel (PCIe Gen2x4) interface, which provides a transmission rate of up to 5 GT / s, ensuring low-latency transmission of control commands and feedback data on the critical path.

[0063] The control process strictly follows a fixed cycle of 50 microseconds. Each control cycle starts with the rising edge of the field programmable gate array (FPGA) global clock, at which time the synchronized position and speed signals of the X, Y, Z and Rz axes are sampled. The sampled data is then transmitted to the digital signal processor (DSP) through the high-speed PCIe channel. This data transmission process is completed within about 1.2 microseconds after the sampling starts. After receiving the data, the DSP immediately executes the complex model predictive control (MPC) algorithm calculation, which takes about 22 microseconds to complete. The optimal control instructions generated by the calculation are returned to the FPGA at the 23rd microsecond after the cycle begins. The FPGA receives and processes these instructions, preparing to update the control signals for each axis. Finally, at the next global clock rising edge (i.e., 50 microseconds after the cycle begins), the FPGA synchronously updates the pulse width modulation (PWM) drive signals to the four axes, driving the workpiece table actuator to achieve precise motion.

[0064] After rigorous testing, the four-axis control system exhibits excellent performance indicators. In terms of synchronization performance, the synchronization error of each axis is controlled at a very low level: the X-axis is 7.2 nanoseconds, the Y-axis is 8.1 nanoseconds, the Z-axis is 5.8 nanoseconds, and the Rz-axis is 6.3 nanoseconds. The positioning accuracy also reaches the nanometer level: the X-axis is ±6.5 nanometers, the Y-axis is ±7.1 nanometers, the Z-axis is ±4.9 nanometers, and the Rz-axis is ±5.7 nanometers. These measured data fully verify the effectiveness of the system hardware design, control algorithm and timing management.

[0065] The system sets the core control period as 50 microseconds, which provides a basis for balancing real-time and control accuracy. The pulse width modulation (PWM) output is driven by a high-frequency clock of 400 MHz, achieving a resolution of up to 2.5 nanoseconds, which provides a guarantee for micron or even nanometer level precision position control. In terms of safety mechanism, the system designs a hardware level emergency stop response link. When the emergency stop signal is triggered, the system can forcibly close the pulse width modulation (PWM) output of all axes in a very short time (less than 80 nanoseconds), ensuring that the worktable movement stops immediately, and maximizing the safety of the equipment and operation.

[0066] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application.

Claims

1. A multi-axis nanoscale real-time synchronous control system based on heterogeneous computing collaboration, characterized in that, The system comprises the following modules: a space-time separation architecture module comprising a computation-intensive layer composed of dual digital signal processor cores of an AM5728 processor and a time-sensitive layer composed of an FPGA; a global synchronization mechanism module comprising a constant-temperature control crystal oscillator clock source, the constant-temperature control crystal oscillator clock source signal being distributed to the FPGA, the AM5728 and the encoder via a low-voltage differential signal network; a collaborative workflow module implementing the following processes: (a) the FPGA synchronously collects multi-axis data at a clock rising edge and adds a time stamp; (b) the multi-axis data with the added time stamp is transmitted to the DSP via a PCIe or GPMC interface; (c) the dual digital signal processor completes control algorithm calculation within a specified time; (d) the calculation result is returned to the FPGA and synchronously updates multi-axis output at a next clock rising edge; the FPGA performs nanoscale interpolation on the collected multi-axis data and monitors axis deviation in real time through a hardware position comparator; Dual digital signal processor dynamically identifies mechanical resonance frequency in multi-axis data and injects anti-phase compensation signal, combines adaptive proportional integral derivative control algorithm, and adjusts gain parameters in real time according to load inertia change, specific process is as follows: real-time capture of encoder vibration signal at 1MHz sampling rate, extraction of mechanical resonance frequency through 1024-point FFT analysis When the resonance energy is above the threshold, an anti-phase compensation signal is generated Superimposed on the PID output, wherein is the compensation signal amplitude, t is the accurate time reference, and φ is the phase correction amount; the load inertia J is estimated in real time, wherein , is the motor torque, and α is the acceleration; when the J change is greater than 10%, the PID gain is adjusted in proportion: K p is updated to , K i is updated to , K d is updated to , wherein is the proportional gain matrix, is the integral gain matrix, is the differential gain matrix, J new is the current load inertia, J old is the load inertia before updating.

2. The system of claim 1, wherein, the FPGA comprises: a 24-channel ADC synchronous sampling unit, wherein the sampling jitter of the ADC synchronous sampling unit is less than a first threshold value; a 16-axis PWM synchronous output unit triggered and updated by the same clock edge; an emergency stop protection circuit, wherein the response time of the emergency stop protection circuit is less than a second threshold value.

3. The system of claim 1, wherein, The DSP core runs a TI-RTOS real-time operating system; parallel computation is realized through the use of vectorized instructions to achieve operation acceleration; a watchdog timer is integrated to monitor whether the task period is overdue.

4. The system of claim 1, wherein, The specific structure of the PCIe or GPMC interface is: The PCIe protocol frame structure is a 12-byte header and a 256-byte payload, and the bandwidth utilization rate is 95%; Or The GPMC interface timing parameters are address line setup time of 4 ns and data line hold time of 2 ns.

5. A multi-axis synchronization control method of a multi-axis nanoscale real-time synchronization control system based on heterogeneous computing cooperation according to any one of claims 1-4, characterized in that, The steps comprise: Step S1, configure a constant-temperature control crystal oscillator master clock to trigger system synchronization; Step S2, use vectorized instructions to perform parallel computation of 16-axis control quantities: ； where U is an axis control quantity output, E is an axis error vector, is a proportional gain matrix, is an integral gain matrix, is a differential gain matrix, and t represents time. Step S3, return the calculation result to the FPGA and synchronously update all axis output signals at a next clock cycle rising edge.

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