A CXL host controller, data transmission method and computer

Abstract

Embodiments of the present application provide a CXL host controller, a data transmission method and a computer. The CXL host controller comprises a CXL host bridge module and a CXL multi-port controller. The CXL multi-port controller is connected to a physical link of a CXL device. A plurality of root ports managed by the CXL multi-port controller are shared. Each root port is used to connect a corresponding CXL device. The plurality of root ports are activated in turn according to a time division multiplexing mechanism, and data transmission is performed using the physical link. The CXL host bridge module receives a processor packet in a sending direction and converts the processor packet into a CXL packet for transmission to the CXL multi-port controller. The CXL multi-port controller receives the CXL packet of the CXL host bridge module in a sending direction, and transmits a data packet corresponding to the CXL packet to a target root port indicated by a time division multiplexing signal of a current clock cycle, and transmits the data packet to the CXL device through the target root port. The CXL host controller realizes multi-port expansion, and provides higher compatibility and flexibility for CXL network and memory device expansion.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a CXL host controller, a data transmission method, and a computer. Background Technology

[0002] With the development of distributed computing, the demand for memory pooling is increasing to enable dynamic allocation and reclamation of memory resources, thereby optimizing overall memory utilization. The CXL (Compute Express Link) protocol provides key support for this, not only expanding the capacity and bandwidth of the memory subsystem, but also enabling interconnection between heterogeneous processors and peripheral devices, achieving decoupling and pooling of computing and memory resources.

[0003] Against this backdrop, how to provide a design scheme for a CXL host controller to achieve multi-port expansion of the CXL host controller and provide higher compatibility and flexibility for the expansion of CXL network and memory devices has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a CXL host controller, a data transmission method, and a computer, which can realize multi-port expansion of the CXL host controller and provide higher compatibility and flexibility for the expansion of CXL network and memory devices.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a CXL host controller, including: a CXL host bridging module and a CXL multi-port controller; the physical link connecting the CXL multi-port controller to CXL devices is shared by multiple root ports managed by the CXL multi-port controller, each root port being used to connect to a corresponding CXL device; and the multiple root ports are activated in turn according to a time-division multiplexing mechanism to take turns using the physical link for data transmission, wherein the time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle;

[0007] The CXL host bridging module is used to receive processor messages from the processor in the sending direction, convert the processor messages into CXL messages, and transmit the CXL messages to the CXL multiport controller.

[0008] The CXL multiport controller is used to receive CXL messages from the CXL host bridging module in the transmitting direction, activate the target root port based on the time division multiplexing signal of the current clock cycle, and transmit the data packet corresponding to the CXL message to the target root port so that the data packet can be transmitted to the corresponding CXL device through the target root port.

[0009] Optionally, the CXL host bridging module is further configured to receive CXL messages uploaded by the CXL multiport controller in the receiving direction and report them to the processor;

[0010] The CXL multiport controller is also used to receive data packets transmitted by each root port in the receiving direction, and when the time division multiplexing signal of the current clock cycle indicates that the accumulated data packets transmitted by the activated target root port have reached the preset data bit width, convert the data packets into CXL messages, and upload the CXL messages to the CXL host bridging module in the next active clock cycle of the target root port.

[0011] Optionally, the time-division multiplexed signal includes:

[0012] The number of flag bits corresponding to the number of the plurality of root ports, wherein one flag bit corresponds to one root port, the flag bits include a valid flag bit and an invalid flag bit, the root port corresponding to the valid flag bit is in an active state, and the time division multiplexed signal in one clock cycle has only one valid flag bit.

[0013] Optionally, the physical link consists of multiple physical channels, which are divided into multiple physical channel groups. A root port is assigned a corresponding physical channel group and data is transmitted through the physical channel group.

[0014] Optionally, during a round-robin activation of multiple root ports, the number of consecutive activation clock cycles corresponding to a root port is related to the number of physical channels in the physical channel group corresponding to the root port.

[0015] Optionally, during a round-robin activation of multiple root ports, the number of consecutive activation clock cycles for each root port is proportionally allocated based on the number of physical channels corresponding to each root port.

[0016] Optionally, it also includes:

[0017] The time-division multiplexing signal generation module is used to generate a time-division multiplexed signal for each clock cycle and transmit it to the CXL multiport controller to indicate the root port that is active for each clock cycle.

[0018] Optionally, it also includes: a cache corresponding to each root port, used to temporarily store data transmitted through each root port;

[0019] The CXL multi-port controller is specifically used for:

[0020] In the transmission direction, the time-division multiplexing signal based on the current clock cycle indicates the active target root port. The transmitting link layer processing logic processes the packets in the buffer of the target root port until multiple progressive transmitting link layer processing logics are completed, resulting in the data packet corresponding to the CXL packet to be transmitted to the target root port. Specifically, one transmitting link layer processing logic is performed in one active clock cycle of a root port. The result of the previous transmitting link layer processing logic is temporarily stored in the buffer of the root port and processed by the next transmitting link layer processing logic in the next active clock cycle of the root port.

[0021] In the receiving direction, the target root port activated in the current clock cycle is determined based on the time-division multiplexing signal of the current clock cycle. When the data packets buffered in the buffer corresponding to the target root port reach the preset data bit width, the data packets are retrieved from the buffer corresponding to the target root port, and the data packets are unpacked into corresponding CXL messages through the link layer unpacking logic and temporarily stored in the buffer corresponding to the target root port. Among them, the unpacked CXL messages in the buffer of a root port are sent to the CXL host bridging module in the next active clock cycle.

[0022] Optionally, the CXL host bridging module is further used for:

[0023] After converting the processor message into a CXL message, the port ID of the root port for transmitting the CXL message is determined according to the mapping relationship between the message address and the routing information. The routing information includes: routing method, number of ports, and port ID.

[0024] The port ID is carried in the CXL message, wherein the CXL message transmitted to the CXL multi-port controller is a CXL message carrying the port ID.

[0025] Optionally, the CXL host bridging module is further used for:

[0026] Before determining the port ID, it is determined whether the packet address is within the routing address range of the multiple root ports. If so, the step of determining the port ID of the root port transmitting the CXL packet based on the mapping relationship between the packet address and the routing information is executed. If not, the converted CXL packet is discarded.

[0027] Secondly, embodiments of this application provide a data transmission method applied to a CXL host controller, comprising:

[0028] Receive processor messages from the processor;

[0029] Convert the processor message to a CXL message;

[0030] Based on the time-division multiplexing signal indicating the active target root port of the current clock cycle, the data packet corresponding to the CXL message is transmitted to the target root port so that the data packet can be transmitted to the corresponding CXL device through the target root port;

[0031] The multiple root ports share the physical link between the CXL host controller and the CXL device. The multiple root ports are activated in turn according to the time-division multiplexing mechanism so as to take turns using the physical link for data transmission. The time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle.

[0032] Thirdly, embodiments of this application provide a computer, including:

[0033] processor;

[0034] CXL host controller, the CXL host controller being as described in the first aspect above;

[0035] CXL equipment;

[0036] The CXL device is connected to the root port of the CXL host controller, or to the root port of the CXL host controller via a CXL connector. One root port can be connected to multiple CXL devices via a CXL connector.

[0037] As can be seen, the CXL host controller provided in this application embodiment includes a CXL host bridging module and a CXL multiport controller; the physical link connecting the CXL device to the CXL multiport controller is shared by multiple root ports managed by the CXL multiport controller, and each root port is used to connect to the corresponding CXL device; and the multiple root ports are activated in turn according to a time-division multiplexing mechanism to take turns using the physical link for data transmission, wherein the time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle; the CXL host bridging module is used to receive processor messages from the processor in the transmitting direction, convert the processor messages into CXL messages, and transmit the CXL messages to the CXL multiport controller; the CXL multiport controller is used to receive CXL messages from the CXL host bridging module in the transmitting direction, and based on the time-division multiplexing signal of the current clock cycle indicating the activated target root port, transmit the data packets corresponding to the CXL messages to the target root port, so that the data packets are transmitted to the corresponding CXL device through the target root port. In other words, under the condition of using a single CXL host bridging module, multiple root ports can be extended by time-division multiplexing the physical link of the CXL multi-port controller. Each root port can independently connect to CXL devices for data transmission. Therefore, the CXL host controller provided in this application can realize multi-port expansion of the CXL host controller, providing higher compatibility and flexibility for the expansion of CXL networks and memory devices. At the same time, compared with the method of directly using multiple CXL controllers to realize root port expansion, it can save resources and area. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 This is an example diagram of an optional structure of the CXL host controller provided in the embodiments of this application;

[0040] Figure 2 This is a schematic diagram of the CXL host bridging module's processing flow for processor packets;

[0041] Figure 3 This is a schematic diagram of data processing in the transmitting direction of the CXL multi-port controller;

[0042] Figure 4 This is a diagram illustrating the allocation of independent caches across multiple ports;

[0043] Figure 5This is a schematic diagram of the CXL multiport controller's data processing in the receiving direction;

[0044] Figure 6 This is an optional flowchart of the data transmission method provided in the embodiments of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] DDR (Double Data Rate) and PCIe (Peripheral Component Interconnect Express) interfaces have always been ideal interfaces for various devices. System memory can be connected via DDR and supports a tiered caching mechanism for the CPU (Central Processing Unit), such as the CPU's three-level cache structure (L1 cache, L2 cache, and L3 cache). Among them, L1 cache is the fastest but has the smallest capacity and is dedicated to each CPU core; L2 cache is the next fastest and has a slightly larger capacity, dedicated to each CPU core or shared by all CPU cores; L3 cache is the slowest but has the largest capacity and is shared by all CPU cores. The larger the cache capacity, the more data it stores, but the slower the speed. Therefore, after adopting a tiered three-level cache structure, L1 cache can be used to store the most urgent data, while L2 / L3 cache can be used to store less important or shared data.

[0047] However, the large number of pins on the DDR interface limits memory scalability, making it unable to meet the demands of increasing memory capacity and bandwidth. In contrast, the PCIe interface has fewer pins, offering greater scalability and supporting the use of retimers (signal boosters) for longer transmission distances, thus providing a significant advantage for memory expansion. However, PCIe devices access system memory through inconsistent read / write operations. While this inconsistency is effective for large data volumes, PCIe devices cannot cache system memory, thus preventing them from utilizing temporal or spatial location to execute atomic operation sequences. In other words, PCIe devices cannot cache system memory data, making it impossible to guarantee data consistency between multiple devices. Because of data synchronization issues, it's impossible to leverage temporal (e.g., the same data in memory might be accessed multiple times, but the PCIe device cannot temporarily store it through caching, leading to inefficiency during repeated accesses) or spatial (e.g., data in adjacent memory stores might be accessed together, but the PCIe device cannot retrieve the data from adjacent stores at once, requiring multiple requests) dependencies to improve access efficiency. Here, an atomic operation sequence is an operation sequence that is executed completely without interruption. Similarly, memory connected to a PCIe device is accessed inconsistently from the host, with each access handled by the PCIe device, and the PCIe device's memory cannot be mapped to a consistent memory space.

[0048] In summary, the DDR interface has a large number of pins and poor memory expandability. Expanding by adding DDR channels will significantly increase platform costs and affect signal integrity. Meanwhile, the PCIe interface does not support consistent access, resulting in high latency for the host to access PCIe devices' memory, and memory read and write operations cannot be performed atomically.

[0049] Against this backdrop, the CXL (Compute Express Link) protocol has gradually attracted attention. The CXL protocol is a high-speed interconnect technology that enables high-speed and efficient interconnection between CPUs and GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays), or other accelerators, while maintaining consistency between CPU memory space and connected device memory. It can provide higher bandwidth and lower latency, and is suitable for scenarios requiring high-performance memory expansion.

[0050] Specifically, the CXL protocol has several iterative versions. In CXL 2.0, a small network consisting of CXL hosts and CXL devices is built by introducing switches, thus achieving memory pooling. CXL devices refer to extended devices conforming to the CXL protocol specification, decoupling memory resources scattered across multiple CXL devices and integrating them through the CXL protocol to form a shared memory resource pool. In CXL 3.0, memory expansion is achieved on a larger scale through multi-level switches, solving the problem of low memory resource utilization efficiency. Multiple CXL hosts are connected in a link through switches, requesting and allocating memory resources as needed. However, the current CXL... Switches have high inherent latency and require a certain amount of space, which may not be supported by some systems or application scenarios. At the same time, during memory expansion, each root port of the CXL host is associated with an independent CXL controller. Therefore, when expanding multiple root ports, multiple CXL controllers are required. Although this method can achieve multi-port expansion of the CXL host and thus memory expansion, multiple CXL controllers occupy a large amount of resources and may affect the performance of the CXL host.

[0051] In view of this, this application provides a CXL host controller that enables multi-port expansion of the CXL host controller, providing higher compatibility and flexibility for CXL network and memory device expansion; at the same time, compared with directly using multiple CXL controllers to achieve root port expansion, it can save resource area.

[0052] Figure 1 This is an example diagram of an optional structure of the CXL host controller provided in the embodiments of this application, such as... Figure 1 As shown, the CXL host controller may include: a CXL host bridging module and a CXL multi-port controller; the physical link connecting the CXL multi-port controller to the CXL device is shared by multiple root ports (RPs) managed by the CXL multi-port controller, and each root port is used to connect to the corresponding CXL device; and the multiple root ports are activated in turn according to a time-division multiplexing mechanism to take turns using the physical link for data transmission, wherein the time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle.

[0053] In this embodiment, multiple root ports are managed by the CXL multiport controller, and each root port is configured to connect to a corresponding CXL device; the multiple root ports serve as interfaces for the CXL host controller to connect to corresponding external devices (e.g., CXL devices), such as... Figure 1As shown, the CXL host controller can connect to the corresponding CXL device through the root port, or it can connect to the corresponding CXL device through the root port and the CXL switch. Multiple root ports can share the same physical link for data transmission; this physical link is the link between the CXL multi-port controller and the CXL device.

[0054] In specific implementations, embodiments of this application may employ Time Division Multiplexing (TDM) technology. TDM is a communication technology that enables multiple signals to share the same channel through time division. Based on the TDM mechanism, embodiments of this application can allocate the resources of the physical link to each root port in turn according to the clock cycle, enabling multiple root ports to multiplex the same physical link for data transmission; for example... Figure 1 As shown, the CXL host controller may further include a time-division multiplexing signal generation module, which generates a time-division multiplexing signal for each clock cycle and transmits it to the CXL multi-port controller to indicate the root port activated in each clock cycle. In turn, multiple root ports can be activated in turn according to the time-division multiplexing mechanism and take turns using the physical link for data transmission.

[0055] In this embodiment of the application, the time-division multiplexing signal generation module is used to generate a time-division multiplexed signal for each clock cycle and allocate a time slice for each root port.

[0056] In an optional implementation, the time-division multiplexing signal may include: flag bits corresponding to the number of multiple root ports, wherein one flag bit corresponds to one root port, the flag bits include a valid flag bit and an invalid flag bit, the root port corresponding to the valid flag bit is in an active state, and the time-division multiplexing signal in one clock cycle has only one valid flag bit.

[0057] In other words, the time-division multiplexed signal consists of flag bits corresponding to the number of multiple root ports. For example, if the CXL host controller is configured with 4 root ports, the corresponding output time-division multiplexed signal includes 4 flag bits; if the CXL host controller is configured with 3 root ports, the corresponding output time-division multiplexed signal includes 3 flag bits, and so on.

[0058] One flag bit corresponds to one root port. The flag bits include valid flag bits and invalid flag bits. The root port corresponding to the valid flag bit is in an active state. In an optional embodiment, the CXL host controller is configured with 4 root ports. Then, the time-division multiplexing signal timing_slot[3:0] output by the time-division multiplexing signal generation module in a certain clock cycle can be 4'b0001. Here, timing_slot[3:0] indicates that the time-division multiplexing signal includes 4 flag bits composed of timing_slot[3] to timing_slot[0]. The value of each flag bit is used to indicate whether the root port corresponding to the flag bit is in an active state. For example, the value of timing_slot[0] is used to indicate whether root port 0 is in an active state. The value of slot[1] is used to indicate whether root port 1 is in an active state, the value of timing_slot[2] is used to indicate whether root port 2 is in an active state, and the value of timing_slot[3] is used to indicate whether root port 3 is in an active state. In this embodiment, the value of the flag bit can be represented in binary. The value of the valid flag bit can be 1, that is, the root port corresponding to the flag bit value of 1 is in an active state. 4'b0001 represents a 4-bit binary value 0001. This time division multiplexing signal indicates that timing_slot[0] is 1, then the root port 0 corresponding to timing_slot[0] is in an active state. The values ​​of other flag bits, i.e. invalid flag bits, are 0, indicating that the root ports corresponding to other flag bits are in an inactive state.

[0059] The time-division multiplexed signal in one clock cycle has only one valid flag bit. For example, the time-division multiplexed signal in one clock cycle has only one flag bit with a value of 1, while the other flag bits have a value of 0. This ensures that only one root port is active in each clock cycle, and the physical link can be used for data transmission.

[0060] Furthermore, in this embodiment of the application, the physical link consists of multiple physical channels (lanes), which can be divided into multiple physical channel groups. A root port is assigned a corresponding physical channel group and data is transmitted through the physical channel group.

[0061] In other words, multiple root ports share a single physical link. By subdividing the original physical link, the multiple physical channels (lanes) of the physical link can be divided into multiple groups. Each group is used independently by a pair of transmitters and receivers. One root port corresponds to one physical channel group, and thus each root port corresponds to a set of transmitters and receivers. These can be connected to CXL devices or CXL switches for data transmission.

[0062] In an optional embodiment, for example, the physical link consists of 16 physical channels (x16). If the CXL host controller is configured with 4 root ports, the 16 physical channels can be divided into 4 physical channel groups corresponding to the 4 root ports. For example, the number of physical channels in the 4 physical channel groups can be 8 physical channels (x8), 4 physical channels (x4), 2 physical channels (x2), and 2 physical channels (x2), respectively. Of course, the number of physical channels in the 4 physical channel groups can also be divided equally, that is, each physical channel group includes 4 physical channels (x4).

[0063] In another optional embodiment, the physical link consists of 16 physical channels (x16). If the CXL host controller is configured with 3 root ports, the 16 physical channels can be divided into 3 physical channel groups corresponding to the 3 root ports. For example, the number of physical channels in the 3 physical channel groups can be 4 physical channels (x4), 2 physical channels (x2), and 2 physical channels (x2), respectively.

[0064] In another optional embodiment, the physical link consists of 16 physical channels (x16). If the CXL host controller is configured with 2 root ports, the 16 physical channels can be divided into 2 physical channel groups corresponding to the 2 root ports. For example, the number of physical channels in the 2 physical channel groups can be divided equally, and each physical channel group includes 8 physical channels (x8).

[0065] It should be noted that the above number of ports and physical channel grouping are only examples, and the embodiments of this application are not limited to the above examples of number of ports and physical channel grouping.

[0066] In this embodiment of the application, the number of root ports of the CXL host controller and the number of physical channels (lanes) in the physical channel group corresponding to each root port can be dynamically adjusted by software.

[0067] It should be noted that the software-based dynamic adjustment method is not only applicable to configuring the number of root ports and the number of physical channels of the root ports, but also applicable to other types of memory network connections and expansion scenarios.

[0068] Furthermore, based on the actual subdivision of the physical link, the corresponding time-division multiplexed signal is output. At the same time, based on the subdivision of the physical link, the number of clock cycles in which a root port is continuously active can be determined.

[0069] In an optional implementation, during a round-robin activation of multiple root ports, the number of consecutive clock cycles for a single root port is related to the number of physical channels in the physical channel group corresponding to the root port.

[0070] In an optional embodiment, during the round-robin activation of multiple root ports, the number of consecutive activation clock cycles corresponding to each root port can be allocated proportionally according to the number of physical channels corresponding to each root port; thereby maximizing the utilization of physical channel resources and minimizing resource contention issues.

[0071] In a specific embodiment, the following description assumes that the physical link consists of 16 physical channels (x16), the CXL host controller is configured with 4 root ports, and the 16 physical channels are divided into 4 physical channel groups corresponding to the 4 root ports, including 8 physical channels (x8), 4 physical channels (x4), 2 physical channels (x2), and 2 physical channels (x2) respectively. In this example, the ratio of the number of physical channels in the 4 root ports is 4:2:1:1. If we assume that a round of activation lasts for 8 clock cycles, then according to the above ratio of the number of physical channels in the 4 root ports, the corresponding number of consecutive activation clock cycles can be configured for each root port, that is, the ratio of the number of consecutive activation clock cycles of the 4 root ports is also 4:2:1:1.

[0072] Specifically, in a round of activation that lasts for 8 clock cycles, a root port with 8 physical channels can be activated for 4 consecutive clock cycles, a root port with 4 physical channels can be activated for 2 consecutive clock cycles, and a root port with 2 physical channels can be activated for 1 consecutive clock cycle.

[0073] Continuing with the example above, the time-division multiplexed signal generation module can continuously output the following time-division multiplexed signal during a round-robin activation process (e.g., 8 clock cycles):

[0074] Clock cycles 1-4: 4'b0001;

[0075] 5th-6th clock cycle: 4'b0010;

[0076] 7th clock cycle: 4'b0100;

[0077] 8th clock cycle: 4'b1000;

[0078] This process repeats in turn, entering the next round of activation.

[0079] In the first to fourth clock cycles, the time-division multiplexing signal indicates that root port 0 is continuously active. The physical channel group corresponding to root port 0 includes 8 physical channels. Thus, with the number of continuously active clock cycles allocated proportionally according to the number of physical channels corresponding to each root port, root port 0 is continuously active for 4 clock cycles in one round of activation. Taking 8 clock cycles as an example, in the fifth and sixth clock cycles, the time-division multiplexing signal indicates that root port 1 is continuously active. The physical channel group corresponding to root port 1 includes 4 physical channels. Root port 1 is continuously active for 2 clock cycles in one round of activation. In the seventh clock cycle, the time-division multiplexing signal indicates that root port 2 is active. The physical channel group corresponding to root port 2 includes 2 physical channels. Root port 2 is continuously active for 1 clock cycle in one round of activation. In the eighth clock cycle, the time-division multiplexing signal indicates that root port 3 is active. The physical channel group corresponding to root port 3 includes 2 physical channels. Root port 3 is continuously active for 1 clock cycle in one round of activation.

[0080] In this embodiment of the application, during the initialization training of the physical link, port configuration information can be generated and stored in a register according to the division of the physical link. The port configuration information can record the clock cycle number activated by each root port and the number of consecutively activated clock cycles. After initialization is completed, the time-division multiplexing signal generation module reads the value of the register and outputs the corresponding time-division multiplexing signal.

[0081] Furthermore, as an optional implementation, the embodiments of this application are not limited to sending fixed polling (i.e., fixed turn-by-turn) time-division multiplexing signals through a time-division multiplexing signal generation module to obtain data from the corresponding root port for processing. A non-fixed polling method can also be used, for example, adding arbitration logic to the buffer of each root port to obtain data from a root port for transmission according to the order of data arrival or a preset priority.

[0082] Based on the configuration methods described above, such as the number of root ports and the division of physical channels, the CXL host controller can achieve multi-port expansion and adapt to various scenarios, providing higher compatibility and flexibility for memory expansion.

[0083] The CXL host bridging module is used to receive processor messages from the processor in the sending direction, convert the processor messages into CXL messages, and transmit the CXL messages to the CXL multiport controller. The sending direction refers to the flow of data during the transmission process from the processor to the CXL device.

[0084] In this embodiment of the application, the CXL host controller includes a common CXL host bridge module, which is a bridge in the CXL host controller used to connect upstream and downstream. The upstream refers to the side pointing to the processor core or closer to the computing core, such as the processor, and the downstream refers to the side pointing to external devices or away from the computing core, such as the CXL multi-port controller and the CXL devices connected to it. The CXL host bridge module can be connected to multiple CXL devices through multiple root ports.

[0085] Among them, reference Figure 1 The data of the CXL host bridging module comes from the data generated during the operation of the software / control system. It is output by the processor in the form of processor messages, and the software / control system is run by the processor.

[0086] In the sending direction, the CXL host bridging module receives processor messages from the processor, which needs to be processed and converted into CXL messages that conform to the CXL transaction layer protocol, and then routed according to the address range to ensure that the CXL messages are transmitted to the designated root port.

[0087] Specifically, Figure 2 This is a schematic diagram illustrating the CXL host bridging module's processing flow of processor packets, as shown below. Figure 2 As shown, the processing flow includes the following steps.

[0088] Step S21: The processor sends a processor message.

[0089] The processor message may be data generated during the execution of an operating system program or application by the processor (specifically, the processor core), or it may be data generated during the execution of a virtual machine program by the processor.

[0090] In the memory expansion scenario provided in this application embodiment, the processor message can be access data for accessing the CXL device, that is, access data for the shared memory resource pool. The shared memory resource pool is formed by decoupling memory resources scattered across multiple CXL devices and integrating them together through the CXL protocol.

[0091] Step S22: Convert the processor message into a CXL message.

[0092] Step S23: Determine whether the packet address is within the routing address range of the multiple root ports. If yes, proceed to step S24; otherwise, proceed to step S26.

[0093] In this embodiment of the application, the message address indicates the location of the target resource (e.g., the target CXL device) requested by the processor message. The routing relationship between the CXL device and the root port is recorded in the mapping relationship between the message address and the routing information. That is, which root port is responsible for the data routing of which CXL device is pre-mapped and recorded.

[0094] In an optional implementation, the CXL host bridging module is further configured to: determine whether the CXL packet address is within the routing address range of the multiple root ports; if so, execute the step of determining the port ID of the root port transmitting the CXL packet based on the mapping relationship between the packet address and the routing information, i.e., step S24; if not, discard the converted CXL packet.

[0095] S24: Determine the port ID of the root port for transmitting CXL messages based on the mapping relationship between message addresses and routing information.

[0096] After determining that the message address is within the routing address range of the multiple root ports, the port ID of the root port transmitting the CXL message can be further determined based on the mapping relationship between the message address and the routing information. This allows us to determine which root port the CXL message is routed to and to carry the port ID of the root port in the CXL message. In other words, the CXL message transmitted to the CXL multi-port controller is a CXL message carrying the port ID (the figure shows CXL message + port ID).

[0097] In this embodiment of the application, the routing information may include: routing method (e.g., static routing or dynamic adaptive routing), number of ports (multiple root ports can be used to support multipath forwarding or load balancing), and port ID (used to identify the switching port connected to the CXL device). The address range of the route can be freely configured, and different address ranges can have different routing methods and number of ports.

[0098] In other words, the message address and routing information can be dynamically adjusted. The message address indicates the location of the target resource (target CXL device) requested by the processor message, and the routing information includes the routing method, the number of ports, and the port ID. Therefore, by dynamically adjusting the message address and routing information, the CXL device connected to the root port can be dynamically adjusted.

[0099] Furthermore, in this embodiment of the application, the routing information is configured before the CXL host bridging module is initialized. The CXL host bridging module can obtain the routing information by reading registers, and then determine the port ID of the root port for transmitting CXL packets according to the mapping relationship between packet address and routing information.

[0100] Step S25: Routing based on message address.

[0101] After determining the port ID, routing can be performed based on the message address to transmit the converted CXL message. The CXL message carries the port ID. Subsequently, after the CXL multi-port controller receives the CXL message, it can temporarily store it in the independent cache corresponding to the root port corresponding to the port ID, based on the attached port ID.

[0102] Step S26: Discard the converted CXL message.

[0103] The CXL multiport controller is used to receive CXL messages from the CXL host bridging module in the transmitting direction, activate the target root port based on the time division multiplexing signal of the current clock cycle, and transmit the data packet corresponding to the CXL message to the target root port so that the data packet can be transmitted to the corresponding CXL device through the target root port.

[0104] In the sending direction, after receiving a CXL message from the CXL host bridging module, the CXL Multi-Port Controller can temporarily store it in the independent buffer corresponding to that port based on the attached port ID.

[0105] In this embodiment of the application, the CXL host controller further includes: a cache corresponding to each root port, used to temporarily store data transmitted through each root port.

[0106] The CXL multi-port controller is specifically used for: in the transmission direction, based on the time-division multiplexing signal indicating the activated target root port of the current clock cycle, processing the packets in the buffer of the target root port with the transmitting end link layer processing logic, until multiple progressive transmitting end link layer processing logics are completed, and obtaining the data packet corresponding to the CXL packet to be transmitted to the target root port; wherein, one transmitting end link layer processing logic is performed in one active clock cycle of a root port, and the result of the previous transmitting end link layer processing logic is temporarily stored in the buffer of the root port, and is processed by the next transmitting end link layer processing logic in the next active clock cycle of the root port.

[0107] Figure 3 This is a schematic diagram of the CXL multiport controller's data processing in the transmitting direction, as shown below. Figure 3As shown, taking four root ports as an example, after the CXL multi-port controller receives a CXL message from the CXL host bridging module, it temporarily stores it in the independent buffer corresponding to that port according to the attached port ID, such as root port 0 buffer, root port 1 buffer, root port 2 buffer, and root port 3 buffer. Based on the time division multiplexing signal indicating the active target root port in the current clock cycle, the CXL message can be extracted from the buffer corresponding to the active target root port from the buffers of multiple root ports. The CXL message is then processed by the link layer. The link layer processing logic includes multiple progressive link layer processing logics (represented as link layer processing logic 41, link layer processing logic 42, and link layer processing logic 43 in the figure). For example, the multiple link layer processing logics may include various progressive sender link layer processing logics such as link layer packetization and bit width conversion, and are performed progressively according to the clock cycle.

[0108] In an optional embodiment, an active clock cycle can be used for link layer packetization logic to package CXL messages into corresponding data packets (Flits). Here, Flit is the packet format of the CXL link layer transmission message with a fixed bit width. The result after processing by the previous link layer processing logic (i.e., link layer packetization logic) can be temporarily stored in the buffer of the target root port. In the next active clock cycle, the CXL message corresponding to the target root port can be extracted from the buffers of multiple root ports for processing by the next link layer logic (e.g., bit width conversion logic). After multiple link layer logic processes are completed, the data packet processed by the link layer is output to the target root port for transmission.

[0109] In this embodiment, the data of different root ports are buffered separately to prevent mutual blocking and interference. At the same time, the complex processing logic in the CXL multi-port controller (such as the sending end link layer processing logic such as link layer packing and bit width conversion, and the receiving end link layer processing logic such as link layer unpacking) can be time-division multiplexed for multiple ports, which is beneficial to saving resources and area.

[0110] In other embodiments, multiple caches can be eliminated, and data from multiple root ports can be stored together to simplify the design.

[0111] In other embodiments, the embodiments of this application are not limited to reusing various complex processing logics. Some complex processing logics can also be copied into multiple copies for use in the transmission data of multiple root ports to simplify the design.

[0112] The following is combined Figure 4 This section provides a detailed introduction to allocating independent caches across multiple ports. Figure 4 This is a diagram illustrating the allocation of independent caches across multiple ports, as shown below. Figure 4As shown, the independent cache of each root port can be flexibly called according to the actual usage of the root port to reduce area waste. This is achieved through the corresponding register group and the control logic of multiple preset read and write pointers.

[0113] Specifically, after system initialization is complete, the port configuration information is read (e.g., 16 physical channels are divided into 3 physical channel groups x8, x4, x4, or into 4 physical channel groups x4, x4, x4, x4, etc.), the corresponding read / write pointer control logic is selected, and the register group is divided. For example, there are 4 register groups corresponding to the 4 root port buffers. The buffer of one root port can be implemented by one register group. Then, the read / write pointer control logic is used to write or read different CXL messages into or out of the corresponding root port register group.

[0114] The mapping between root ports and register groups corresponding to the write pointer control logic mapping and the read instruction control logic mapping is configured by the port configuration information, configuring the register groups corresponding to different root ports. Through the write pointer control logic mapping, CXL packets can be written into the register groups corresponding to the buffers of different root ports. When a time-division multiplexing signal is received indicating the target root port activated in the current cycle, the read pointer control logic mapping can be used to obtain the CXL packets buffered in the register group corresponding to the target root port. After processing by the link layer logic, the corresponding target root port is selected for transmission. When resetting a specific port after data transmission is completed, the read and write pointers of that port can be reset directly, thus not affecting the data paths of other ports.

[0115] Correspondingly, the CXL multiport controller is also used to receive data packets transmitted by each root port in the receiving direction, and when the time division multiplexing signal of the current clock cycle indicates that the accumulated data packets transmitted by the activated target root port have reached the preset data bit width, convert the data packets into CXL messages, and upload the CXL messages to the CXL host bridging module in the next active clock cycle of the target root port.

[0116] The receiving direction refers to the flow of data from the CXL device to the processor.

[0117] In an optional implementation, the CXL multiport controller, in the receiving direction, determines the target root port activated in the current clock cycle based on the time-division multiplexing signal of the current clock cycle. When the data packets buffered in the buffer corresponding to the target root port reach a preset data bit width, the data packets are retrieved from the buffer corresponding to the target root port, and the data packets are unpacked into corresponding CXL messages through the link layer unpacking logic, and temporarily stored in the buffer corresponding to the target root port. The unpacked CXL messages in the buffer of a root port are sent to the CXL host bridging module in the next active clock cycle.

[0118] Figure 5 This is a schematic diagram of the CXL multiport controller's data processing in the receiving direction, as shown below. Figure 5 As shown, taking four root ports (RP0, RP1, RP2, RP3) as an example, after receiving the CXL data packets (Flit) from each root port, they are temporarily stored in their respective independent buffers, such as root port 0 buffer, root port 1 buffer, root port 2 buffer, and root port 3 buffer. Since the bit width [RPi_Width-1:0] (i takes the value 0, 1, 2, 3) of the CXL data packets (Flit) reported by each root port may be different, which is related to the corresponding channel width, the buffer needs to be converted in terms of bit width. Here, [RPi_Width-1:0] represents a data with an RPi_Width bit width, with the most significant bit index being RPi_Width-1 and the least significant bit index being 0. It contains all bit indices from RPi_Width-1 to 0, for a total of RPi_Width bits.

[0119] In this context, the data path of the link layer takes the maximum Flit bit width as [DL_Width-1:0], where [DL_Width-1:0] represents a data with a DL_Width bit width, the most significant bit index is DL_Width-1, and the least significant bit index is 0. It contains all bit indices from DL_Width-1 to 0, for a total of DL_Width bits. Furthermore, when the data packet buffered in the buffer corresponding to the target root port conforms to the link layer data bit width, the corresponding CXL data packet (Flit) can be retrieved and sent to the receiving end link layer processing logic (including receiving end link layer processing logic 51 and receiving end link layer processing logic 52). The receiving end link layer processing logic 51 can be a link layer unpacking logic that unpacks the corresponding CXL data packet into the corresponding CXL transaction layer message format, and then, according to the active target root port indicated by the time-division multiplexing signal, temporarily stores the CXL message in the receiving end buffer (Rx) of the corresponding root port. In the buffer), specifically the receiver link layer register corresponding to the receiver buffer; after unpacking, the CXL message can be processed by the receiver link layer processing logic 52 in the next active clock cycle of the corresponding root port, and then the CXL message buffered on that port can be selected and sent to the CXL host bridging module.

[0120] Furthermore, the CXL host bridging module is also used to receive CXL messages uploaded by the CXL multiport controller in the receiving direction and report them to the processor.

[0121] On the receiving side, the CXL host bridging module can convert the received CXL messages into the format required by the upstream (such as a processor) and report them.

[0122] Furthermore, in this embodiment, for the control path, independent control logic can be added to each root port, so that each root port can independently perform link control behaviors such as retransmission, link initialization, and letter of credit forced response; wherein, the link control uses control data packets (Flit) as carriers and shares the same data path with CXL Flit, so it is still necessary to select the corresponding root port through time-division multiplexing signals, generate the corresponding control Flit and send it to the root port for processing.

[0123] As can be seen, the CXL host controller provided in this application embodiment includes a CXL host bridging module and a CXL multiport controller; the physical link connecting the CXL device to the CXL multiport controller is shared by multiple root ports managed by the CXL multiport controller, and each root port is used to connect to the corresponding CXL device; and the multiple root ports are activated in turn according to a time-division multiplexing mechanism to take turns using the physical link for data transmission, wherein the time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle; the CXL host bridging module is used to receive processor messages from the processor in the transmitting direction, convert the processor messages into CXL messages, and transmit the CXL messages to the CXL multiport controller; the CXL multiport controller is used to receive CXL messages from the CXL host bridging module in the transmitting direction, and based on the time-division multiplexing signal of the current clock cycle indicating the activated target root port, transmit the data packets corresponding to the CXL messages to the target root port, so that the data packets are transmitted to the corresponding CXL device through the target root port. In other words, under the condition of using a single CXL host bridging module, multiple root ports can be extended by time-division multiplexing the physical link of the CXL multi-port controller. Each root port can independently connect to CXL devices for data transmission. Therefore, the CXL host controller provided in this application can realize multi-port expansion of the CXL host controller, providing higher compatibility and flexibility for the expansion of CXL networks and memory devices. At the same time, compared with the method of directly using multiple CXL controllers to realize root port expansion, it can save resources and area.

[0124] In a further optional implementation, based on the CXL host controller provided in the embodiments of this application, the embodiments of this application also provide a data transmission method applied to the CXL host controller. In an optional implementation, Figure 6 This is an optional flowchart of the data transmission method provided in an embodiment of this application. (Refer to...) Figure 6 The data transmission method may include the following steps.

[0125] Step S601: Receive a processor message from the processor;

[0126] Step S602: Convert the processor message into a CXL message;

[0127] Step S603: Based on the time division multiplexing signal indication of the current clock cycle, the target root port is activated, and the data packet corresponding to the CXL message is transmitted to the target root port so that the data packet is transmitted to the corresponding CXL device through the target root port;

[0128] The multiple root ports share the physical link between the CXL host controller and the CXL device. The multiple root ports are activated in turn according to the time-division multiplexing mechanism so as to take turns using the physical link for data transmission. The time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle.

[0129] In an optional implementation, the data transmission method further includes:

[0130] Receive data packets transmitted from each root port;

[0131] When the time-division multiplexing signal of the current clock cycle indicates that the accumulated data packets transmitted by the active target root port have reached the preset data bit width, the data packets are converted into CXL messages, and the CXL messages are uploaded to the processor in the next active clock cycle of the target root port.

[0132] It should be noted that the optional and extended implementations of the data transmission method for the CXL host controller provided in this application embodiment can be referred to in conjunction with the descriptions in the corresponding sections above, and will not be elaborated here.

[0133] In a further optional implementation, this application embodiment also provides a computer, including: a processor; a CXL host controller, the CXL host controller being as described in the foregoing embodiments; and CXL devices; wherein the CXL devices are connected to the root port of the CXL host controller, or connected to the root port of the CXL host controller via a CXL connector, and one root port is connected to multiple CXL devices via a CXL connector.

[0134] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0135] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A CXL host controller, characterized in that, include: The CXL host bridging module and the CXL multi-port controller; the CXL multi-port controller connects to the physical link of the CXL device, and multiple root ports managed by the CXL multi-port controller are shared, each root port is used to connect to the corresponding CXL device; and the multiple root ports are activated in turn according to the time-division multiplexing mechanism to take turns using the physical link for data transmission, wherein the time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle; The CXL host bridging module is used to receive processor messages from the processor in the sending direction, convert the processor messages into CXL messages, and transmit the CXL messages to the CXL multiport controller. The CXL multiport controller is used to receive CXL messages from the CXL host bridging module in the transmitting direction, indicate the active target root port based on the time division multiplexing signal of the current clock cycle, and transmit the data packet corresponding to the CXL message to the target root port so that the data packet can be transmitted to the corresponding CXL device through the target root port. The CXL host bridging module is also used to receive CXL messages uploaded by the CXL multiport controller in the receiving direction and report them to the processor. The CXL multiport controller is also used to receive data packets transmitted by each root port in the receiving direction, and when the time division multiplexing signal of the current clock cycle indicates that the accumulated data packets transmitted by the activated target root port have reached the preset data bit width, convert the data packets into CXL messages, and upload the CXL messages to the CXL host bridging module in the next active clock cycle of the target root port.

2. The CXL host controller according to claim 1, characterized in that, The time-division multiplexed signal includes: The number of flag bits corresponding to the number of the plurality of root ports, wherein one flag bit corresponds to one root port, the flag bits include a valid flag bit and an invalid flag bit, the root port corresponding to the valid flag bit is in an active state, and the time division multiplexed signal in one clock cycle has only one valid flag bit.

3. The CXL host controller according to claim 2, characterized in that, The physical link consists of multiple physical channels, which are divided into multiple physical channel groups. Each root port is assigned a corresponding physical channel group and data is transmitted through the physical channel group.

4. The CXL host controller according to claim 3, characterized in that, In a round-robin activation process of multiple root ports, the number of consecutive activation clock cycles corresponding to a root port is related to the number of physical channels in the physical channel group corresponding to the root port.

5. The CXL host controller according to claim 4, characterized in that, During the round-robin activation of multiple root ports, the number of consecutive activation clock cycles corresponding to each root port is proportionally allocated according to the number of physical channels corresponding to each root port.

6. The CXL host controller according to any one of claims 1-5, characterized in that, Also includes: The time-division multiplexing signal generation module is used to generate a time-division multiplexed signal for each clock cycle and transmit it to the CXL multiport controller to indicate the root port that is active for each clock cycle.

7. The CXL host controller according to claim 6, characterized in that, Also includes: The cache corresponding to each root port is used to temporarily store the data transmitted through each root port; The CXL multi-port controller is specifically used for: In the transmission direction, the time-division multiplexing signal based on the current clock cycle indicates the active target root port. The transmitting link layer processing logic processes the packets in the buffer of the target root port until multiple progressive transmitting link layer processing logics are completed, resulting in the data packet corresponding to the CXL packet to be transmitted to the target root port. Specifically, one transmitting link layer processing logic is performed in one active clock cycle of a root port. The result of the previous transmitting link layer processing logic is temporarily stored in the buffer of the root port and processed by the next transmitting link layer processing logic in the next active clock cycle of the root port. In the receiving direction, the target root port activated in the current clock cycle is determined based on the time-division multiplexing signal of the current clock cycle. When the data packets buffered in the buffer corresponding to the target root port reach the preset data bit width, the data packets are retrieved from the buffer corresponding to the target root port, and the data packets are unpacked into corresponding CXL messages through the link layer unpacking logic and temporarily stored in the buffer corresponding to the target root port. Among them, the unpacked CXL messages in the buffer of a root port are sent to the CXL host bridging module in the next active clock cycle.

8. The CXL host controller according to claim 1, characterized in that, The CXL host bridging module is also used for: After converting the processor message into a CXL message, the port ID of the root port for transmitting the CXL message is determined according to the mapping relationship between the message address and the routing information. The routing information includes: routing method, number of ports, and port ID. The port ID is carried in the CXL message, wherein the CXL message transmitted to the CXL multi-port controller is a CXL message carrying the port ID.

9. The CXL host controller according to claim 8, characterized in that, The CXL host bridging module is also used for: Before determining the port ID, it is determined whether the packet address is within the routing address range of the multiple root ports. If so, the step of determining the port ID of the root port transmitting the CXL packet based on the mapping relationship between the packet address and the routing information is executed. If not, the converted CXL packet is discarded.

10. A data transmission method, characterized in that, Applied to the CXL host controller, including: Receive processor messages from the processor; Convert the processor message to a CXL message; Based on the time-division multiplexing signal indicating the active target root port of the current clock cycle, the data packet corresponding to the CXL message is transmitted to the target root port so that the data packet can be transmitted to the corresponding CXL device through the target root port; Multiple root ports share the physical link between the CXL host controller and the CXL device. The multiple root ports are activated in turn according to the time-division multiplexing mechanism so as to take turns using the physical link for data transmission. The time-division multiplexing signal of each clock cycle indicates the root port activated in each clock cycle. The method further includes: Receive data packets transmitted from each root port; When the time-division multiplexing signal of the current clock cycle indicates that the accumulated data packets transmitted by the active target root port have reached the preset data bit width, the data packets are converted into CXL messages, and the CXL messages are uploaded to the processor in the next active clock cycle of the target root port.

11. A computer, characterized in that, include; processor; CXL host controller, the CXL host controller as described in any one of claims 1-9; CXL equipment; The CXL device is connected to the root port of the CXL host controller, or to the root port of the CXL host controller via a CXL connector. One root port can be connected to multiple CXL devices via a CXL connector.

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