Double-loop chip structure, set communication method and device, equipment and storage medium

Abstract

The embodiment of the invention provides a double-loop chip structure, a set communication method and device, equipment and a storage medium, and relates to the technical field of chip communication. The double-loop chip structure comprises a plurality of chip sets, each chip set comprises a first chip and a second chip, and the corresponding first chip and second chip are in direct communication connection; the first chips in different chip groups are sequentially connected according to the sequence of the chip groups to form a first loop; and the second chips in different chip groups are sequentially connected according to the sequence of the chip groups to form a second loop. The first chip and the second chip of each chipset in the plurality of chipsets can realize information interaction between the chips in the chipset through direct communication connection, loop transfer is not needed, and efficient interaction can be realized through a direct link. The first loop and the second loop are mutually independent and parallel, so that the data blocking probability of cross-group communication can be reduced. The intra-group direct connection + cross-group double-ring parallel structure can significantly improve the execution efficiency of set communication.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip communication technical field, and particularly relates to a double-loop chip structure, a collection communication method, device and storage medium. BACKGROUND

[0002] With the rapid development of large-scale model training technology, models in the field of artificial intelligence are becoming increasingly complex. However, the growth of model complexity makes collection communication a key bottleneck for improving training efficiency. Collection communication overhead, especially the overhead brought by AllReduce operation, is still the main performance constraint factor. Even in an environment equipped with high-bandwidth interconnection, collection communication can still account for about 10% to 50% of the total execution time.

[0003] In related technologies, a processor based on Chiplet packaging is used to improve the computing efficiency of collection communication algorithms. Among them, the processor based on Chiplet packaging introduces an explicit die-to-die direct interconnection between two computing dies in a chip to provide higher bandwidth. However, the overall execution efficiency of collection communication is still poor. SUMMARY

[0004] The main purpose of the embodiments of the present application is to provide a double-loop chip structure, a collection communication method, device and storage medium to improve the execution efficiency of collection communication.

[0005] To achieve the above purpose, a first aspect of the embodiments of the present application provides a double-loop chip structure, comprising: a plurality of chip groups, each of the chip groups comprising a first chip and a second chip, and a direct communication connection existing between the corresponding first chip and the second chip; the first chips in different chip groups are connected in turn according to the order of the chip groups to form a first loop; the second chips in different chip groups are connected in turn according to the order of the chip groups to form a second loop.

[0006] To achieve the above purpose, a second aspect of the embodiments of the present application provides a collection communication method, comprising: obtaining a preset number of initial data components contained in all chips in a double-loop chip structure, the initial data components corresponding to including component identifiers, the component identifiers being grouped into target identifier groups two by two, and the double-loop chip structure being the double-loop chip structure of the first aspect; determining a first iteration number according to the number of chips, and determining the target identifier group corresponding to the chip group at each iteration, wherein the target identifier group in the same chip group is different at each iteration in the continuous iteration process, and the chip group corresponding to the same target identifier group is updated along the order of the chip groups. iterating based on the first iteration number, at each iteration, alternately transmitting two initial data components corresponding to the target identification group based on the corresponding direct communication connection between two chips in the same chip group, and / or transmitting the two initial data components corresponding to the target identification group based on the first loop and the second loop respectively between the chip groups; until the iteration ends, aggregating the initial data components corresponding to the same component identification to obtain a preset number of initial aggregated data, and each chip obtains one initial aggregated data.

[0007] In an embodiment, the alternately transmitting the two initial data components corresponding to the target identification group based on the corresponding direct communication connection between two chips in the same chip group comprises: allocating two component identifications in the target identification group to the first chip and the second chip respectively in sequence; swapping and transmitting the initial data components in the first chip consistent with the component identifications of the second chip and the initial data components in the second chip consistent with the component identifications of the first chip through the direct communication connection.

[0008] In an embodiment, the transmitting the two initial data components corresponding to the target identification group based on the first loop and the second loop respectively between the chip groups comprises: In the iteration after the second time, selecting each chip group as a current chip group one by one, taking the chip group corresponding to the target identification group in the previous iteration process as a target chip group in the current iteration process, and determining the correspondence between two chips in the target chip group and the component identifications in the target identification group; taking at least one initial data component corresponding to two component identifications of the target identification group in the previous iteration process in two chips of the current chip group as a target data component sequence; transmitting the target data component sequence to the corresponding chip of the target chip group through the first loop or the second loop based on the correspondence.

[0009] In an embodiment, the method further comprises: determining a second iteration number according to the number of chips; iterating based on the second iteration number, at each iteration, for two chips in the same chip group, determining the initial aggregated data missing from one chip relative to the other chip as first direct transmission aggregated data, alternately transmitting the first direct transmission aggregated data based on the corresponding direct communication connection, for two adjacent chip groups, based on the direction of the chip group, determining the initial aggregated data missing from one chip relative to the other chip as inter-group aggregated data, transmitting the inter-group aggregated data based on the direction of the first loop and the second loop respectively; after the iteration, for two chips in the same chip group, determining the initial aggregated data missing from one chip relative to the other chip as second direct transmission aggregated data, alternately transmitting the first direct transmission aggregated data based on the corresponding direct communication connection, until each chip contains all the initial aggregated data.

[0010] To achieve the above object, a third aspect of the embodiments of the present application provides a set communication method, comprising: determining a source chip from all chips contained in a double-loop chip structure, dividing a preset number of initial block data in the source chip equally to obtain a first data group and a second data group, the number of chips is not less than the preset number, and the double-loop chip structure is the double-loop chip structure of the first aspect; transmitting the second data group to another chip corresponding to the source chip through the corresponding direct communication connection; broadcasting and transmitting the first data group and the second data group through the first loop, the second loop and each direct communication connection until each chip contains all the initial block data.

[0011] In an embodiment, the broadcasting and transmitting the first data group and the second data group through the first loop, the second loop and each direct communication connection until each chip contains all the initial block data comprises: determining a third iteration number according to the number of chips and the preset number; iterating based on the third iteration number, at each iteration, for two chips in the same chip group, determining one initial block data missing from one chip relative to the other chip as third direct transmission aggregated data, alternately transmitting the third direct transmission aggregated data based on the corresponding direct communication connection, for two adjacent chip groups, based on the direction of the chip group, determining one initial block data missing from one chip relative to the other chip as inter-group block data, transmitting the inter-group block data based on the direction of the first loop and the second loop respectively. After the iteration is completed, for the two chips in the same chipset, the initial aggregated data that is missing from the chip relative to the other chip is respectively determined as the fourth direct transmission aggregated data, and the fourth direct transmission aggregated data is transmitted alternately based on the corresponding direct communication connection until all the initial block data are contained in each chip.

[0012] To achieve the above objectives, a fourth aspect of an embodiment of the present application provides a collective communication device, including: A data acquisition module is configured to acquire a preset number of initial data components contained in all chips in a dual-loop chip structure, wherein the initial data components include component identifiers, and the component identifiers are grouped into target identifier groups in pairs. The dual-loop chip structure is the dual-loop chip structure described in the first aspect. a communication preparation module configured to determine a first iteration number based on the number of chips, and determine the target identification group corresponding to the chipset in each iteration; wherein, during successive iterations, the target identification group in the same chipset is different in each iteration, and the chipsets corresponding to the same target identification group are updated in the order of the chipsets; a data transmission module configured to iterate based on the first number of iterations, and in each iteration, alternately transmit the two initial data components corresponding to the target identification group to two chips in the same chipset based on the corresponding direct communication connection, and / or transmit the two initial data components corresponding to the target identification group between the chipsets based on the first loop and the second loop, respectively; Aggregation module: used for aggregating the initial data components corresponding to the same component identifier until the iteration ends to obtain the preset number of initial aggregated data, and each chip obtains one piece of the initial aggregated data.

[0013] To achieve the above objectives, a fifth aspect of an embodiment of the present application provides a collective communication device, including: An initial data allocation module is configured to determine a source chip from all chips included in a dual-loop chip structure, and evenly divide a preset number of initial block data in the source chip to obtain a first data group and a second data group, wherein the number of the chips is not less than the preset number, and the dual-loop chip structure is the dual-loop chip structure described in the first aspect; Intra-group transmission module: used for transmitting the second data group to another chip corresponding to the source chip through a corresponding direct communication connection; A broadcast transmission module is configured to broadcast the first data group and the second data group on the first loop, the second loop, and each of the direct communication connections until each of the chips contains all of the initial block data.

[0014] To achieve the above object, a sixth aspect of the embodiments of the present application provides an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor implements the method of the second aspect or the third aspect when executing the computer program.

[0015] To achieve the above object, a seventh aspect of the embodiments of the present application provides a storage medium, which is a storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the method of the second aspect or the third aspect.

[0016] The dual-loop chip structure, the set communication method, the device and the storage medium provided by the embodiments of the present application, wherein the dual-loop chip structure comprises: a plurality of chip groups, each chip group comprising a first chip and a second chip, and a direct communication connection between the corresponding first chip and the second chip; the first chips in different chip groups are connected in turn according to the order of the chip groups, constituting a first loop; and the second chips in different chip groups are connected in turn according to the order of the chip groups, constituting a second loop. The dual-loop chip structure provided by the embodiments of the present application is applied to a scene of set communication, in which data needs to be broadcast, converged or synchronized between multiple chips, etc. The first chip and the second chip of each chip group in the multiple chip groups can realize information interaction between chips in the group through the direct communication connection, without passing through the loop transfer, and the direct link can realize efficient interaction, reducing the delay and path loss of intra-group communication. At the same time, the first loop and the second loop constituted by the first chips and the second chips of different chip groups are independent and parallel, which can reduce the data blocking probability of cross-group communication, and make the communication path more flexible. The structure of "intra-group direct connection + cross-group dual-loop parallel" can shorten the communication path and improve the data transmission efficiency, thereby significantly improving the execution efficiency of set communication. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a connection diagram of a Chiplet packaged processor in the related art.

[0018] Figure 2 is a schematic diagram of a dual-loop chip structure provided by the embodiments of the present application.

[0019] Figure 3 is a flowchart of a set communication method provided by the embodiments of the present application.

[0020] Figure 4 is a data flow diagram of the Reduce Scatter function provided by the embodiments of the present application.

[0021] Figure 5is a schematic diagram of a target identification group provided by an embodiment of the present application.

[0022] Figure 6 is a flowchart of a process of alternately transmitting two initial data components corresponding to a target identification group based on a corresponding direct communication connection between two chips in a chip set provided by an embodiment of the present application.

[0023] Figure 7 is a detailed data transmission schematic diagram of Figure 4

[0024] Figure 8 is a flowchart of a process of transmitting two initial data components corresponding to a target identification group based on a first loop and a second loop between chip sets respectively provided by an embodiment of the present application.

[0025] Figure 9 is a flowchart of an All Gather function provided by an embodiment of the present application.

[0026] Figure 10 is a principle schematic diagram of an All Gather function provided by an embodiment of the present application.

[0027] Figure 11 is still another optional flowchart of a set communication method provided by an embodiment of the present application.

[0028] Figures 12a to 12c is a principle schematic diagram of a Broadcast function provided by an embodiment of the present application.

[0029] Figure 13 is a flowchart of broadcasting transmission of a first data group and a second data group on a first loop, a second loop and each direct communication connection until each chip contains all initial block data provided by an embodiment of the present application.

[0030] Figure 14 is a structure block diagram of a set communication device provided by still another embodiment of the present application.

[0031] Figure 15 is still another structure block diagram of a set communication device provided by still another embodiment of the present application.

[0032] Figure 16 is a hardware structure schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0034] ​It should be noted that although the functional modules are divided in the device schematic diagram, the logical order is shown in the flowchart, but in some cases, the steps shown or described can be performed in a manner different from the module division in the device or the order in the flowchart.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the specification is for describing the embodiments of the application only and not intended to limit the application.

[0036] In the field of parallel computing, especially in high performance computing (HPC) and large-scale distributed training, collective communication (CC) is a key communication mode, which refers to a global communication operation in which all processes in a process group (such as a group of chips or CPU cores) participate. Unlike point-to-point communication between two processes, collective communication involves coordination and data exchange among a group of processes.

[0037] To simplify parallel programming and efficiently utilize underlying hardware, these common and repetitive global communication patterns are abstracted into a set of standard interfaces, namely collective communication primitives (CCP). These primitives are the basic modules for building parallel algorithms, implemented by specialized communication libraries (such as MPI, NCCL, CCL), and optimized for specific hardware and network topology to achieve high bandwidth and low latency.

[0038] Here are some of the most common collective communication primitives and their functions: Reduce Scatter (Scatter-Gather) Function: First, perform a reduction operation (such as summation) on the data of all processes, then divide the reduced results into blocks, and distribute them to all processes. Each process only receives a part of the final result.

[0039] All Gather (All-Gather) Function: Each process in the communication group sends its own data to all other processes. After the operation is completed, each process has a complete data set composed of the original data of all processes in the group.

[0040] Broadcast (Broadcast) Function: A designated "root" process (root) sends its data (broadcast) to all other processes in the process group. After the operation is completed, all processes in the group have the same copy of the root's original data.

[0041] All Reduce (global reduce) function: It collects data from all processes and performs a reduce operation, then broadcasts the final reduce result back to all processes. After the operation is completed, all processes in the group have the same final result.

[0042] With the rapid development of large-scale model training technology, AI models are becoming increasingly complex. However, this growth in model complexity has made collective communication a key bottleneck in improving training efficiency. Collective communication overhead, particularly the overhead of AllReduce operations, remains a major performance constraint. Even in environments equipped with high-bandwidth interconnects, collective communication can still account for approximately 10% to 50% of total execution time.

[0043] In related technologies, chiplet-based processors are used to improve the computational efficiency of collective communication algorithms. In particular, chiplet-based processors introduce explicit die-to-die direct interconnection between two computing dies within a chip to provide higher bandwidth. Figure 1 , Figure 1 This is a connection diagram of a chiplet-packaged processor in related technology. As can be seen from the figure, the processor uses chiplet packaging technology to package two NPU (Neural Network Processing Unit) chips, such as NPU0 and NPU1 in the figure, on a single baseboard. A high-speed communication link (Super Input / Output, SIO) connects the two chips, and both chips can exchange data with the system-level package via an HCCS link. Although this connection method can provide higher bandwidth and improve the communication efficiency of distributed systems to a certain extent, when it comes to collective communication, the potential of the communication link is underdeveloped, resulting in poor overall execution efficiency.

[0044] Based on this, the embodiments of the present application provide a dual-loop chip structure, a collective communication method, an apparatus, a device, and a storage medium, wherein the dual-loop chip structure is applied to scenarios where collective communication data needs to be broadcast, aggregated, or synchronized between multiple chips. The first chip and the second chip of each chipset in multiple chipsets can realize information interaction between chips in the group through a direct communication connection. Without the need for loop transit, the direct link can achieve efficient interaction and reduce the delay and path loss of intra-group communication. At the same time, the first loop and the second loop formed by the first chip and the second chip of different chipsets are independent of each other and parallel, which can reduce the probability of data blocking in cross-group communication and make the communication path more flexible. This "intra-group direct connection + cross-group dual-loop parallel" structure can shorten the communication path and improve data transmission efficiency, thereby significantly improving the execution efficiency of collective communication.

[0045] The embodiment of the application provides a dual-loop chip structure, a set communication method, device and equipment, and a storage medium. The set communication method is described first.

[0046] The set communication method provided by the embodiment of the application relates to the technical field of chip communication. The set communication method provided by the embodiment of the application can be applied to a terminal, can be applied to a server end, and can also be a computer program running in the terminal or the server end. For example, the computer program can be a native program or a software module in an operating system; can be a native application (Application, APP), that is, a program that needs to be installed in an operating system to run, such as a client supporting dual-ring set communication, that is, a program that can run only by being downloaded into a browser environment; and can also be an applet that can be embedded into any APP. In summary, the computer program can be any form of application program, module or plug-in. The terminal communicates with the server through a network. The set communication method can be executed by the terminal or the server, or cooperatively executed by the terminal and the server.

[0047] In some embodiments, the terminal can be a smart phone, a tablet computer, a notebook computer, a desktop computer or a smart watch, etc. The server can be a stand-alone server, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as big data and artificial intelligence platforms; or a service node in a blockchain system, the service nodes in the blockchain system form a peer-to-peer (Peer To Peer, P2P) network, and the P2P protocol is an application layer protocol running on the transmission control protocol (Transmission Control Protocol, TCP) protocol. The terminal and the server can be connected through a communication connection mode such as Bluetooth, universal serial bus (Universal Serial Bus, USB) or network, which is not limited in the embodiment.

[0048] The application is operable in a multitude of computing system environments or configurations. For example, a personal computer, a server computer, a handheld or laptop device, a tablet device, a multiprocessor system, a microprocessor-based system, a set top box, programmable consumer electronics, network PC, minicomputer, mainframe computer, distributed computing environments that include any of the above systems or devices, and the like. The application can be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, and the like, that perform particular tasks or implement particular abstract data types. The application can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote computer storage media including memory storage devices.

[0049] Firstly, a double-loop chip structure provided by an embodiment of the application is described.

[0050] Referring to Figure 2 , Figure 2 is a schematic diagram of the double-loop chip structure provided by an embodiment of the application. Figure 2 Eight chips are taken as an example in the figure, and the chips are numbered as 0-8. The chips form four chip groups, for example, chip 0 and chip 1 form chip group 1, chip 2 and chip 3 form chip group 2, chip 4 and chip 5 form chip group 3, and chip 6 and chip 7 form chip group 4.

[0051] Specifically, each chip group includes a first chip and a second chip, and the corresponding first chip and second chip are directly connected in communication. Referring to Figure 2 The chips numbered even can be taken as the first chips, and the chips numbered odd can be taken as the second chips. Therefore, in chip group 1, the first chip is chip 0, and the second chip is chip 1. Chip 0 and chip 1 are directly connected in communication, which is represented by a high-speed communication link SIO. In the figure, the direct communication connection between the first chip and the second chip is represented by a double-arrow dashed line.

[0052] Further, the first chips in different chip groups are sequentially connected in the order of the chip groups to form a first loop, and the second chips in different chip groups are sequentially connected in the order of the chip groups to form a second loop. Referring to Figure 2That is, the four first chips corresponding to chipsets 1 through 4 form a first loop, and the four second chips corresponding to chipsets 1 through 4 form a second loop. The first loop is represented as: chip 0 -> chip 2 -> chip 4 -> chip 6 -> chip 0, and the second loop is represented as: chip 1 -> chip 3 -> chip 5 -> chip 7 -> chip 1. Since chip 0 in chipset 1 points to chip 2 in chipset 2, and chip 1 points to chip 3 in chipset 2, chipset 1 can be considered to point to chipset 2. The order between the chipsets is: chipset 1 -> chipset 2 -> chipset 3 -> chipset 4 -> chipset 1. Therefore, the directions of the first and second loops can be considered to be connected in the order of the chipsets.

[0053] It is understandable that the above chipset order is only for illustration, and it may also be the reverse order of chipset 4 -> chipset 3 -> chipset 2 -> chipset 1 -> chipset 4. This embodiment does not limit this, and it can be determined according to actual conditions.

[0054] Depend on Figure 2 It can be seen from the dual-loop chip structure that the first chip and the second chip of each chipset in the multiple chipsets of the dual-loop chip structure can realize information interaction between chips in the group through direct communication connection. There is no need to go through the loop transit. The direct link can achieve efficient interaction and reduce the delay and path loss of intra-group communication. At the same time, the first loop and the second loop composed of the first chip and the second chip of different chipsets are independent of each other and parallel, which can reduce the probability of data blocking in cross-group communication and make the communication path more flexible. Specifically, when the dual-loop chip structure is applied to the collective communication algorithm, the first loop and the second loop are responsible for communication between chipsets and can transmit data simultaneously, while the direct communication connection is responsible for synchronizing data between the two loops and processing high-speed communication between the two chips in the chipset. Through this dual-loop chip structure, higher bandwidth utilization and scalability for large-scale AI model distributed training tasks can be achieved.

[0055] The following combination Figure 2 The dual-loop chip structure describes the data stream processing logic of the collective communication method in the dual-loop chip structure in the embodiment of the present application. Here, the Broadcast function and the All Reduce function are introduced for collective communication respectively.

[0056] Figure 3 This is an optional flowchart of the collective communication method provided in an embodiment of the present application. Figure 3 The method in is the implementation logic of the All Reduce function, which may include but is not limited to steps 310 to 340. It can also be understood that this embodiment is for Figure 3The order of steps 310 to 340 is not specifically limited, and the order of steps can be adjusted, or some steps can be reduced or added, according to actual needs.

[0057] Step 310: Obtain a preset number of initial data components contained in all chips in the double-loop chip structure.

[0058] In an embodiment, the All Reduce function is decomposed into a Reduce Scatter function and an All Gather function. The Reduce Scatter function is used to perform a reduction operation (such as summation) on the data of all chips, and then divide the reduced result into blocks and distribute them to all chips. Finally, each chip only receives a part of the final result. Therefore, the data before the reduction operation in each chip is referred to as an initial data component, and each chip contains a preset number of initial data components. The preset number can be set according to the actual scene, but the preset number needs to be less than or equal to the number of chips.

[0059] In an embodiment, the corresponding collective communication scene of distributed deep learning training includes data parallelism or model parallelism.

[0060] In the data parallelism scene, model parameters are completely copied to each chip, but training data is divided into different batches, each chip processes a different data subset, and calculates the corresponding local gradient. Assuming that the model includes multiple network layers, different chips will calculate the gradient component of the corresponding weight of each network layer using their own data subset. For example, the model has 8 layers, and there are 8 chips to process the corresponding network layers, and the network layers are A, B, …, H. At this time, chip 0 processes the 0th data batch and calculates the local gradient of each layer as A0, B0, …, H0. Similarly, chip 1 processes the 1st data batch and calculates the local gradient of each layer as A1, B1, …, H1, …, and chip 7 processes the 0th data batch and calculates the local gradient of each layer as A7, B7, …, H7. Here, the local gradient in each chip is regarded as the initial data component of the chip, and is distinguished within the same chip by a component identifier. The component identifier here can be an identifier such as A, B. Next, the Reduce Scatter function is used to sum the components of the initial data components corresponding to the same component identifier on different chips, such as adding all chip A components: A = A0 + A1 + … + A7. Then, the aggregated A is distributed to chip 0, B is distributed to chip 1, and so on. Chip 0 obtains the total gradient A of the 0th layer weight of all batches for updating the 0th layer parameter, chip 1 obtains the total gradient B of the 1st layer weight of all batches for updating the 1st layer parameter, and so on for the last chip.

[0061] In the model parallel scenario, it is assumed that each component identifier (A, B,..., H) represents a different parameter block of the model, A can be the weight matrix of the 0th layer of the neural network, B can be the weight matrix of the 1st layer of the neural network, and so on. At this time, chip 0 stores A0, B0,..., H0, such as A0 is the 0th row of matrix A, chip 1 stores A1, B1,..., H1, such as A1 is the 1st row of matrix A, and so on. The initial data components corresponding to the same component identifier are summed by using the Reduce Scatter function, and then the corresponding components are distributed, for example, A is distributed to chip 0, B is distributed to chip 1, and so on. Finally, chip 0 obtains the complete A for subsequent calculation or update, chip 1 obtains the complete B, and so on.

[0062] It can be understood that the above is only an illustration of the collective communication scenario, and does not represent a limitation on the details thereof.

[0063] In an embodiment, with reference to Figure 4 , Figure 4 is a data flow diagram of the Reduce Scatter function provided by the embodiment of the application. Here, 8 chips are taken as an example for illustration, and the chips are NPU0, NPU1, NPU2, NPU3, NPU4, NPU5, NPU6, and NPU7, wherein NPU0 and NPU1, NPU2 and NPU3, NPU4 and NPU5, and NPU6 and NPU7 respectively form four chip groups, and the order of the chip groups is: chip group 4 -> chip group 3 -> chip group 2 -> chip group 1 -> chip group 4. Correspondingly, the first loop can be represented as: NPU6 -> NPU4 -> NPU2 -> NPU0 -> NPU6, and the second loop can be represented as: NPU7 -> NPU5 -> NPU3 -> NPU1 -> NPU7. And each chip contains 8 initial data components A-H, NPU0 contains A0, B0, C0,..., H0, NPU1 contains A1, B1, C1,..., H1, and so on, and NPU7 contains A7, B7, C7,..., H7.

[0064] In an embodiment, the component identifiers are grouped into target identifier groups in pairs according to actual needs or in a random manner. With reference to Figure 5 , Figure 5 is a schematic diagram of the target identifier groups provided by the embodiment of the application. Figure 5 In the above, the component identifiers A-H are divided into four groups AB, CD, EF, and GH, and four target identifier groups are obtained, and the target identifier groups are distributed to different chip groups.

[0065] Step 320: Determine the first iteration number according to the number of chips, and determine the target identifier groups corresponding to the chip groups in each iteration.

[0066] In an embodiment, assuming the number of chips is n, the first iteration number is (n / 2), when n=8, the first iteration number is 4. In each iteration, each chip group needs to obtain the target identifier group currently assigned to it. Referring to Figure 5 , a total of 4 iterations, in the first iteration, chip group 1 corresponds to the target identifier group CD, chip group 2 corresponds to the target identifier group EF, chip group 3 corresponds to the target identifier group GH, and chip group 4 corresponds to the target identifier group AB, in the second iteration, chip group 1 corresponds to the target identifier group EF, chip group 2 corresponds to the target identifier group GH, chip group 3 corresponds to the target identifier group AB, and chip group 4 corresponds to the target identifier group CD, in the third iteration, chip group 1 corresponds to the target identifier group GH, chip group 2 corresponds to the target identifier group AB, chip group 3 corresponds to the target identifier group CD, and chip group 4 corresponds to the target identifier group EF, in the fourth iteration, chip group 1 corresponds to the target identifier group AB, chip group 2 corresponds to the target identifier group CD, chip group 3 corresponds to the target identifier group EF, and chip group 4 corresponds to the target identifier group GH. As can be seen, in the process of continuous iteration, the target identifier group in the same chip group is different in each iteration, for example, in the process of 4 iterations of chip group 1, the target identifier group is CD, GH, EF, and AB, respectively, and the chip group corresponding to the same target identifier group is updated along the order of the chip group, taking the target identifier group CD as an example, the update order is chip group 1, chip group 4, chip group 3, and chip group 2, and the order of the corresponding chip group is chip group 4->chip group 3->chip group 2->chip group 1->chip group 4 in a ring direction.

[0067] Step 330: iteration based on the first iteration number, in each iteration, for two chips in the same chip group, alternately transmit two initial data components corresponding to the target identifier group based on the corresponding direct communication connection, and / or, between chip groups, respectively transmit two initial data components corresponding to the target identifier group based on the first loop and the second loop.

[0068] In an embodiment, iteration is performed according to the first iteration number, in each iteration, for two chips in the same chip group, alternately transmit two initial data components corresponding to the target identifier group based on the corresponding direct communication connection, and / or, between chip groups, respectively transmit two initial data components corresponding to the target identifier group based on the first loop and the second loop. Specifically, in the first iteration, only the data transmission of the direct communication connection is performed, and in the subsequent iterations, the data transmission of the direct communication connection, the first loop, and the second loop is performed. It can be understood that if the transmission within the chip group and between the chip groups is performed simultaneously, the double-loop data transmission needs to be performed after the direct transmission link within the chip group is completed.

[0069] In an embodiment, the data transmission process of the direct communication connection is introduced first. Referring to Figure 6 , Figure 6 The flowchart provided by the embodiment of the present application for two chips in the same chip set to alternately transmit two initial data components corresponding to the target identification group based on the corresponding direct communication connection comprises the following steps: Step 610: Assign the two component identifications in the target identification group to the first chip and the second chip respectively in sequence.

[0070] In an embodiment, referring to Figure 4 and Figure 5 , for example, in the first iteration, the target identification group corresponding to the chip set 1 is CD, at this time, the component identification C is assigned to the first chip NPU0, and the component identification D is assigned to the second chip NPU1. The assignment here can be set according to actual conditions. NPU2 is assigned to the component identification E, NPU3 is assigned to the component identification F, NPU4 is assigned to the component identification G, NPU5 is assigned to the component identification H, NPU6 is assigned to the component identification A, and NPU7 is assigned to the component identification B. In the same way and sequence, the corresponding component identification is assigned in each iteration process.

[0071] Step 620: Exchange and transmit the initial data components with the same component identification in the first chip and the second chip and the initial data components with the same component identification in the second chip and the first chip through the direct communication connection.

[0072] In an embodiment, referring to Figure 7 , Figure 7 is a detailed data transmission schematic diagram of Figure 4 . In the figure, the direct communication connection is schematized by a dashed line, and the data transmission of the first loop and the second loop is schematized by a solid line. The data in the dashed line box corresponding to the chip is the data obtained through the direct communication connection during iteration, and the data in the thick solid line box is the related data obtained through the first loop or the second loop during iteration. Referring to Figure 4 and Figure 7 , in the first iteration process, only the data transmission of the direct communication connection occurs, Figure 4 , although the solid line loop data transmission is marked in the first iteration, at this time, in combination with Figure 7 , there is no related data transmission in the loop.

[0073] In an embodiment, for the data transmission of the direct communication connection, only the initial data components with the same component identification in the first chip and the second chip and the initial data components with the same component identification in the second chip and the first chip need to be exchanged and transmitted through the direct communication connection. Referring to Figure 7For the chip set 1, the component identifier of the first chip NPU0 is C, and the component identifier of the second chip NPU1 is D, so the initial data component consistent with the component identifier D of the second chip NPU1 in the first chip NPU0 is D0, and the initial data component consistent with the component identifier C of the first chip NPU0 in the second chip NPU1 is C0, therefore, the two can be exchanged and transmitted through the direct communication connection. At this time, after the first iteration, Figure 7 The NPU0 obtains C0 through the direct communication connection, and the NPU1 obtains D0 through the direct communication connection, all the initial data components contained in the NPU0 at this time are A0, B0, C0, C1, E0, F0, G0, and H0, and all the initial data components contained in the NPU1 at this time are A1, B1, D0, D1, E1, F1, G1, and H1. In this way, the direct transmission of the initial data components is performed once in each chip set.

[0074] The data exchange process of the first loop and the second loop between the chip sets is described below. Referring to Figure 8 , Figure 8 is a flowchart provided by the embodiment of the application for transmitting two initial data components corresponding to a target identifier group based on the first loop and the second loop between the chip sets, and specifically includes the following steps: Step 810: In the iteration after the second time, each chip set is selected as a current chip set one by one, the chip set corresponding to the target identifier group in the current iteration process in the previous iteration process is selected as a target chip set, and the correspondence between the two chips in the target chip set and the component identifiers in the target identifier group is determined.

[0075] In an embodiment, for the iteration after the second time, the direct communication connection data transmission in the chip set and the loop data transmission between the chip sets are required. At this time, in each iteration, each chip set is selected as a current chip set one by one, the chip set corresponding to the target identifier group in the current iteration process in the previous iteration process is selected as a target chip set, and the correspondence between the two chips in the target chip set and the component identifiers in the target identifier group is determined.

[0076] Referring to Figure 7In the second iteration, one chip group is selected as the current chip group in sequence of chip group 1 to chip group 4. Assuming that the current chip group is chip group 1, the target identification group in the previous iteration (i.e. the first iteration) is CD, and the chip group corresponding to the target identification group CD in the current iteration (i.e. the second iteration) is chip group 4, chip group 4 is taken as the target chip group of the current chip group, and the two chips in the target chip group are NPU6 and NPU7, wherein NPU6 corresponds to the component identification C in the target identification group CD, and NPU7 corresponds to the component identification D in the target identification group CD. By analogy, in each iteration process after the second iteration process, the correspondence between the current chip group, the target chip group and the component identification is determined in sequence.

[0077] Step 820: taking at least one initial data component corresponding to each of the two component identifications of the target identification group in the previous iteration process in the two chips of the current chip group as the target data component sequence.

[0078] In an embodiment, referring to Figure 7 , taking chip group 1 as the current chip group in the second iteration process, the two component identifications of the target identification group in the previous iteration process are component identification C and component identification D, at this time, component identification C corresponds to two initial data components C0 and C1 in NPU0 of chip group 1, so C0 and C1 are taken as the target data component sequence of NPU0, and correspondingly, component identification D corresponds to two initial data components D0 and D1 in NPU1 of chip group 1, so D0 and D1 are taken as the target data component sequence of NPU1. It can be understood that with the increase of the number of iterations, the number of initial data components contained in the related target data component sequence also increases.

[0079] Step 830: based on the correspondence, transmitting the target data component sequence to the corresponding chip of the target chip group through the first loop or the second loop.

[0080] In an embodiment, referring to Figure 7 , NPU6 in the target chip group corresponds to component identification C in the target identification group CD, and NPU7 corresponds to component identification D in the target identification group CD, and NPU6 is located in the first loop and NPU7 is located in the second loop, therefore, the target data component sequence C0 and C1 of NPU0 is transmitted to NPU6 through the first loop, and the target data component sequence D0 and D1 of NPU1 is transmitted to NPU7 through the second loop.

[0081] In the following, referring to Figure 4 and Figure 7The above-mentioned on-ring data transmission process is now explained using chipset 3 as the current chipset during the third iteration as an example. The target identifier group in chipset 3's previous iteration (i.e., the second iteration) is AB. In the current iteration (i.e., the third iteration), the chipset corresponding to target identifier group AB is chipset 2. Chipset 2 is used as the target chipset for the current chipset. The two chips in the target chipset are NPU2 and NPU3. NPU2 corresponds to component identifier A in target identifier group AB, and NPU3 corresponds to component identifier B in target identifier group AB.

[0082] At the same time, in NPU4 of chipset 3, component identifier A corresponds to four initial data components A4, A5, A6, and A7, so A4, A5, A6, and A7 are used as the target data component sequence of NPU4. Correspondingly, in NPU5 of chipset 3, component identifier B corresponds to four initial data components B4, B5, B6, and B7, so B4, B5, B6, and B7 are used as the target data component sequence of NPU5.

[0083] Since NPU2 in the target chipset corresponds to component identifier A in the target identifier group AB, NPU3 corresponds to component identifier B in the target identifier group AB, and NPU2 is located in the first loop and NPU3 is located in the second loop, the target data component sequence A4, A5, A6, and A7 of NPU4 in chipset 3 is transmitted to NPU6 through the first loop, and the target data component sequence B4, B5, B6, and B7 of NPU5 in chipset 3 is transmitted to NPU3 through the second loop.

[0084] By performing multiple iterations in the above manner, refer to Figure 7 Finally, multiple initial data components corresponding to the same component identifier are aggregated in each chip. For example, A0, A1, A2, A3, A4, A5, A6, and A7 correspond to the aggregate component identifier A in NPU0; B0, B1, B2, B3, B4, B5, B6, and B7 correspond to the aggregate component identifier B in NPU1; and H0, H1, H2, H3, H4, H5, H6, and H7 correspond to the aggregate component identifier H in NPU7.

[0085] Step 340: The iteration ends, and the initial data components corresponding to the same component identifier are aggregated to obtain a preset number of initial aggregated data.

[0086] In an embodiment, the initial data components corresponding to the same component identifier are aggregated to obtain a preset number of initial aggregated data. For example, 8 initial data components corresponding to component identifier A are aggregated in NPU0 to obtain initial aggregated data A. The aggregation of the initial data components can be described as A=A0+A1+A2+A3+A4+A5+A6+A7. In this way, each chip can obtain an initial aggregated data.

[0087] In an embodiment, the initial data components corresponding to the same component identifier are aggregated to obtain a preset number of initial aggregated data. For example, 8 initial data components corresponding to component identifier A are aggregated in NPU0 to obtain initial aggregated data A. The aggregation of the initial data components can be described as A=A0+A1+A2+A3+A4+A5+A6+A7. In this way, each chip can obtain an initial aggregated data. Figure 4 In an embodiment, the initial data components corresponding to the same component identifier are aggregated to obtain a preset number of initial aggregated data. For example, 8 initial data components corresponding to component identifier A are aggregated in NPU0 to obtain initial aggregated data A. The aggregation of the initial data components can be described as A=A0+A1+A2+A3+A4+A5+A6+A7. In this way, each chip can obtain an initial aggregated data.

[0088] In the second iteration, first, data transmission is performed in each chip group through the direct communication connection. At this time, in chip group 3, data is exchanged between NPU4 and NPU5, and B4 in NPU4 and A5 in NPU5 are exchanged. Next, chip 3 is taken as the target chip group, NPU4 corresponds to component identifier A in the target identifier group AB, and NPU5 corresponds to component identifier B in the target identifier group AB. A6 and A7 in the target data component sequence in NPU6 are sent to NPU4 through the first loop, and B6 and B7 in the target data component sequence in NPU7 are sent to NPU5 through the second loop. At this time, the target data component sequence in NPU4 contains A4, A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7. If a reduction calculation is performed before the double-loop transmission, the target data component sequence in NPU4 contains A4+A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7. 45 =A4+A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7. 45 =A4+A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7.

[0089] In the third iteration, first, data transmission is performed in each chip group through the direct communication connection. At this time, in chip group 3, data is exchanged between NPU4 and NPU5, and B4 in NPU4 and A5 in NPU5 are exchanged. Next, chip 3 is taken as the target chip group, NPU4 corresponds to component identifier A in the target identifier group AB, and NPU5 corresponds to component identifier B in the target identifier group AB. A6 and A7 in the target data component sequence in NPU6 are sent to NPU4 through the first loop, and B6 and B7 in the target data component sequence in NPU7 are sent to NPU5 through the second loop. At this time, the target data component sequence in NPU4 contains A4, A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7. If a reduction calculation is performed before the double-loop transmission, the target data component sequence in NPU4 contains A4+A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7. 45 =A4+A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7. 45 =A4+A5, A6, and A7, and the target data component sequence in NPU5 contains B4, B5, B6, and B7. 4567, NPU3 contains B2, B3, B 4567 .

[0090] In the fourth iteration, first, the direct communication connection data transmission is carried out in each chip group, at this time, the direct data exchange is carried out between NPU0 and NPU1 in chip group 1, and B0 in NPU0 and A1 in NPU1 are exchanged. Next, taking chip 1 as the target chip group, A2, A3, A 4567 are sent to NPU0 through the first ring, B2, B3, B 4567 are sent to NPU1 through the second ring, at this time, the target data component sequence in NPU0 contains A0, A1, A 234567 , the target data component sequence in NPU1 contains B0, B1, B 234567 . After the last reduction aggregation, the data in NPU0 is A=A 01234567 , and the data in NPU1 is B=B 01234567 .

[0091] From the above process, it can be seen that the implementation of the Reduce Scatter function using the double-ring chip structure in the embodiment of the application can be regarded as three stages. They are: the initial reduction stage, the double-ring transmission stage and the final reduction stage. Among them, the initial reduction stage is the first iteration process, and the data transmission is carried out in the chip group using the direct communication connection. This stage uses SIO and HCCS to realize the load balancing of the double-link. Next, the double-ring transmission stage, that is, all iteration processes after the second iteration. The data is transmitted through HCCS in two independent rings, the first ring and the second ring, and the data synchronization between the two rings is carried out through the direct communication connection. The double-ring transmission stage needs a total of (n / 2-1) steps of communication. And the final reduction stage: since it is not possible to perform the in-place reduction operation when receiving the SIO and HCCS link data at the same time, an additional reduction operation is needed to combine the intermediate results from the SIO and HCCS buffers. This stage does not produce communication overhead and takes very short time.

[0092] In an embodiment, after the Reduce Scatter function is executed, the All Gather function stage is entered. Referring to Figure 9 , Figure 9 is a flowchart of the All Gather function provided by the embodiment of the application, and specifically includes the following steps: Step 910: determining the second iteration number according to the number of chips.

[0093] In an embodiment, the second iteration number of the All Gather function is (n / 2-1), n is the number of chips, if n=8, the second iteration number is 3 times.

[0094] Step 920: iteration is performed based on the second iteration number, in each iteration, for two chips in the same chip group, the initial aggregated data missing of the chip relative to the other chip is determined as the first direct transmission aggregated data, the first direct transmission aggregated data is alternately transmitted based on the corresponding direct communication connection, for two adjacent chip groups, the initial aggregated data missing of the latter chip relative to the former chip is determined as the inter-group aggregated data based on the direction of the chip group, and the inter-group aggregated data is transmitted based on the direction of the first ring and the second ring respectively.

[0095] In an embodiment, similar to the Reduce Scatter function, it can be divided into a double-ring transmission phase and a final synchronization phase. In the double-ring transmission phase, data is transmitted through HCCS in two independent rings, the first ring and the second ring, and data synchronization is performed between the two rings through the direct communication connection. In each iteration process, the direct communication connection transmission data and the double-ring transmission data in the chip group are included.

[0096] In an embodiment, referring to Figure 10 , Figure 10 is a schematic diagram of the principle of the All Gather function provided by the embodiment of the present application. Here, the results of Figure 4 or Figure 7 are processed, before starting the processing, the initial aggregated data A is included in NPU0, the initial aggregated data B is included in NPU1, the initial aggregated data C is included in NPU2, the initial aggregated data D is included in NPU3, the initial aggregated data E is included in NPU4, the initial aggregated data F is included in NPU5, the initial aggregated data G is included in NPU6, and the initial aggregated data H is included in NPU7.

[0097] In each iteration, for two chips in the same chip group, the initial aggregated data missing of the chip relative to the other chip is determined as the first direct transmission aggregated data, and the first direct transmission aggregated data is alternately transmitted based on the corresponding direct communication connection. Referring to Figure 10 , taking the first iteration process as an example, for the chip group 1, the initial aggregated data missing of NPU0 relative to NPU1 is B included in NPU1, and the initial aggregated data missing of NPU1 relative to NPU0 is A included in NPU0, so the first direct transmission aggregated data includes A and B, at this time, A included in NPU0 is transmitted to NPU1, and B included in NPU1 is transmitted to NPU0. Similarly, the corresponding first direct transmission aggregated data in other chip groups is also determined, and the alternately transmission of the direct communication connection is performed.

[0098] At the same time, during iteration, two adjacent chipsets determine the initial aggregated data missing from the latter chip relative to the former chip based on the direction of the chipsets as inter-group aggregated data, and transmit the inter-group aggregated data based on the directions of the first loop and the second loop. Figure 10 , chipset 1 and chipset 2 are two adjacent chipsets. At this time, the direction of the chipset is: chipset 2-> chipset 1, so the direction of the first loop and the second loop is also determined. For the first loop, the initial aggregated data that the subsequent chip NPU0 lacks relative to the previous chip NPU2 is C. C is used as the inter-group aggregated data, and the inter-group aggregated data C is transmitted from NPU2 to NPU0 based on the direction of the first loop. Correspondingly, for the second loop, the initial aggregated data that the subsequent chip NPU1 lacks relative to the previous chip NPU3 is D. D is used as the inter-group aggregated data, and the inter-group aggregated data D is transmitted from NPU3 to NPU1 based on the direction of the second loop. The same operation is performed between other adjacent chipsets.

[0099] After the first iteration, NPU0 contains initial aggregated data A, B, and C, NPU1 contains initial aggregated data A, B, and D, NPU2 contains initial aggregated data C, D, and E, NPU3 contains initial aggregated data C, D, and F, NPU4 contains initial aggregated data E, F, and G, NPU5 contains initial aggregated data E, F, and H, NPU6 contains initial aggregated data A, G, and H, and NPU7 contains initial aggregated data B, G, and H.

[0100] Next, enter the second iteration process. Figure 10 For chipset 1, the initial aggregate data missing from NPU0 relative to NPU1 is D in NPU1, and the initial aggregate data missing from NPU1 relative to NPU0 is C in NPU0. Therefore, the first direct aggregate data includes D and C. At this time, D in NPU0 is transmitted to NPU1, and C in NPU1 is transmitted to NPU0. Similarly, the corresponding first direct aggregate data is also clearly defined in the other chipsets, and alternating transmission is performed on it via direct communication connections.

[0101] Meanwhile, chip set 1 and chip set 2 are two adjacent chip sets, for the first ring, the next chip NPU0 is missing initial aggregation data D, E relative to the previous chip NPU2, D, E are taken as inter-group aggregation data, and the inter-group aggregation data D, E are transmitted from NPU2 to NPU0 based on the direction of the first ring. Correspondingly, for the second ring, the next chip NPU1 is missing initial aggregation data C, F relative to the previous chip NPU3, C, F are taken as inter-group aggregation data, and the inter-group aggregation data C, F are transmitted from NPU3 to NPU1 based on the direction of the second ring. The same operation is performed between other adjacent chip sets.

[0102] After the second iteration, NPU0 contains initial aggregation data A, B, C, D, E, NPU1 contains initial aggregation data A, B, C, D, F, NPU2 contains initial aggregation data C, D, E, F, G, NPU3 contains initial aggregation data C, D, E, F, H, NPU4 contains initial aggregation data A, E, F, G, H, NPU5 contains initial aggregation data B, E, F, G, H, NPU6 contains initial aggregation data A, B, C, G, H, and NPU7 contains initial aggregation data A, B, D, G, H.

[0103] The third iteration is continued according to the above process, and after the execution ends, each chip contains 7 different initial aggregation data.

[0104] Step 930: After the iteration ends, for two chips in the same chip set, the initial aggregation data missing in one chip relative to the other chip is determined as the second direct transmission aggregation data, and the first direct transmission aggregation data is alternately transmitted based on the corresponding direct communication connection until all initial aggregation data are contained in each chip.

[0105] In an embodiment, after the iteration ends, the double-ring transmission phase is completed, and at this time, each chip is missing one piece of initial aggregation data. Referring to Figure 10, NPU0 is missing initial aggregation data H, NPU1 is missing initial aggregation data G, NPU2 is missing initial aggregation data B, and so on. Therefore, the last piece of initial aggregation data is transmitted by the HCCS / SIO double link in the final synchronization stage. Here, the transmission is performed by using the direct communication connection within the chip group. For two chips in the same chip group, the initial aggregation data missing from one chip relative to the other chip is determined as the second direct transmission aggregation data, and the first direct transmission aggregation data is alternately transmitted based on the corresponding direct communication connection until all initial aggregation data is included in each chip. For example, for chip group 1, the initial aggregation data missing from NPU0 relative to NPU1 is H included in NPU1, and the initial aggregation data missing from NPU1 relative to NPU0 is G included in NPU0. Therefore, the second direct transmission aggregation data includes H and G, and at this time, G included in NPU0 is transmitted to NPU1, and H included in NPU1 is transmitted to NPU0. In this way, data transmission of all direct communication connections within the chip group is completed.

[0106] At this point, the All Gather function is completed. It can be seen that the All Reduce operation is realized by the double-loop chip structure, combined with the Reduce Scatter function and the All Gather function in the embodiment of the application. In the operation process, the first chip and the second chip of each chip group in the multiple chip groups can realize information interaction between chips within the group by the direct communication connection, without passing through the loop transfer. The direct link can realize efficient interaction, reducing the delay and path loss of intra-group communication. At the same time, the first loop and the second loop formed by the first chip and the second chip of different chip groups are independent and parallel, which can reduce the data blocking probability of cross-group communication, making the communication path more flexible. The structure of "intra-group direct connection + cross-group double-loop parallel" can shorten the communication path and improve the data transmission efficiency, thereby significantly improving the execution efficiency of collective communication.

[0107] In an embodiment, the Broadcast function in collective communication based on the double-loop chip structure is described. Referring to Figure 11 , Figure 11 is another optional flowchart of the collective communication method provided by the embodiment of the application, Figure 11 The method in the embodiment is the implementation logic of the Broadcast function, which can include but is not limited to steps 1110 to 1130. It can be understood that the order of steps 1110 to 1130 in the embodiment is not specifically limited, and the order of steps can be adjusted or some steps can be reduced or added according to actual needs. Figure 11

[0108] ​Step 1110: determining a source chip from all chips contained in the dual-loop chip structure, and dividing a preset number of initial block data in the source chip to obtain a first data group and a second data group.

[0109] In an embodiment, the source chip is determined from all chips contained in the dual-loop chip structure, wherein the source chip can be set according to actual conditions, and the source chip contains a preset number of initial block data, and then the initial block data is divided to obtain a first data group and a second data group, wherein the first data group and the second data group contain the same number of initial block data.

[0110] In an embodiment, referring to Figures 12a to 12c , Figures 12a to 12c is a schematic diagram of the Broadcast function provided by the embodiment of the application. It is assumed that NPU0 is a source chip, which contains 8 initial block data A'-H'. At this time, the 8 initial block data are first divided, and are divided into two parts according to actual requirements, as shown in Figure 12a A', B', C', and D in the first data group and E', F', G', and H' in the second data group are shown in the schematic diagram.

[0111] Step 1120: transmitting the second data group to another chip corresponding to the source chip through a corresponding direct communication connection.

[0112] In an embodiment, the Broadcast function can also be divided into an initial stage, a dual-loop transmission stage, and a final synchronization stage. In the initial stage, the second data group is transmitted to another chip corresponding to the source chip through a corresponding direct communication connection. Referring to Figure 12a , the source chip NPU0 is located in Chipset 1, and the other chip corresponding to the source chip is NPU1, and at this time, the second data group E', F', G', and H' is transmitted to the other chip NPU1 corresponding to the source chip through the direct communication connection in Chipset 1.

[0113] Step 1130: broadcasting and transmitting the first data group and the second data group in the first loop, the second loop, and each direct communication connection until each chip contains all initial block data.

[0114] In an embodiment, referring to Figure 13 , Figure 13 is a flowchart of broadcasting and transmitting the first data group and the second data group in the first loop, the second loop, and each direct communication connection until each chip contains all initial block data provided by the embodiment of the application, and specifically includes the following steps: Step 1310: determining a third iteration number according to the number of chips and a preset number.

[0115] In one embodiment, the third iteration number of the dual-ring transmission phase is determined according to the number of chips and the preset number, and is expressed as (m+n) / 2-2, where m is the preset number. Assuming m=n=8, the third iteration number is 6.

[0116] Step 1320: Iterate based on the third number of iterations. In each iteration, for two chips in the same chipset, determine an initial block data that is missing from one chip relative to the other chip as the third direct transmission aggregate data, and transmit the third direct transmission aggregate data alternately based on the corresponding direct communication connection. In two adjacent chipsets, determine an initial block data that is missing from the latter chip relative to the former chip as the inter-group block data based on the direction of the chipset, and transmit the inter-group block data based on the directions of the first loop and the second loop.

[0117] In one embodiment, in each iteration, for two chips in the same chipset, an initial block data missing from one chip relative to the other chip is determined as the third direct transmission aggregate data, and the third direct transmission aggregate data is transmitted alternately based on the corresponding direct communication connection. Figure 12b Taking the first iteration as an example, for chipset 1, NPU0 and NPU1 communicate with each other and determine that chip NPU1 is missing an initial block data A' relative to chip NPU0. However, NPU0 does not have any missing initial block data relative to chip NPU1. Therefore, only A' is used as the third direct transmission aggregate data. Then, based on the corresponding direct communication connection in chipset 1 (indicated by the dotted line in the figure), the third direct transmission aggregate data is alternately transmitted, and the initial block data A' in NPU0 is transmitted to NPU1. At this time, since the other chipsets do not have any initial block data, the corresponding third direct transmission aggregate data can be considered empty.

[0118] Then, in two adjacent chip groups, based on the direction of the chip groups, the initial block data missing from the latter chip relative to the former chip is determined as inter-group block data, and the inter-group block data is transmitted based on the directions of the first loop and the second loop. Figure 12bIn the first iteration, chip group 1 and chip group 2 are adjacent, and the direction of the chip group is chip group 1 -> chip group 2, so in the first loop, the initial block data missing from the latter chip NPU2 relative to the former chip NPU0 is A', so A' is taken as the corresponding inter-group block data of the first loop, and the inter-group block data is transmitted based on the direction of the first loop, and A' in NPU0 is transmitted to NPU2 along the first loop. Similarly, in the second loop, the initial block data missing from the latter chip NPU3 relative to the former chip NPU1 is H', so H' is taken as the corresponding inter-group block data of the second loop, and the inter-group block data is transmitted based on the direction of the second loop, and H' in NPU1 is transmitted to NPU3 along the second loop.

[0119] Next, with reference to Figure 12b The second iteration is taken as an example for further description.

[0120] For chip group 1, it is determined that the initial block data missing from the chip NPU1 relative to the other chip NPU0 is B', and NPU0 has no initial block data missing relative to the other chip NPU1, so only B' is taken as the third direct transmission aggregation data, and then the initial block data B' in NPU0 is transmitted to NPU1 based on the corresponding direct communication connection in chip group 1. At this time, for chip group 2, it is determined that the initial block data missing from the chip NPU2 relative to the other chip NPU3 is H', and the initial block data missing from the chip NPU3 relative to the other chip NPU2 is A', so A' and H' are taken as the third direct transmission aggregation data, and then the initial block data A' in NPU2 is transmitted to NPU3, and the initial block data H' in NPU3 is transmitted to NPU2 based on the corresponding direct communication connection in chip group 2. Since there is no initial block data in chip group 3 and chip group 4, it can be regarded as that the corresponding third direct transmission aggregation data is empty.

[0121] Then, chip group 1 and chip group 2 are adjacent, so in the first loop, the last chip NPU2 is missing one initial block data B' relative to the previous chip NPU0, so B' is taken as the corresponding inter-group block data of the first loop, and the inter-group block data is transmitted based on the direction of the first loop, so B' in NPU0 is transmitted to NPU2 along the first loop. Similarly, in the second loop, the last chip NPU3 is missing one initial block data G' relative to the previous chip NPU1, so G' is taken as the corresponding inter-group block data of the second loop, and the inter-group block data is transmitted based on the direction of the second loop, so G' in NPU1 is transmitted to NPU3 along the second loop. Meanwhile, chip group 3 and chip group 2 are adjacent, so in the first loop, the last chip NPU4 is missing one initial block data A' relative to the previous chip NPU2, so A' is taken as the corresponding inter-group block data of the first loop, and the inter-group block data is transmitted based on the direction of the first loop, so A' in NPU2 is transmitted to NPU4 along the first loop. Similarly, in the second loop, the last chip NPU5 is missing one initial block data H' relative to the previous chip NPU3, so H' is taken as the corresponding inter-group block data of the second loop, and the inter-group block data is transmitted based on the direction of the second loop, so H' in NPU3 is transmitted to NPU5 along the second loop.

[0122] Similarly, until the third iteration number corresponds to the end of the execution of the iteration process.

[0123] Step 1330: After the iteration, for two chips in the same chip group, respectively determine the initial aggregated data missing by the chip relative to the other chip as the fourth direct transmission aggregated data, and alternately transmit the fourth direct transmission aggregated data based on the corresponding direct communication connection, until all initial block data is contained in each chip.

[0124] In an embodiment, referring to Figure 12b , all initial block data is contained in two chips in other chip groups except the last chip group, and each of the two chips in the last chip group is missing one initial block data, so in the last synchronization stage, data completion is performed by using the direct communication connection within the chip group. For two chips in the same chip group, respectively determine the initial aggregated data missing by the chip relative to the other chip as the fourth direct transmission aggregated data, and alternately transmit the fourth direct transmission aggregated data based on the corresponding direct communication connection, until all initial block data is contained in each chip.

[0125] Referring to Figure 12b , after the last iteration, NPU6 in chip group 4 is missing E', and NPU7 is missing D', so D' in NPU6 and E' in NPU7 are alternately transmitted by using the direct communication connection within chip group 4. Referring to Figure 12cAfter the alternate transmission inside the chip set 4, all the initial block data are also contained in the NPUs 6 and 7.

[0126] At this point, all the chips contain all the initial block data, and the Broadcast function is implemented.

[0127] It can be seen that the embodiment of the application performs collective communication based on a double-loop chip structure, places two computing dies (such as NPUs) in the Chiplet package in two independent logical ring networks respectively, forms two parallel ring loops by the traditional link HCCS, and obtains a first loop and a second loop. At the same time, the corresponding odd and even NPUs in the same chip package are connected as a chip set by using a high-bandwidth SIO link, responsible for data synchronization between the two loops and high-speed communication inside the chip. The inter-chip high-speed link SIO resources of the Chiplet package chip can be effectively utilized, the first loop and the second loop can simultaneously perform data transmission, and data exchange and synchronization can be performed through direct communication connection inside the chip set, realizing load balancing of double links and higher bandwidth utilization, fully developing the hardware potential, and further improving the communication bandwidth and efficiency.

[0128] In an embodiment, experiments show that the collective communication method of the embodiment of the application realizes significant algorithm bandwidth improvement on the Ascend NPU cluster, for example, an average improvement of 15.81% under a 4NPU configuration and an average improvement of 9.15% under a 128NPU configuration. Secondly, the communication mode is decoupled into coordinated double-loop operations, reducing the base of the ring (by 50%) and the communication volume of the HCCS link, while retaining the bandwidth advantage of the SIO. Finally, good scalability is shown under different cluster scales of 4 to 128 NPUs, which can significantly improve the overall communication efficiency of large-scale AI model distributed training.

[0129] In the technical scheme provided in the embodiments of the present application, the double-loop chip structure comprises: a plurality of chip groups, each chip group comprising a first chip and a second chip, and a direct communication connection existing between the corresponding first chip and the second chip; the first chips in different chip groups are sequentially connected in the order of the chip groups to form a first loop; and the second chips in different chip groups are sequentially connected in the order of the chip groups to form a second loop. When the double-loop chip structure provided in the embodiments of the present application is applied to a scenario of collective communication, in which data needs to be broadcast, converged or synchronized between a plurality of chips, the first chip and the second chip of each chip group in the plurality of chip groups can realize information interaction between chips in the group through the direct communication connection, without needing to pass through the loop relay, and the direct link can realize efficient interaction, thereby reducing the delay and path loss of intra-group communication. Meanwhile, the first loop and the second loop formed by the first chips and the second chips of different chip groups are independent and parallel to each other, which can reduce the data blocking probability of cross-group communication and make the communication path more flexible. The structure of "intra-group direct connection + cross-group double-loop parallelism" can shorten the communication path and improve the data transmission efficiency, thereby significantly improving the execution efficiency of the collective communication.

[0130] The embodiments of the present application also provide a collective communication device, which can implement the collective communication method of the All Reduce function. Figure 14 The device comprises: The data acquisition module 1410 is configured to acquire a preset number of initial data components contained in all chips in the double-loop chip structure, the initial data components corresponding to component identifiers, the component identifiers being grouped into target identifier groups two by two, and the double-loop chip structure being the double-loop chip structure of claim 1.

[0131] The communication preparation module 1420 is configured to determine a first iteration number according to the number of chips, and determine the target identifier groups corresponding to the chip groups at each iteration, wherein the target identifier groups in the same chip group are different at each iteration in the continuous iteration process, and the chip groups corresponding to the same target identifier group are updated in the order of the chip groups.

[0132] The data transmission module 1430 is configured to perform iteration based on the first iteration number, and at each iteration, alternately transmit, based on the corresponding direct communication connection, the two initial data components corresponding to the target identifier groups for the two chips in the same chip group, and / or transmit, based on the first loop and the second loop respectively, the two initial data components corresponding to the target identifier groups between the chip groups.

[0133] The aggregation module 1440 is configured to aggregate the initial data components corresponding to the same component identifier to obtain a preset number of initial aggregated data until the iteration ends, and each chip obtains one initial aggregated data.

[0134] The specific implementation of the collective communication device of this embodiment is basically the same as the specific implementation of the above-mentioned collective communication method, and will not be repeated here.

[0135] The embodiment of the present application also provides a collective communication device that can implement the collective communication method of the above-mentioned Broadcast function, referring to Figure 15 , the device comprises: Initial data allocation module 1510: used to determine a source chip from all chips included in the dual-loop chip structure, and evenly divide a preset number of initial block data in the source chip to obtain a first data group and a second data group. The number of chips is not less than the preset number. The dual-loop chip structure is the dual-loop chip structure of claim 1.

[0136] Intra-group transmission module 1520: configured to transmit the second data group to another chip corresponding to the source chip through a corresponding direct communication connection.

[0137] The broadcast transmission module 1530 is configured to broadcast the first data group and the second data group in the first loop, the second loop and each direct communication connection until each chip contains all the initial block data.

[0138] The specific implementation of the collective communication device of this embodiment is basically the same as the specific implementation of the above-mentioned collective communication method, and will not be repeated here.

[0139] An embodiment of the present application further provides an electronic device, including: at least one memory; at least one processor; at least one program; The program is stored in the memory, and the processor executes the at least one program to implement the collective communication method described above. The electronic device can be any smart terminal including a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, etc.

[0140] See also Figure 16 , Figure 16 The hardware structure of an electronic device according to another embodiment is shown. The electronic device includes: The processor 1601 may be implemented as a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute relevant programs to implement the technical solutions provided in the embodiments of the present application. The memory 1602 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM), etc. The memory 1602 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory 1602 and are called and executed by the processor 1601 to implement the set communication method of the embodiments of the present application; The input / output interface 1603 is configured to realize information input and output. The communication interface 1604 is configured to realize the communication interaction between the device and other devices. The communication can be realized by a wired manner (for example, a USB, a network cable, etc.) or a wireless manner (for example, a mobile network, WIFI, Bluetooth, etc.). The bus 1605 is configured to transmit information between various components (for example, the processor 1601, the memory 1602, the input / output interface 1603, and the communication interface 1604) of the device. The processor 1601, the memory 1602, the input / output interface 1603, and the communication interface 1604 are connected to each other through the bus 1605 to realize the communication connection between the devices.

[0141] The embodiments of the present application also provide a storage medium. The storage medium is a storage medium, and the storage medium stores a computer program. The computer program is executed by the processor to implement the set communication method.

[0142] The memory is a non-transitory storage medium and can be used to store a non-transitory software program and a non-transitory computer executable program. In addition, the memory can include a high-speed random access memory and can also include a non-transitory memory, for example, at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely arranged relative to the processor. These remote memories can be connected to the processor through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0143] The double-loop chip structure, the set communication method, the device, the equipment and the storage medium provided by the embodiments of the present application have the technical solutions and beneficial effects.

[0144] The embodiments described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0145] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation to the embodiments of the present application, and can include more or fewer steps than the figures, or combine certain steps, or different steps.

[0146] The device embodiments described above are merely illustrative, and units described as separate components can or can not be physically separate, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments.

[0147] Those skilled in the art can understand that all or some of the steps in the above disclosed method, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware and their appropriate combinations.

[0148] The terms "first", "second", "third", "fourth" and the like in the specification of the present application and the above-described drawings, if any, are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0149] It should be understood that in the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association between the associated objects, which means that there can be three relationships, for example, "A and / or B" can represent three cases: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can mean a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0150] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the above units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0151] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they can be located in one place or distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0152] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0153] When the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various program storage media.

[0154] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, but this does not limit the scope of the embodiments of the present application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the embodiments of the present application.

Claims

1. A dual-loop chip structure, characterized in that: include: A plurality of chipsets, each of the chipsets comprising a first chip and a second chip, wherein a direct communication connection exists between the first chip and the second chip; The first chips in different chipsets are connected in sequence according to the order of the chipsets to form a first loop; The second chips in different chipsets are connected in sequence according to the order of the chipsets to form a second loop.

2. A collective communication method, characterized in that: include: Obtaining a preset number of initial data components contained in all chips in the dual-loop chip structure, wherein the initial data components correspondingly include component identifiers, wherein the component identifiers are grouped in pairs into target identifier groups, and the dual-loop chip structure is the dual-loop chip structure according to claim 1; Determining a first number of iterations based on the number of chips, and determining the target identification group corresponding to the chipset in each iteration, wherein in a continuous iteration process, the target identification group in the same chipset is different in each iteration, and the chipsets corresponding to the same target identification group are updated along the order of the chipsets; Iterating based on the first number of iterations, and in each iteration, alternately transmitting the two initial data components corresponding to the target identification group to two chips in the same chipset based on the corresponding direct communication connection, and / or transmitting the two initial data components corresponding to the target identification group between the chipsets based on the first loop and the second loop, respectively; Until the iteration ends, the initial data components corresponding to the same component identifier are aggregated to obtain the preset number of initial aggregated data, and each chip obtains one piece of the initial aggregated data.

3. The collective communication method according to claim 2, characterized in that: The alternately transmitting the two initial data components corresponding to the target identification group to the two chips in the same chipset based on the corresponding direct communication connection includes: Allocating the two component identifiers in the target identifier group to the first chip and the second chip in sequence respectively; The initial data component in the first chip that is consistent with the component identifier of the second chip and the initial data component in the second chip that is consistent with the component identifier of the first chip are exchanged and transmitted through the direct communication connection.

4. The collective communication method according to claim 3, characterized in that: The transmitting, between the chipsets, the two initial data components corresponding to the target identification group based on the first loop and the second loop, respectively, includes: In the second and subsequent iterations, each of the chipsets is selected one by one as the current chipset, the chipset corresponding to the target identification group in the previous iteration in the current iteration is used as the target chipset, and a correspondence between the two chips in the target chipset and the component identifications in the target identification group is determined; taking at least one of the initial data components corresponding to the two component identifiers of the target identifier group in the previous iteration in the two chips of the current chipset as a target data component sequence; Based on the corresponding relationship, the target data component sequence is transmitted to the corresponding chip of the target chipset through the first loop or the second loop.

5. The collective communication method according to claim 2, characterized in that: The method further comprises: Determining the second iteration number according to the number of chips; Iterating based on the second number of iterations, in each iteration, for two chips in the same chipset, respectively determining the initial aggregated data missing from the chip relative to the other chip as first direct aggregated data, and alternately transmitting the first direct aggregated data based on the corresponding direct communication connection; and in two adjacent chipsets, respectively determining the initial aggregated data missing from the latter chip relative to the former chip based on the directions of the chipsets as inter-group aggregated data, and transmitting the inter-group aggregated data based on the directions of the first loop and the second loop, respectively; After the iteration is completed, for the two chips in the same chipset, the initial aggregate data that is missing from the chip relative to the other chip is respectively determined as the second direct transmission aggregate data, and the first direct transmission aggregate data is alternately transmitted based on the corresponding direct communication connection until all the initial aggregate data are contained in each chip.

6. A collective communication method, characterized in that: include: Determining a source chip from all chips included in a dual-loop chip structure, and equally dividing a preset number of initial block data in the source chip to obtain a first data group and a second data group, wherein the number of the chips is not less than the preset number, and the dual-loop chip structure is the dual-loop chip structure according to claim 1; transmitting the second data group to another chip corresponding to the source chip through a corresponding direct communication connection; The first data group and the second data group are broadcasted on the first loop, the second loop and each of the direct communication connections until each of the chips contains all of the initial block data.

7. The collective communication method according to claim 6, characterized in that: The broadcasting of the first data group and the second data group on the first loop, the second loop, and each of the direct communication connections until each chip includes all of the initial block data includes: Determining a third iteration number according to the number of the chips and the preset number; Iterating based on the third number of iterations, in each iteration, for two chips in the same chipset, respectively determining one initial block data missing from one chip relative to the other chip as third direct transmission aggregate data, and alternately transmitting the third direct transmission aggregate data based on the corresponding direct communication connection; and in two adjacent chipsets, respectively determining one initial block data missing from the latter chip relative to the former chip based on the direction of the chipsets as inter-group block data, and transmitting the inter-group block data based on the directions of the first loop and the second loop, respectively; After the iteration is completed, for the two chips in the same chipset, the initial aggregated data that is missing from the chip relative to the other chip is respectively determined as the fourth direct transmission aggregated data, and the fourth direct transmission aggregated data is alternately transmitted based on the corresponding direct communication connection until all the initial block data are contained in each chip.

8. A collective communication device, characterized in that: include: A data acquisition module is configured to acquire a preset number of initial data components contained in all chips in a dual-loop chip structure, wherein the initial data components include component identifiers, and the component identifiers are grouped into target identifier groups in pairs. The dual-loop chip structure is the dual-loop chip structure according to claim 1. a communication preparation module configured to determine a first iteration number based on the number of chips, and determine the target identification group corresponding to the chipset in each iteration; wherein, during successive iterations, the target identification group in the same chipset is different in each iteration, and the chipsets corresponding to the same target identification group are updated in the order of the chipsets; a data transmission module configured to perform iteration based on the first number of iterations, and in each iteration, alternately transmit the two initial data components corresponding to the target identification group to two chips in the same chipset based on the corresponding direct communication connection, and / or transmit the two initial data components corresponding to the target identification group between the chipsets based on the first loop and the second loop, respectively; Aggregation module: used for aggregating the initial data components corresponding to the same component identifier until the iteration ends to obtain the preset number of initial aggregated data, and each chip obtains one piece of the initial aggregated data.

9. A collective communication device, characterized in that: include: an initial data allocation module configured to determine a source chip from all chips included in a dual-loop chip structure, and evenly divide a preset number of initial block data in the source chip to obtain a first data group and a second data group, wherein the number of the chips is not less than the preset number, and the dual-loop chip structure is the dual-loop chip structure according to claim 1; Intra-group transmission module: used for transmitting the second data group to another chip corresponding to the source chip through a corresponding direct communication connection; A broadcast transmission module is configured to broadcast the first data group and the second data group on the first loop, the second loop, and each of the direct communication connections until each of the chips contains all of the initial block data.

10. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the collective communication method according to any one of claims 2 to 7 when executing the computer program.

11. A storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the collective communication method according to any one of claims 2 to 7 is implemented.

Images