Electrical test structure and test method for monitoring performance of MOS (Metal Oxide Semiconductor) transistor junction

Abstract

The invention provides an electrical test structure and a test method for monitoring the junction performance of an MOS (Metal Oxide Semiconductor) transistor, and the structure of the test unit is provided with a structure similar to that of the MOS transistor, namely, the test unit comprises a substrate layer, a well layer, a gate structure, a doped region and a test bonding pad, but the doped region is divided into two regions with opposite doping types, so that the junction performance of the MOS transistor is monitored. The junction capacitance, the junction breakdown voltage and the junction leakage current between the first conductive type doped region and the well layer, the junction breakdown voltage and the junction leakage current between the second conductive type doped region and the well layer can be monitored by connecting different types of required voltages into the first test bonding pad and the second test bonding pad, so that the junction structure characteristics of the MOS transistor can be comprehensively monitored, and the reliability of the MOS transistor can be improved through a process reliability test. The junction capacitance, the junction breakdown voltage and the junction leakage current of the MOS transistor junction are effectively monitored, and risk investigation can be carried out on related processes in the MOS transistor process.

Description

Technical Field

[0001] The present invention relates to the field of wafer testing, and in particular to an electrical testing structure and a testing method for monitoring MOS tube junction performance. Background Art

[0002] Wafer Acceptance Test (WAT) measures the electrical parameters of specific test structures after wafer product tape-out and before quality inspection. The goal is to test the electrical parameters of specific test structures on the wafer to detect the process conditions of each wafer product, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer products meet the electrical specifications of the process technology platform. WAT data can serve as quality certification for wafer product delivery. In addition, WAT data can also reflect the actual production status of the production line. By collecting and analyzing WAT data, the production line status can be monitored, and the trend of production line changes can be determined, providing early warning of possible situations.

[0003] The test structure on the wafer used to collect WAT data is called a WAT ​​test key. It is not designed inside the actual product chip because designing it inside the chip would occupy additional chip area, and the additional chip area would increase the chip cost. Therefore, the WAT test key is generally designed in the dicing grooves between chips on the wafer, also known as the dicing area.

[0004] There are many types of WAT tests. Currently, the test structure for MOS transistor junctions only monitors the effects of ion implantation (IMP) and silicon metallization (Silicide) processes on electrical properties. These two types of test structures cannot effectively reflect the structural characteristics of MOS device junctions. In the preparation process of MOS device structure, the gate structure size including the sidewall determines the actual area of ​​source and drain ion implantation. For example, when the gate structure is widened, the width of the source and drain ion implantation will decrease, and when the gate structure is narrowed, the width of the source and drain ion implantation will increase. When the actual area of ​​source and drain ion implantation (mainly referring to the width) changes, it will produce a loading effect on the subsequent deposition and etching processes. For example, it will cause the thickness of the subsequent deposited film layer to be inconsistent, with the film thickness being thinner in the dense pattern area and thicker in the sparse pattern area; thicker film layers are prone to incomplete etching, and thinner film layers are prone to over-etching; and in SMT (stress memory process), the stress transfer of the stress film layer is affected, thereby affecting the speed of the MOS device. Therefore, it is necessary to propose an electrical test structure to monitor the impact of the change of the gate spacing of the MOS device on the MOS device junction. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide an electrical test structure and test method for monitoring the performance of MOS transistor junctions, so as to address the problem that the test structures of MOS transistor junctions in the prior art only monitor the effects of ion implantation (IMP) and silicon metallization (Silicide) processes on electrical properties, and that these two types of test structures cannot effectively reflect the junction structure characteristics of MOS devices.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides an electrical test structure for monitoring MOS tube junction performance, the electrical test structure comprising:

[0007] A test unit is provided on a base wafer, wherein the base wafer includes a chip area and a test area between the chip areas;

[0008] The testing unit is located on the testing area;

[0009] The test unit includes, from bottom to top, a substrate layer, a well layer and a gate structure, and also includes a first conductive type doped region and a second conductive type doped region and a first test pad and a second test pad formed on the surfaces of the first conductive type doped region and the second conductive type doped region, respectively; wherein the first conductive type doped region and the second conductive type doped region are arranged on both sides of the gate structure and extend inward from the surface of the well layer to a preset depth, and the conductivity type of the first conductive type doped region and the second conductive type doped region are opposite.

[0010] Optionally, the width of the first conductive type doping region and the second conductive type doping region is the minimum allowable value of the design rules, and the direction of the width is defined as the direction along which the first conductive type doping region, the gate structure and the second conductive type doping region are arranged in sequence.

[0011] Optionally, the width of the first conductive type doping region and the second conductive type doping region is 100nm to 300nm, and the direction of the width is defined as the direction along which the first conductive type doping region, the gate structure and the second conductive type doping region are arranged in sequence.

[0012] Optionally, the gate structure includes a gate dielectric layer, a gate polycrystalline layer and a gate spacer.

[0013] Optionally, the first conductive type doping region is an N-type doping region or a P-type doping region, and the second conductive type doping region is a P-type doping region or an N-type doping region.

[0014] Optionally, the shape and size of the gate structure in the test unit are the same as the shape and size of the gate structure of the MOS device in the chip area; the doping concentration and doping depth of the first conductive type doping region and the second conductive type doping region in the test unit are the same as the doping concentration and doping depth of the source / drain of the MOS device in the chip area.

[0015] Optionally, the number of the test units is more than 2.

[0016] Furthermore, the test units are arranged in an M×N array, where M and N are both natural numbers, and M≥2 or N≥2; wherein the first conductive type doping region, the gate structure and the second conductive type doping region of the test unit are arranged in sequence along the first direction of the array, and in the second direction of the array, three columns consisting of the first conductive type doping region, the gate structure and the second conductive type doping region are repeated in sequence as cycle units, the first direction intersects with the second direction, and between two adjacent gate structures along the first direction is the first conductive type doping region or the second conductive type doping region.

[0017] The present invention also provides a test method for monitoring MOS tube junction performance, the test method comprising:

[0018] Providing an electrical test structure for monitoring MOS tube junction performance as described in any one of the above;

[0019] Applying the same required voltage to the first test pad and the second test pad in each of the test units to form a test circuit;

[0020] Acquire test results from the test circuit.

[0021] Optionally, the testing method is used to test the junction capacitance, junction breakdown voltage and junction leakage current of a MOS tube.

[0022] As described above, the electrical test structure and test method for monitoring the junction performance of a MOS tube of the present invention are provided by providing a test unit, and the test unit structure has a structure similar to that of a MOS tube, namely, including a substrate layer, a well layer, a gate structure, a doped region, and a test pad, but the doped region is divided into two regions of opposite doping types, namely, first and second conductivity type doped regions. By connecting different types of required voltages to the first and second test pads, the junction capacitance, junction breakdown voltage, and junction leakage current between the first and second conductivity type doped regions and the well layer can be monitored, thereby achieving comprehensive monitoring of the MOS tube junction structure characteristics. The junction capacitance, junction breakdown voltage, and junction leakage current of the MOS tube junction can be effectively monitored through process reliability testing, and risk screening can be performed on related processes in the MOS tube manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic cross-sectional view of an exemplary electrical test structure of a junction is shown.

[0024] Figure 2 Shown is a schematic cross-sectional view of an exemplary MOS tube structure.

[0025] Figure 3 The figure shows a cross-sectional structural diagram of another example of a MOS tube structure.

[0026] Figure 4 It shows a cross-sectional structural schematic diagram of an electrical test structure for monitoring MOS tube junction performance according to the present invention.

[0027] Figure 5 Display as Figure 4 Schematic diagram of the cross-sectional structure of the middle gate structure.

[0028] Figure 6 The diagram shows a top view of the electrical test structure for monitoring MOS junction performance according to the present invention, wherein the first conductive type doping region and the second conductive type doping region are not shown.

[0029] Figure 7 A top view showing the positional relationship of various structures in a test unit of an electrical test structure for monitoring MOS transistor junction performance according to the present invention is shown.

[0030] Figure 8 Shown is a circuit diagram of an electrical test structure for monitoring MOS tube junction performance according to the present invention, wherein the electrical test structure is a schematic diagram of a cross-sectional structure.

[0031] Figure 9 Shown is a top view of the circuit layout of the electrical test structure for monitoring MOS tube junction performance of the present invention.

[0032] Component number description

[0033] 10-knot test structure

[0034] 100 substrate layer

[0035] 101 well layer

[0036] 102 first doping region

[0037] 103 second doping region

[0038] 11 MOS tube structure

[0039] 110 substrate layer

[0040] 111 well layer

[0041] 112 Gate structure

[0042] 113 Source

[0043] 114 Drain

[0044] 12 Electrical test structure

[0045] 120 test units

[0046] 121 substrate layer

[0047] 122 well layer

[0048] 123 Gate Structure

[0049] 123a Gate dielectric layer

[0050] 123b gate polycrystalline layer

[0051] 123c gate sidewall

[0052] 124 first conductive type doping region

[0053] 125 second conductivity type doping region

[0054] 126 First test pad

[0055] 127 Second test pad

[0056] 13 Well region

[0057] 14 Quarantine Zone

[0058] 15 Active region

[0059] 16 First voltage

[0060] 17 Second voltage DETAILED DESCRIPTION

[0061] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] See also Figures 1 to 9 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0063] As described in the background art, the current test structure for MOS transistors only monitors the effects of ion implantation (IMP) and silicon metallization (Silicide) processes on electrical properties. Figure 1 The figure shows an electrical test structure, which is mainly used to monitor the junction performance of MOS transistors. This structure forms a first doping region 102 and a second doping region 103 by ion implantation on the surface of the well layer 101 on the substrate layer 100, thereby monitoring the junction process. However, this structure does not form the gate structure of the MOS transistor. In the preparation process of the MOS device structure, the gate structure size determines the actual area of ​​the source and drain ion implantation, because the source and drain are between two adjacent gate structures. When the gate structure process (the existing MOS transistor process generally adopts the gate first process) fluctuates and causes the gate structure size to change, it will directly cause the actual area of ​​the self-aligned ion implanted source and drain to fluctuate. For example, when the gate structure is widened, the width of the source and drain ion implantation will be reduced. When the gate structure is narrowed, the width of the source and drain ion implantation will be increased. When the actual area of ​​the source and drain ion implantation (here mainly refers to the width, such as Figure 2 and Figure 3 When W) changes, it will have a loading effect on the subsequent deposition and etching processes, for example, causing the thickness of the subsequent deposited film to be inconsistent, such as Figure 2 The film thickness in the densely packed area is relatively thin, as shown in the figure. Figure 3 The film thickness in the sparsely-spaced area of ​​the pattern shown is relatively thick; thicker film layers are prone to incomplete etching, while thinner film layers are prone to over-etching; and stress transfer in the stress film layer is affected in SMT (stress memory process), thereby affecting the speed of the MOS device.

[0064] Based on this, this embodiment provides an electrical test structure for monitoring MOS tube junction performance, so as to achieve comprehensive monitoring of the structural characteristics of MOS tube junction performance. Figures 4 to 6 As shown, the electrical test structure 12 includes:

[0065] A test unit 120 is provided on a base wafer, wherein the base wafer includes a chip area and a test area between the chip areas;

[0066] The testing unit 120 is located on the testing area;

[0067] The test unit 120 comprises, from bottom to top, a substrate layer 121, a well layer 122, and a gate structure 123, and further comprises a first conductive type doped region 124 and a second conductive type doped region 125, and a first test pad 126 and a second test pad 127 formed on surfaces of the first conductive type doped region 124 and the second conductive type doped region 125 respectively; wherein the first conductive type doped region 124 and the second conductive type doped region 125 are arranged on both sides of the gate structure 123 and extend inward from a surface of the well layer 122 by a preset depth, and the first conductive type doped region 124 and the second conductive type doped region 125 are of opposite conductive types.

[0068] It is to be noted that the preset depth at which the first conductive type doped region 124 and the second conductive type doped region 125 extend inward from the surface of the well layer 122 is consistent with the depth of ion implantation of the source and drain of the MOS transistor in the chip region.

[0069] As described above, when the MOS transistor is prepared on the base wafer, the electrical test structure 12 of the embodiment is arranged in the non-chip region of the base wafer, such as the scribe lane region. The electrical test structure 12 can be formed to match the preparation process of the MOS transistor, for example, the shape and size of the gate structure 123 of each test unit 120 in the electrical test structure 12 can be the same as those of the gate structure of the MOS device in the chip region, and the doping concentration and doping depth of the first conductive type doped region 124 and the second conductive type doped region 125 of each test unit 120 are the same as those of the source / drain of the MOS device in the chip region.

[0070] The electrical test structure 12 of the embodiment can monitor the junction capacitance, junction breakdown voltage, and junction leakage current between the first and second conductive type doped regions and the well layer by connecting different types of voltages to the first and second test pads, so as to comprehensively monitor the junction structure characteristics of the MOS transistor, effectively monitor the junction capacitance, junction breakdown voltage, and junction leakage current of the MOS transistor through process reliability test, and check the risks of related processes in the MOS transistor process.

[0071] For example, the substrate layer 121 in the test unit 120 can be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc., and can also be a substrate containing other elemental semiconductors or compound semiconductors. The specific selection is made according to actual needs.

[0072] As shown in Figure 6 As an example, the electrical test structure 12 is disposed in a non-chip region of a substrate wafer, a well region 13 is generally formed in the non-chip region, and an isolation region 14 is formed around the periphery of the well region 13, so that an inner region surrounded by the isolation region 14 is formed as an active region 15 of the electrical test structure 12.

[0073] As a preferred example, since the width of the first conductive type doped region 124 and the second conductive type doped region 125 is more sensitive to the critical dimension of the gate pitch between the two gate structures 123, the width of the first conductive type doped region 124 and the second conductive type doped region 125 is set to the minimum allowable value of the design rule to improve the measurement accuracy. As shown in Figure 4 Here, the direction of the width is defined as the direction along which the first conductive type doped region 124, the gate structure 123, and the second conductive type doped region 125 are arranged in sequence, i.e. Figure 4 the left-right direction in the cross-sectional view.

[0074] As another specific example, the width of the first conductive type doped region 124 and the second conductive type doped region 125 is 100nm-300nm, such as 150nm, 180nm, 210nm, 240nm, 270nm, etc. As shown in Figure 4 Here, the direction of the width is defined as the direction along which the first conductive type doped region 124, the gate structure 123, and the second conductive type doped region 125 are arranged in sequence, i.e. Figure 4 the left-right direction in the cross-sectional view.

[0075] As shown in Figure 5 As an example, the gate structure 123 includes a gate side wall 123c, specifically including: a gate dielectric layer 123a at the bottom, a gate polysilicon layer 123b on the gate dielectric layer 123a, and a gate side wall 123c covering the side walls of the gate dielectric layer 123 and the gate polysilicon layer 123b. The preparation process of the gate structure 123 uses existing conventional processes, such as deposition, photolithography and etching of the gate dielectric layer and the gate polysilicon layer, deposition and etching of the gate side wall, etc., which will not be described in detail here.

[0076] As an example, the first conductivity type doping region 124 and the second conductivity type doping region 125 have opposite conductivity types. That is, when the first conductivity type doping region 124 is N-type doped, the second conductivity type doping region 125 is P-type doped; and when the first conductivity type doping region 124 is P-type doped, the second conductivity type doping region 125 is N-type doped. In addition, the doping ions used for the N-type and P-type doping are consistent with the doping ions used for the source and drain of the MOS transistor in the chip area. For example, the N-type doping ions can be P ions or As ions, and the P-type doping ions can be B ions.

[0077] In some embodiments, the number of the test units 120 in the electrical test structure 12 is greater than or equal to 2. When the number of the test units 120 is greater than or equal to 2, the monitoring structure measured is the sum of the monitoring results of multiple test units 120, which can effectively improve the monitoring accuracy.

[0078] As a preferred example, Figure 6 As shown, the arrangement of the plurality of test units 120 can imitate the arrangement of the MOS tubes in the chip area, that is, it is arranged in a compact array, for example, it is arranged in an M×N array, M and N are both natural numbers, and M≥2 or N≥2, wherein the first conductive type doping region 124, the gate structure 123 and the second conductive type doping region 125 of the test unit 120 are arranged along the first direction of the array (for example Figure 6 In the X direction of the array) are arranged in sequence, and in the second direction of the array (for example Figure 6 The first conductive type doping region 124, the gate structure 123 and the second conductive type doping region 125 are three rows as a cycle unit, and the first direction intersects the second direction, and between two adjacent gate structures 123 along the first direction is the first conductive type doping region 124 or the second conductive type doping region 125. Figure 6 As shown, in this embodiment, the first direction X is preferably perpendicular to the second direction Y. This arrangement is the most densely packed MOS transistor arrangement, and the area between two adjacent gate structures 123 corresponds to the doping width of the first conductivity type doping region 124 or the second conductivity type doping region 125. Therefore, if a problem occurs in the process of the gate structure 123, causing the doping width of the first conductivity type doping region 124 or the second conductivity type doping region 125 to change, the problem can be detected by testing the leakage current of the junction between the first conductivity type doping region 124 and the second conductivity type doping region 125.

[0079] As an example, Figure 7As shown, in order to ensure the effect of ion doping of the first conductive type doping region 124 or the second conductive type doping region 125, ion doping is fully achieved in these regions. Therefore, during the ion implantation process, the range of ion implantation is greater than the width of the first conductive type doping region 124 and the second conductive type doping region 125, and extends to a partial width region of the gate structure 123, as shown in FIG. Figure 7 As shown by the arrows in , ion implantation of the first conductive type doping region 124 and the second conductive type doping region 125 is performed starting from the middle region in the width direction of two adjacent gate structures 123 .

[0080] The first test pad 126 and the second test pad 127 are made of conventional metal electrode materials, and their widths are generally smaller than the widths of the corresponding first conductivity type doped regions 124 and second conductivity type doped regions 125. The first test pad 126 and the second test pad 127 serve as electrode lead-out structures for the first conductivity type doped regions 124 and the second conductivity type doped regions 125, respectively, and as access points for subsequent circuit structures.

[0081] This embodiment further provides a test method for monitoring MOS transistor junction performance. The test method is applied to the above-mentioned electrical test structure for monitoring MOS transistor junction performance, and specifically includes the following steps:

[0082] S1, such as Figure 4 and Figure 6 As shown, an electrical test structure for monitoring MOS tube junction performance as described above is provided;

[0083] S2, such as Figure 8 and Figure 9 As shown, the same required voltage is applied to the first test pad 126 and the second test pad 127 in each of the test units 120 to form a test circuit;

[0084] S3, collecting test results in the test circuit.

[0085] What needs to be explained here is Figure 8 To facilitate understanding of the structure of the test unit 120, the structures of the first test pad 126 and the second test pad 127 are omitted. In practice, the first test pad 126 and the second test pad 127 are respectively formed on the surfaces of the first conductivity type doped region 124 and the second conductivity type doped region 125. When a voltage is applied, it is applied to the first test pad 126 and the second test pad 127 respectively.

[0086] When the test units 120 in the electrical test structure 12 are arranged in an array, as shown in FIG. Figure 8 and Figure 9As shown, the first test pads 126 (i.e., the first conductivity type doped regions 124) of all test cells 120 are commonly connected to the second voltage 17 of PAD2, and the second test pads 127 (i.e., the second conductivity type doped regions 125) of all test cells 120 are commonly connected to the first voltage 16 of PAD1. When the second voltage 17 of PAD2 and the first voltage 16 of PAD1 are applied, it is equivalent to applying the second voltage 17 to the first test pads 126 of all test cells 120 and applying the first voltage 16 to the second test pads 127 of all test cells 120.

[0087] The test method of this embodiment can monitor the junction capacitance, junction breakdown voltage and junction leakage current of the MOS tube. Figure 8 and Figure 9 As shown, the well layer 122 is defined as N-type doping, the first conductive type doping region 124 is defined as N-type doping, and the second conductive type doping region 125 is defined as P-type doping.

[0088] When monitoring the junction capacitance of the MOS tube, an AC second voltage of 0V to 45mV is applied to the first test pad 126 on the N-type doped first conductive type doping region 124, and a DC first voltage of 0V is applied to the second test pad 127 on the P-type doped second conductive type doping region 125. A test circuit is formed between the first voltage and the second voltage, and the capacitance value in the test circuit is collected to obtain the junction capacitance between the P-type doped second conductive type doping region 125 and the N-type doped well layer 122. When the measured value of the junction capacitance exceeds a preset value, it indicates that there is a problem with the related process. Similarly, on the contrary, when the well layer 122 is P-type doped, the first conductive type doped region 124 is P-type doped, and the second conductive type doped region 125 is N-type doped, when monitoring the junction capacitance of the MOS tube, a second voltage of DC 0V is applied to the first test pad 126 on the P-type doped first conductive type doped region 124, and an AC first voltage of 0V to 45mV is applied to the second test pad 127 on the N-type doped second conductive type doped region 125. A test circuit is formed between the first voltage and the second voltage, and the capacitance value in the test circuit is collected to obtain the junction capacitance between the N-type doped second conductive type doped region 125 and the P-type doped well layer 122.

[0089] When monitoring the junction breakdown voltage of a MOS transistor, a first voltage of 0V DC is applied to the second test pad 127 on the P-type doped second conductivity type doped region 125, and a second voltage is applied to the first test pad 126 on the N-type doped first conductivity type doped region 124. The second voltage is gradually increased from 0V in a fixed step size, and the current at the port of the first test pad 126 is measured each time the second voltage increases. When the measured current reaches a jump point, the corresponding second voltage is the junction breakdown voltage between the P-type doped second conductivity type doped region 125 and the N-type doped well layer 122. When the junction breakdown voltage exceeds a preset value, it indicates a problem with the related process. Similarly, on the contrary, when the well layer 122 is P-type doped, the first conductive type doped region 124 is P-type doped, and the second conductive type doped region 125 is N-type doped, when monitoring the junction breakdown voltage of the MOS tube, a second voltage of DC 0V is applied to the first test pad 126 on the P-type doped first conductive type doped region 124, and a first voltage is applied to the second test pad 127 on the N-type doped second conductive type doped region 125. The first voltage starts from 0V and gradually increases with a fixed step size, and the current at the port of the second test pad 127 is measured each time it increases. When the measured current jumps, the corresponding first voltage is the junction breakdown voltage between the N-type doped second conductive type doped region 125 and the P-type doped well layer 122.

[0090] When monitoring the junction leakage current of the MOS transistor, a first voltage of DC 0V is applied to the second test pad 127 on the P-type doped second conductivity type doped region 125, and a second voltage of DC Vdd is applied to the first test pad 126 on the N-type doped first conductivity type doped region 124. A test circuit is formed between the first and second voltages, and the current value in the test circuit is collected to obtain the leakage current between the P-type doped second conductivity type doped region 125 and the N-type doped well layer 122. When the measured leakage current value exceeds a preset value, it indicates a problem with the related process. Similarly, on the contrary, when the well layer 122 is P-type doped, the first conductive type doping region 124 is P-type doped, and the second conductive type doping region 125 is N-type doped, when monitoring the junction leakage current of the MOS tube, a first voltage of DC Vdd is applied to the second test pad 127 on the N-type doped second conductive type doping region 125, and a second voltage of DC 0V is applied to the first test pad 126 on the P-type doped first conductive type doping region 124. A test circuit is formed between the first voltage and the second voltage, and the current value in the test circuit is collected to obtain the leakage current between the N-type doped second conductive type doping region 125 and the P-type doped well layer 122.

[0091] In summary, the present invention provides an electrical test structure and test method for monitoring MOS transistor junction performance. By providing a test unit, the test unit structure has a structure similar to that of a MOS transistor, namely, including a substrate layer, a well layer, a gate structure, a doped region, and a test pad. However, the doped region is divided into two regions of opposite doping types, namely, first and second conductivity type doped regions. By applying different required voltages to the first and second test pads, the junction capacitance, junction breakdown voltage, and junction leakage current between the first and second conductivity type doped regions and the well layer can be monitored, thereby achieving comprehensive monitoring of the MOS transistor junction structural characteristics. Through process reliability testing, the junction capacitance, junction breakdown voltage, and junction leakage current of the MOS transistor junction can be effectively monitored, allowing risk screening of related processes in the MOS transistor manufacturing process. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. An electrical test structure for monitoring MOS tube junction performance, characterized in that: The electrical test structure includes: A test unit is provided on a base wafer, wherein the base wafer includes a chip area and a test area between the chip areas; The testing unit is located on the testing area; The test unit includes, from bottom to top, a substrate layer, a well layer and a gate structure, and also includes a first conductive type doped region and a second conductive type doped region and a first test pad and a second test pad formed on the surfaces of the first conductive type doped region and the second conductive type doped region, respectively; wherein the first conductive type doped region and the second conductive type doped region are arranged on both sides of the gate structure and extend inward from the surface of the well layer to a preset depth, and the conductivity type of the first conductive type doped region and the second conductive type doped region are opposite.

2. The electrical test structure for monitoring MOS transistor junction performance according to claim 1, characterized in that: The widths of the first conductive type doping region and the second conductive type doping region are the minimum allowable values ​​of the design rules, and the direction of the width is defined as the direction along which the first conductive type doping region, the gate structure and the second conductive type doping region are arranged in sequence.

3. The electrical test structure for monitoring MOS transistor junction performance according to claim 1, characterized in that: The width of the first conductive type doping region and the second conductive type doping region is 100 nm to 300 nm, and the direction of the width is defined as the direction along which the first conductive type doping region, the gate structure and the second conductive type doping region are arranged in sequence.

4. The electrical test structure for monitoring MOS transistor junction performance according to claim 1, wherein: The gate structure includes a gate dielectric layer, a gate polycrystalline layer and a gate sidewall.

5. The electrical test structure for monitoring MOS transistor junction performance according to claim 1, wherein: The first conductive type doping region is an N-type doping region or a P-type doping region, and the second conductive type doping region is a P-type doping region or an N-type doping region.

6. The electrical test structure for monitoring MOS transistor junction performance according to claim 1, wherein: The shape and size of the gate structure in the test unit are the same as the shape and size of the gate structure of the MOS device in the chip area; the doping concentration and doping depth of the first conductive type doping region and the second conductive type doping region in the test unit are the same as the doping concentration and doping depth of the source / drain of the MOS device in the chip area.

7. The electrical test structure for monitoring MOS transistor junction performance according to claim 1, characterized in that: The number of the test units is more than 2.

8. The electrical test structure for monitoring MOS transistor junction performance according to claim 7, characterized in that: The test units are arranged in an M×N array, where M and N are both natural numbers, and M≥2 or N≥2; wherein the first conductive type doping region, the gate structure and the second conductive type doping region of the test unit are arranged in sequence along the first direction of the array, and in the second direction of the array, three columns consisting of the first conductive type doping region, the gate structure and the second conductive type doping region are repeated in sequence as cycle units, the first direction intersects with the second direction, and the first conductive type doping region or the second conductive type doping region is between two adjacent gate structures along the first direction.

9. A test method for monitoring MOS tube junction performance, characterized in that: The test method includes: Providing an electrical test structure for monitoring MOS tube junction performance according to any one of claims 1 to 8; Applying the same required voltage to the first test pad and the second test pad in each of the test units to form a test circuit; Acquire test results from the test circuit.

10. The test method for monitoring MOS transistor junction performance according to claim 9, characterized in that: The test method is used to test the junction capacitance, junction breakdown voltage and junction leakage current of a MOS tube.

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