Fault-tolerant control method for open-circuit fault of parallel rectifiers

Abstract

The invention discloses a fault-tolerant control method for an open-circuit fault of a parallel rectifier. The fault-tolerant control method comprises the following steps: constructing a common direct-current link system comprising double parallel rectifiers; establishing a three-level space vector relation model based on the switch state combination; dividing a voltage space into six main sectors and nineteen voltage vectors, and selecting adjacent voltage vectors for synthesis according to the sector where the reference voltage vector Vref is located; detecting the open-circuit fault type, and judging the influence of the fault on the switching state based on the phase current direction; when an open-circuit fault is detected, adjusting a space vector synthesis strategy according to an affected voltage sector corresponding to a fault mode; adjusting a power grid current vector and a reference voltage vector to be kept in phase by injecting reactive current; for multiple switch fault modes, a superposed fault-tolerant control strategy is adopted, and reference voltage vector compensation is realized by modifying a switch state sequence and adjusting vector action time. The method has the advantages of strong fault-tolerant capability, good harmonic suppression effect, high system reliability and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power system fault control, in particular to a fault-tolerant control method and system for open-circuit fault of parallel rectifier. BACKGROUND

[0002] Two parallel three-phase PWM rectifiers as key devices in high-power application scenarios play an important role in the fields of wind power grid-connected system, electric vehicle charging station and industrial uninterruptible power supply, etc. Although this kind of parallel structure can improve the system power capacity and operating efficiency, it is prone to open-circuit fault in actual operation due to the long-term high-frequency switching state of the switching devices. Especially when multiple switches fail at the same time, the traditional fault-tolerant control strategy often fails to maintain stable operation of the system, resulting in a decline in power quality or even system shutdown.

[0003] Current solutions for converter open-circuit fault mainly include hardware redundancy and software fault tolerance. Although the hardware redundancy scheme can achieve rapid fault isolation, it requires additional power switching devices and supporting circuits, significantly increasing the system cost and volume. Existing software fault tolerance methods are mostly designed for a single converter, achieving fault tolerance by improving the space vector modulation strategy or adjusting the reference voltage vector. These methods have obvious limitations when applied to parallel rectifier systems: on the one hand, they fail to fully consider the mutual influence between parallel units, and on the other hand, they lack effective measures to deal with the superposition effect of multiple switch faults.

[0004] In terms of parallel rectifier control architecture, the existing decentralized control is difficult to achieve coordinated operation in fault state, while the traditional centralized control has better coordination, but its fault tolerance strategy often only considers single fault mode. Especially when multiple switch faults occur in the system, the existing methods are difficult to accurately divide the fault influence area, resulting in deviation in voltage vector synthesis, and further causing DC side voltage fluctuation and current imbalance, etc. In addition, the existing technology also has a simple treatment of the voltage and current vector coupling relationship in fault state, and fails to effectively solve the control error caused by the vector lag angle.

[0005] In view of the above problems, the existing technology needs to be improved. SUMMARY

[0006] Therefore, the present application provides a fault-tolerant control method and system for open-circuit fault of parallel rectifier, which has the advantages of effectively dealing with multiple switch open-circuit faults, accurately dividing the fault influence area, realizing dynamic voltage vector compensation and maintaining stable operation of the system.

[0007] The present application provides a fault-tolerant control method for open-circuit fault of parallel rectifier, comprising:

[0008] S1, a common DC link system comprising a first rectifier and a second rectifier in parallel is constructed; wherein each rectifier generates an equivalent three-level voltage state through a combination of three-phase bridge arm switches;

[0009] S2, a three-level space vector modulation model based on switch state combination is established, the parallel rectifiers are equivalent to a three-level rectifier, and P, O1, O2, N four switch states and corresponding voltage levels are defined;

[0010] S3, the voltage space is divided into six main sectors and nineteen voltage vectors, and according to the sector where the reference voltage vector V ref is located, adjacent voltage vectors are selected for synthesis;

[0011] S4, the open-circuit fault type of the rectifier switch is detected, including single switch, double switch and three switch fault modes, and the influence of the fault on the switch state is judged based on the phase current direction;

[0012] S5, when the open-circuit fault is detected, the space vector synthesis strategy is adjusted according to the affected voltage sector corresponding to the fault mode: the original modulation strategy is maintained in the white sector not affected by the fault, and the compensation vector sequence is used in the colored sector affected by the fault;

[0013] S6, the grid current vector phase is adjusted by injecting reactive current to make the reference voltage vector and the grid current vector in phase, and eliminate the boundary error caused by the vector lag angle;

[0014] S7, for multiple switch fault modes, a superimposed fault-tolerant control strategy is adopted, and the reference voltage vector compensation is realized by modifying the switch state sequence and adjusting the vector action time.

[0015] In an optional embodiment, when the three-level space vector relationship model is established, the switch state combination of the first rectifier and the second rectifier satisfies:

[0016] When the upper switches of the two rectifiers in the same phase arm are both turned on, it is equivalent to P state and outputs +U dc / 2 voltage;

[0017] When the lower switches of the two rectifiers in the same phase arm are both turned on, it is equivalent to N state and outputs-U dc / 2 voltage;

[0018] When the switch states of the two rectifiers in the same phase arm are opposite, it is equivalent to O state and outputs zero voltage; wherein the upper switch of the first rectifier is turned on and recorded as O1 state, and the upper switch of the second rectifier is turned on and recorded as O2 state.

[0019] In an optional embodiment, the specific implementation steps of the three-level space vector relationship model include:

[0020] The voltage space is divided into a complex plane coordinate system containing six main sectors, each of which is further subdivided into six sub-sectors;

[0021] According to the sub-sector where the reference voltage vector is located, three adjacent voltage vectors are selected for linear combination to meet V ref = (V l *T l + V m *T m + V n *T n ) / T s ; wherein V l , V m , V n are three adjacent voltage vectors; T l , T m , T n are the turn-on times of V l , V m , V n ;

[0022] For each switching period T s , the turn-on time of each voltage vector is allocated according to the preset vector action time sequence.

[0023] In an alternative embodiment, the S4 comprises: establishing a correspondence table of twelve basic switching fault modes and voltage vector deviation;

[0024] By real-time monitoring of the matching degree of the phase current direction and the switching state, the specific fault switching position is determined;

[0025] According to the position of the fault switching in the bridge arm and the direction of the phase current, the affected equivalent three-level state transition relationship is determined.

[0026] 5. The method of claim 1, wherein the reactive current calculation step is:

[0027] The dynamic equation of the grid voltage and the grid current in the dq0 rotating coordinate system is established;

[0028] By solving a cubic equation containing equivalent inductance parameters, the q-axis current component i gq to be injected is calculated;

[0029] The output of the current controller is adjusted to eliminate the phase deviation between the grid current vector and the reference voltage vector;

[0030] Wherein, the calculation expression of the reactive current is:

[0031]

[0032] Leq = L g + L1 / 2

[0033]

[0034] wherein ω s is the grid voltage frequency; L g is the grid inductance; L1 is the AC measurement inductance of the rectifier; i gq is the injected q-axis current; i gd is the d-axis grid current; u gd is the d-axis grid voltage.

[0035] In an alternative embodiment, the S6 further comprises: when an open-circuit fault is detected, adjusting the space vector synthesis strategy according to the affected voltage sector corresponding to the fault mode: keeping the original modulation strategy in the white sector not affected by the fault, and adopting a compensation vector sequence in the affected color sector.

[0036] In an alternative embodiment, the superimposed fault-tolerant control strategy comprises:

[0037] For type II-1 double-switch fault, a vector sequence reconstruction technology is adopted in the overlapping affected area, and normal small vectors and zero vectors are adopted;

[0038] For type II-2 double-fault of the same bridge arm, a sector-independent compensation strategy is adopted, and the upper and lower bridge arm faults are processed respectively;

[0039] For type III-1 triple-switch fault, a three-level superimposed compensation algorithm is adopted, and the vector deviation corresponding to each fault switch is corrected step by step.

[0040] The present application has the following advantages:

[0041] The parallel rectifier open-circuit fault fault-tolerant control method provided by the present application effectively solves the technical problems of difficult coordination and processing of multiple switch faults, large vector synthesis deviation, poor system stability and the like in the prior art by establishing an equivalent three-level space vector relationship model, dividing a fault affected area, implementing dynamic vector compensation and multiple fault superimposition control, and has the advantages of strong fault tolerance, good harmonic suppression effect and high system reliability. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the following description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0043] Figure 1 is a flow chart of a fault-tolerant control method for open-circuit fault of a parallel rectifier according to an embodiment of the present application;

[0044] Figure 2 is a circuit schematic diagram of a two-level PWM rectifier with two common DC links according to an embodiment of the present application;

[0045] Figure 3 is a voltage space vector diagram including six main sectors according to an embodiment of the present application;

[0046] Figure 4 is a SVPWM synthesis schematic diagram of a reference voltage vector according to an embodiment of the present application; (a) is a SVPWM synthesis schematic diagram of a reference voltage vector located in sub-sector 1 and sub-sector 2; (b) is a SVPWM synthesis schematic diagram of a reference voltage vector located in sub-sector 3 and sub-sector 4; (c) is a SVPWM synthesis schematic diagram of a reference voltage vector located in sub-sector 5; (c) is a SVPWM synthesis schematic diagram of a reference voltage vector located in sub-sector 6;

[0047] Figure 5 is a voltage space vector diagram of each voltage vector under open-circuit fault of VT1 switch according to an embodiment of the present application;

[0048] Figure 6 is an effect diagram of vector deviation on voltage space sector under different fault modes according to an embodiment of the present application; (a) is an effect diagram of single open-circuit fault of VT1; (b) is an effect diagram of single open-circuit fault of VT3; (c) is an effect diagram of double open-circuit fault of VT1 and VT3; (d) is an effect diagram of double open-circuit fault of VT1 and VT4; (e) is an effect diagram of double open-circuit fault of VT1 and VT6; (f) is an effect diagram of three open-circuit fault of VT1, VT3 and VT5; (g) is an effect diagram of three open-circuit fault of VT1, VT3 and VT2; (h) is an effect diagram of double open-circuit fault of VT1, VT4 and VT3;

[0049] Figure 7 is an effect diagram of voltage space sector under current vector control according to an embodiment of the present application;

[0050] Figure 8 is an active vector compensation diagram according to an embodiment of the present application;

[0051] Figure 9 is a fault-tolerant control simulation result diagram under open-circuit fault of TV1 according to an embodiment of the present application; (a) is a grid current waveform diagram; (b) is a phase current waveform diagram of rectifier #1; (c) is a phase current waveform diagram of rectifier #2; (d) is a DC voltage waveform diagram.

[0052] Figure 10 Fig. 6 is a fault-tolerant control simulation result diagram under open-circuit fault of TV1, TV3 according to an embodiment of the present application; wherein (a) is a grid current waveform diagram; (b) is a phase current waveform diagram of rectifier #1; (c) is a phase current waveform diagram of rectifier #2; (d) is a DC voltage waveform diagram.

[0053] Figure 11 Fig. 7 is a fault-tolerant control simulation result diagram under open-circuit fault of TV1, TV4 according to an embodiment of the present application; wherein (a) is a grid current waveform diagram; (b) is a phase current waveform diagram of rectifier #1; (c) is a phase current waveform diagram of rectifier #2; (d) is a DC voltage waveform diagram.

[0054] Figure 12 Fig. 8 is a fault-tolerant control simulation result diagram under open-circuit fault of TV1, TV3, TV5 according to an embodiment of the present application; wherein (a) is a grid current waveform diagram; (b) is a phase current waveform diagram of rectifier #1; (c) is a phase current waveform diagram of rectifier #2; (d) is a DC voltage waveform diagram. DETAILED DESCRIPTION

[0055] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0056] In the prior art, two parallel three-phase PWM rectifiers are widely used in high-power scenarios to improve system capacity and efficiency. Existing fault-tolerant methods mainly aim at open-circuit fault of a single converter, and realize fault tolerance through hardware redundancy or improved modulation algorithm. However, the interaction of parallel rectifiers and the superposition effect of multiple switch faults have not been fully studied, and the traditional decentralized control architecture is difficult to coordinate the vector synthesis after the fault, and the centralized architecture can unify the control but lacks compensation strategies under multiple fault modes. The existing methods have technical bottlenecks in voltage vector phase deviation processing, multiple fault region division and zero vector balance maintenance.

[0057] To solve the above problems, research finds that parallel rectifier will produce voltage vector offset when open circuit fault occurs, leading to the failure of traditional space vector modulation. By analyzing the influence law of different fault modes on voltage space sector, it is realized that the superposition effect of multi-switch fault needs to be quantified by establishing a vector relationship model. To solve the phase deviation problem, it is proposed to realize the phase alignment of voltage and current vectors by injecting reactive current. For the problem of multi-fault region division, an improved SVPWM scheme is adopted to generate a specific switch sequence. Finally, a fault-tolerant control method based on vector model analysis, phase adjustment and dynamic compensation is formed.

[0058] Therefore, the application proposes a fault-tolerant control method for open circuit fault of parallel rectifier, which includes establishing a space vector relationship model of parallel rectifier, determining the voltage space sector offset corresponding to different open circuit fault modes; according to the lag angle of current vector and voltage vector, the reactive current is injected by adjusting the grid current vector to eliminate the phase deviation between the voltage synthesis boundary and the vector compensation boundary; based on the affected voltage space sector, an improved space vector pulse width modulation scheme is used to generate a fault-tolerant switch sequence; according to the number and position of fault switches, the proportion of active vector compensation in the fault-tolerant switch sequence is adjusted, and the zero vector state affected by the fault is replaced.

[0059] Compared with the prior art, the traditional method can only handle a single fault mode and cannot eliminate the phase deviation, while the present scheme realizes accurate quantification of multiple fault modes through a vector relationship model. The prior art uses a fixed compensation strategy, which fails when multiple faults are superimposed. The present scheme can cope with the cross effects of different types of faults by dynamically adjusting the compensation ratio and vector sequence reconstruction. Compared with the redundancy scheme which requires hardware modification, the present method can realize multi-fault tolerance through control algorithm improvement, reducing the implementation cost.

[0060] Through the above technical solutions, the present application effectively solves the vector synthesis distortion problem of parallel rectifier under multi-switch fault, and maintains the normal operation ability in fault state. By eliminating the phase deviation of voltage and current, the compensation error caused by the lag angle in the traditional method is avoided. The dynamically adjusted vector compensation strategy can adapt to the superimposition effect of different fault modes, solving the technical problem of unavailable vectors in multi-fault region. Replacing the affected zero vector state ensures the stability of the DC bus voltage and reduces the risk of current imbalance caused by faults.

[0061] As shown in Figure 1 The present application provides a fault-tolerant control method for open circuit fault of parallel rectifier, which includes:

[0062] Step S1, a common DC link system containing a parallel first rectifier and a second rectifier is constructed; wherein each rectifier generates an equivalent three-level voltage state through a three-phase bridge arm switch combination.

[0063] Step S2: Establish a three-level space vector relationship model based on the switch state combination, treat the parallel rectifier as an equivalent three-level rectifier, and define four switch states of P, O1, O2, and N and their corresponding voltage levels.

[0064] In an optional implementation, when establishing the three-level space vector relationship model, the switching state combination of the first rectifier and the second rectifier satisfies:

[0065] When the upper switches of the same phase bridge arms of the two rectifiers are turned on, it is equivalent to the P state and outputs +U dc / 2 voltage;

[0066] When the lower switches of the same phase bridge arms of the two rectifiers are turned on, it is equivalent to the N state and outputs -U dc / 2 voltage;

[0067] When the switch states of the same-phase bridge arms of the two rectifiers are opposite, it is equivalent to the O state and outputs zero voltage; among them, when the switch on the first rectifier is turned on, it is recorded as the O1 state, and when the switch on the second rectifier is turned on, it is recorded as the O2 state.

[0068] Specifically, such as Figure 2 As shown in FIG, a two-level PWM rectifier with two common DC links is shown, including a rectifier #1 (first rectifier) ​​and a rectifier #2 (second rectifier) ​​connected in parallel. ga 、u gb 、u gc The parallel rectifier generates an equivalent three-phase voltage u through the switch combination a0 、u b0 、u c0 ,u a1 、u b1 、u c1 and u a2 、u b2 、u c2 The filter is equivalent to the inductor L g , L1 and L2; and, L1 and L2 have the same value. C is the DC bus capacitor, U dc is the DC bus voltage. VT1-VT 12 D1-D is the switch of the parallel rectifier. 12 is a freewheeling diode. Define the current i flowing out of the AC grid as ga 、i gb 、i gc ,i a1 、i b1 、i c1 and i a2 、i b2 、i c2 The direction is positive.

[0069] For a single rectifier (rectifier #1 or rectifier #2), the switch states of the upper and lower parts of the same bridge arm must be opposite to prevent short circuit. For example: when VT1 of the phase a bridge arm of rectifier #1 is on, VT4 belonging to the same bridge arm must be off. When the upper switch of a three-phase bridge arm is on and the lower switch is off, the switch state is recorded as "1". Conversely, when the upper switch of a three-phase bridge arm is off and the lower switch is on, the switch state is recorded as "0".

[0070] Therefore, according to the switch state combination of the two rectifiers, the two parallel two-level PWM rectifiers can further work as a three-level PWM rectifier. As shown in Table 1, the switch states and corresponding voltages of the two parallel rectifiers in phase x (x = a, b, c) are shown, as well as the switch states and corresponding voltages of the equivalent three-level rectifier. When the switch states of rectifier #1 and rectifier #2 are both "1", the switch state of the equivalent three-level rectifier is recorded as "P", and the corresponding voltage is U dc / 2; when the switch states of rectifier #1 and rectifier #2 are both "0", the switch state of the equivalent three-level rectifier is recorded as "N", and the corresponding voltage is -U dc / 2; when the switch states of rectifier #1 and rectifier #2 exist one "0" and the other "1", the switch state of the equivalent three-level rectifier is recorded as "O". Among them, the switch state "O" of the equivalent three-level rectifier can be further divided into two symmetrical cases "O1" and "O2". "O1" corresponds to the switch state of rectifier #1 being "1" and the switch state of rectifier #2 being "0"; "O2" corresponds to the switch state of rectifier #1 being "0" and the switch state of rectifier #2 being "1". The corresponding voltages of the equivalent three-level rectifier in the above two symmetrical cases are both 0.

[0071] Table 1

[0072]

[0073] S3, divide the voltage space vector into six main sectors and nineteen voltage vectors, and select adjacent voltage vectors to be synthesized according to the sector where the reference voltage vector V ref is located.

[0074] In an optional embodiment, the specific implementation steps of the three-level space vector relationship model include:

[0075] Divide the voltage space into a complex plane coordinate system containing six main sectors, and each main sector is further divided into six sub-sectors;

[0076] According to the sub-sector where the reference voltage vector is located, select three adjacent voltage vectors to be linearly combined, satisfying V ref = (V l *Tl +V m *T m +V n *T n ) / T s The synthetic relationship of l 、V m 、V n are three adjacent voltage vectors; T l 、T m 、T n V l 、V m 、V n On-time;

[0077] For each switching cycle T s , the conduction time of each voltage vector is allocated according to the preset vector action time sequence.

[0078] Specifically, such as Figure 3 As shown in the figure, the voltage space is divided into six sectors (Ⅰ, Ⅱ, Ⅲ, Ⅳ, Ⅴ, Ⅵ) and 19 voltage vectors (V0-V 18 ), each voltage vector corresponds to 1-3 groups of switch states. Among them, the voltage vectors V2, V3, V5, V6, V8, V9, V 11 、V 12 、V 14 、V 15 、V 17 、V 18 Each corresponds to a set of switch states. Among them, the voltage vectors V1, V4, V7, V 10 、V 13 、V 16 The inner and outer hexagons share a center point, and the voltage vector V0 at the center point corresponds to three sets of switch states.

[0079] The reference voltage vector V is synthesized by three adjacent voltage vectors ref for:

[0080]

[0081] Among them, V l 、V m 、V n are three adjacent voltage vectors; T l 、T m 、T n V l 、V m 、V n The on-time, T s is the switching cycle.

[0082] As Figure 4 shown, the basic SVPWM synthesis method of reference voltage vector V ref is demonstrated. Take sector I as an example, it can be further divided into 6 sub-sectors. Among them, as shown in Figure 4 (a), the reference voltage vector V ref is located in sub-sector 1 and sub-sector 2, then the adjacent voltage vectors V0, V1 and V4 are used to synthesize the reference voltage vector V ref ; as shown in Figure 4 (b), the reference voltage vector V ref is located in sub-sector 3 and sub-sector 4, then the adjacent voltage vectors V1, V3 and V4 are used to synthesize the reference voltage vector V ref ; as shown in Figure 4 (c), the reference voltage vector V ref is located in sub-sector 5, then the adjacent voltage vectors V1, V2 and V3 are used to synthesize the reference voltage vector V ref ; as shown in Figure 4 (d), the reference voltage vector V ref is located in sub-sector 6, then the adjacent voltage vectors V3, V4 and V5 are used to synthesize the reference voltage vector V ref .

[0083] It should be noted that since the three adjacent voltage vectors used correspond to different switching states, these switching states also need to be reasonably allocated to reduce harmonic and zero sequence circulating current.

[0084] The reference voltage vector V ref synthesized by different voltage vectors V l , V m , V n is actually the equivalent three-phase voltage of the rectifier AC side synthesized by different switching states. Among them, the relationship between the voltage, current and reference voltage of the AC grid side on the dq0 axis is as follows:

[0085]

[0086] Among them, ω s is the grid voltage frequency, u gd is the d-axis grid voltage, i gd , i gq are the d-axis and q-axis grid currents, u d0 , u q0 are the d-axis and q-axis equivalent voltages of the parallel rectifier, u d1 , u q1 are the d-axis and q-axis AC equivalent voltages of rectifier #1, u d2 , uq2 are the d-axis and q-axis ac equivalent voltages of rectifier #2, respectively.

[0087] Under unity power factor control, i gq is controlled to be zero. In dq0 frame, the steady-state condition can be expressed as:

[0088]

[0089] Step S4, detecting the rectifier switch open-circuit fault type, including single switch, double switch and three switch fault modes, and judging the influence of the fault on the switch state based on the phase current direction.

[0090] In an optional embodiment, step S4 includes:

[0091] establishing a correspondence table of twelve basic switch fault modes and voltage vector deviation;

[0092] judging the specific fault switch position by real-time monitoring of the matching degree of the phase current direction and the switch state;

[0093] determining the affected equivalent three-level state transition relationship according to the position of the fault switch in the bridge arm and the phase current direction.

[0094] Specifically, when the upper switches VT1, VT3 and VT5 of rectifier #1 have open-circuit faults, and the corresponding phase current i n0 >0 (n=a, b, c), the freewheeling diodes D1, D3 and D5 of the upper bridge arm allow current to flow through the load. The rectifier can still operate normally. However, when the phase current i n <0, the faulty upper switch forces the phase current to flow through the freewheeling diodes D2, D4 and D6 of the lower bridge arm. The switch state is equivalent to changing from "1" to "0", affecting the synthesis of voltage space vectors. When the lower switches VT4, VT6 and VT2 have open-circuit faults, and the corresponding phase current i n0 >0 (n=a, b, c), the switch state changes from "0" to "1". The switch state of the equivalent three-level rectifier also changes from P to O2, O1 to N. The open-circuit fault analysis of rectifier #2 is the same, and will not be repeated here. Specifically, the changes of the switch state under switch faults are shown in Table 2 after sorting.

[0095] Table 2

[0096]

[0097]

[0098] The grid voltage vector V g , the grid current vector I g , the reference voltage vector Vref and voltage vector V of rectifier #1 c1 , voltage vector V of rectifier #2 c2 are shown in the voltage space vector diagram as Figure 5 Since using the affected switching state vector will produce distortion, Figure 5 shows the affected sectors under VT1 switch open-circuit fault. When VT1 switch fails, if i a0 <0, V c1 will rotate to these affected sectors (corresponding to the red sectors in Figure 5 ), and all voltage vectors corresponding to “P” and “O1” states in one phase will be affected. However, if i a0 >0 and V c1 rotates to the white sector, the freewheeling diode D1 allows the phase current to flow, and the voltage vector remains normal. However, the fault boundary will vary with the calculated current amplitude, which may affect the fault-tolerant application range in the vector space.

[0099] Single-switch and multi-switch open-circuit faults are divided into multiple modes, such as the six representative fault modes shown in Table 3. Single-switch open-circuit faults in the upper or lower part of the bridge are type I. Double-switch faults include three cases: both fault switches are located in the upper or lower part of different bridges (i.e., type II-1), both fault switches are located in the same bridge (i.e., type II-2), and the two fault switches are located in the upper and lower parts of different bridges, respectively (i.e., type II-3). Triple-switch faults also include three cases: three fault switches are located in the upper or lower part of different bridges (i.e., type III-1), three fault switches are located in the lower and upper parts of three different bridges, respectively (i.e., type III-2), and three fault switches are located in two bridges (i.e., type III-3).

[0100] Table 3

[0101]

[0102]

[0103] As shown in Figure 6 , the influence of vector deviation on voltage space sectors under different fault modes is shown. To correctly analyze the distortion, the direction of the phase current and the lag angle of the reference vector should be considered. Different fault regions are marked with different colors. The overlapping parts affected by double and triple fault switches are represented by purple and gray, respectively. Single-switch fault affects half of the voltage vector space. Double-switch fault may affect 8 / 12, 10 / 12, or even the entire vector space. Triple-switch fault may affect 10 / 12 or the entire vector space. The boundaries of the fault sectors are different from those of the voltage synthesis sectors, because the affected division of the vector space is determined by the vector, V c1 , Vc2 The lag angle and the three-phase current direction together determine the sector. Therefore, it is important to consider the phase current direction and improve the voltage synthesis method in the voltage space to reduce the impact of switching faults on the affected voltage space sector.

[0104] S5, adjusting the grid current vector phase by injecting reactive current, keeping the reference voltage vector and the grid current vector in phase, eliminating the boundary error caused by the vector lag angle.

[0105] Specifically, V c1 and the lag angle of I g will introduce boundary errors between the voltage synthesis sector and the affected sector. By injecting reactive current, I g can be in phase with V ref . Through the original segmentation method of voltage synthesis, the affected area boundary can be clearly separated. Figure 7 The sectors affected by the current vector adjustment control are shown. The impact of open circuit fault on the phase current is evenly distributed in the voltage space, and the fault impact becomes symmetrical.

[0106] The reactive current that needs to be injected is calculated by similar triangles, and its expression is:

[0107]

[0108] Where, L eq = L g + L1 / 2;

[0109] Solving equations (4) and (5) together, we get a cubic equation with unknown i gq :

[0110]

[0111] Since u d0 should not be zero, the equation can be further simplified by ignoring unreasonable solutions:

[0112]

[0113] At the same time, L eq satisfies the following restrictions:

[0114]

[0115] From equation (7) and equation (8), the reactive current that needs to be injected can be obtained.

[0116] Where, ω s is the grid voltage frequency; L g is the grid inductance; L1 is the AC measurement inductance of the rectifier; i gq is the injected q-axis current; igd is the d-axis grid current; u gd is the d-axis grid voltage.

[0117] S6, for multiple switch fault modes, a superimposed fault-tolerant control strategy is adopted, and voltage vector compensation is achieved by modifying the switch state sequence and adjusting the vector action time.

[0118] In an optional embodiment, step S6 further comprises: when an open-circuit fault is detected, adjusting the space vector synthesis strategy according to the affected voltage sector corresponding to the fault mode: keeping the original modulation strategy in the white sector not affected by the fault, and adopting a compensation vector sequence in the affected colored sector.

[0119] In an optional embodiment, the superimposed fault-tolerant control strategy:

[0120] For type II-1 double switch fault, vector sequence reconstruction technology is adopted in the overlapping influence area, and normal small vectors and zero vectors are adopted;

[0121] For type II-2 double fault of the same bridge arm, a sector-independent compensation strategy is adopted to handle the upper and lower bridge arm faults respectively;

[0122] For type III-1 triple switch fault, a three-level superimposed compensation algorithm is adopted to correct the vector deviation corresponding to each fault switch step by step.

[0123] Specifically, after current vector regulation control is adopted, a fault-tolerant scheme can be executed according to the position of V ref . For type I fault modes listed in Table 3 and shown in Figure 7 , when V ref is in the white sector, the vector does not change and the voltage synthesis does not need to be compensated. When V ref reaches other colored sectors, vector deviation will occur, and fault-tolerant control should be adopted to maintain system performance. For example, when VT1 fails, fault-tolerant control is divided into two parts. In sectors III and IV, the affected V ref can be normally synthesized with the modified SVPWM, which has the same modulus and direction as the original V ref . Table 4 shows the fault-tolerant vector sequence in sector III. This sequence only uses the switch state with "N" in phase a, avoiding the fault states "P" and "O1". The switch period is divided into nine segments in sub-sectors 1, 2, 5 and 6, and eleven segments in sub-sectors 3 and 4, so that the states "O1" and "O2" are distributed symmetrically and the circulating current is reduced.

[0124] Table 4

[0125]

[0126] In the red area of ​​sectors II and V, V ref The initial synthesis is as follows:

[0127]

[0128] Among them, V ref-II-2 Represents the reference voltage vector of the second sub-sector in sector II, V ref-II-4 It represents the reference voltage vector of the 4th sub-sector in sector II. The rest of the definitions are similar and will not be repeated here.

[0129] Affected V4, V6, V 15 and V 16 Not applicable, because the state "O1" in phase a is affected and circulating current balance cannot be achieved. Use the following compensation method:

[0130]

[0131] Among them, V p-II-2 represents the compensation value of the reference voltage vector in the second sub-sector of sector II, V p-II-4 It represents the compensation value of the reference voltage vector located in the 4th sub-sector of sector II. The rest of the definitions are similar and will not be repeated here.

[0132] In sectors II and V, since there are only vectors V7, V8, V 13 and V 14 available, so only partial compensation can be performed in these sectors. It is difficult to synthesize V using vectors with the same direction ref The original coefficients α, β and γ are applied to the remaining normal vectors and the affected vectors are replaced by the remaining vectors. With this scheme, the total vector operation time before and after the fault is the same. From a geometric point of view, V7, V8, V 13 and V 14 The compensation ratio is based on the original V4, V6, V 16 and V 15 i a = Determined by the 0-axis projection component, such as Figure 8 As shown. p The modulus length and V ref The original modulus length is similar.

[0133] The double switch open circuit fault is summarized into three representative modes listed in Table 3. Type II-1 faults, such as VT1 and VT3 faults, can be divided into three different areas, such as Figure 6 (c) In the red and blue regions of the vector space, the fault mode is equivalent to the single switch fault of VT1 and VT3. However, the purple overlapping region shows the characteristics of double fault. ref In the overlapping region affected by the distortion active vector, Vref Initially synthesized as follows:

[0134]

[0135] Affected by the fault switch, V 12 and V 15 are unavailable because the state "O1" in phase a and phase b are both affected. V 10 the state "O1" in phase b and V 16 the state "O1" in phase a are both unavailable. The following compensation method is adopted:

[0136]

[0137] The compensation in sector V is the same as the single VT1 open-circuit fault. The II-1 type fault compensation can also be regarded as the superposition of the corresponding single switch fault compensation. One of the zero vectors "PPP" or "NNN" is still available for the fault compensation of V ref . For the II-2 type fault mode, such as VT1 and VT4 fault, the fault-tolerant scheme can be regarded as two separate single switch open-circuit fault tolerance, because the two fault switches located in the upper and lower parts of the same bridge arm will affect completely independent sectors, as shown in Figure 5 (d). Double switch faults do not affect the same sector at the same time. The division method of six large sectors and six small sectors can effectively separate the affected sectors from the unaffected sectors. Single switch fault tolerance control is performed separately in different sectors to compensate for the II-1 type case. The II-3 type fault mode simultaneously affects "P", "O1" in phase a and "N", "O2" in phase b, resulting in only "NPP", "NPO" and "NPN" vectors available. Neither small vectors nor zero vectors are available. Therefore, it is not possible to achieve ideal compensation for the reference voltage vector. Table III also lists three representative triple switch open-circuit fault modes. The III-1 type fault mode, such as VT1, VT3 and VT5 fault, is similar to the II-1 type fault. The zero vector as "NNN" is still available. The fault-tolerant control scheme can be regarded as the superposition of three corresponding single switch fault compensation. The fault-tolerant control method proposed by the present application is still applicable and can be implemented in different sectors. The III-2 type and III-3 type fault modes are similar to the II-3 type fault mode.

[0138] In order to verify the technical effect of the present application, a two-parallel three-phase rectifier system is established, and fault-tolerant control is performed on single fault switch, double fault switch and triple fault switch respectively. Among them, the parameters of the two-parallel three-phase rectifier system are shown in Table 5.

[0139] Table 5

[0140]

[0141]

[0142] (1) Single fault switch

[0143] As shown in FIG. 5A, Figure 9 the waveform results of the line current, phase currents of rectifier #1, phase currents of rectifier #2, and DC voltage under open circuit fault of TV1 are shown. After the fault occurs at 0.26 sec, the phase currents of rectifier #1 have positive DC components. As shown in FIG. 5B, Figure 9 (b), the assembly results in no negative current in phase a of rectifier #1, because negative current cannot flow through TV1. To keep the line current balanced, the phase currents of rectifier #2 have negative DC components. After using fault-tolerant control, the imbalance of phase currents is significantly reduced. The line current is slightly increased due to reactive current injection. The DC voltage ripple is increased due to current imbalance.

[0144] (2) Double fault switch

[0145] As shown in FIG. 6A, Figure 10 the waveform results of the line current, phase currents of rectifier #1, phase currents of rectifier #2, and DC voltage under open circuit fault of TV1, TV3 are shown as an example of type II-1. After the fault occurs at 0.26 sec, the a-phase and b-phase currents of rectifier #1 have positive DC components, resulting in no negative current, because negative current cannot flow through TV1 and TV3. Rectifier #2 provides negative DC components in a-phase and b-phase to keep the line current normal. After using fault-tolerant control, the imbalance of a-phase and b-phase currents is significantly reduced.

[0146] As shown in FIG. 7A, Figure 11 the waveform results of the line current, phase currents of rectifier #1, phase currents of rectifier #2, and DC voltage under open circuit fault of TV1, TV4 are shown as an example of type II-2. After the fault occurs at 0.26 sec, the phase currents of rectifier #1 produce severe distortion, because current cannot flow through TV1 and TV4. After using fault-tolerant control, the severe distortion of current is reconstructed. There are two parts in which the current is almost zero at the beginning and end of a half cycle. In these parts, the rate of change of the phase angle of current tends to zero, because the compensated vector still has error compared to the original vector.

[0147] (3) Triple fault switch

[0148] As shown in FIG. 8A, Figure 12TV1, TV3, TV5 under open-circuit fault, phase currents of rectifier #1, phase currents of rectifier #2, and DC voltage waveforms are shown as an example of type III-1. After the fault occurs at 0.26 s, all three phase currents of rectifier #1 produce positive DC components, resulting in no negative current because the negative current cannot flow through the upper switches. Rectifier #2 provides negative DC components to keep the grid current normal. After using fault tolerance, the current imbalance is significantly reduced. The DC voltage is always stable at the rated value.

[0149] Table 6 shows the performance of grid current, circulating current, and DC voltage under different switch faults. When the fault occurs, the grid current produced by the parallel rectifiers is not uniform. Therefore, the grid current will not have significant distortion. However, the zero-sequence current increases, resulting in excessive current on other switches. The proposed method can reduce the circulating current by at least 60%. The current total harmonic distortion and DC voltage ripple are still within an acceptable range.

[0150] Table 6

[0151]

[0152] While the embodiments of the present application have been described in connection with the preferred embodiments of the application, various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the application, and such modifications and variations are also within the scope of the application as defined by the appended claims.

Claims

1. A fault-tolerant control method for open-circuit faults of parallel rectifiers, characterized in that: include: S1. Constructing a common DC link system including a first rectifier and a second rectifier connected in parallel; wherein each rectifier generates an equivalent three-level voltage state through a three-phase bridge arm switch combination; S2. Establish a three-level space vector relationship model based on the combination of switch states, equating the parallel rectifier to a three-level rectifier, and define the four switch states of P, O1, O2, and N and their corresponding voltage levels; S3, divide the voltage space into six main sectors and nineteen voltage vectors, according to the reference voltage vector V ref The adjacent voltage vectors are selected for synthesis in the sector; S4. Detect the type of rectifier switch open circuit fault, including single-switch, double-switch, and triple-switch fault modes, and determine the impact of the fault on the switch state based on the phase current direction; S5. Adjust the grid current vector phase by injecting reactive current so that the reference voltage vector and the grid current vector remain in phase, eliminating the boundary error caused by the vector lag angle; S6. For multiple switch fault types, a superposition fault-tolerant control strategy is adopted to achieve reference voltage vector compensation by modifying the switch state sequence and adjusting the vector action time.

2. The method according to claim 1, characterized in that When establishing a three-level space vector relationship model, the switching state combination of the first rectifier and the second rectifier satisfies: When the upper switches of the same phase bridge arms of the two rectifiers are turned on, it is equivalent to the P state and outputs +U dc / 2 voltage; When the lower switches of the same phase bridge arms of the two rectifiers are turned on, it is equivalent to the N state and outputs -U dc / 2 voltage; When the switch states of the same-phase bridge arms of the two rectifiers are opposite, it is equivalent to the O state and outputs zero voltage; among them, when the switch on the first rectifier is turned on, it is recorded as the O1 state, and when the switch on the second rectifier is turned on, it is recorded as the O2 state.

3. The method according to claim 1, characterized in that The specific implementation steps of the three-level space vector relationship model include: The voltage space is divided into a complex plane coordinate system consisting of six main sectors, each of which is further subdivided into six sub-sectors; According to the sub-sector where the reference voltage vector is located, three adjacent voltage vectors are selected for linear combination to satisfy V ref =(V l *T l +V m *T m +V n *T n ) / T s The synthetic relationship of l 、V m 、V n are three adjacent voltage vectors; T l 、T m 、T n V l 、V m 、V n On-time; For each switching cycle T s , the conduction time of each voltage vector is allocated according to the preset vector action time sequence.

4. The method according to claim 1, wherein The S4 includes: establishing a corresponding relationship table between twelve basic switch failure modes and voltage vector deviations; By real-time monitoring of the phase current direction and the matching degree of the switch status, the specific fault switch position can be determined; According to the position of the bridge arm where the fault switch is located and the direction of the phase current, the affected equivalent three-level state conversion relationship is determined.

5. The method according to claim 1, wherein The calculation steps of the reactive current are: Establish the dynamic equations of grid voltage and grid current in the dq0 rotating coordinate system; By solving the cubic equation containing the equivalent inductance parameters, the q-axis current component i that needs to be injected is calculated gq ; Adjust the current controller output to make the system operate at unity power factor and eliminate the phase deviation between the grid current vector and the reference voltage vector; Among them, the calculation expression of reactive current is: L eq =L g +L1 / 2 Among them, ω s is the grid voltage frequency; L g is the grid inductance; L1 is the rectifier AC inductance; i gq is the injected q-axis current; i gd is the d-axis grid current; u gd is the d-axis grid voltage.

6. The method according to claim 1, characterized in that The S6 further includes: when an open circuit fault is detected, adjusting the space vector synthesis strategy according to the affected voltage sector corresponding to the fault mode: maintaining the original modulation strategy in the white sector not affected by the fault, and using the compensation vector sequence in the affected color sector.

7. The method according to claim 6, characterized in that The superimposed fault-tolerant control strategy: For type II-1 double-switch faults, a vector sequence reconstruction technique is used in the overlapping impact area, using normal small vectors and zero vectors; For type II-2 double faults in the same bridge arm, a sector-by-sector independent compensation strategy is adopted to handle the impact of the upper and lower bridge arm faults respectively; For type III-1 three-switch fault, a three-level superposition compensation algorithm is used to correct the vector deviation corresponding to each faulty switch step by step.

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