Squeal-eliminating drive circuit and negative voltage charge pump circuit

Abstract

The application belongs to the technical field of electronic circuits, and provides a driving circuit and a negative voltage charge pump circuit for eliminating howling. The driving circuit comprises a control module, a driving module and a power module. The driving module is connected with the gate of a first power tube, the gate of a second power tube, the gate of a third power tube and the gate of a fourth power tube in the control module, the power module and the charge pump circuit respectively. The control module is used for being connected with the source of the fourth power tube. The power module is used for being connected with the drain and the source of the third power tube respectively. When the charge pump circuit is in an idle state, the driving circuit provided by the application embodiment can make the vibration frequency of the flying capacitor CFLY become 31KHz. The frequency is not in the frequency range (20Hz~20kHz) that can be heard by human ears, so that the influence caused by howling is eliminated.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a drive circuit for eliminating howling and a negative voltage charge pump circuit. BACKGROUND

[0002] In today's information society, with the rapid development of LCD (Liquid Crystal Display) technology, LCD liquid crystal display screens have been widely used in various electronic devices. In the driving system of the LCD liquid crystal display screen, VGH (high) and VGL (low) voltage signals are needed to control the gate switch, so the driving system needs to provide both positive and negative power supplies. As a common negative power supply generation method, the negative voltage charge pump plays a key role in the driving system of the LCD liquid crystal display screen. However, the vibration frequency of the flying capacitor of the current negative voltage charge pump in the idle state is easy to be within the frequency range (20Hz~20kHz) audible to the human ear, resulting in howling problems of the display screen. SUMMARY

[0003] The application provides a drive circuit for eliminating howling and a negative voltage charge pump circuit, which can solve the problem that the vibration frequency of the flying capacitor of the current negative voltage charge pump in the idle state is easy to be within the frequency range audible to the human ear, resulting in howling problems of the display screen.

[0004] In a first aspect, the application provides a drive circuit for eliminating howling, comprising a control module, a drive module and a power module, the drive module is connected with the gate of a first power tube, the gate of a second power tube, the gate of a third power tube and the gate of a fourth power tube in the control module, the power module and a charge pump circuit respectively, the control module is used to be connected with the source of the fourth power tube, and the power module is used to be connected with the drain and the source of the third power tube respectively.

[0005] When the charge pump circuit is in the idle state, the control module is used to output a first signal according to the output voltage and the reference voltage of the charge pump circuit; the drive module is used to output a first drive signal, a second drive signal, a third drive signal, a fourth drive signal and a fifth drive signal according to the first signal and a clock signal; when the first signal is at a low level, the fifth drive signal is used to drive the power module to be periodically turned on at a target frequency, so that the flying capacitor in the charge pump circuit vibrates at the target frequency, the first drive signal is used to drive the first power tube to be periodically turned off at the target frequency, the second drive signal is used to drive the second power tube to be periodically turned off at the target frequency, the third drive signal is used to drive the third power tube to be turned off, and the fourth drive signal is used to drive the fourth power tube to be turned off; wherein the target frequency is located outside the frequency range audible to the human ear.

[0006] In a possible implementation manner of the first aspect, when the first signal is at a high level, the first driving signal is used to drive the first power tube to be turned off, the second driving signal is used to drive the second power tube to be turned off, the third driving signal is used to drive the third power tube to be turned on, the fourth driving signal is used to drive the fourth power tube to be turned on, and the fifth driving signal is used to drive the power module to be turned on.

[0007] In a possible implementation manner of the first aspect, the power module comprises a fifth power tube, a gate of the fifth power tube is connected with the driving module, a drain of the fifth power tube is used to be connected with a drain of the third power tube, and a source of the fifth power tube is used to be connected with a source of the third power tube; a size of the fifth power tube is smaller than a size of the third power tube.

[0008] In a possible implementation manner of the first aspect, the driving module comprises a clock generating unit and a driving unit, the clock generating unit is connected with the control module and the driving unit respectively, and the driving unit is connected with a gate of the first power tube, a gate of the second power tube, a gate of the third power tube, and a gate of the fourth power tube in the power module and the charge pump circuit respectively.

[0009] The clock generating unit is used to generate a second signal, a third signal, and a fourth signal according to the first signal and the clock signal; and the driving unit is used to output a first driving signal and a second driving signal according to the second signal, output a third driving signal and a fourth driving signal according to the third signal, and output a fifth driving signal according to the fourth signal.

[0010] In a possible implementation manner of the first aspect, the clock generating unit comprises a first clock generating subunit and a second clock generating subunit, the first clock generating subunit and the second clock generating subunit are connected with the control module, and the second clock generating subunit is connected with the first clock generating subunit and the driving unit respectively.

[0011] The first clock generating subunit is used to generate a target signal according to the first signal and the clock signal; the second clock generating subunit is used to generate a second signal, a third signal, and a fourth signal according to the first signal, the target signal, and the clock signal; and a frequency of the target signal is a target frequency when the first signal is at a low level.

[0012] In a possible implementation manner of the first aspect, the first clock generation subunit comprises a first inverter, a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first AND gate, a second AND gate and a third AND gate; an input end of the first inverter is connected with the control module and the second clock generation subunit respectively, output ends of the first inverter are connected with reset ends of the first D flip-flop, the second D flip-flop, the third D flip-flop, the fourth D flip-flop and the fifth D flip-flop respectively, a clock input end of the first D flip-flop is configured to receive a clock signal, data input ends of the first D flip-flop are connected with an inverted output end of the first D flip-flop and a clock input end of the second D flip-flop respectively, data input ends of the second D flip-flop are connected with an inverted output end of the second D flip-flop and a clock input end of the third D flip-flop respectively, data input ends of the third D flip-flop are connected with an inverted output end of the third D flip-flop and a clock input end of the fourth D flip-flop respectively, data input ends of the fourth D flip-flop are connected with an inverted output end of the fourth D flip-flop and a clock input end of the fifth D flip-flop respectively, a data input end of the fifth D flip-flop is connected with an inverted output end of the fifth D flip-flop, an output end of the first D flip-flop is connected with a first input end of the first AND gate, a second input end of the first AND gate is configured to receive the clock signal, a first input end of the second AND gate is connected with an output end of the second D flip-flop, a second input end of the second AND gate is connected with an output end of the third D flip-flop, a third input end of the second AND gate is connected with an output end of the fourth D flip-flop, a fourth input end of the second AND gate is connected with an output end of the fifth D flip-flop, an output end of the second AND gate is connected with a first input end of the third AND gate, an output end of the first AND gate is connected with a second input end of the third AND gate, and an output end of the third AND gate is connected with the second clock generation subunit.

[0013] In a possible implementation manner of the first aspect, the second clock generation subunit comprises a pulse generator, a first delay, a second delay, a first OR gate, a first NOR gate, a second NOR gate, a second inverter, a third inverter, a fourth inverter, a fourth AND gate, a fifth AND gate, a sixth AND gate, a sixth D flip-flop and a seventh D flip-flop; an input terminal of the pulse generator, a reset terminal of the sixth D flip-flop and a reset terminal of the seventh D flip-flop are all configured to receive a clock signal, an output terminal of the pulse generator is connected with a first input terminal of the fourth AND gate, a first input terminal of the first OR gate is connected with the control module, the first clock generation subunit and a first input terminal of the fifth AND gate respectively, a second input terminal of the first OR gate is connected with the first clock generation subunit, an output terminal of the first OR gate is connected with a second input terminal of the fourth AND gate, an output terminal of the fourth AND gate is connected with a clock input terminal of the sixth D flip-flop and a second input terminal of the fifth AND gate respectively, a data input terminal of the sixth D flip-flop receives a first voltage, an output terminal of the sixth D flip-flop is connected with an input terminal of the second inverter, an output terminal of the second inverter is connected with an input terminal of the third inverter and a first input terminal of the second NOR gate respectively, an output terminal of the third inverter is connected with a first input terminal of the first NOR gate, a second input terminal of the first NOR gate is connected with an output terminal of the second delay, a first input terminal of the sixth AND gate and the driving unit respectively, an output terminal of the first NOR gate is connected with an input terminal of the first delay, an output terminal of the first delay is connected with a second input terminal of the second NOR gate and an input terminal of the fourth inverter respectively, an output terminal of the second NOR gate is connected with an input terminal of the second delay, an output terminal of the fourth inverter is connected with the driving unit, an output terminal of the fifth AND gate is connected with a clock input terminal of the seventh D flip-flop, a data input terminal of the seventh D flip-flop receives the first voltage, an output terminal of the seventh D flip-flop is connected with a second input terminal of the sixth AND gate, and an output terminal of the sixth AND gate is connected with the driving unit.

[0014] In a possible implementation manner of the first aspect, the driving unit comprises a first driving subunit, a second driving subunit, a third driving subunit, a fourth driving subunit and a fifth driving subunit, the first driving subunit, the second driving subunit, the third driving subunit, the fourth driving subunit and the fifth driving subunit are all connected with the clock generation unit, the first driving subunit is configured to be connected with a gate of the first power tube, the second driving subunit is configured to be connected with a gate of the second power tube, the third driving subunit is configured to be connected with a gate of the third power tube, the fourth driving subunit is configured to be connected with a gate of the fourth power tube, and the fifth driving subunit is connected with the power module.

[0015] The first driving subunit is configured to output a first driving signal according to the second signal; the second driving subunit is configured to output a second driving signal according to the second signal; the third driving subunit is configured to output a third driving signal according to the third signal; the fourth driving subunit is configured to output a fourth driving signal according to the third signal; and the fifth driving subunit is configured to output a fifth driving signal according to the fourth signal.

[0016] In a possible implementation of the first aspect, the fifth driving subunit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; a source of the first transistor, a source of the third transistor, a source of the fifth transistor and a source of the seventh transistor all receive a first voltage; a gate of the first transistor and a gate of the second transistor are connected to the clock generation unit; a drain of the first transistor is connected to a drain of the second transistor, a gate of the third transistor and a gate of the fourth transistor respectively; a drain of the third transistor is connected to a drain of the fourth transistor, a gate of the fifth transistor and a gate of the sixth transistor respectively; a drain of the fifth transistor is connected to a drain of the sixth transistor, a gate of the seventh transistor and a gate of the eighth transistor respectively; a drain of the seventh transistor is connected to a drain of the eighth transistor and the power module; a source of the second transistor, a source of the fourth transistor, a source of the sixth transistor and a source of the eighth transistor are all grounded.

[0017] In a second aspect, the embodiments of the present application provide a negative voltage charge pump circuit, including the driving circuit in any of the first aspect.

[0018] In a third aspect, the embodiments of the present application provide a driving system, including the charge pump circuit in any of the second aspect.

[0019] In a fourth aspect, the embodiments of the present application provide a display screen, including the driving system in any of the third aspect.

[0020] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0021] The embodiments of the present application provide a driving circuit for eliminating howling, including a control module, a driving module and a power module, the driving module is connected with the gate of the first power transistor, the gate of the second power transistor, the gate of the third power transistor and the gate of the fourth power transistor in the charge pump circuit respectively, the control module is connected with the source of the fourth power transistor, and the power module is connected with the drain and the source of the third power transistor respectively.

[0022] The control module is configured to output a first signal according to an output voltage of the charge pump circuit and a reference voltage when the charge pump circuit is in an idle state. The driving module is configured to output a first driving signal, a second driving signal, a third driving signal, a fourth driving signal and a fifth driving signal according to the first signal and a clock signal.

[0023] When the first signal is at a low level, the fifth driving signal is configured to drive the power module to periodically turn on at a target frequency. When the power module is turned on, the upper plate of the flying capacitor in the charge pump circuit is pulled down to the ground, the lower plate of the flying capacitor becomes -Vin, and the voltage change between the upper plate and the lower plate of the flying capacitor forms a first vibration. As the power module is periodically turned on at the target frequency, the flying capacitor also vibrates at the target frequency, wherein the target frequency is outside the frequency range audible to human ears. Since the target frequency is not within the frequency range audible to human ears, the vibration of the flying capacitor can be avoided to affect the human ears, and the problem of whistling of the display screen is solved.

[0024] Meanwhile, when the first signal is at a low level, the first driving signal is configured to drive the first power tube to periodically turn off at the target frequency, and the second driving signal is configured to drive the second power tube to periodically turn off at the target frequency. The third driving signal is configured to drive the third power tube to turn off, and the fourth driving signal is configured to drive the fourth power tube to turn off. The application further limits that in this state, the third power tube and the fourth power tube in the charge pump circuit are always turned off, and the first power tube and the second power tube in the charge pump circuit are both turned off when the power module is turned on. When the power module is turned off, the first power tube and the second power tube are both turned on, so as to maintain the stability of the feedback loop of the charge pump circuit.

[0025] In summary, the driving circuit proposed in the application solves the problem that the vibration frequency of the flying capacitor of the current negative voltage charge pump in the idle state is easily within the frequency range audible to human ears, resulting in the problem of whistling of the display screen.

[0026] It can be understood that the beneficial effects of the above-mentioned second aspect to the fourth aspect can be referred to the related description in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0028] Figure 1 is a circuit principle diagram of the prior art charge pump circuit;

[0029] Figure 2is a schematic diagram of a driving circuit provided by an embodiment of the present application;

[0030] Figure 3 is a schematic diagram of a driving circuit provided by another embodiment of the present application;

[0031] Figure 4 is a schematic diagram of a driving circuit provided by another embodiment of the present application;

[0032] Figure 5 is a schematic diagram of a circuit connection of a first clock generating sub-unit;

[0033] Figure 6 is a schematic diagram of a circuit connection of a second clock generating sub-unit;

[0034] Figure 7 is a schematic diagram of a circuit connection of a control module;

[0035] Figure 8 is a schematic diagram of a circuit connection of a power module;

[0036] Figure 9 is a schematic diagram of a circuit connection of a fifth driving sub-unit;

[0037] Figure 10 is a schematic diagram of a circuit connection of a third driving sub-unit.

[0038] In the figure: 1, driving circuit; 10, control module; 20, driving module; 21, clock generating unit; 211, first clock generating sub-unit; 212, second clock generating sub-unit; 22, driving unit; 221, first driving sub-unit; 222, second driving sub-unit; 223, third driving sub-unit; 224, fourth driving sub-unit; 225, fifth driving sub-unit; 30, power module; 2, charge pump circuit. DETAILED DESCRIPTION

[0039] In the following description, for the purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0040] It should be understood that the term "comprising" when used in this specification and the appended claims, specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0041] It should also be understood that, in the description of the present application and in the claims that follow, the term "and / or" means any combination of one or more of the associated listed items and all possible combinations of those items, including the combination of one item only.

[0042] As used in the description of the application and the appended claims, the term "if' can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the described condition or event]" or "in response to detecting [the described condition or event]."

[0043] In addition, the description in the specification of the application and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0044] In the present specification, the phrase "one embodiment" or "some embodiments" etc. means that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Therefore, the phrases "in one embodiment", "in some embodiments", "in other some embodiments", "in further some embodiments" etc. appearing in different places in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized.

[0045] Figure 1 The circuit diagram of the existing charge pump circuit 2 is shown as Figure 1As shown, the charge pump circuit 2 mainly comprises a first power transistor M1, a second power transistor M2, a third power transistor M3, a fourth power transistor M4, a flying capacitor CFLY and an output capacitor COUT. The charge pump circuit 2 has two phases, i.e. a first phase and a second phase, when working. The first power transistor M1 and the second power transistor M2 are controlled by the first phase, and the third power transistor M3 and the fourth power transistor M4 are controlled by the second phase. In the first phase, the first power transistor M1 and the second power transistor M2 are turned on, and the third power transistor M3 and the fourth power transistor M4 are turned off, so that the flying capacitor CFLY is charged by the input voltage Vin; in the second phase, the first power transistor M1 and the second power transistor M2 are turned off, and the third power transistor M3 and the fourth power transistor M4 are turned on, so that the flying capacitor CFLY is connected to the output capacitor COUT through the fourth power transistor M4, and the charge is transferred from the flying capacitor CFLY to the output capacitor COUT, and the output voltage Vneg is obtained, which is a negative voltage.

[0046] In the no-load state (i.e. the state that the charge pump circuit 2 is not connected to a load), the ideal charge pump circuit 2 will generate a constant negative voltage that does not change with time. However, the vibration frequency of the flying capacitor CFLY in the no-load state is easy to be in the frequency range (20Hz~20kHz) that can be heard by human ears, which causes the problem of whistling of the display screen.

[0047] In view of the above problems, the embodiment of the present application provides a driving circuit for eliminating whistling, as shown in Figure 2 As shown, the driving circuit 1 comprises a control module 10, a driving module 20 and a power module 30. The driving module 20 is connected to the gate of the first power transistor M1, the gate of the second power transistor M2, the gate of the third power transistor M3 and the gate of the fourth power transistor M4 in the charge pump circuit 2 respectively, the control module 10 is connected to the source of the fourth power transistor M4, and the power module 30 is connected to the drain and the source of the third power transistor M3 respectively.

[0048] Specifically, when the charge pump circuit 2 is in the no-load state, the control module 10 is configured to output a first signal D according to the output voltage Vneg of the charge pump circuit 2 and a reference voltage Vref. The driving module 20 is configured to output a first driving signal A, a second driving signal A', a third driving signal B, a fourth driving signal B' and a fifth driving signal C according to the first signal D and a clock signal CLK.

[0049] When the first signal D is low, the charge pump circuit 2 works in the first phase, and the fifth driving signal C is used to drive the power module 30 to periodically turn on at a target frequency: when the power module 30 is turned on, the upper plate of the flying capacitor CFLY in the charge pump circuit 2 is pulled down to the ground, the lower plate of the flying capacitor CFLY becomes -Vin, and the voltage change between the upper plate and the lower plate of the flying capacitor CFLY forms a first vibration; as the power module 30 is periodically turned on at the target frequency, the flying capacitor CFLY also vibrates at the target frequency, where the target frequency is outside the frequency range audible to the human ear. Since the target frequency is not in the frequency range audible to the human ear, the vibration of the flying capacitor CFLY can be avoided to affect the human ear, and the problem of the display screen whistling is solved. In the embodiment of the present application, the target frequency is 31KHz.

[0050] Meanwhile, when the first signal D is low, the first driving signal A is used to drive the first power tube M1 to periodically turn off at the target frequency, and the second driving signal A' is used to drive the second power tube M2 to periodically turn off at the target frequency; the third driving signal B is used to drive the third power tube M3 to turn off, and the fourth driving signal B' is used to drive the fourth power tube M4 to turn off. The present application further limits that in this state, the third power tube M3 and the fourth power tube M4 in the charge pump circuit 2 are always turned off, and when the power module 30 is turned on, the first power tube M1 and the second power tube M2 in the charge pump circuit 2 are both turned off; when the power module 30 is turned off, the first power tube M1 and the second power tube M2 are both turned on, so as to maintain the stability of the feedback loop of the charge pump circuit 2.

[0051] The core idea of the present application is that when the charge pump circuit 2 works in the first phase, the driving circuit 1 proposed by the present application adjusts the vibration frequency of the flying capacitor CFLY to the target frequency, and the specific way is: the fifth driving signal C is generated by the control module 10 and the driving module 20, the fifth driving signal C drives the power module 30 to periodically turn on at the target frequency, and then the flying capacitor CFLY vibrates at the target frequency. It should be noted that when the power module 30 is turned on, the first power tube M1, the second power tube M2, the third power tube M3 and the fourth power tube M4 are all in the off state; when the power module 30 is turned off, it should be ensured that the switching action of the first power tube M1, the second power tube M2, the third power tube M3 and the fourth power tube M4 still meets the requirements when the charge pump circuit 2 works in the first phase.

[0052] In summary, the driving circuit 1 proposed by the present application solves the problem that the vibration frequency of the flying capacitor CFLY is easy to be in the frequency range audible to the human ear when the charge pump circuit 2 is in the idle state, resulting in the problem of the display screen whistling.

[0053] It should be noted that when the first signal D is high, the charge pump circuit 2 works in the second phase. In this state, the vibration frequency of the flying capacitor CFLY is greater than the target frequency, which is not in the frequency range audible to human ears, so it is only necessary to ensure that the power module 30 follows the third power tube M3 to be turned on, and the switching actions of the first power tube M1, the second power tube M2, the third power tube M3 and the fourth power tube M4 meet the requirements when the charge pump circuit 2 works in the second phase. The specific way is: when the first signal D is high, the first driving signal A is used to drive the first power tube M1 to be turned off, the second driving signal A' is used to drive the second power tube M2 to be turned off, the third driving signal B is used to drive the third power tube M3 to be turned on, the fourth driving signal B' is used to drive the fourth power tube M4 to be turned on, and the fifth driving signal C is used to drive the power module 30 to be turned on.

[0054] In some embodiments, as shown in FIG. 2, the driving module 20 includes a clock generating unit 21 and a driving unit 22, the clock generating unit 21 is connected with the control module 10 and the driving unit 22 respectively, and the driving unit 22 is connected with the gate of the first power tube M1, the gate of the second power tube M2, the gate of the third power tube M3 and the gate of the fourth power tube M4 in the power module 30 and the charge pump circuit 2 respectively. Figure 3

[0055] Specifically, the clock generating unit 21 is used to generate the second signal CLKP, the third signal CLKN and the fourth signal CLKN1 according to the first signal D and the clock signal CLK. The driving unit 22 is used to output the first driving signal A and the second driving signal A' according to the second signal CLKP, output the third driving signal B and the fourth driving signal B' according to the third signal CLKN, and output the fifth driving signal C according to the fourth signal CLKN1.

[0056] When the first signal D is low, the second signal CLKP and the fourth signal CLKN1 are two same signals, and the frequencies of the two signals are both the target frequency. Specifically, when the fourth signal CLKN1 is high, the second signal CLKP is also high, and when the fourth signal CLKN1 is low, the second signal CLKP is also low. At the same time, the third signal CLKN remains low in this state.

[0057] When the first signal D is high, the second signal CLKP, the third signal CLKN and the fourth signal CLKN1 are all high.

[0058] In some embodiments, as shown in FIG. 2, the driving module 20 includes a clock generating unit 21 and a driving unit 22, the clock generating unit 21 is connected with the control module 10 and the driving unit 22 respectively, and the driving unit 22 is connected with the gate of the first power tube M1, the gate of the second power tube M2, the gate of the third power tube M3 and the gate of the fourth power tube M4 in the power module 30 and the charge pump circuit 2 respectively. Figure 4 ​As shown, the clock generating unit 21 comprises a first clock generating sub-unit 211 and a second clock generating sub-unit 212, both of which are connected with the control module 10, and the second clock generating sub-unit 212 is connected with the first clock generating sub-unit 211 and the driving unit 22 respectively.

[0059] Specifically, the first clock generating sub-unit 211 is configured to generate a target signal CLK31K according to the first signal D and the clock signal CLK. The second clock generating sub-unit 212 is configured to generate a second signal CLKP, a third signal CLKN and a fourth signal CLKN1 according to the first signal D, the target signal CLK31K and the clock signal CLK. When the first signal D is at a low level, the frequency of the target signal CLK31K is a target frequency. When the first signal D is at a high level, the target signal CLK31K is at a low level.

[0060] As Figure 5As shown, the first clock generating subunit 211 includes a first inverter INV1, a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a first AND gate AND1, a second AND gate AND2, and a third AND gate AND3. The input end of the first inverter INV1 is connected with the control module 10 and the second clock generating subunit 212 respectively, and receives the first signal D. The output end of the first inverter INV1 is connected with the reset end of the first D flip-flop DFF1, the reset end of the second D flip-flop DFF2, the reset end of the third D flip-flop DFF3, the reset end of the fourth D flip-flop DFF4, and the reset end of the fifth D flip-flop DFF5 respectively. The clock input end of the first D flip-flop DFF1 is used for receiving the clock signal CLK. The data input end of the first D flip-flop DFF1 is connected with the inverse output end of the first D flip-flop DFF1 and the clock input end of the second D flip-flop DFF2 respectively. The data input end of the second D flip-flop DFF2 is connected with the inverse output end of the second D flip-flop DFF2 and the clock input end of the third D flip-flop DFF3 respectively. The data input end of the third D flip-flop DFF3 is connected with the inverse output end of the third D flip-flop DFF3 and the clock input end of the fourth D flip-flop DFF4 respectively. The data input end of the fourth D flip-flop DFF4 is connected with the inverse output end of the fourth D flip-flop DFF4 and the clock input end of the fifth D flip-flop DFF5 respectively. The data input end of the fifth D flip-flop DFF5 is connected with the inverse output end of the fifth D flip-flop DFF5. The output end of the first D flip-flop DFF1 is connected with the first input end of the first AND gate AND1. The second input end of the second AND gate AND2 is used for receiving the clock signal CLK. The first input end of the second AND gate AND2 is connected with the output end of the second D flip-flop DFF2. The second input end of the second AND gate AND2 is connected with the output end of the third D flip-flop DFF3. The third input end of the second AND gate AND2 is connected with the output end of the fourth D flip-flop DFF4. The fourth input end of the second AND gate AND2 is connected with the output end of the fifth D flip-flop DFF5. The output end of the second AND gate AND2 is connected with the first input end of the third AND gate AND3. The output end of the first AND gate AND1 is connected with the second input end of the third AND gate AND3. The output end of the third AND gate AND3 is connected with the second clock generating subunit 212.

[0061] Specifically, the clock input end of the first D flip-flop DFF1 is used for receiving the clock signal CLK, the data input end and the inverse output end are connected, and the output is given to the next stage, which is used for once frequency division of the clock signal CLK. The second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4, and the fifth D flip-flop DFF5 perform the same operation.

[0062] The signal of the output terminal of the first D flip-flop DFF1 is Q2, the signal of the output terminal of the second D flip-flop DFF2 is Q4, the signal of the output terminal of the third D flip-flop DFF3 is Q8, the signal of the output terminal of the fourth D flip-flop DFF4 is Q16, and the signal of the output terminal of the fifth D flip-flop DFF5 is Q32.

[0063] The signal Q2 is ANDed with the clock signal CLK, the signals Q4, Q8, Q16 and Q32 are ANDed, and the outputs of the two are ANDed to obtain the target signal CLK31K.

[0064] The signal of the reset terminal of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 is the inverse signal of the first signal D, that is, when the first signal D is high, the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 are reset.

[0065] The purpose of the first clock generating subunit 211 is to divide the clock signal CLK by 5. Assuming that the period of the clock signal CLK is 1us, the period of the signal Q32 is 32us, the target signal CLK31K output by the third AND gate AND3 is a square wave with a frequency of 31KHz, a period of 32us and a pulse width of 0.5us. The signal of 31KHz is not in the audible range of human ears, and when the charge pump circuit 2 is in an idle state, the flying capacitor CFLY vibrates at a frequency of 31KHz, avoiding the influence of the vibration of the flying capacitor CFLY on human ears and eliminating the harm of whistling.

[0066] As Figure 6As shown, the second clock generating subunit 212 includes a pulse generator, a first delay, a second delay, a first OR gate OR1, a first NOR gate NOR1, a second NOR gate NOR2, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fourth AND gate AND4, a fifth AND gate AND5, a sixth AND gate AND6, a sixth D flip-flop DFF6 and a seventh D flip-flop DFF7; an input terminal of the pulse generator, a reset terminal of the sixth D flip-flop DFF6 and a reset terminal of the seventh D flip-flop DFF7 are all used for receiving a clock signal CLK, an output terminal of the pulse generator is connected with a first input terminal of the fourth AND gate AND4, a first input terminal of the first OR gate OR1 is connected with the control module 10, the first clock generating subunit 211 and a first input terminal of the fifth AND gate AND5 respectively, a second input terminal of the first OR gate OR1 is connected with the first clock generating subunit 211, receiving a target signal CLK31K, an output terminal of the first OR gate OR1 is connected with a second input terminal of the fourth AND gate AND4, an output terminal of the fourth AND gate AND4 is connected with a clock input terminal of the sixth D flip-flop DFF6 and a second input terminal of the fifth AND gate AND5 respectively, a data input terminal of the sixth D flip-flop DFF6 receives a first voltage VDD, an output terminal of the sixth D flip-flop DFF6 is connected with an input terminal of the second inverter INV2, an output terminal of the second inverter INV2 is connected with an input terminal of the third inverter INV3 and a first input terminal of the second NOR gate NOR2 respectively, an output terminal of the third inverter INV3 is connected with a first input terminal of the first NOR gate NOR1, a second input terminal of the first NOR gate NOR1 is connected with an output terminal of the second delay, a first input terminal of the sixth AND gate AND6 and the driving unit 22 respectively, an output terminal of the first NOR gate NOR1 is connected with an input terminal of the first delay, an output terminal of the first delay is connected with a second input terminal of the second NOR gate NOR2 and an input terminal of the fourth inverter INV4 respectively, an output terminal of the second NOR gate NOR2 is connected with an input terminal of the second delay, an output terminal of the fourth inverter INV4 is connected with the driving unit 22, an output terminal of the fifth AND gate AND5 is connected with a clock input terminal of the seventh D flip-flop DFF7, a data input terminal of the seventh D flip-flop DFF7 receives the first voltage VDD, an output terminal of the seventh D flip-flop DFF7 is connected with a second input terminal of the sixth AND gate AND6, and an output terminal of the sixth AND gate AND6 is connected with the driving unit 22.

[0067] Specifically, the pulse generator is used to generate a small pulse at the rising edge of the clock signal CLK, and the small pulse is high. If the first signal D is high, the signal CLK1 is high. The sixth D flip-flop DFF6 is used to generate the signal CLK2 at the rising edge of the signal CLK1. The first NOR gate OR1 and the second NOR gate OR2 are used as an RS flip-flop. The first delay and the second delay determine the dead time, so as to generate the second signal CLKP and the third signal CLKN. After the second signal CLKP is high, the third signal CLKN is high after the dead time. After the third signal CLKN is low, the second signal CLKP is low after the dead time.

[0068] The first OR gate OR1 is used to make the second signal CLKP high and the fourth signal CLKN1 high when the first signal D or the target signal CLK31K is high.

[0069] The fifth AND gate AND5, the seventh D flip-flop DFF7 and the sixth AND gate AND6 are used to make the fourth signal CLKN1 high and the third signal CLKN low when the first signal D is low and the target signal CLK31K is high.

[0070] In some embodiments, as shown in Figure 7 The control module 10 includes an error amplifier EA, a first resistor R1, a second resistor R2 and a comparator CMP. The first input terminal of the error amplifier EA receives a reference voltage Vref. The second input terminal of the error amplifier EA is connected with the output terminal of the error amplifier EA and the first terminal of the first resistor R1 respectively. The second terminal of the first resistor R1 is connected with the first terminal of the second resistor R2 and the first input terminal of the comparator CMP respectively. The second terminal of the second resistor R2 receives an output voltage Vneg. The output terminal of the comparator CMP outputs a first signal D. In the embodiments of the present application, the first input terminal of the error amplifier EA is a positive input terminal, and the second input terminal is a negative input terminal. The first input terminal of the comparator CMP is a positive input terminal, and the second input terminal is a negative input terminal.

[0071] Specifically, the input of the error amplifier EA is the reference voltage Vref, and the error amplifier EA is used to output a stable voltage Vref1. Assuming that the resistance ratio of the second resistor R2 to the first resistor R1 is K, when the charge pump circuit 2 works in the first phase, if |Vneg|>K×Vref1, the first signal D is low. When the charge pump circuit 2 works in the second phase, if |Vneg|<K×Vref1, the first signal D is high.

[0072] In some embodiments, as shown in Figure 8As shown, the power module 30 includes a fifth power transistor M5, a gate of the fifth power transistor M5 is connected with the driving module 20 to receive a fifth driving signal C, a drain of the fifth power transistor M5 is used to be connected with a drain of the third power transistor M3, and a source of the fifth power transistor M5 is used to be connected with a source of the third power transistor M3. The size of the fifth power transistor M5 is smaller than the size of the third power transistor M3.

[0073] Specifically, the channel width of the fifth power transistor M5 is 1 / N of the channel width of the third power transistor M3, where N is very large, up to thousands, so as to ensure that the on-resistance of the fifth power transistor M5 is large and the generated current is small.

[0074] When the first signal D is low and the fifth power transistor M5 is turned on, the first power transistor M1, the second power transistor M2, the third power transistor M3 and the fourth power transistor M4 are all in the off state. At this time, the energy released by the flying capacitor CFLY will not be directly transferred to the output capacitor COUT, but will still be transferred by the coupling capacitor of the fourth power transistor M4, and the output capacitor COUT will also be charged by the internal trace load. It needs to be ensured that the amount of charge transferred by the flying capacitor CFLY after the fifth power transistor M5 is turned on is less than the loss of the amount of charge of the output capacitor COUT itself, so as to ensure the stability of the output voltage Vneg.

[0075] In some embodiments, as Figure 4 As shown, the driving unit 22 includes a first driving subunit 221, a second driving subunit 222, a third driving subunit 223, a fourth driving subunit 224 and a fifth driving subunit 225, all of which are connected with the clock generating unit 21, the first driving subunit 221 is used to be connected with the gate of the first power transistor M1, the second driving subunit 222 is used to be connected with the gate of the second power transistor M2, the third driving subunit 223 is used to be connected with the gate of the third power transistor M3, the fourth driving subunit 224 is used to be connected with the gate of the fourth power transistor M4, and the fifth driving subunit 225 is connected with the power module 30.

[0076] Specifically, the first driving subunit 221 is used to output the first driving signal A according to the second signal CLKP. The second driving subunit 222 is used to output the second driving signal A' according to the second signal CLKP. The third driving subunit 223 is used to output the third driving signal B according to the third signal CLKN. The fourth driving subunit 224 is used to output the fourth driving signal B' according to the third signal CLKN. The fifth driving subunit 225 is used to output the fifth driving signal C according to the fourth signal CLKN1.

[0077] As Figure 9As shown, the fifth driving sub-unit 225 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8. The sources of the first transistor Q1, the third transistor Q3, the fifth transistor Q5, and the seventh transistor Q7 all receive a first voltage VDD. The gates of the first transistor Q1 and the second transistor Q2 are both connected to the clock generation unit 21 to receive a fourth signal CLKN1. The drain of the first transistor Q1 is connected to the drain of the second transistor Q2. The drain of transistor Q3 is connected to the drain of transistor Q4, the gate of transistor Q5, and the gate of transistor Q6. The drain of transistor Q5 is connected to the drain of transistor Q6, the gate of transistor Q7, and the gate of transistor Q8. The drain of transistor Q7 is connected to the drain of transistor Q8 and the power module 30. The source of transistor Q2, the source of transistor Q4, the source of transistor Q6, and the source of transistor Q8 are all grounded.

[0078] Specifically, the fifth drive subunit 225 is essentially composed of four inverters, which are used to enhance the driving capability of the fourth signal CLKN1 and ensure that the power module 30 can be turned on or off quickly and reliably.

[0079] like Figure 10 As shown, the third driving sub-unit 223 includes a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, and a sixteenth transistor Q16. The sources of the ninth transistor Q9, the eleventh transistor Q11, the thirteenth transistor Q13, and the fifteenth transistor Q15 all receive the first voltage VDD. The gate of the ninth transistor Q9 is connected to the gate of the tenth transistor Q10 and the clock generation unit 21, respectively, and receives the third signal CLKN. The drain of the ninth transistor Q9 is connected to the drain of the tenth transistor Q10 and the eleventh transistor Q16, respectively. The gate of transistor Q11 is connected to the gate of transistor Q12. The drain of transistor Q11 is connected to the drain of transistor Q12, the gate of transistor Q13, and the gate of transistor Q14. The drain of transistor Q13 is connected to the drain of transistor Q14, the gate of transistor Q15, and the gate of transistor Q16. The drain of transistor Q15 is connected to the drain of transistor Q16 and the gate of power transistor M3. The sources of transistors Q10, Q12, Q14, and Q16 are all grounded.

[0080] Specifically, the third driving sub-unit 223 is essentially composed of four inverters, which is used to enhance the driving capability of the third signal CLKN, and ensure that the third power tube M3 can be turned on or turned off quickly and reliably.

[0081] It should be noted that the first driving sub-unit 221, the second driving sub-unit 222 and the fourth driving sub-unit 224 can all be implemented by using the existing driving circuit structure, which will not be described here.

[0082] In summary, when the charge pump circuit 2 is in an idle state, the driving circuit 1 provided by the embodiment of the present application can make the vibration frequency of the flying capacitor CFLY become 31KHz, which is not in the frequency range (20Hz~20kHz) that can be heard by human ears, thereby eliminating the influence of the howling.

[0083] The embodiment of the present application also provides a negative voltage charge pump circuit, which comprises the driving circuit described above. Since the negative voltage charge pump circuit provided by the embodiment of the present application comprises the driving circuit described above, the negative voltage charge pump circuit provided by the embodiment of the present application can eliminate the influence of the howling.

[0084] The embodiment of the present application also provides a driving system, which comprises the negative voltage charge pump circuit described above. Since the driving system provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described here one by one.

[0085] The embodiment of the present application also provides a display screen, which comprises the driving system described above. Since the display screen provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described here one by one.

[0086] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0087] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A drive circuit for eliminating howling, characterized by comprising: The control module, the driving module and the power module are included, the driving module is connected with the gate of the first power tube, the gate of the second power tube, the gate of the third power tube and the gate of the fourth power tube in the control module, the power module and the charge pump circuit respectively, the control module is used for being connected with the source of the fourth power tube, and the power module is used for being connected with the drain and the source of the third power tube respectively; When the charge pump circuit is in the idle state, the control module is used for outputting a first signal according to the output voltage of the charge pump circuit and a reference voltage; The driving module is used for outputting a first driving signal, a second driving signal, a third driving signal, a fourth driving signal and a fifth driving signal according to the first signal and a clock signal, when the first signal is low, the fifth driving signal is used for driving the power module to be periodically turned on at a target frequency, the first driving signal is used for driving the first power tube to be periodically turned off at the target frequency, the second driving signal is used for driving the second power tube to be periodically turned off at the target frequency, the third driving signal is used for driving the third power tube to be turned off, and the fourth driving signal is used for driving the fourth power tube to be turned off, wherein the target frequency is located outside the frequency range that can be heard by human ears; The source of the first power tube receives a power supply voltage, the drain of the first power tube is connected with the drain of the third power tube and the first end of the flying capacitor respectively, the second end of the flying capacitor is connected with the drain of the second power tube and the drain of the fourth power tube respectively, and the source of the second power tube and the source of the third power tube are grounded.

2. The drive circuit according to claim 1, characterized by When the first signal is high, the first driving signal is used for driving the first power tube to be turned off, the second driving signal is used for driving the second power tube to be turned off, the third driving signal is used for driving the third power tube to be turned on, the fourth driving signal is used for driving the fourth power tube to be turned on, and the fifth driving signal is used for driving the power module to be turned on.

3. The drive circuit according to claim 1 or 2, characterized in that, The power module includes a fifth power tube, the gate of the fifth power tube is connected with the driving module, the drain of the fifth power tube is used for being connected with the drain of the third power tube, and the source of the fifth power tube is used for being connected with the source of the third power tube, wherein the size of the fifth power tube is smaller than the size of the third power tube.

4. The drive circuit according to claim 1 or 2, characterized in that, The driving module includes a clock generating unit and a driving unit, the clock generating unit is connected with the control module and the driving unit respectively, and the driving unit is connected with the gate of the first power tube, the gate of the second power tube, the gate of the third power tube and the gate of the fourth power tube in the power module and the charge pump circuit respectively. The clock generating unit is configured to generate a second signal, a third signal and a fourth signal according to the first signal and the clock signal; and the driving unit is configured to output a first driving signal and a second driving signal according to the second signal, output a third driving signal and a fourth driving signal according to the third signal, and output a fifth driving signal according to the fourth signal.

5. The drive circuit according to claim 4, characterized in that, The clock generating unit comprises a first clock generating subunit and a second clock generating subunit, both of which are connected with the control module, and the second clock generating subunit is connected with the first clock generating subunit and the driving unit respectively. The first clock generating subunit is configured to generate a target signal according to the first signal and the clock signal. The second clock generating subunit is configured to generate a second signal, a third signal and a fourth signal according to the first signal, the target signal and the clock signal; and when the first signal is at a low level, the frequency of the target signal is a target frequency.

6. The drive circuit according to claim 5, characterized in that, The first clock generation subunit comprises a first inverter, a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first AND gate, a second AND gate and a third AND gate; the input end of the first inverter is connected with the control module and the second clock generation subunit respectively, the output end of the first inverter is connected with the reset end of the first D flip-flop, the reset end of the second D flip-flop, the reset end of the third D flip-flop, the reset end of the fourth D flip-flop and the reset end of the fifth D flip-flop respectively, the clock input end of the first D flip-flop is used for receiving a clock signal, the data input end of the first D flip-flop is connected with the inverse output end of the first D flip-flop and the clock input end of the second D flip-flop respectively, the data input end of the second D flip-flop is connected with the inverse output end of the second D flip-flop and the clock input end of the third D flip-flop respectively, the data input end of the third D flip-flop is connected with the inverse output end of the third D flip-flop and the clock input end of the fourth D flip-flop respectively, the data input end of the fourth D flip-flop is connected with the inverse output end of the fourth D flip-flop and the clock input end of the fifth D flip-flop respectively, the data input end of the fifth D flip-flop is connected with the inverse output end of the fifth D flip-flop, the output end of the first D flip-flop is connected with the first input end of the first AND gate, the second input end of the first AND gate is used for receiving a clock signal, the first input end of the second AND gate is connected with the output end of the second D flip-flop, the second input end of the second AND gate is connected with the output end of the third D flip-flop, the third input end of the second AND gate is connected with the output end of the fourth D flip-flop, the fourth input end of the second AND gate is connected with the output end of the fifth D flip-flop, the output end of the second AND gate is connected with the first input end of the third AND gate, the output end of the first AND gate is connected with the second input end of the third AND gate, and the output end of the third AND gate is connected with the second clock generation subunit.

7. The drive circuit according to claim 5, characterized by The second clock generation subunit comprises a pulse generator, a first delay, a second delay, a first OR gate, a first NOR gate, a second NOR gate, a second inverter, a third inverter, a fourth inverter, a fourth AND gate, a fifth AND gate, a sixth AND gate, a sixth D flip-flop and a seventh D flip-flop; the input end of the pulse generator, the reset end of the sixth D flip-flop and the reset end of the seventh D flip-flop are all used for receiving a clock signal, the output end of the pulse generator is connected with the first input end of the fourth AND gate, the first input end of the first OR gate is connected with the control module, the first clock generation subunit and the first input end of the fifth AND gate respectively, the second input end of the first OR gate is connected with the first clock generation subunit, the output end of the first OR gate is connected with the second input end of the fourth AND gate, the output end of the fourth AND gate is connected with the clock input end of the sixth D flip-flop and the second input end of the fifth AND gate respectively, the data input end of the sixth D flip-flop receives a first voltage, the output end of the sixth D flip-flop is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the third inverter and the first input end of the second NOR gate respectively, the output end of the third inverter is connected with the first input end of the first NOR gate, the second input end of the first NOR gate is connected with the output end of the second delay, the first input end of the sixth AND gate and the driving unit respectively, the output end of the first NOR gate is connected with the input end of the first delay, the output end of the first delay is connected with the second input end of the second NOR gate and the input end of the fourth inverter respectively, the output end of the second NOR gate is connected with the input end of the second delay, the output end of the fourth inverter is connected with the driving unit, the output end of the fifth AND gate is connected with the clock input end of the seventh D flip-flop, the data input end of the seventh D flip-flop receives a first voltage, the output end of the seventh D flip-flop is connected with the second input end of the sixth AND gate, and the output end of the sixth AND gate is connected with the driving unit.

8. The drive circuit of claim 4, wherein, The driving unit comprises a first driving subunit, a second driving subunit, a third driving subunit, a fourth driving subunit and a fifth driving subunit, the first driving subunit, the second driving subunit, the third driving subunit, the fourth driving subunit and the fifth driving subunit are all connected with the clock generation unit, the first driving subunit is used for being connected with the gate of the first power tube, the second driving subunit is used for being connected with the gate of the second power tube, the third driving subunit is used for being connected with the gate of the third power tube, the fourth driving subunit is used for being connected with the gate of the fourth power tube, and the fifth driving subunit is connected with the power module. The first driving sub-unit is configured to output a first driving signal according to the second signal; the second driving sub-unit is configured to output a second driving signal according to the second signal; the third driving sub-unit is configured to output a third driving signal according to the third signal; the fourth driving sub-unit is configured to output a fourth driving signal according to the third signal; and the fifth driving sub-unit is configured to output a fifth driving signal according to the fourth signal.

9. The drive circuit according to claim 8, characterized in that, The fifth driving sub-unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; a source of the first transistor, a source of the third transistor, a source of the fifth transistor and a source of the seventh transistor all receive a first voltage; a gate of the first transistor and a gate of the second transistor are connected with the clock generating unit; a drain of the first transistor is connected with a drain of the second transistor, a gate of the third transistor and a gate of the fourth transistor respectively; a drain of the third transistor is connected with a drain of the fourth transistor, a gate of the fifth transistor and a gate of the sixth transistor respectively; a drain of the fifth transistor is connected with a drain of the sixth transistor, a gate of the seventh transistor and a gate of the eighth transistor respectively; a drain of the seventh transistor is connected with a drain of the eighth transistor and the power module; a source of the second transistor, a source of the fourth transistor, a source of the sixth transistor and a source of the eighth transistor are all grounded.

10. A negative voltage charge pump circuit, characterized by, The driving circuit comprises any one of claims 1-9.

Images