Low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology

Abstract

The invention relates to the technical field of radio frequency integrated circuits, and discloses a low-jitter injection-locked phase-locked loop based on a two-dimensional space-time correction technology, comprising a phase-locked loop which comprises a frequency-locked loop and a sub-sampling phase-locked loop; the injection locking circuit is used for providing an injection pulse signal to the phase-locked loop; the input end of the two-dimensional space-time correction circuit is connected with an oscillation signal and an injection pulse signal, and the output end of the two-dimensional space-time correction circuit outputs a delay adjustment signal to the injection locking circuit; the period and phase information of the oscillation signal and the injection pulse signal is compared through the two-dimensional space-time correction circuit, a delay adjustment signal is generated and fed back to the injection locking circuit, the injection intensity is improved, the noise suppression bandwidth is expanded, the problems that injection of the injection locking structure is difficult to align, and the pulse width is difficult to optimize are solved, and the service life of the injection locking structure is prolonged. The low jitter of the phase-locked loop is realized, and a technical solution is provided for the application of the injection-locked phase-locked loop in a millimeter wave communication and high-speed data conversion system with high clock precision and low jitter requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a low-jitter injection-locked phase-locked loop based on a two-dimensional space-time correction technology. Background Art

[0002] A phase-locked loop (PLL) is a closed-loop control circuit that uses a feedback mechanism to synchronize the frequency and phase of the output signal with the input signal. Its core function is to lock the frequency and phase of the input signal, thereby outputting a stable and synchronized signal, enabling operations such as frequency synthesis, clock recovery, and modulation and demodulation. In the communications field, it is used in wireless transceivers to achieve carrier synchronization and frequency synthesis, ensuring accurate demodulation and transmission of signals during transmission. In electronic equipment, it can be used to generate high-precision clock signals to ensure the synchronous operation of various modules in the digital system. In radar and navigation systems, it can accurately track the frequency changes of target signals, improving measurement accuracy and reliability. As a key component of modern electronic systems, the PLL plays an important role in wireless communications, integrated circuits, measurement and control equipment, and other fields due to its frequency tracking, signal purification, and synchronization capabilities. It is one of the core technologies for achieving signal stability and precise control.

[0003] The injection-locked phase-locked loop (PLL) has demonstrated significant advantages in high-frequency integrated systems due to its unique phase synchronization mechanism. It phase-pulls the oscillator by injecting signals to achieve an ultra-wideband frequency locking range, making it particularly suitable for scenarios with stringent bandwidth requirements, such as millimeter-wave communications and high-speed frequency synthesis. Unlike traditional phase-locked loops, it does not require a complex loop filter design. While simplifying some circuit modules, it naturally possesses low-jitter characteristics based on the injection locking mechanism, and can provide a clock signal with higher timing stability in high-speed data transmission, meeting the needs of jitter-sensitive applications such as high-frequency SerDes transceivers. At the same time, this mechanism can effectively suppress the inherent phase noise of the oscillator, exhibiting excellent signal purity in the high-frequency band, which is suitable for scenarios with extremely high phase noise requirements, such as radar and satellite communications. However, the core flaw of the injection-locked phase-locked loop is its extremely strict dependence on the phase alignment accuracy of the zero-crossing points of the injected signal and the local oscillation signal. The midpoint of the injected pulse must precisely coincide with the corresponding zero-crossing point of the oscillation signal within an extremely narrow time window. Any nanosecond-level timing misalignment will lead to phase error accumulation and locked loop instability, which in turn will cause frequency jumps, phase noise surges, and even complete lock failure. At the same time, the injection intensity is directly related to the width of the injected pulse, affecting the jitter performance of the phase-locked loop.

[0004] Therefore, how to accurately align the midpoint of the injected pulse signal with the zero-crossing point of the oscillation signal, while optimizing the injected pulse width to ensure sufficient injection intensity, so as to overcome the inherent defects of the injection-locked structure and give full play to its application potential in low jitter, low phase noise, etc., is a key technical challenge that urgently needs to be solved by technicians in this field. SUMMARY

[0005] In order to solve the problems in the prior art, the application provides a low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology, which comprises a sub-sampling locking loop, a frequency-locked loop, an injection-locked circuit and a two-dimensional space-time correction circuit.

[0006] The application provides a low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology. The phase-locked loop comprises a frequency-locked loop and a sub-sampling phase-locked loop, wherein the sub-sampling phase-locked loop is used for realizing phase locking, and the frequency-locked loop is used for realizing frequency locking; during the signal locking process of the phase-locked loop, frequency locking is completed first, and then phase locking is completed. The injection-locked circuit is connected with the phase-locked loop and is used for providing an injection pulse signal to the phase-locked loop. The two-dimensional space-time correction circuit is connected with the injection-locked circuit and is used for comparing the period and phase information of the oscillation signal and the injection pulse signal, generating a delay adjustment signal and feeding back the delay adjustment signal to the injection-locked circuit, so as to realize the correction of the time and pulse width of the injection pulse signal.

[0007] Further, the two-dimensional space-time correction circuit comprises injection time correction and injection pulse width correction. The injection time correction outputs a first delay adjustment signal to the injection-locked circuit, which is used for correcting the time of the injection pulse signal, so that the midpoint of the injection pulse signal is aligned with the zero-crossing point of the oscillation signal. The injection pulse width correction outputs a second delay adjustment signal to the injection-locked circuit, which is used for correcting the pulse width of the injection pulse signal, so that the injection strength of the pulse signal is improved, and the jitter of the phase-locked loop is suppressed.

[0008] Further, the injection-locked circuit comprises a first variable delay unit, a second variable delay unit and an AND logic gate. The input end of the first variable delay unit is connected with a reference signal and the first delay adjustment signal. The input end of the second variable delay unit is connected to the output end of the first variable delay unit and the second delay adjustment signal; The output end of the first variable delay unit and the output end of the second variable delay unit are both connected to the input end of an AND logic gate, and the output end of the AND logic gate outputs an injection pulse signal.

[0009] Furthermore, the injection time correction includes a first comparator, a first accumulator and a second sub-sampling phase detector; The input end of the second sub-sampling phase detector is connected to the oscillation signal and the injection pulse signal, the output end of the second sub-sampling phase detector is connected to the negative input end of the first comparator, the positive input end of the first comparator is connected to the voltage, the output end of the first comparator is connected to the input end of the first accumulator, and the output end of the first accumulator outputs the first delay adjustment signal; The injection pulse width correction includes a second comparator, a second accumulator and a second charge pump; The input end of the second charge pump is connected to the oscillation signal and the injection pulse signal, the output end of the second charge pump is connected to the negative input end of the second comparator, the positive input end of the second comparator is connected to the voltage, the output end of the second comparator is connected to the input end of the second accumulator, and the output end of the second accumulator outputs the second delay adjustment signal.

[0010] Furthermore, the second sub-sampling phase detector includes a first capacitor and a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the oscillation signal, the drain of the fifth NMOS transistor is connected to the injection pulse signal, the source of the fifth NMOS transistor is connected to one end of the first capacitor and serves as the output end of the second sub-sampling phase detector; the other end of the first capacitor is grounded.

[0011] Further, the second charge pump includes a second capacitor, a sixth NMOS transistor and a fourth PMOS transistor; The source of the fourth PMOS transistor is connected to the power supply, and the gate thereof is connected to the injected pulse signal; the gate of the sixth NMOS transistor is connected to the oscillation signal, and the source thereof is grounded; the drain of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor and one end of the second capacitor, and serves as the output end of the second charge pump; the other end of the second capacitor is grounded.

[0012] Furthermore, the first variable delay unit and the second variable delay unit each include a variable current source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a first inverter, a second inverter and several stages of delay units; The input end of the first inverter is the input end of the first variable delay unit and the second variable delay unit; The output end of the second inverter is the output end of the first variable delay unit and the second variable delay unit; The negative terminal of the variable current source is connected to a power supply, the positive terminal thereof is connected to the gate and drain of the first NMOS transistor, and the control terminal of the variable current source is connected to a delay adjustment signal; the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the VN voltage, and the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded; the drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the VP voltage; the source of the first PMOS transistor is connected to a power supply; The output end of the first inverter is connected to the first input end of the first-stage delay unit, the first input end of each stage of the delay unit is connected to the output end of the previous stage of the delay unit, the second input end of each stage of the delay unit is connected to the VP voltage, and the third input end of each stage of the delay unit is connected to the VN voltage; the output end of the last stage of the delay unit is connected to the input end of the second inverter.

[0013] Furthermore, each stage of the delay unit includes a second PMOS transistor, a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; In each level of the delay unit, the gate of the second PMOS transistor is the second input terminal of the delay unit, the source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the source of the third PMOS transistor; the gate of the third PMOS transistor is connected to the gate of the fourth NMOS transistor and is the first input terminal of the delay unit; the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor and is the output terminal of the delay unit; the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is the third input terminal of the delay unit.

[0014] Furthermore, the frequency locked loop includes a phase frequency detector, a first charge pump, a frequency divider, a loop filter, and an injection locked oscillator; The injection locked oscillator outputs an oscillation signal; The input end of the frequency divider is connected to the oscillation signal, and the output end thereof is connected to the phase frequency detector; the other input end of the phase frequency detector is connected to the reference signal, the output end of the phase frequency detector is connected to the input end of the first charge pump, the output end of the first charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the injection locked oscillator.

[0015] Furthermore, the sub-sampling phase-locked loop includes a first sub-sampling phase detector and a transconductance module; An input end of the first sub-sampling phase detector is connected to a reference signal and an oscillation signal, an output end thereof is connected to an input end of a transconductance module, an output end of the transconductance module is connected to another input end of the loop filter, and the first sub-sampling phase detector, the transconductance module, the loop filter, and the injection-locked oscillator form the sub-sampling phase-locked loop.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology proposed in the present invention uses two-dimensional correction of injection time and injection pulse width to achieve precise alignment of the midpoint of the injection pulse with the zero-crossing point of the oscillation signal, as well as the optimal pulse width, thereby resolving the defects of the injection-locked phase-locked loop, eliminating the phase offset caused by injection, improving the injection strength, expanding the noise suppression bandwidth, enhancing the jitter suppression capability of the phase-locked loop, and achieving low jitter. At the same time, a subsampling architecture is also adopted to avoid the contribution of the divider to phase noise and reduce the in-band phase noise. The present invention compensates for the mechanism defects of the traditional injection-locked phase-locked loop through two-dimensional space-time correction technology, realizes a low-jitter and low-phase-noise phase-locked loop system, and provides a key technical foundation for the next generation of communication systems with high timing accuracy requirements. It is suitable for high-frequency communication systems, radars, millimeter-wave receivers, and other scenarios that require low jitter and low phase noise ranges. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure. Figure 1 A schematic diagram of the overall structure of a low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology provided by the present invention; Figure 2 A schematic diagram of the specific structure of a low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology provided by the present invention; Figure 3 A schematic structural diagram of the injection locking circuit and the two-dimensional space-time correction circuit provided by the present invention; Figure 4 This is a schematic diagram of the circuit structure of the variable delay unit in the injection locking circuit provided by the present invention. DETAILED DESCRIPTION

[0018] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0019] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0020] In the description of the present application, it should be noted that the terms, "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" and the like are only used for differentiation in description, and cannot be understood as indicating or implying relative importance.

[0021] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "arrangement", "installation", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0022] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0023] As shown in Figure 1 The present application provides a low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology, which specifically comprises: The phase-locked loop comprises a frequency-locked loop and a sub-sampling phase-locked loop. The sub-sampling phase-locked loop is used to realize phase locking, and the frequency-locked loop is used to realize frequency locking. During the signal locking process of the phase-locked loop, frequency locking is completed first, and then phase locking is completed. The injection-locked circuit is connected with the phase-locked loop and is used to provide an injection pulse signal to the phase-locked loop. The two-dimensional time-space correction circuit is connected with an oscillation signal and an injection pulse signal at input ends, and outputs a delay adjustment signal to an injection locking circuit at an output end; the two-dimensional time-space correction circuit compares the period and phase information of the oscillation signal and the injection pulse signal, generates the delay adjustment signal, and feeds back the delay adjustment signal to the injection locking circuit, so that the time and pulse width of the injection pulse signal are corrected.

[0024] In some embodiments of the application, the injection locking circuit and the two-dimensional time-space correction circuit are core parts of a phase-locked loop for low-jitter implementation, the injection time correction is used to accurately align the midpoint of the injection pulse with the zero-crossing point of the oscillation signal, and the injection pulse width correction is used to achieve optimal injection pulse width, improve injection strength, expand noise suppression bandwidth, and suppress phase-locked loop jitter; the frequency-locked loop is a frequency locking part of the phase-locked loop, and is a traditional charge pump phase-locked loop structure; the sub-sampling phase-locked loop is a phase locking part of the phase-locked loop, and is a traditional sub-sampling frequency-locked loop and a sub-sampling phase-locked loop that are used together to realize frequency and phase locking, i.e., the frequency-locked loop is first used to complete frequency locking, and then the sub-sampling phase-locked loop is used to complete phase locking.

[0025] As shown in Figure 2 and Figure 3 , the two-dimensional time-space correction circuit includes injection time correction and injection pulse width correction; the injection time correction outputs a first delay adjustment signal to the injection locking circuit, which is used to correct the time of the injection pulse signal, so that the midpoint of the injection pulse signal is accurately aligned with the zero-crossing point of the oscillation signal; the injection pulse width correction outputs a second delay adjustment signal to the injection locking circuit, which is used to correct the pulse width of the injection pulse signal, so that the injection strength of the pulse signal is improved, and phase-locked loop jitter is suppressed.

[0026] The injection locking circuit includes a first variable delay unit, a second variable delay unit, and an AND logic gate; the input end of the first variable delay unit is connected with a reference signal and the first delay adjustment signal; the input end of the second variable delay unit is connected with the output end of the first variable delay unit and the second delay adjustment signal; the output ends of the first variable delay unit and the second variable delay unit are both connected with the input end of the AND logic gate, and the output end of the AND logic gate outputs the injection pulse signal.

[0027] Specifically, the injection time correction includes a first comparator, a first accumulator, and a second sub-sampling phase detector; the input ends of the second sub-sampling phase detector are connected with the oscillation signal and the injection pulse signal, the output end of the second sub-sampling phase detector is connected with the negative input end of the first comparator, the positive input end of the first comparator is connected with a voltage, the output end of the first comparator is connected with the input end of the first accumulator, and the output end of the first accumulator outputs the first delay adjustment signal. The injection pulse width correction includes a second comparator, a second accumulator and a second charge pump; the input end of the second charge pump is connected to the oscillation signal and the injection pulse signal, the output end is connected to the negative input end of the second comparator, the positive input end of the second comparator is connected to the voltage, the output end of the second comparator is connected to the input end of the second accumulator, and the output end of the second accumulator outputs the second delay adjustment signal.

[0028] In some embodiments of the present invention, a two-dimensional spatiotemporal correction circuit compares the period and phase information of an injected pulse signal with that of an oscillating signal, and then generates a feedback signal to adjust the delays of a first variable delay unit and a second variable delay unit. The first delay adjustment signal adjusts the delay of the first variable delay unit to achieve an optimal injection time, i.e., aligning the midpoint of the injected pulse with the zero crossing point of the oscillating signal. The second delay adjustment signal adjusts the delay of the second variable delay unit to achieve an optimal injected pulse width of 1 / 4 the oscillating signal period. This two-dimensional adjustment of the injection time and injected pulse width resolves the bottleneck of an injection-locked phase-locked loop (PLL), improves injection strength, expands the noise suppression bandwidth, and achieves low jitter in the PLL.

[0029] Specifically, in the injection time correction path, the injected pulse signal is sampled by the second sub-sampling phase detector, and then outputs a signal containing the phase error between the injected pulse signal and the oscillation signal, which enters the negative input terminal of the first comparator. The first comparator compares the signal containing the phase error with the comparison threshold voltage and outputs +1 or -1. The first accumulator accumulates the signals and outputs a first delay adjustment signal to adjust the first variable delay unit. If the output voltage of the second sub-sampling phase detector is higher than the comparison threshold voltage, the first comparator outputs -1, the output voltage of the first accumulator decreases, and the delay of the first variable delay unit is controlled to decrease. If the output voltage of the second sub-sampling phase detector is lower than the comparison threshold voltage, the first comparator outputs +1, the output voltage of the first accumulator increases, and the delay of the first variable delay unit is controlled to increase. This adjusts the generation time of the injected pulse signal to achieve the optimal injection time, that is, the midpoint of the injected pulse is aligned with the zero crossing point of the oscillation signal.

[0030] In the injection pulse width correction path, the injection pulse signal and the oscillation signal enter the second charge pump. The injection pulse signal controls the charging of the second charge pump, while the oscillation signal controls the discharging of the second charge pump. The second charge pump outputs a signal indicating the difference between the injection pulse width and the optimal pulse width, which enters the negative input of the second comparator. The second comparator compares this signal containing the width error with a comparison threshold voltage and outputs a +1 or -1 signal. The output of the second comparator is then accumulated by a second accumulator, which then outputs a second delay adjustment signal to adjust the second variable delay unit. If the output voltage of the second charge pump is higher than the comparison threshold voltage, the second comparator outputs a -1 signal, which reduces the output voltage of the second accumulator and controls the delay of the second variable delay unit to decrease. If the output voltage of the second charge pump is lower than the comparison threshold voltage, the second comparator outputs a +1 signal, which increases the output voltage of the first accumulator and controls the delay of the second variable delay unit to increase. This adjusts the width of the injection pulse signal to achieve the optimal injection pulse width, i.e., 1 / 4 of the oscillation signal period.

[0031] like Figure 3 As shown, the second sub-sampling phase detector includes a first capacitor C1 and a fifth NMOS transistor N5; the gate of the fifth NMOS transistor N5 is connected to the oscillation signal, the drain of the fifth NMOS transistor N5 is connected to the injection pulse signal, the source of the fifth NMOS transistor N5 is connected to one end of the first capacitor C1, and serves as the output end of the second sub-sampling phase detector; the other end of the first capacitor C1 is grounded.

[0032] The second charge pump includes a second capacitor C2, a sixth NMOS transistor N6 and a fourth PMOS transistor P4; the source of the fourth PMOS transistor P4 is connected to the power supply, and its gate is connected to the injected pulse signal; the gate of the sixth NMOS transistor N6 is connected to the oscillation signal, and its source is grounded; the drain of the sixth NMOS transistor N6 is connected to the drain of the fourth PMOS transistor P4 and one end of the second capacitor C2, and serves as the output end of the second charge pump; the other end of the second capacitor C2 is grounded.

[0033] like Figure 4As shown, the first variable delay unit and the second variable delay unit each include a variable current source, a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a first inverter, a second inverter and several stages of delay units; the input end of the first inverter is the input end of the first variable delay unit and the second variable delay unit; the output end of the second inverter is the output end of the first variable delay unit and the second variable delay unit; the negative end of the variable current source is connected to the power supply, the positive end is connected to the gate and drain of the first NMOS transistor N1, and the control end of the variable current source is connected to the delay adjustment signal; the gate of the first NMOS transistor N1 is connected to the drain of the first NMOS transistor N1, The gate of the second NMOS transistor N2 and the VN voltage, the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are all grounded; the drain of the second NMOS transistor N2 is connected to the gate of the first PMOS transistor N1, the drain of the first PMOS transistor P1 and the VP voltage; the source of the first PMOS transistor P1 is connected to the power supply; the output end of the first inverter is connected to the first input end of the first-stage delay unit, the first input end of each stage of the delay unit is connected to the output end of the previous stage of the delay unit, the second input end of each stage of the delay unit is connected to the VP voltage, and the third input end of each stage of the delay unit is connected to the VN voltage; the output end of the last stage of the delay unit is connected to the input end of the second inverter.

[0034] Specifically, each stage of the delay unit includes a second PMOS transistor P2, a third PMOS transistor P3, a third NMOS transistor N3 and a fourth NMOS transistor N4; in each stage of the delay unit, the gate of the second PMOS transistor P2 is the second input end of the delay unit, the source of the second PMOS transistor P2 is connected to the power supply, and its drain is connected to the source of the third PMOS transistor P3; the gate of the third PMOS transistor P3 is connected to the gate of the fourth NMOS transistor N4 and is the first input end of the delay unit; the drain of the third PMOS transistor P3 is connected to the drain of the fourth NMOS transistor N4 and is the output end of the delay unit; the source of the fourth NMOS transistor N4 is connected to the drain of the third NMOS transistor N3, the source of the third NMOS transistor N3 is grounded, and the gate of the third NMOS transistor N3 is the third input end of the delay unit.

[0035] In some embodiments of the present invention, in a variable delay unit, a delay adjustment signal adjusts a variable current source to change the VP voltage and the VN voltage, thereby changing the delay of each delay unit, thereby controlling the delay of the entire variable delay unit. Specifically, when the voltage of the delay adjustment signal decreases, the current of the variable current source increases, the VN voltage increases, the VP voltage decreases, and the conductivity of the third NMOS transistor N3 and the second PMOS transistor P2 in each delay unit increases, reducing the delay of each delay unit, thereby reducing the delay of the variable delay unit; when the voltage of the delay adjustment signal increases, the current of the variable current source decreases, the VN voltage decreases, the VP voltage increases, and the conductivity of the third NMOS transistor N3 and the second PMOS transistor P2 in each delay unit decreases, increasing the delay of each delay unit, thereby increasing the delay of the variable delay unit.

[0036] The frequency-locked loop includes a phase frequency detector, a first charge pump, a frequency divider, a loop filter, and an injection-locked oscillator; the injection-locked oscillator outputs an oscillation signal; an input end of the frequency divider is connected to the oscillation signal, and an output end thereof is connected to the phase frequency detector; another input end of the phase frequency detector is connected to a reference signal, an output end of the phase frequency detector is connected to an input end of the first charge pump, an output end of the first charge pump is connected to an input end of the loop filter, and an output end of the loop filter is connected to the injection-locked oscillator.

[0037] The sub-sampling phase-locked loop includes a first sub-sampling phase detector and a transconductance module; the input end of the first sub-sampling phase detector is connected to a reference signal and an oscillation signal, the output end thereof is connected to the input end of the transconductance module, the output end of the transconductance module is connected to the other input end of the loop filter, and the first sub-sampling phase detector, the transconductance module, the loop filter and the injection-locked oscillator form a sub-sampling phase-locked loop.

[0038] In some embodiments of the present invention, phase and frequency locking of a phase-locked loop (PLL) is achieved through the collaboration of a subsampling phase-locked loop (PSL) and a frequency-locked loop (FLL). The FLL first performs the frequency lock task. Once the frequency is locked, the FLL stops, and the subsampling phase-locked loop (PSL) starts, beginning phase tracking and ultimately achieving lock.

[0039] Specifically, in the frequency locked loop, the present invention uses a traditional three-state PFD with a dead zone as the phase frequency detector; the phase frequency detector is used to detect the phase difference between the reference signal and the output signal of the frequency divider. Higher than the injection locked oscillator frequency after the frequency divider is divided by N , that is When , the phase frequency detector (PFD) will output a phase advance pulse to control the current injected by the first charge pump; and when When the phase frequency detector (PFD) outputs a phase-lag pulse, controlling the first charge pump to extract current. The output current of the first charge pump is CPIt will be integrated through the loop filter to generate the control voltage V CTRL ; Control voltage V CTRL The oscillation frequency of the injection-locked oscillator can be adjusted up to , achieving frequency lock. After the frequency lock is completed, the sub-sampling phase-locked loop starts to work. In the sub-sampling phase-locked loop, the first sub-sampling phase detector uses the low-frequency reference signal to perform sub-sampling on the high-frequency injection-locked oscillator output signal, and converts the phase error between the reference signal and the oscillation signal into a voltage signal. The voltage signal containing the phase error information It will be converted into a current signal through the transconductance module, and then pass through the loop filter to generate a smooth voltage signal V CTRL , and then accurately adjust the phase of the injection-locked oscillator output signal to ensure phase locking.

[0040] The present invention uses two-dimensional space-time correction technology and injection time correction to achieve precise alignment of the midpoint of the injected pulse and the zero-crossing point of the oscillation signal. The aligned phase error is less than 1.67%. The injection pulse width correction achieves the optimal injection pulse width, i.e., 1 / 4 of the oscillation signal period, thereby improving the injection intensity, expanding the noise suppression bandwidth, and effectively suppressing jitter. At the same time, the sub-sampling phase-locked loop structure is used to further reduce the phase noise, providing a technical solution for the application of injection-locked oscillators in millimeter-wave communications and high-speed data conversion systems with high clock accuracy and low jitter requirements.

[0041] The above embodiments are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions or replacements made by those skilled in the art based on the technical features of the present invention fall within the scope of protection of the present invention.

Claims

1. A low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology, characterized in that: The injection locked phase locked loop comprises: A phase-locked loop (PLL) comprising a frequency-locked loop (FLL) and a sub-sampling phase-locked loop (PSLL); the sub-sampling PLL is used to achieve phase locking, and the FLL is used to achieve frequency locking; during the PLL signal locking process, frequency locking is completed first, followed by phase locking; an injection locking circuit, connected to the phase-locked loop, for providing an injection pulse signal to the phase-locked loop; A two-dimensional space-time correction circuit has an input end connected to an oscillation signal and an injection pulse signal, and an output end of the two-dimensional space-time correction circuit outputs a delay adjustment signal to an injection locking circuit; the two-dimensional space-time correction circuit compares the period and phase information of the oscillation signal and the injection pulse signal, generates a delay adjustment signal and feeds it back to the injection locking circuit, thereby achieving correction of the time and pulse width of the injection pulse signal.

2. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 1, characterized in that: The two-dimensional space-time correction circuit includes injection time correction and injection pulse width correction; The injection time correction outputs a first delay adjustment signal to the injection locking circuit, which is used to correct the time of the injection pulse signal so that the midpoint of the injection pulse signal is aligned with the zero crossing point of the oscillation signal; The injection pulse width correction outputs a second delay adjustment signal to the injection locking circuit, which is used to correct the pulse width of the injection pulse signal, thereby increasing the injection strength of the pulse signal and suppressing the phase-locked loop jitter.

3. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 2, characterized in that: The injection locking circuit includes a first variable delay unit, a second variable delay unit and an AND logic gate; An input end of the first variable delay unit is connected to a reference signal and a first delay adjustment signal; The input end of the second variable delay unit is connected to the output end of the first variable delay unit and the second delay adjustment signal; The output end of the first variable delay unit and the output end of the second variable delay unit are both connected to the input end of an AND logic gate, and the output end of the AND logic gate outputs an injection pulse signal.

4. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 2, characterized in that: The injection time correction includes a first comparator, a first accumulator and a second sub-sampling phase detector; The input end of the second sub-sampling phase detector is connected to the oscillation signal and the injection pulse signal, the output end of the second sub-sampling phase detector is connected to the negative input end of the first comparator, the positive input end of the first comparator is connected to the voltage, the output end of the first comparator is connected to the input end of the first accumulator, and the output end of the first accumulator outputs the first delay adjustment signal; The injection pulse width correction includes a second comparator, a second accumulator and a second charge pump; The input end of the second charge pump is connected to the oscillation signal and the injection pulse signal, the output end of the second charge pump is connected to the negative input end of the second comparator, the positive input end of the second comparator is connected to the voltage, the output end of the second comparator is connected to the input end of the second accumulator, and the output end of the second accumulator outputs the second delay adjustment signal.

5. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 4, characterized in that: The second sub-sampling phase detector includes a first capacitor and a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the oscillation signal, the drain of the fifth NMOS transistor is connected to the injection pulse signal, the source of the fifth NMOS transistor is connected to one end of the first capacitor and serves as the output end of the second sub-sampling phase detector; the other end of the first capacitor is grounded.

6. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 4, characterized in that: The second charge pump includes a second capacitor, a sixth NMOS transistor and a fourth PMOS transistor; The source of the fourth PMOS transistor is connected to the power supply, and the gate thereof is connected to the injected pulse signal; the gate of the sixth NMOS transistor is connected to the oscillation signal, and the source thereof is grounded; the drain of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor and one end of the second capacitor, and serves as the output end of the second charge pump; the other end of the second capacitor is grounded.

7. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 3, characterized in that: The first variable delay unit and the second variable delay unit each include a variable current source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a first inverter, a second inverter and a plurality of stages of delay units; The input end of the first inverter is the input end of the first variable delay unit and the second variable delay unit; The output end of the second inverter is the output end of the first variable delay unit and the second variable delay unit; The negative terminal of the variable current source is connected to a power supply, the positive terminal thereof is connected to the gate and drain of the first NMOS transistor, and the control terminal of the variable current source is connected to a delay adjustment signal; the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the VN voltage, and the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded; the drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the VP voltage; and the source of the first PMOS transistor is connected to a power supply; The output end of the first inverter is connected to the first input end of the first-stage delay unit, the first input end of each stage of the delay unit is connected to the output end of the previous stage of the delay unit, the second input end of each stage of the delay unit is connected to the VP voltage, and the third input end of each stage of the delay unit is connected to the VN voltage; the output end of the last stage of the delay unit is connected to the input end of the second inverter.

8. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 7, characterized in that: Each stage of the delay unit includes a second PMOS transistor, a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; In each level of the delay unit, the gate of the second PMOS transistor is the second input terminal of the delay unit, the source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the source of the third PMOS transistor; the gate of the third PMOS transistor is connected to the gate of the fourth NMOS transistor and is the first input terminal of the delay unit; the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor and is the output terminal of the delay unit; the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is the third input terminal of the delay unit.

9. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 1, characterized in that: The frequency locked loop includes a phase frequency detector, a first charge pump, a frequency divider, a loop filter, and an injection locked oscillator; The injection locked oscillator outputs an oscillation signal; The input end of the frequency divider is connected to the oscillation signal, and the output end thereof is connected to the phase frequency detector; the other input end of the phase frequency detector is connected to the reference signal, the output end of the phase frequency detector is connected to the input end of the first charge pump, the output end of the first charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the injection locked oscillator.

10. The low-jitter injection-locked phase-locked loop based on two-dimensional space-time correction technology according to claim 9, characterized in that: The sub-sampling phase-locked loop includes a first sub-sampling phase detector and a transconductance module; An input end of the first sub-sampling phase detector is connected to a reference signal and an oscillation signal, an output end thereof is connected to an input end of a transconductance module, an output end of the transconductance module is connected to another input end of the loop filter, and the first sub-sampling phase detector, the transconductance module, the loop filter, and the injection-locked oscillator form the sub-sampling phase-locked loop.

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