A low-power and low-jitter digital injection locked phase-locked loop

Abstract

This invention belongs to the field of mixed-signal integrated circuit design technology, and specifically discloses a low-power and low-jitter digital injection-locked loop (DIL), including an injection pulse path, a pulse width calibration path, a pulse time calibration path, and a dual-injection numerically controlled oscillator. The low power consumption of the DIL is achieved through the synergistic effect of the pulse width calibration path, the pulse time calibration path, and the dual-injection numerically controlled oscillator. The injection pulse path, pulse width calibration path, and pulse time calibration path process the reference signal, and adjust the timing and pulse width of the injection pulse under changes in process, voltage, and temperature through self-calibration technology, and then inject it into the dual-injection numerically controlled oscillator to achieve maximum injection strength while minimizing jitter.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design technology, specifically relating to a low-power and low-jitter digital injection lock-in phase-locked loop. Background Technology

[0002] Phase-locked loops (PLLs), as a key module in wireless biosensor systems, provide the local oscillator signal for both wireless and wired communication electronics within the sensor. Their performance directly impacts the power consumption, frequency, and communication quality of the entire sensor system. Currently, wireless biosensors primarily utilize energy harvesting systems for power supply, which effectively reduces battery replacement frequency and enables large-scale deployment. However, energy harvesting systems face two challenges: low power supply voltage and insufficient energy conversion efficiency, imposing stringent power requirements on the electronic systems. Furthermore, with the continuous increase in biosensor data transmission rates, the jitter requirements for PLLs are becoming increasingly stringent.

[0003] To address these issues, various low-power and low-jitter phase-locked loops (PLLs) have been proposed, such as all-digital PLLs, subsampled PLLs, and injection-locked PLLs. However, in all-digital PLLs, the quantization noise generated by the time-to-digital converter with limited resolution reduces the in-band phase noise. Traditional subsampled PLLs and injection-locked PLLs are often based on analog architectures, resulting in high power consumption, large area, and poor anti-interference capabilities, making them unsuitable for wearable health management applications. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a low-power and low-jitter digital injection-locked phase-locked loop, comprising:

[0005] The injection pulse path has a reference signal connected to its input and an injection pulse signal output at its output.

[0006] The pulse width calibration path includes a first phase detector and a successive approximation register; the input of the first phase detector is connected to the injected pulse signal and the clock signal, and the output of the first phase detector is connected to the input of the successive approximation register; the output of the successive approximation register outputs a second control signal to the injected pulse path to adjust the pulse width of the injected pulse signal.

[0007] The pulse timing calibration path includes a second phase detector and an accumulator; the input of the second phase detector is connected to the injected pulse signal and the clock signal, and the output of the second phase detector is connected to the input of the accumulator; the output of the accumulator outputs a first control signal to the injected pulse path to regulate the injection time of the injected pulse signal.

[0008] A dual-injection numerically controlled oscillator includes a first injection terminal and a second injection terminal; the first injection terminal is connected to the positive terminal of an injection pulse signal, and the second injection terminal is connected to the negative terminal of the injection pulse signal; the output terminal of the dual-injection numerically controlled oscillator outputs a clock signal.

[0009] By adjusting the timing and pulse width of the injected pulse signal through the pulse time calibration path and pulse width calibration path respectively, low jitter of the digital injection locked phase-locked loop is achieved. Low power consumption of the digital injection locked phase-locked loop is achieved through the synergistic effect of the pulse width calibration path, the pulse time calibration path and the dual-injection CNC oscillator.

[0010] Furthermore, the injection pulse path includes a first controllable delay line, a second controllable delay line, and an AND gate;

[0011] The first input terminal of the first controllable delay line is connected to the reference signal, its second input terminal is connected to the first control signal, and the output terminal of the first controllable delay line is connected to the second input terminal of the AND gate and the first input terminal of the second controllable delay line.

[0012] The second input terminal of the second controllable delay line is connected to the second control signal, and the output terminal of the second controllable delay line is connected to the first input terminal of the AND gate;

[0013] The output of the AND gate is connected to the first and second injection terminals of the dual-injection CNC oscillator and outputs an injection pulse signal.

[0014] Furthermore, the digital injection-locked phase-locked loop also includes a frequency-locked loop, the first input terminal of which is connected to a reference signal, the second input terminal of which is connected to a frequency control signal, and the output terminal of which is connected to the input terminal of the dual-injection digitally controlled oscillator.

[0015] Furthermore, the digital injection-locked phase-locked loop also includes a time-to-digital converter, a digital filter, a buffer, and a frequency divider;

[0016] The first input terminal of the time-to-digital converter is connected to a reference signal, and its second input terminal is connected to the output terminal of the frequency divider. The output terminal of the time-to-digital converter is connected to the input terminal of the digital filter. The output terminal of the digital filter is connected to the input terminal of the dual-injection numerically controlled oscillator. The output terminal of the dual-injection numerically controlled oscillator is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the input terminal of the frequency divider.

[0017] Furthermore, the dual-injection numerically controlled oscillator also includes a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0018] The first output terminal of the first delay unit is connected to the second input terminal of the second delay unit and the first input terminal of the third delay unit; the second output terminal of the first delay unit is connected to the third input terminal of the second delay unit and the fourth input terminal of the third delay unit; the first output terminal of the second delay unit is connected to the second input terminal of the third delay unit and the first input terminal of the fourth delay unit; the second output terminal of the second delay unit is connected to the third input terminal of the third delay unit and the fourth input terminal of the fourth delay unit; the first output terminal of the third delay unit is connected to the second input terminal of the fourth delay unit; the first output terminal of the fourth delay unit is connected to the first input terminal of the first delay unit, the third input terminal of the first delay unit, and the fourth input terminal of the second delay unit, and serves as the in-phase signal output terminal of the dual-injection numerically controlled oscillator; the second output terminal of the fourth delay unit is connected to the second input terminal of the first delay unit, the fourth input terminal of the first delay unit, and the first input terminal of the second delay unit, and serves as the in-phase signal output terminal of the dual-injection numerically controlled oscillator.

[0019] The drain of the first NMOS transistor is connected to the first output terminal of the first delay unit, its source is connected to the second output terminal of the first delay unit, and its gate is connected to the first injection terminal; the drain of the second NMOS transistor is connected to the first output terminal of the second delay unit, its source is connected to the second output terminal of the second delay unit, and its gate is connected to the second injection terminal; the drain of the third NMOS transistor is connected to the first output terminal of the third delay unit, its source is connected to the second output terminal of the third delay unit, and its gate is connected to the first injection terminal; the drain of the fourth NMOS transistor is connected to the first output terminal of the fourth delay unit, its source is connected to the second output terminal of the fourth delay unit, and its gate is connected to the second injection terminal; the fifth input terminals of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit are all connected to the input terminals of the dual-injection numerically controlled oscillator.

[0020] Furthermore, the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit each include a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a thirteenth NMOS transistor.

[0021] The sources of the first, second, third, and fourth PMOS transistors are all connected to the power supply voltage. The drain of the first PMOS transistor is connected to the gate of the third PMOS transistor, and the gate of the first PMOS transistor is the first input terminal of the first, second, third, and fourth delay units. The drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor is the fourth input terminal of the first, second, third, and fourth delay units. The drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor and is the first output terminal of the first, second, third, and fourth delay units. The drain of the third PMOS transistor is connected to the drain of the sixth NMOS transistor and is the second output terminal of the first, second, third, and fourth delay units.

[0022] The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to the drain of the thirteenth NMOS transistor. The source of the thirteenth NMOS transistor is grounded. The gate of the thirteenth NMOS transistor is the fifth input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit. The gate of the fifth NMOS transistor is the second input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit. The gate of the sixth NMOS transistor is the third input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit.

[0023] Furthermore, both the first phase detector and the second phase detector include a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor.

[0024] The sources of the fifth PMOS transistor, the sixth PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the power supply voltage; the gates of the fifth PMOS transistor, the seventh PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eighth NMOS transistor, and the eleventh NMOS transistor are all signal injection terminals of the first phase detector and the second phase detector.

[0025] The drain of the fifth PMOS transistor and the drain of the ninth PMOS transistor are both output terminals of the first phase detector and the second phase detector, respectively. The drain of the fifth PMOS transistor is connected to the drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the tenth PMOS transistor, and the gate of the tenth NMOS transistor. The drain of the ninth PMOS transistor is connected to the source of the seventh PMOS transistor, the gate of the sixth PMOS transistor, the source of the tenth PMOS transistor, and the gate of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source of the seventh NMOS transistor is connected to the gate of the eighth PMOS transistor. The drain of the S transistor; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; the drain of the tenth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; the gate of the ninth NMOS transistor is the first input terminal of the first phase detector and the second phase detector; the gate of the twelfth NMOS transistor is the second input terminal of the first phase detector and the second phase detector; the sources of the ninth NMOS transistor and the twelfth NMOS transistor are both grounded.

[0026] Compared with the prior art, the present invention has the following beneficial technical effects:

[0027] First, the present invention achieves stronger robustness through a digital injection locking architecture, while reducing power consumption and area, which can meet the needs of wearable health management applications.

[0028] Second, the pulse width calibration path and pulse time calibration path of the present invention adopt a digital background self-calibration technology to achieve low jitter under changes in process, voltage and temperature.

[0029] Third, the numerically controlled injection oscillator proposed in this invention adopts a four-stage cascaded pseudo-differential structure, which significantly reduces power consumption while increasing the oscillation frequency through feedforward technology. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0031] Figure 1 This is a system block diagram of a low-power and low-jitter digital injection lock-in phase-locked loop proposed in this invention;

[0032] Figure 2 This is a structural diagram of the dual-injection numerically controlled oscillator in the digital injection-locked phase-locked loop proposed in this invention;

[0033] Figure 3 This is a schematic diagram of the delay unit in the dual-injection numerically controlled oscillator proposed in this invention;

[0034] Figure 4 This is a schematic diagram of the phase detector in the pulse width calibration path and pulse time calibration path proposed in this invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0036] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0037] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0038] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0039] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0040] like Figures 1 to 4 As shown, this invention provides a low-power and low-jitter digital injection-locked phase-locked loop, including a frequency-locked loop, a time-to-digital converter, a digital filter, a buffer, a frequency divider, a dual-injection digitally controlled oscillator, an injection pulse path, a pulse width calibration path, and a pulse time calibration path.

[0041] An injection pulse path is provided, with its input connected to a reference signal and its output outputting an injected pulse signal. The injection pulse path includes a first controllable delay line, a second controllable delay line, and an AND gate. The first input of the first controllable delay line is connected to the reference signal, and its second input is connected to a first control signal. The output of the first controllable delay line is connected to the second input of the AND gate and the first input of the second controllable delay line. The second input of the second controllable delay line is connected to a second control signal, and its output is connected to the first input of the AND gate. The output of the AND gate is connected to the first and second injection terminals of a dual-injection numerically controlled oscillator and outputs the injected pulse signal.

[0042] The pulse width calibration path includes a first phase detector and a successive approximation register; the input of the first phase detector is connected to the injected pulse signal and the clock signal, and the output of the first phase detector is connected to the input of the successive approximation register; the output of the successive approximation register outputs a second control signal to the injected pulse path to adjust the pulse width of the injected pulse signal.

[0043] The pulse timing calibration path includes a second phase detector and an accumulator; the input of the second phase detector is connected to the injected pulse signal and the clock signal, and the output of the second phase detector is connected to the input of the accumulator; the output of the accumulator outputs a first control signal to the injected pulse path to regulate the injection time of the injected pulse signal.

[0044] A dual-injection numerically controlled oscillator includes a first injection terminal and a second injection terminal; the first injection terminal is connected to the positive terminal of the injected pulse signal, and the second injection terminal is connected to the negative terminal of the injected pulse signal; the output terminal of the dual-injection numerically controlled oscillator outputs a clock signal.

[0045] By adjusting the timing and pulse width of the injected pulse signal through the pulse time calibration path and pulse width calibration path respectively, low jitter of the digital injection locked phase-locked loop is achieved. Low power consumption of the digital injection locked phase-locked loop is achieved through the synergistic effect of the pulse width calibration path, the pulse time calibration path and the dual-injection CNC oscillator.

[0046] In some embodiments of the present invention, in the injection pulse path, a first controllable delay line and a second controllable delay line respectively determine the injection time and pulse width of the injected pulse signal; the first and second controllable delay lines in the injection pulse path are analog circuits sensitive to process, voltage, and temperature variations; furthermore, the injection pulse time and width should be optimized under different frequency division ratios; according to injection lock-in theory, the maximum injection strength can be obtained to achieve the lowest jitter when the injected pulse signal is aligned with the zero-crossing of the output signal and the pulse width is equal to one-quarter of the period of the dual-injection CNC oscillator. Therefore, adjusting the delays of the first and second controllable delay lines under all operating conditions to obtain the optimal injection pulse signal is crucial for achieving low jitter in digital injection lock-in phase-locked loops; additionally, pulse width calibration paths and pulse time calibration paths are used to process the reference signal and inject it into the dual-injection CNC oscillator to achieve cumulative jitter elimination.

[0047] Specifically, the first input terminal of the frequency-locked loop is connected to the reference signal, its second input terminal is connected to the frequency control signal, and the output terminal of the frequency-locked loop is connected to the input terminal VC of the dual-injection numerically controlled oscillator.

[0048] The first input terminal of the time-to-digital converter is connected to the reference signal, and its second input terminal is connected to the output terminal of the frequency divider. The output terminal of the time-to-digital converter is connected to the input terminal of the digital filter. The output terminal of the digital filter is connected to the input terminal of the dual-injection numerically controlled oscillator. The output terminal of the dual-injection numerically controlled oscillator is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the input terminal VC of the frequency divider.

[0049] In some embodiments of the present invention, a frequency-controlled frequency-locked loop is used to perform fast frequency locking and stops working after frequency locking to reduce power consumption; the input of the time-to-digital converter is connected to a reference signal and a feedback clock signal, and outputs a phase error digital code to measure and digitize the phase difference between the reference signal and the feedback clock signal; the digital filter inputs the phase error digital code and outputs a digital control word to filter noise; the dual-injection numerically controlled oscillator inputs the digital control word and outputs a clock signal to generate a clock signal of the required frequency according to the digital control word; the frequency divider inputs the clock signal and outputs a feedback clock signal to divide the high-frequency output by N to near the reference frequency, forming a closed loop.

[0050] like Figure 2As shown, the dual-injection numerically controlled oscillator further includes a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. The first output terminal of the first delay unit is connected to the second input terminal of the second delay unit and the first input terminal of the third delay unit; the second output terminal of the first delay unit is connected to the third input terminal of the second delay unit and the fourth input terminal of the third delay unit; the first output terminal of the second delay unit is connected to the second input terminal of the third delay unit and the first input terminal of the fourth delay unit; the second output terminal of the second delay unit is connected to the third input terminal of the third delay unit and the fourth input terminal of the fourth delay unit; the first output terminal of the fourth delay unit is connected to the first input terminal of the first delay unit, the third input terminal of the first delay unit, and the fourth input terminal of the second delay unit, and serves as the in-phase signal output terminal OUT of the dual-injection numerically controlled oscillator. P; The second output terminal of the fourth delay unit is connected to the second input terminal of the first delay unit, the fourth input terminal of the first delay unit, and the first input terminal of the second delay unit, and is also the inverted signal output terminal OUT of the dual-injection numerically controlled oscillator. N; The drain of the first NMOS transistor N1 is connected to the first output terminal of the first delay unit, its source is connected to the second output terminal of the first delay unit, and its gate is connected to the first injection terminal; The drain of the second NMOS transistor N2 is connected to the first output terminal of the second delay unit, its source is connected to the second output terminal of the second delay unit, and its gate is connected to the second injection terminal; The drain of the third NMOS transistor N3 is connected to the first output terminal of the third delay unit, its source is connected to the second output terminal of the third delay unit, and its gate is connected to the first injection terminal; The drain of the fourth NMOS transistor N4 is connected to the first output terminal of the fourth delay unit, its source is connected to the second output terminal of the fourth delay unit, and its gate is connected to the second injection terminal; The fifth input terminals of the first, second, third, and fourth delay units are all connected to the input terminal VC of the dual-injection numerically controlled oscillator.

[0051] In some embodiments of the present invention, the dual-injection CNC oscillator adopts a four-stage cascaded pseudo-differential structure; a dual-injection technique is employed to further suppress the phase noise of the injected CNC oscillator by performing multi-phase injection at the differential nodes; by employing feedforward technology to accelerate signal conversion, the dual-injection CNC oscillator reduces power consumption while maintaining the same oscillation frequency compared to the traditional architecture; the two injection paths avoid the additional power consumption caused by continuous high-power injection by precisely controlling the width and time of the injection pulses; the entire system can operate normally at a 0.6V power supply voltage with extremely low power consumption.

[0052] like Figure 3 As shown, the first, second, third, and fourth delay units each include a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a thirteenth NMOS transistor N13; the sources of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are all connected to the power supply voltage; the drain of the first PMOS transistor P1 is connected to the gate of the third PMOS transistor P3, and the gate of the first PMOS transistor P1 is the first input terminal VSN of the first, second, third, and fourth delay units; the drain of the fourth PMOS transistor P4 is connected to the gate of the second PMOS transistor P2, and the gate of the fourth PMOS transistor P4 is the fourth input terminal VSP of the first, second, third, and fourth delay units; the second PMOS transistor P1... The drain of transistor P2 is connected to the drain of the fifth NMOS transistor N5, and serves as the first output terminal VOP of the first, second, third, and fourth delay units; the drain of the third PMOS transistor P3 is connected to the drain of the sixth NMOS transistor N6, and serves as the second output terminal VON of the first, second, third, and fourth delay units; the sources of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are both connected to the drain of the thirteenth NMOS transistor N13, the source of the thirteenth NMOS transistor N13 is grounded, and the gate of the thirteenth NMOS transistor N13 serves as the fifth input terminal VC of the first, second, third, and fourth delay units; the gate of the fifth NMOS transistor N5 serves as the second input terminal VPN of the first, second, third, and fourth delay units; and the gate of the sixth NMOS transistor serves as the third input terminal VPP of the first, second, third, and fourth delay units.

[0053] like Figure 4As shown, both the first and second phase detectors include a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, and a twelfth NMOS transistor N12; the source of the fifth PMOS transistor P5, the source of the sixth PMOS transistor P6, the source of the eighth PMOS transistor P8, and the source of the ninth PMOS transistor P10. The source of MOS transistor P9 is connected to the power supply voltage; the gates of the fifth PMOS transistor P5, the seventh PMOS transistor P7, the ninth PMOS transistor P9, the tenth PMOS transistor P10, the eighth NMOS transistor N8, and the eleventh NMOS transistor N11 are all signal INJ injection terminals of the first and second phase detectors; the drains of the fifth PMOS transistor P5 and the ninth PMOS transistor P9 are both output terminals of the first and second phase detectors; the drain of the fifth PMOS transistor P5 is connected to the drain of the seventh PMOS transistor P7. The gate of the eighth PMOS transistor P8, the drain of the tenth PMOS transistor P10, and the gate of the tenth NMOS transistor N10; the drain of the ninth PMOS transistor P9 is connected to the source of the seventh PMOS transistor P7, the gate of the sixth PMOS transistor P6, the source of the tenth PMOS transistor P10, and the gate of the seventh NMOS transistor N7; the drain of the seventh NMOS transistor N7 is connected to the drain of the sixth PMOS transistor P6, and the source of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8; the source of the eighth NMOS transistor N8 is connected to the drain of the ninth NMOS transistor N9; the... The drain of the tenth NMOS transistor N10 is connected to the drain of the eighth PMOS transistor P8, and the source of the tenth NMOS transistor N10 is connected to the drain of the eleventh NMOS transistor N11; the source of the eleventh NMOS transistor N11 is connected to the drain of the twelfth NMOS transistor N12; the gate of the ninth NMOS transistor N9 is the first input terminal DCON of the first phase detector and the second phase detector; the gate of the twelfth NMOS transistor N12 is the second input terminal DCOP of the first phase detector and the second phase detector; the sources of the ninth NMOS transistor N9 and the twelfth NMOS transistor N12 are both grounded.

[0054] This invention provides a low-power and low-jitter digital injection-locked loop (DIL) using 28nm CMOS technology. The DIL operates on a 0.6V power supply, consuming only 820μW. The proposed DIL has a bandwidth extended to 2.3MHz, significantly suppressing phase noise contributed by the digitally controlled oscillator. At a 2.4GHz output frequency, the measured jitter is 542fs, and the reference spurious is -65.8dBc, indicating that the calibration circuit effectively aligns the injected pulse with the output signal.

[0055] The embodiments given above are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions or substitutions made by those skilled in the art based on the technical features of the present invention are within the protection scope of the present invention.

Claims

1. A low-power and low-jitter digital injection-locked phase-locked loop, characterized in that, The digital injection-locked phase-locked loop includes: The injection pulse path has a reference signal connected to its input and an injection pulse signal output at its output. The pulse width calibration path includes a first phase detector and a successive approximation register; the input of the first phase detector is connected to the injected pulse signal and the clock signal, and the output of the first phase detector is connected to the input of the successive approximation register; the output of the successive approximation register outputs a second control signal to the injected pulse path to adjust the pulse width of the injected pulse signal. The pulse timing calibration path includes a second phase detector and an accumulator; the input of the second phase detector is connected to the injected pulse signal and the clock signal, and the output of the second phase detector is connected to the input of the accumulator; the output of the accumulator outputs a first control signal to the injected pulse path to regulate the injection time of the injected pulse signal. A dual-injection numerically controlled oscillator includes a first injection terminal and a second injection terminal; the first injection terminal is connected to the positive terminal of an injection pulse signal, and the second injection terminal is connected to the negative terminal of the injection pulse signal; the output terminal of the dual-injection numerically controlled oscillator outputs a clock signal. By adjusting the timing and pulse width of the injected pulse signal through the pulse time calibration path and pulse width calibration path respectively, low jitter of the digital injection locked phase-locked loop is achieved. Low power consumption of the digital injection locked phase-locked loop is achieved through the synergistic effect of the pulse width calibration path, the pulse time calibration path and the dual-injection CNC oscillator.

2. The low-power and low-jitter digital injection lock-in phase-locked loop according to claim 1, characterized in that, The injection pulse path includes a first controllable delay line, a second controllable delay line, and an AND gate; The first input terminal of the first controllable delay line is connected to the reference signal, its second input terminal is connected to the first control signal, and the output terminal of the first controllable delay line is connected to the second input terminal of the AND gate and the first input terminal of the second controllable delay line. The second input terminal of the second controllable delay line is connected to the second control signal, and the output terminal of the second controllable delay line is connected to the first input terminal of the AND gate; The output of the AND gate is connected to the first and second injection terminals of the dual-injection CNC oscillator and outputs an injection pulse signal.

3. The low-power and low-jitter digital injection lock-in phase-locked loop according to claim 1, characterized in that, The digital injection-locked phase-locked loop also includes a frequency-locked loop. The first input terminal of the frequency-locked loop is connected to a reference signal, and its second input terminal is connected to a frequency control signal. The output terminal of the frequency-locked loop is connected to the input terminal of the dual-injection digitally controlled oscillator.

4. The low-power and low-jitter digital injection lock-in phase-locked loop according to claim 1, characterized in that, The digital injection-locked phase-locked loop also includes a time-to-digital converter, a digital filter, a buffer, and a frequency divider; The first input terminal of the time-to-digital converter is connected to a reference signal, and its second input terminal is connected to the output terminal of the frequency divider. The output terminal of the time-to-digital converter is connected to the input terminal of the digital filter. The output terminal of the digital filter is connected to the input terminal of the dual-injection numerically controlled oscillator. The output terminal of the dual-injection numerically controlled oscillator is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the input terminal of the frequency divider.

5. A low-power and low-jitter digital injection lock-in phase-locked loop according to claim 1, characterized in that, The dual-injection numerically controlled oscillator further includes a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The first output terminal of the first delay unit is connected to the second input terminal of the second delay unit and the first input terminal of the third delay unit; the second output terminal of the first delay unit is connected to the third input terminal of the second delay unit and the fourth input terminal of the third delay unit; the first output terminal of the second delay unit is connected to the second input terminal of the third delay unit and the first input terminal of the fourth delay unit; the second output terminal of the second delay unit is connected to the third input terminal of the third delay unit and the fourth input terminal of the fourth delay unit; the first output terminal of the third delay unit is connected to the second input terminal of the fourth delay unit; the first output terminal of the fourth delay unit is connected to the first input terminal of the first delay unit, the third input terminal of the first delay unit, and the fourth input terminal of the second delay unit, and serves as the in-phase signal output terminal of the dual-injection numerically controlled oscillator; the second output terminal of the fourth delay unit is connected to the second input terminal of the first delay unit, the fourth input terminal of the first delay unit, and the first input terminal of the second delay unit, and serves as the in-phase signal output terminal of the dual-injection numerically controlled oscillator. The drain of the first NMOS transistor is connected to the first output terminal of the first delay unit, its source is connected to the second output terminal of the first delay unit, and its gate is connected to the first injection terminal. The drain of the second NMOS transistor is connected to the first output terminal of the second delay unit, its source is connected to the second output terminal of the second delay unit, and its gate is connected to the second injection terminal; the drain of the third NMOS transistor is connected to the first output terminal of the third delay unit, its source is connected to the second output terminal of the third delay unit, and its gate is connected to the first injection terminal; the drain of the fourth NMOS transistor is connected to the first output terminal of the fourth delay unit, its source is connected to the second output terminal of the fourth delay unit, and its gate is connected to the second injection terminal; the fifth input terminals of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit are all connected to the input terminals of the dual-injection numerically controlled oscillator.

6. A low-power and low-jitter digital injection lock-in phase-locked loop according to claim 5, characterized in that, The first delay unit, the second delay unit, the third delay unit, and the fourth delay unit each include a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a thirteenth NMOS transistor; The sources of the first, second, third, and fourth PMOS transistors are all connected to the power supply voltage. The drain of the first PMOS transistor is connected to the gate of the third PMOS transistor, and the gate of the first PMOS transistor is the first input terminal of the first, second, third, and fourth delay units. The drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor is the fourth input terminal of the first, second, third, and fourth delay units. The drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor and is the first output terminal of the first, second, third, and fourth delay units. The drain of the third PMOS transistor is connected to the drain of the sixth NMOS transistor and is the second output terminal of the first, second, third, and fourth delay units. The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to the drain of the thirteenth NMOS transistor. The source of the thirteenth NMOS transistor is grounded. The gate of the thirteenth NMOS transistor is the fifth input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit. The gate of the fifth NMOS transistor is the second input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit. The gate of the sixth NMOS transistor is the third input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit.

7. A low-power and low-jitter digital injection lock-in phase-locked loop according to claim 1, characterized in that, Both the first phase detector and the second phase detector include a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. The sources of the fifth PMOS transistor, the sixth PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the power supply voltage; the gates of the fifth PMOS transistor, the seventh PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eighth NMOS transistor, and the eleventh NMOS transistor are all signal injection terminals of the first phase detector and the second phase detector. The drain of the fifth PMOS transistor and the drain of the ninth PMOS transistor are both output terminals of the first phase detector and the second phase detector, respectively. The drain of the fifth PMOS transistor is connected to the drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the tenth PMOS transistor, and the gate of the tenth NMOS transistor. The drain of the ninth PMOS transistor is connected to the source of the seventh PMOS transistor, the gate of the sixth PMOS transistor, the source of the tenth PMOS transistor, and the gate of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source of the seventh NMOS transistor is connected to... The drain of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; the drain of the tenth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; the gate of the ninth NMOS transistor is the first input terminal of the first phase detector and the second phase detector; the gate of the twelfth NMOS transistor is the second input terminal of the first phase detector and the second phase detector; the sources of the ninth NMOS transistor and the twelfth NMOS transistor are both grounded.

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