A phase-locked loop, a phase-locked loop circuit and a clock circuit

Abstract

The application discloses a phase-locked loop circuit, a phase-locked loop and a clock circuit, and relates to the technical field of clock circuits. An integration module can perform integration processing according to the phase relationship between a reference clock signal and an output clock signal detected by a phase detection module. A current output module can output a current signal linearly related to the phase difference between the reference clock signal and the output clock signal based on a pulse signal output by the phase detection module and a voltage signal output by the integration module. Thus, the double-loop structure formed by the corresponding integration path of the integration module and the corresponding proportional path of the current output module can realize the function of the linear control loop of the charge pump, so that the phase-locked loop of the clock signal is realized without using the charge pump. As a result, the power consumption and the occupied area of the entire phase-locked loop circuit and the phase-locked loop are effectively reduced, so that the clock signal can be provided for each transceiving channel in the SerDes transceiver under the premise of low power consumption and small area.

Description

Technical Field

[0001] This invention relates to the field of clock circuit technology, and in particular to a phase-locked circuit, a phase-locked loop, and a clock circuit. Background Technology

[0002] As chip functionality and integration increase, chiplet packaging technology is becoming increasingly widespread. Communication between different chiplets requires die-to-die (D2D) interconnects. D2D interconnects rely on SerDes (serialize-deserialize) transceivers, which demand extremely low latency and power consumption. To reduce latency, SerDes transceivers need to integrate multiple transceiver channels to decrease the rate of individual channels, thereby reducing latency in single-channel serial-to-parallel and parallel-to-serial conversions. Simultaneously, to increase the number of transceiver channels without significantly increasing the overall chip area, the area of ​​each individual channel must be sufficiently small. Furthermore, the normal operation of each transceiver channel in a SerDes transceiver depends on strict clock synchronization.

[0003] It is evident that how to provide clock signals for each transceiver channel in a SerDes transceiver while maintaining low power consumption and small area is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a phase-locked loop (PLL) circuit, a PLL, and a clock circuit that can solve the problem of how to provide clock signals for each transceiver channel in a SerDes transceiver while maintaining low power consumption and small area.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a phase-locked loop circuit, comprising:

[0006] The phase detection module has a reference clock signal connected to its first input terminal and an output clock signal connected to its second input terminal. It is used to detect the phase sequence relationship between the reference clock signal and the output clock signal and to output a pulse signal based on the phase sequence relationship.

[0007] The integration module, whose input is connected to the output of the phase detection module, is used to integrate the pulse signal to generate the corresponding voltage signal.

[0008] The current output module has its input terminals connected to the output terminals of the phase detection module and the integration module, respectively, and is used to output a current signal based on pulse signals and voltage signals; the phase difference between the current signal and the reference clock signal and the output clock signal is linearly correlated.

[0009] The oscillator's control terminal is connected to the output terminal of the current output module. The output terminal serves as the output terminal of the phase-locked loop (PLL) circuit, used to output the PLL's clock signal. The frequency of the output clock signal is adjusted based on the current signal to keep the phase of the output clock signal synchronized with the reference clock signal.

[0010] Optionally, the phase detection module includes a binary phase detector, with a reference clock signal connected to the first input terminal and the output clock signal of the phase-locked loop circuit connected to the second input terminal.

[0011] A binary phase detector outputs a first level when the phase of the output clock signal leads the reference clock signal, and outputs a second level when the phase of the output clock signal lags the reference clock signal; the first level and the second level are opposite.

[0012] The points module includes:

[0013] The first capacitor has its first terminal grounded.

[0014] The second capacitor has its first terminal grounded.

[0015] The first control module has its input terminal connected to the output terminal of the binary phase detector, and its output terminal connected to the second terminal of the first capacitor and the second terminal of the second capacitor respectively. It also serves as the output terminal of the integration module. When the binary phase detector outputs a first level, it controls the transfer of charge from the second capacitor to the first capacitor; when the binary phase detector outputs a second level, it controls the transfer of charge from the first capacitor to the second capacitor.

[0016] Optionally, the first control module includes:

[0017] The step size configuration module has its input end connected to the output end of the integration module. It is used to generate a first voltage and a second voltage based on the voltage signal output by the integration module. The voltage value of the first voltage is greater than the voltage across the first capacitor, and the voltage across the first capacitor is greater than the voltage value of the second voltage.

[0018] The selector has a first input terminal connected to the first output terminal of the step size configuration module, a second input terminal connected to the second output terminal of the step size configuration module, and a control terminal connected to the output terminal of the binary phase detector. It is used to output a first voltage when the binary phase detector outputs a first level and to output a second voltage when the binary phase detector outputs a second level.

[0019] Optional, the step size configuration module includes:

[0020] The voltage divider circuit has a first input terminal connected to the power supply and a second input terminal grounded, used to output a preset voltage based on the power supply.

[0021] Third capacitor;

[0022] The first switch, with its first end connected to the output end of the integration module, is used to turn on when the voltage of the third capacitor reaches a preset voltage.

[0023] The second switch has its first end connected to the output of the voltage divider circuit and its second end connected to the first end of the third capacitor. It also serves as the first output of the step size configuration module. The switch is turned on when a charging signal is received and turned off when the voltage of the third capacitor reaches a preset voltage.

[0024] The third switch has its first terminal grounded and its second terminal connected to both the second terminal of the first switch and the second terminal of the third capacitor. It is used to turn on when a charging signal is received and turn off when the voltage of the third capacitor reaches a preset voltage.

[0025] Fourth capacitor;

[0026] The fourth switch, with its first terminal connected to the output terminal of the integration module, is used to turn on when the voltage of the fourth capacitor reaches a preset voltage.

[0027] The fifth switch has its first end connected to the output of the voltage divider circuit, and its second end connected to the first end of the fourth capacitor and the second end of the fourth switch, respectively. It is used to turn on when a charging signal is received and turn off when the voltage of the fourth capacitor reaches the preset voltage.

[0028] The sixth switch has its first terminal grounded and its second terminal connected to the second terminal of the fourth capacitor. It also serves as the second output terminal of the step size configuration module. The switch is turned on when a charging signal is received and turned off when the voltage of the third capacitor reaches a preset voltage.

[0029] Optionally, the voltage divider circuit includes:

[0030] A fixed resistor, with its first end connected to the power supply;

[0031] The variable resistor has its first end grounded and its second end connected to the second end of the fixed resistor, serving as the output of the voltage divider circuit.

[0032] Optionally, the step size configuration module also includes:

[0033] The first follower has its non-inverting input connected to the output of the integration module, and its output connected to the inverting input of the first follower and the first terminal of the first switch, respectively.

[0034] The second follower has its non-inverting input connected to the output of the integrator module, and its output connected to the inverting input of the second follower and the first terminal of the fourth switch.

[0035] Optionally, the oscillator includes:

[0036] The first inverter has its control terminal connected to the output terminal of the current output module, and its ground terminal is grounded.

[0037] The second inverter has its control terminal connected to the output terminal of the current output module, its ground terminal grounded, and its input terminal connected to the output terminal of the first inverter.

[0038] The third inverter has its control terminal connected to the output terminal of the current output module, its ground terminal grounded, its input terminal connected to the output terminal of the second inverter, its output terminal connected to the input terminal of the first inverter, and serves as the output terminal of the oscillator.

[0039] Optionally, the phase detection module includes a frequency and phase detector, and the pulse signal includes a first pulse and a second pulse;

[0040] The first input terminal of the frequency and phase detector is connected to a reference clock signal, and the second input terminal is connected to the output clock signal of the phase-locked loop circuit. The first output terminal is used to output a first pulse, and the second output terminal is used to output a second pulse. The first pulse is configured to indicate that the phase of the output clock signal leads the reference clock signal, and the second pulse is configured to indicate that the phase of the output clock signal lags the reference clock signal. The pulse width difference between the first pulse and the second pulse is configured to indicate the phase difference between the reference clock signal and the output clock signal.

[0041] The current output module includes:

[0042] The first PMOS transistor has its source connected to the power supply and its gate connected to the output of the integration module.

[0043] The second PMOS transistor has its source connected to the power supply and its gate connected to the output of the integration module.

[0044] The third PMOS transistor has its source connected to the power supply and its gate connected to the output of the integration module.

[0045] The seventh switch has its first terminal connected to the drain of the second PMOS transistor, and its control terminal connected to the second output terminal of the frequency and phase detector.

[0046] The eighth switch has its first terminal connected to the drain of the third PMOS transistor, its control terminal connected to the first output terminal of the frequency and phase detector, and its second terminal connected to the second terminal of the seventh switch and the drain of the first PMOS transistor, and serves as the output terminal of the current output module.

[0047] When the phase of the output clock signal leads the reference clock signal, both the seventh and eighth switches are turned off. When the phase of the output clock signal lags the reference clock signal, both the seventh and eighth switches are turned on. When the phase of the output clock signal is synchronized with the reference clock signal, either the seventh or the eighth switch is turned on.

[0048] Optional, also includes:

[0049] The amplification module has its first input terminal connected to the first output terminal of the frequency and phase detector, its second input terminal connected to the second output terminal of the frequency and phase detector, its first output terminal connected to the control terminal of the eighth switch, and its second output terminal connected to the control terminal of the seventh switch.

[0050] The amplification module is used to amplify the signal edge time difference between the first pulse and the second pulse.

[0051] Optional, the amplification module includes:

[0052] The fourth inverter, whose output terminal serves as the first output terminal of the amplification module, is used to output a low level when the first input voltage of the fourth inverter's input terminal is greater than the first threshold voltage, and to output a high level when the first input voltage of the fourth inverter's input terminal is less than or equal to the first threshold voltage.

[0053] The fifth inverter's output terminal serves as the second output terminal of the amplification module. It outputs a low level when the second input voltage at the fifth inverter's input terminal is greater than the first threshold voltage, and outputs a high level when the second input voltage at the fifth inverter's input terminal is less than or equal to the first threshold voltage.

[0054] The first discharge branch has its control terminal connected to the first output terminal of the frequency and phase detector, its first terminal connected to the power supply, its second terminal grounded, and its third terminal connected to the input terminal of the fourth inverter. It is used to turn on when the first pulse is present and the level changes.

[0055] The second discharge branch has its control terminal connected to the first output terminal of the frequency and phase detector, the first terminal being grounded, and the second terminal connected to the input terminal of the fourth inverter. It is used to turn on when the second input voltage is greater than the second threshold voltage; the second threshold voltage is greater than the first threshold voltage; the discharge rate of the first discharge branch is less than the discharge rate of the second discharge branch.

[0056] The third discharge branch has its control terminal connected to the second output terminal of the frequency and phase detector, its first terminal connected to the power supply, its second terminal grounded, and its third terminal connected to the input terminal of the fifth inverter. It is used to turn on when the second pulse has a level transition.

[0057] The fourth discharge branch has its control terminal connected to the second output terminal of the frequency and phase detector, its first terminal grounded, and its second terminal connected to the input terminal of the fifth inverter. It is used to turn on when the first input voltage is greater than the second threshold voltage. The discharge speed of the third discharge branch is less than that of the fourth discharge branch.

[0058] Optionally, the first discharge branch includes:

[0059] The fourth PMOS transistor has its source connected to the power supply.

[0060] The gate of the first NMOS transistor is connected to the gate of the fourth PMOS transistor and the first output terminal of the frequency and phase detector, respectively, and the drain is connected to the drain of the fourth PMOS transistor and the input terminal of the fourth inverter, respectively.

[0061] The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, the gate is connected to a preset power supply, and the source is grounded.

[0062] The third discharge branch includes:

[0063] The fifth PMOS transistor has its source connected to the power supply.

[0064] The gate of the third NMOS transistor is connected to the gate of the fifth PMOS transistor and the second output terminal of the frequency and phase detector, respectively, and the drain is connected to the drain of the fifth PMOS transistor and the input terminal of the fifth inverter, respectively.

[0065] The fourth NMOS transistor has its drain connected to the source of the third NMOS transistor, its gate connected to a preset power supply, and its source grounded.

[0066] Optionally, the second discharge branch includes:

[0067] The fifth NMOS transistor has its gate connected to the first output terminal of the frequency and phase detector;

[0068] The drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, and the source is grounded.

[0069] The fourth discharge branch includes:

[0070] The seventh NMOS transistor has its gate connected to the second output terminal of the frequency and phase detector, and its drain connected to the input terminal of the fifth inverter and the gate of the sixth NMOS transistor, respectively.

[0071] The drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor, the source is grounded, and the gate is connected to the input of the fourth inverter and the drain of the fifth NMOS transistor, respectively.

[0072] Optionally, the second discharge branch may also include:

[0073] Several first sub-transistors are connected in series, and the first end of the series circuit is connected to the source of the sixth NMOS transistor. The second end of the series circuit is grounded. The control terminals of the several first sub-transistors are all connected to the first drive signal. The first drive signal is configured to control the number of first sub-transistors connected to the second discharge branch.

[0074] And / or,

[0075] The fourth discharge branch also includes:

[0076] Several second sub-transistors are connected in series, and the first end of the series circuit is connected to the source of the eighth NMOS transistor. The second end of the series circuit is grounded. The control terminals of the several second sub-transistors are all connected to the second drive signal. The second drive signal is configured to control the number of second sub-transistors connected to the fourth discharge branch.

[0077] To address the aforementioned technical problems, this invention also provides a phase-locked loop (PLL), comprising a frequency divider and the aforementioned PLL circuit. The input terminal of the frequency divider is connected to the output terminal of the oscillator in the PLL circuit, and the output terminal is connected to the second input terminal of the phase detection module in the PLL circuit.

[0078] To address the aforementioned technical problems, this invention also provides a clock circuit for use in a transceiver; including a clock distribution buffer and several of the aforementioned phase-locked loops connected one-to-one with several transceiver channels in the transceiver;

[0079] The input of the clock distribution buffer is connected to a reference clock signal; the phase-locked loop is used to provide a clock signal for the corresponding transceiver channel based on the reference clock signal.

[0080] As can be seen from the above technical solution, the integration module can perform integration processing based on the phase sequence relationship between the reference clock signal and the output clock signal detected by the phase detection module. The current output module can output a current signal that is linearly related to the phase difference between the reference clock signal and the output clock signal based on the pulse signal output by the phase detection module and the voltage signal output by the integration module. The beneficial effect of this invention is that it utilizes the dual-loop structure formed by the integration path corresponding to the integration module and the proportional path corresponding to the current output module to achieve the function of a linear control loop similar to a charge pump, avoiding the use of a charge pump to achieve phase-locked loop of the clock signal. This effectively reduces the power consumption and area occupied by the entire phase-locked circuit and phase-locked loop, so as to provide clock signals for each transceiver channel in the SerDes transceiver under the premise of low power consumption and small area. Attached Figure Description

[0081] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0082] Figure 1 This is a schematic diagram of a phase-locked loop circuit provided in an embodiment of the present invention;

[0083] Figure 2 A schematic diagram of the structure of an integration module provided in an embodiment of the present invention;

[0084] Figure 3 This is a schematic diagram of the structure of a step size configuration module provided in an embodiment of the present invention;

[0085] Figure 4 A schematic diagram of a current output module and an oscillator provided in an embodiment of the present invention;

[0086] Figure 5 This is a schematic diagram of the structure of an amplification module provided in an embodiment of the present invention;

[0087] Figure 6 This is a schematic diagram illustrating the signal amplification function of an amplification module provided in an embodiment of the present invention;

[0088] Figure 7 This is a schematic diagram of a phase-locked loop provided in an embodiment of the present invention;

[0089] Figure 8 This is a schematic diagram of a clock circuit provided in an embodiment of the present invention. Detailed Implementation

[0090] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0091] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0092] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0093] Next, a phase-locked circuit provided by an embodiment of the present invention will be described in detail. See also Figure 1 As shown, Figure 1 This is a schematic diagram of a phase-locked loop (PLL) circuit provided in an embodiment of the present invention; the PLL circuit includes:

[0094] Phase detection module 1 has a first input terminal connected to a reference clock signal and a second input terminal connected to the output clock signal of a phase-locked loop circuit. It is used to detect the phase sequence relationship between the reference clock signal and the output clock signal and output a pulse signal based on the phase sequence relationship.

[0095] Integration module 2, with its input end connected to the output end of phase detection module 1, is used to integrate the pulse signal to generate a corresponding voltage signal;

[0096] The current output module 3 has its input terminals connected to the output terminals of the phase detection module 1 and the integration module 2, respectively, and is used to output a current signal based on pulse signals and voltage signals; the current signal is linearly correlated with the phase difference between the reference clock signal and the output clock signal.

[0097] Oscillator 4 has its control terminal connected to the output terminal of current output module 3. The output terminal serves as the output terminal of the phase-locked loop circuit, used to output the output clock signal of the phase-locked loop circuit. Based on the current signal, the frequency of the output clock signal is adjusted to control the phase of the output clock signal to remain synchronized with the reference clock signal.

[0098] Understandably, considering the complex circuit structure of the charge pump used in current PLLs (Phase-locked loops), which require a large area and consume a lot of power, this application provides a novel phase-locked circuit architecture to better apply PLLs in low-power, small-area SerDes transceivers. The phase-locked circuit specifically includes a phase detection module 1, an integration module 2, a current output module 3, and an oscillator 4. The output clock signal from the phase-locked circuit is fed back to the second input of the phase detection module 1. The phase detection module 1 compares this signal with the reference clock signal connected to its first input to detect the phase relationship between the reference clock signal and the output clock signal. This phase relationship includes whether the output clock signal leads or lags the reference clock signal. Furthermore, the phase detection module 1 outputs a corresponding pulse signal to characterize this phase relationship. After receiving the pulse signal output by the phase detection module 1, the integration module 2 smoothly converts the pulse signal representing the phase error into a continuous voltage signal for controlling the current output module 3 through integration processing. After receiving the voltage signal and the pulse signal, the current output module 3 generates a current signal that is linearly related to the phase difference between the reference clock signal and the output clock signal. Generally, the current signal is positively linearly related to the phase difference between the reference clock signal and the output clock signal. The larger the phase difference, the larger the current signal, and the greater the frequency adjustment of the oscillator 4 for the output clock signal. The oscillator 4 is used to generate and output the output clock signal, and dynamically adjusts the frequency of the output clock signal under the action of the current signal. Through the feedback control of the entire feedback loop, the final output clock signal is synchronized with the reference clock signal. Even better, the phase of the output clock signal is completely consistent with the reference clock signal.

[0099] It should be noted that the phase detection module 1 and the current output module 3 work together to form the proportional feedback loop in the phase-locked loop (PLL) circuit, and the phase detection module 1 and the integral module 2 work together to form the integral feedback loop in the PLL circuit. When there is a phase error in the output clock signal, the integral loop accumulates the deviation by integrating the phase error over time. This accumulates the deviation and controls the current output module 3 and the oscillator 4 to adjust in a manner proportional to the accumulated deviation. The accumulation and persistence of the integral provide a coarse adjustment direction for the oscillator 4, ensuring that the phase of the final output clock signal converges to the target of synchronization with the reference clock signal, thus achieving large-scale adjustment of the output clock signal phase. At the same time, considering that the PLL circuit may experience small, instantaneous deviation fluctuations due to external disturbances, the proportional loop directly outputs an adjustment amount based on the phase error of the current output clock signal to quickly respond to the phase deviation between the two clock signals, suppress the fluctuation amplitude, and perform dynamic calibration based on the coarse adjustment of the integral loop. This dual-loop structure combines an integral loop and a proportional loop, with the current output module 3 of the proportional loop connected to the oscillator 4. This achieves a linear control loop function similar to a charge pump, enabling the phase-locked loop (PLL) to achieve phase locking without using a charge pump, thus reducing power consumption and area. The integral module 2 also provides infinite DC gain, ensuring zero static phase error after locking, enabling low-pass filtering of the voltage signal, smoothing the control voltage, and suppressing noise and spurious signals. By setting the bandwidth and stability of the integral loop, the response speed and smoothness of the PLL can be effectively guaranteed.

[0100] Furthermore, this application does not make any special limitations on the specific types and implementation methods of the phase detection module 1, the integration module 2, the current output module 3, and the oscillator 4. The phase detection module 1 can be implemented using various types of phase detectors, and the integration module 2 can be implemented using various types of integrators. In order to further reduce the area and power consumption, the integration module 2 can be implemented using a charge-shared integrator. The oscillator 4 needs to be able to perform frequency control according to the current signal, so it can be implemented using a current-controlled oscillator 4.

[0101] This invention provides a phase-locked loop (PLL) circuit. By adjusting the PLL's circuit architecture, the power consumption and area of ​​the PLL can be significantly reduced while maintaining low jitter performance. This allows for a reshaping of the clock generation and distribution method in multi-channel SerDes transceivers. Each transceiver channel can be individually configured with this low-power, small-area PLL to multiply the clock signal, enabling the use of a low-frequency input reference clock for clock distribution across each transceiver channel. This avoids the need for high-frequency clocks in long-distance, multi-load clock distribution and transmission, significantly reducing the power consumption of the clock circuit. This further reduces the power consumption of multi-channel SerDes transceivers for D2D applications, improving their energy efficiency. Based on the PLL circuit provided in this application, a PLL clock multiplier integrated circuit design with ultra-small area and low power consumption characteristics can be realized.

[0102] See Figure 2 As shown, Figure 2 This is a schematic diagram of an integration module provided in an embodiment of the present invention; as an optional embodiment, the phase detection module 1 includes a binary phase detector 12, the first input terminal of the binary phase detector 12 is connected to a reference clock signal, and the second input terminal is connected to the output clock signal of a phase-locked loop circuit;

[0103] The binary phase detector 12 is used to output a first level when the phase of the output clock signal leads the reference clock signal, and output a second level when the phase of the output clock signal lags the reference clock signal; the first level and the second level are opposite.

[0104] Integration module 2 includes:

[0105] The first capacitor C1 has its first terminal grounded.

[0106] The first terminal of the second capacitor C2 is grounded.

[0107] The first control module has its input terminal connected to the output terminal of the binary phase detector 12, and its output terminal connected to the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2, respectively. It also serves as the output terminal of the integration module 2. When the binary phase detector 12 outputs a first level, it controls the transfer of charge from the second capacitor C2 to the first capacitor C1; when the binary phase detector 12 outputs a second level, it controls the transfer of charge from the first capacitor C1 to the second capacitor C2.

[0108] It is easy to understand that, considering the differences in the control signals required by the integration module 2 and the current output module 3, the phase detection module 1 is designed with a frequency-phase detector 11 and a binary phase detector 12 to respectively implement the control signals required by the current output module 3 and the integration module 2. The binary phase detector 12 and the integration module 2 form an integration loop. The integration module 2 only needs to determine the phase sequence between the output clock signal and the reference clock signal to control the integration capacitor to charge or discharge accordingly. Therefore, the binary phase detector 12 is used to identify the phase sequence between the output clock signal and the reference clock signal, and outputs the corresponding level signal according to the different phase sequences. To avoid the high power consumption and large area occupied by the large capacitance of the integration capacitor, this application uses a charge-sharing integrator to implement the integration module 2. The integration module 2 is equipped with a first capacitor C1 as the integration capacitor and a second capacitor C2 as a shared capacitor that shares the charge with the integration capacitor. The voltage across the integration capacitor is the voltage signal output by the integration module 2.

[0109] Furthermore, to avoid the influence of the voltage of the second capacitor C2 on the final output voltage signal, an intermediate switch S0 can be added to the integration module 2. The intermediate switch S0 is located between the second terminals of the first capacitor C1 and the second capacitor C2. The intermediate switch S0 is turned on when charge transfer between the two capacitors is required, and turned off after the charge transfer is complete and the voltage across the second capacitor C2 stabilizes. Specifically, the level signal BBPD output by the binary phase detector 12 can be directly used. OUT To control the intermediate switch S0, when the level signal BBPD... OUT During level switching, the intermediate switch S0 is turned on for a preset time and then turned off, as long as the level signal BBPD is active. OUT When a level switch is performed, the intermediate switch S0 will be turned on for a preset duration. This application does not impose any specific limitations on the specific type or implementation method of the intermediate switch S0; other drive signals can also be used to control the intermediate switch S0, not limited to the level signal BBPD. OUT This application does not impose any special restrictions on the specific value of the preset duration, etc., and it can be set according to the actual capacity of the first capacitor C1 and the second capacitor C2, etc.

[0110] It should be noted that if the output clock signal leads the reference clock signal, the first control module will control the charge of the second capacitor C2 to transfer to the first capacitor C1 to charge the integrating capacitor, thereby increasing the voltage signal output by the integrating module 2. The increased voltage signal will control the current signal output by the current output module 3 to decrease. After receiving the decreased current signal, the oscillator 4 will control the frequency of the output clock signal to decrease, thus slowing down the output clock signal and correcting the lead error of the output clock signal. If the output clock signal lags the reference clock signal, the first control module will control the charge of the first capacitor C1 to transfer to the second capacitor C2 to discharge the integrating capacitor, thereby decreasing the voltage signal output by the integrating module 2. The decreased voltage signal will control the current signal output by the current output module 3 to increase. After receiving the increased current signal, the oscillator 4 will control the frequency of the output clock signal to increase, thus speeding up the output clock signal and correcting the lag error of the output clock signal. This application does not impose any special limitations on the specific types and implementation methods of the binary phase detector 12 and its output first and second levels, nor does it impose any special limitations on the specific types and implementation methods of the first capacitor C1, the second capacitor C2, and the first control module.

[0111] It should be further noted that the voltage signal V of the previous reference clock cycle is set. I For V I(n-1) The voltage signal V of the current reference clock cycle I For V I(n) Then, the voltage V sampled at the first terminal of the second capacitor C2 during the current reference clock cycle is... CS It can be represented as:

[0112] V CS(n) =V I(n-1) + ;

[0113] in, The voltage corresponding to the amount of charge transferred during the charge transfer process. Therefore, based on charge conservation, the relationship between the voltages across the first capacitor C1 and the second capacitor C2 can be expressed as:

[0114] V CS(n) C S +V I(n-1) C I =V I(n) [C S +C I ];

[0115] Among them, C I Let C1 be the capacitance value. S Let C2 be the capacitance value of the second capacitor; combining the two formulas above, we can obtain:

[0116] V I(n) -V I(n-1) =[C S / (C S +C I )]× ;

[0117] Therefore, it can be seen that the integration module 2 has an integration function, and the integration output step size, i.e., the gain V of the integrator, is... I(n) -V I(n-1) With C S C I and Relevant. If C S < <C I Therefore, the integrator gain is approximately equal to (C). S / C I The gain is proportional to the integrator. To ensure loop stability, the integrator gain of the PLL needs to be sufficiently small. Therefore, for the charge-shared integrator used in this embodiment, a C... S A sufficiently small second capacitor C2 is sufficient to avoid using a larger C. I The second capacitor C2 is used to ensure a sufficiently low integral gain. A sufficiently small second capacitor C2 ensures a sufficiently small integrator gain to guarantee loop stability of the phase-locked loop. Therefore, this integrator module 2 supports synchronous reduction of C. S and C I By using small capacitors to implement both the first capacitor C1 and the second capacitor C2, the capacitance value of the integrating capacitor is significantly reduced, thereby significantly reducing the area of ​​the entire phase-locked loop (PLL) circuit while maintaining a suitable gain. The capacitance value of the second capacitor C2 is C... S In the smallest case, the second capacitor C2 is implemented directly using the intermediate switch S0, the 2-to-1 selector 22, and the parasitic capacitance of the connection between them, which is only 1~2 fF; therefore, in order to ensure C S The value should be small enough to minimize the size of the intermediate capacitor and the crystal size of the 2-to-1 selector 22 while meeting the setup time requirements, ideally approaching the smallest transistor size of the process node used.

[0118] Specifically, this embodiment utilizes the configuration of the first capacitor C1 and the second capacitor C2 in the charge-sharing integrator to integrate the phase error. By setting the second capacitor C2 to be sufficiently small, the size of the integrating capacitor can be significantly reduced while ensuring the gain, thereby significantly reducing the area of ​​the integrating module 2 and the entire phase-locked circuit.

[0119] As an optional embodiment, the first control module includes:

[0120] The step size configuration module 21 has its input terminal connected to the output terminal of the integration module 2, and is used to generate a first voltage and a second voltage based on the voltage signal output by the integration module 2; the voltage value of the first voltage is greater than the voltage across the first capacitor C1, and the voltage across the first capacitor C1 is greater than the voltage value of the second voltage.

[0121] Selector 22 has a first input terminal connected to the first output terminal of step configuration module 21, a second input terminal connected to the second output terminal of step configuration module 21, and a control terminal connected to the output terminal of binary phase detector 12. It is used to output a first voltage when binary phase detector 12 outputs a first level and output a second voltage when binary phase detector 12 outputs a second level.

[0122] Understandably, the charge transfer between the first capacitor C1 and the second capacitor C2 can be controlled by configuring the first control module to output different voltage values. Simultaneously, considering that the integrator module 2 needs to maintain a relatively constant gain in order to achieve a low and stable integration path gain, [further details needed]. To achieve charge transfer, if a fixed potential is directly used to achieve the first and second voltages, then... Will follow V I The gain of the integral path changes with V, causing it to change accordingly. I The voltage changes drastically, which in turn deteriorates the loop stability of the PLL. Therefore, this embodiment further proposes the design of a step size configuration module 21, which is used to implement the first voltage and the second voltage. A 2-to-1 selector 22 is used to output either the first voltage or the second voltage. Taking a high level as an example, if the phase of the output clock signal leads the reference clock signal, BBPDOUT=1, and the step size configuration module 21 outputs the first voltage V. H At this time, the voltage across the second capacitor C2 is set to the first voltage V by the first control module. H And the first voltage V H The voltage across the first capacitor C1 is always greater than the voltage across the second capacitor C2, which has a higher voltage, so charge will transfer from the second capacitor C2 to the first capacitor C1, thus charging the integrating capacitor. If the phase of the output clock signal lags behind the reference clock signal, BBPDOUT=0, and the step size configuration module 21 outputs the second voltage V. L At this time, the voltage across the second capacitor C2 is set by the first control module to the second voltage V. L And the second voltage V LThe voltage across the first capacitor C1 is always less than the voltage across the second capacitor C2, thus transferring charge from the higher-voltage first capacitor C1 to the second capacitor C2, discharging the integrating capacitor. This application does not specifically limit the specific type and implementation of the step size configuration module 21 and the selector 22. Specifically, the step size configuration module 21 can follow the voltage across the first capacitor C1 using a follower, and then further combine this with a circuit topology consisting of switches and capacitors to achieve voltage superposition and voltage reduction, thereby achieving a constant voltage. .

[0123] Specifically, the selector 22 can be used to select either the first voltage or the second voltage output, thereby controlling the charging or discharging of the integrating capacitor. Meanwhile, a constant voltage can be achieved by designing the step size configuration module 21. This ensures a stable step size and constant integrator gain, thereby guaranteeing loop stability and the stability of the entire phase-locked loop (PLL).

[0124] See Figure 3 As shown, Figure 3 A schematic diagram of a step size configuration module provided in an embodiment of the present invention; as an optional embodiment, the step size configuration module 21 includes:

[0125] The voltage divider circuit has a first input terminal connected to the power supply and a second input terminal grounded, used to output a preset voltage based on the power supply.

[0126] Third capacitor C3;

[0127] The first switch S1, with its first end connected to the output end of the integration module 2, is used to turn on when the voltage of the third capacitor C3 reaches a preset voltage.

[0128] The second switch S2 has its first end connected to the output end of the voltage divider circuit and its second end connected to the first end of the third capacitor C3. It also serves as the first output end of the step size configuration module 21, which is used to turn on when a charging signal is received and turn off when the voltage of the third capacitor C3 reaches a preset voltage.

[0129] The third switch S3 has its first terminal grounded and its second terminal connected to the second terminal of the first switch S1 and the second terminal of the third capacitor C3, respectively. It is used to turn on when a charging signal is received and turn off when the voltage of the third capacitor C3 reaches a preset voltage.

[0130] Fourth capacitor C4;

[0131] The fourth switch S4 has its first end connected to the output end of the integration module 2, and is used to turn on when the voltage of the fourth capacitor C4 reaches a preset voltage.

[0132] The fifth switch S5 has its first end connected to the output of the voltage divider circuit, and its second end connected to the first end of the fourth capacitor C4 and the second end of the fourth switch S4, respectively. It is used to turn on when a charging signal is received and turn off when the voltage of the fourth capacitor C4 reaches the preset voltage.

[0133] The sixth switch S6 has its first end grounded, its second end connected to the second end of the fourth capacitor C4, and serves as the second output terminal of the step configuration module 21. It is used to turn on when a charging signal is received and to turn off when the voltage of the third capacitor C3 reaches a preset voltage.

[0134] It's easy to understand that the step size configuration module 21 can be implemented directly using a circuit architecture consisting of switches and capacitors. First, a voltage divider circuit is used to provide a preset voltage. After the preset voltage is established, the second switch S2 and the third switch S3 can be turned on by a preset charging signal. At this time, the first switch S1 is turned off, and the third capacitor C3 will be charged through the charging circuit formed by the second switch S2 and the third switch S3. Eventually, the voltage across the third capacitor C3 will stabilize at the preset voltage. After the voltage across the third capacitor C3 reaches the preset voltage and stabilizes, the second switch S2 and the third switch S3 are turned off, and the first switch S1 is turned on. At this time, the voltage across the second terminal of the third capacitor C3 will be equal to the voltage across the first capacitor C1 and the first switch S1, which is the output voltage V of the integrator module 2. I Keeping them equal, the voltage at the first terminal of the third capacitor C3 is set to V. I + This outputs the first voltage V. H =V I + On the other hand, after the preset voltage is established, the fifth switch S5 and the sixth switch S6 can be turned on by a preset charging signal. At this time, the fourth switch S4 is turned off, and the fourth capacitor C4 will be charged through the charging circuit formed by the fifth switch S5 and the sixth switch S6. Finally, the voltage across the fourth capacitor C4 stabilizes at the preset voltage. After the voltage across the fourth capacitor C4 reaches the preset voltage and stabilizes, the fifth switch S5 and the sixth switch S6 are turned off, and the fourth switch S4 is turned on. At this time, the voltage across the first terminal of the fourth capacitor C4 will be equal to the voltage across the first capacitor C1, i.e., the output voltage V of the integrator module 2, due to the voltage across the fourth switch S4 and the first capacitor C1. I Keeping them equal, the voltage at the second terminal of the fourth capacitor C4 is set to V. I - This outputs a second voltage V. L =V I - .

[0135] It should be noted that this application does not impose any special limitations on the specific implementation method of the voltage divider circuit or the specific value of the preset voltage, which can be set according to the gain requirements of the integrator, etc. Similarly, this application does not impose any special limitations on the specific type and implementation method of the power supply. This application does not impose any special limitations on the specific types and implementation methods of the third capacitor C3, the fourth capacitor C4, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6. The switches can be implemented using various types of controllable switches. It is preferable that the third capacitor C3 and the fourth capacitor C4 be implemented using capacitors of approximately 100fF, which, on the one hand, will not significantly increase the area, and on the other hand, can be significantly larger than the parasitic capacitance of the switches and wiring (i.e., the minimum capacitance value of the second capacitor C2), thereby avoiding… The losses during the transfer process between the third capacitor C3 and the fourth capacitor C4. The specific implementation of the preset charging signal can be set according to the specific application requirements of the integrator; this application does not impose any particular limitations here. The step size configuration module 21 maintains the output of the first voltage and the second voltage, waiting for the selector 22 to select the output.

[0136] Specifically, this embodiment proposes a specific implementation of the step size configuration module 21, which utilizes a switched capacitor circuit to respectively implement V H =V I + and V L =V I - Thus providing a constant And is able to provide a constant To stabilize the gain of the charge-sharing integrator, and combined with the circuit design of the charge-sharing integrator, the stability of the PLL loop is maintained while significantly reducing the area. This ensures the stability and reliability of the loop while reducing power consumption and area.

[0137] As an optional embodiment, the voltage divider circuit includes:

[0138] A fixed resistor R1 is connected to the power supply at its first end.

[0139] The variable resistor R2 has its first end grounded and its second end connected to the second end of the fixed resistor R1, serving as the output terminal of the voltage divider circuit.

[0140] Understandably, a voltage divider circuit can be implemented using a fixed resistor R1 and a variable resistor R2 connected in series, with the voltage across the variable resistor R2 serving as the voltage divider. The output is generated through a resistor voltage divider. This is so that when the gain requirement of the integration module 2 changes, the gain of the integration module 2 can be adjusted directly by adjusting the resistance value of the variable resistor R2. This application does not specifically limit the specific types and implementation methods of the fixed resistor R1 and the variable resistor R2.

[0141] Specifically, the preset voltage is generated through a voltage divider circuit, which is simple, effective, and easy to implement. The entire circuit structure is simple, easy to implement, low in cost, and small in size, which is beneficial to the low power consumption and small area of ​​the entire phase-locked circuit. At the same time, the gain of the integral module 2 is adjustable through the design of the variable resistor R2, which expands the application scenarios and applicable range of the entire phase-locked circuit and improves the flexibility of the phase-locked circuit.

[0142] See Figure 4 As shown, Figure 4 A schematic diagram of a current output module and an oscillator provided for an embodiment of the present invention; as an optional embodiment, the step size configuration module 21 further includes:

[0143] The first follower U1 has its non-inverting input connected to the output of the integration module 2, and its output connected to the inverting input of the first follower U1 and the first terminal of the first switch S1, respectively.

[0144] The second follower U2 has its non-inverting input connected to the output of the integrator module 2, and its output connected to the inverting input of the second follower U2 and the first terminal of the fourth switch S4.

[0145] It is not difficult to understand that, in order to further ensure To maintain the constant step size, the step size configuration module 21 can be further configured to set a first follower U1 and a second follower U2 to generate two follower V paths. I The voltage signal, based on these two follower V I The voltage signal is implemented using a rail-to-rail input / output structure to achieve the first voltage and the second voltage respectively, ensuring that the first voltage and the second voltage are consistent with V. I The following changes between them. This application does not make any special restrictions on the specific type and implementation method of the first follower U1 and the second follower U2, and they can be implemented by means of voltage followers based on operational amplifiers.

[0146] Specifically, V is amplified through a rail-to-rail input / output structure. I The dynamic range allows the integrator module 2 to operate at a relatively large V. I It has a relatively constant gain within the range, further ensuring the stability and reliability of the loop.

[0147] As an optional embodiment, the oscillator 4 includes:

[0148] The first inverter INV1 has its control terminal connected to the output terminal of the current output module 3, and its ground terminal is grounded.

[0149] The second inverter INV2 has its control terminal connected to the output terminal of the current output module 3, its ground terminal grounded, and its input terminal connected to the output terminal of the first inverter INV1.

[0150] The third inverter INV3 has its control terminal connected to the output terminal of the current output module 3, its ground terminal grounded, its input terminal connected to the output terminal of the second inverter INV2, its output terminal connected to the input terminal of the first inverter INV1, and serves as the output terminal of the oscillator 4.

[0151] It is understandable that an inverter circuit can be used to implement oscillator 4. The switching characteristics of the inverters are used to introduce self-oscillation, thereby generating the output clock signal. Simultaneously, the current signal output from current output module 3 is applied to the control terminals of each inverter. Specifically, the control terminals of the inverters can be the gate control paths of the transistors in the inverters, to achieve frequency control of the output clock signal. This application does not impose any particular limitations on the specific types and implementation methods of the first inverter INV1, the second inverter INV2, and the third inverter INV3. In practical applications, the implementation of oscillator 4 is not limited to three inverters; the number of inverters can be set and adjusted according to actual application requirements.

[0152] Specifically, the oscillator 4 is implemented using an inverter circuit, which has a simple structure, low cost and is easy to integrate. This is beneficial for the small-area implementation of the entire phase-locked circuit and phase-locked loop. In addition, the inverter has relatively low static power consumption, which is beneficial for the low power consumption implementation of the entire phase-locked circuit and phase-locked loop.

[0153] As an optional embodiment, the phase detection module 1 includes a frequency and phase detector 11, and the pulse signal includes a first pulse and a second pulse;

[0154] The first input terminal of the frequency and phase detector 11 is connected to a reference clock signal, and the second input terminal is connected to the output clock signal of the phase-locked loop circuit. The first output terminal is used to output a first pulse, and the second output terminal is used to output a second pulse. The first pulse is configured to indicate that the phase of the output clock signal leads the reference clock signal, and the second pulse is configured to indicate that the phase of the output clock signal lags the reference clock signal. The pulse width difference between the first pulse and the second pulse is configured to indicate the phase difference between the reference clock signal and the output clock signal.

[0155] Current output module 3 includes:

[0156] The first PMOS transistor MP1 has its source connected to the power supply and its gate connected to the output of the integration module 2.

[0157] The source of the second PMOS transistor MP2 is connected to the power supply, and the gate is connected to the output of the integration module 2.

[0158] The third PMOS transistor MP3 has its source connected to the power supply and its gate connected to the output of the integration module 2.

[0159] The seventh switch S7 has its first terminal connected to the drain of the second PMOS transistor MP2, and its control terminal connected to the second output terminal of the frequency and phase detector 11.

[0160] The eighth switch S8 has its first terminal connected to the drain of the third PMOS transistor MP3, its control terminal connected to the first output terminal of the frequency and phase detector 11, and its second terminal connected to the second terminal of the seventh switch S7 and the drain of the first PMOS transistor MP1, and serves as the output terminal of the current output module 3.

[0161] When the phase of the output clock signal leads the reference clock signal, both the seventh switch S7 and the eighth switch S8 are turned off. When the phase of the output clock signal lags the reference clock signal, both the seventh switch S7 and the eighth switch S8 are turned on. When the phase of the output clock signal is synchronized with the reference clock signal, either the seventh switch S7 or the eighth switch S8 is turned on.

[0162] Understandably, the phase-locked circuit and phase-locked loop provided in this application adopt a current-controlled oscillator 4 design. A frequency-phase detector 11 is set in the phase detection module 1, and the frequency-phase detector 11 and the current output module 3 cooperate to form a proportional loop. The current output module 3 is specifically implemented using a current mirror composed of a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3. The first PMOS transistor MP1 outputs a current I under the action of the voltage signal output by the integrator module 2. I When the output clock signal leads the reference clock signal, I I It decreases; when the output clock signal lags behind the reference clock signal, I I The voltage increases. Simultaneously, the gates of the second PMOS transistor MP2 and the third PMOS transistor MP3 are also connected to the output terminal of the integrating module 2, forming a current mirror with the first PMOS transistor MP1 at a ratio of 1:α. Under the action of the voltage signal output from the integrating module 2, the second PMOS transistor MP2 and the third PMOS transistor MP3 output current I. PSimultaneously, the seventh switch S7 is connected in series with the second PMOS transistor MP2, and the eighth switch S8 is connected in series with the third PMOS transistor MP3. The eighth switch S8 is controlled by the first pulse, and the seventh switch S7 is controlled by the second pulse. This application does not impose any special limitations on the specific types and implementation methods of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3; they are specifically implemented using enhancement-mode PMOS transistors (P-channel Metal-Oxide-Semiconductor Field-Effect Transistors). Similarly, this application does not impose any special limitations on the specific types and implementation methods of the seventh switch S7 and the eighth switch S8; various types of controllable switches can be used.

[0163] It should be noted that, to ensure the accuracy and reliability of phase difference identification, the frequency and phase detector 11 uses a wide pulse and a narrow pulse to implement the first pulse and the second pulse, respectively. Taking the rising edge of the clock signal as the basis for phase detection, when the phase of the output clock signal leads the reference clock signal, the first pulse is a wide pulse and the second pulse is a narrow pulse. When the rising edge of the output clock signal is detected, the first pulse changes from low to high. When the rising edge of the reference clock signal is detected, the second pulse changes from low to high. Afterward, both the first and second pulses remain at a high level for a specific period of time before returning to a low level. Therefore, the difference between the high-level pulse width of the first pulse and the high-level pulse width of the second pulse is equal to the phase difference between the output clock signal and the reference clock signal, i.e., the phase lead error. When the phase of the output clock signal lags behind the reference clock signal, the second pulse is a wide pulse and the first pulse is a narrow pulse. When the rising edge of the reference clock signal is detected, the second pulse changes from low to high. When the rising edge of the output clock signal is detected, the first pulse changes from low to high. After that, both the first and second pulses remain at a high level for a specific period of time before returning to a low level. Therefore, the difference between the high-level pulse width of the second pulse and the high-level pulse width of the first pulse is equal to the phase difference between the reference clock signal and the output clock signal, i.e., the phase lag error.

[0164] As a specific embodiment, taking the UP signal representing the pulse signal after the difference between the first and second pulses when the output clock signal has a phase lead, and the DN signal representing the pulse signal after the difference between the second and first pulses when the output clock signal has a phase lag, for example, when the phase of the output clock signal leads the reference clock signal, i.e., UP=1, DN=0, both the seventh switch S7 and the eighth switch S8 are turned off, and the current sources formed by the second PMOS transistor MP2 and the third PMOS transistor MP3 are both turned off, and the instantaneous output current of the two current sources is 0; when the frequency and phase detector 11 has no output, i.e., UP=DN=0, either the seventh switch S7 or the eighth switch S8 is turned on, only one of the two current sources is turned on, and the other current source is turned off, and the output current of the two current sources is I. P When the phase of the output clock signal lags behind the reference clock signal, UP=0, DN=1, both the seventh switch S7 and the eighth switch S8 are turned on, the two current sources open synchronously, and the instantaneous output current of the two current sources is 2I. P Therefore, if the output clock signal leads the reference clock signal, the current signal output by the current output module 3 will decrease. Upon receiving this decreased current signal, the oscillator 4 will control the frequency of the output clock signal to decrease, thus slowing down the output clock signal and correcting the lead error. Conversely, if the output clock signal lags the reference clock signal, the current signal output by the current output module 3 will increase. Upon receiving this increased current signal, the oscillator 4 will control the frequency of the output clock signal to increase, thus speeding up the output clock signal and correcting the lag error.

[0165] It should be noted that, since the pulse width difference between the first and second pulses characterizes the phase difference between the reference clock signal and the output clock signal, and the high level of the first and second pulses directly determines the conduction duration of the corresponding seventh switch S7 or eighth switch S8, the average current output by the current output module 3 is I when the output clock signal leads the reference clock signal. P_AVG =I I +I P -I P ×( / 2π), where, This represents the phase difference between the output clock signal and the reference clock signal. When the output clock signal lags behind the reference clock signal, the average current output by current output module 3 is I. P_AVG =I I +I P +I P ×( / 2π), where, The reference clock signal is used to determine the phase difference between the reference clock signal and the output clock signal. Therefore, by using the current output module 3 in conjunction with the current-controlled oscillator 4, a linear proportional path can be achieved in the phase-locked loop (PLL), thus avoiding the use of a complex charge pump and further reducing the PLL's power consumption and area. The control current of the oscillator 4 is obtained by the current output module 3 in the proportional loop based on the pulse signal output from the frequency and phase detector 11 (I...). P ) and the integral output voltage V in the integral loop I The conversion yields (I) I ), I P Also through I I This is achieved using a current mirror. Therefore, the frequency of the PLL's output clock signal is mainly determined by the voltage signal V output from the integrating loop. I , i.e. I I Decision. Therefore, I I This can be approximated by the total current controlling oscillator 4. By using I... P_AVG Set with I I Proportional and significantly smaller than I I This allows the loop bandwidth of the phase-locked loop to be approximately constant and basically unaffected by changes in PVT conditions (process, temperature, and voltage conditions), enabling loop bandwidth tracking. This, in turn, can improve loop bandwidth while ensuring circuit stability, enhance the suppression of oscillator 4-phase noise, and reduce clock jitter and power consumption.

[0166] Specifically, based on the current output module 3 provided in this embodiment, in conjunction with the integration module 2, a charge pump-free PLL can be effectively realized. The entire current output module 3 has a simple structure, is easy to implement, and uses low-cost, small-sized components that are easy to integrate. Combined with the small capacitor design in the integration module 2, the area of ​​the entire phase-locked loop can be significantly reduced. At the same time, based on the cooperation of the current output module 3 and the integration module 2, a calibration-free loop bandwidth tracking technology is proposed, which can realize the immunity of the phase-locked loop and the PLL to PVT fluctuations. It can reliably increase the PLL bandwidth, enhance the phase noise suppression effect of the oscillator 4, and relax the phase noise requirements of the oscillator 4. This reduces the power consumption of the PLL on the one hand, and on the other hand, the enhanced phase noise suppression effect of the oscillator 4 can reduce the phase noise performance requirements of the oscillator 4, thereby reducing the power consumption of the oscillator 4 and further reducing the power consumption of the PLL. This simultaneously reduces the overall jitter and power consumption of the PLL, ultimately realizing an ultra-small area, low-jitter, low-power phase-locked loop integrated circuit that reduces the power consumption and area of ​​the PLL while maintaining low jitter.

[0167] As an optional embodiment, it also includes:

[0168] Amplification module 5 has a first input terminal connected to the first output terminal of frequency and phase detector 11, a second input terminal connected to the second output terminal of frequency and phase detector 11, a first output terminal connected to the control terminal of the eighth switch S8, and a second output terminal connected to the control terminal of the seventh switch S7.

[0169] Amplification module 5 is used to amplify the signal edge time difference between the first pulse and the second pulse.

[0170] Understandably, to further reduce the in-band phase noise of the PLL and suppress PLL output clock jitter, this application further designs an amplification module 5 in the phase-locked loop circuit. The amplification module 5 can effectively amplify the signal edge delay difference between the first and second pulses, that is, by amplifying the edge delay difference of the output signal of the frequency-phase detector 11, the gain of the frequency-phase detector 11 is effectively increased, thereby achieving the purpose of reducing the in-band phase noise of the PLL using a higher phase detector gain. Since an increase in the gain of the binary phase detector 12 is equivalent to an increase in the gain of the integration module 2, to avoid an increase in the gain of the integration module 2, this application only designs the amplification module 5 in the proportional loop, thereby reducing PLL jitter by increasing the phase detection gain. This application does not specifically limit the specific type and implementation method of the amplification module 5.

[0171] See Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of an amplification module provided in an embodiment of the present invention; see also Figure 6 As shown, Figure 6 A schematic diagram illustrating the signal amplification function of an amplification module provided in an embodiment of the present invention; as an optional embodiment, the amplification module 5 includes:

[0172] The fourth inverter INV4 has its output terminal serving as the first output terminal of the amplifier module 5. It outputs a low level when the first input voltage at the input terminal of the fourth inverter INV4 is greater than the first threshold voltage, and outputs a high level when the first input voltage at the input terminal of the fourth inverter INV4 is less than or equal to the first threshold voltage.

[0173] The fifth inverter INV5 has its output terminal serving as the second output terminal of the amplifier module 5. It outputs a low level when the second input voltage at the input terminal of the fifth inverter INV5 is greater than the first threshold voltage, and outputs a high level when the second input voltage at the input terminal of the fifth inverter INV5 is less than or equal to the first threshold voltage.

[0174] The first discharge branch 51 has its control terminal connected to the first output terminal of the frequency and phase detector 11, its first terminal connected to the power supply, its second terminal grounded, and its third terminal connected to the input terminal of the fourth inverter INV4. It is used to turn on when the first pulse exists and the level changes.

[0175] The second discharge branch 52 has its control terminal connected to the first output terminal of the frequency and phase detector 11. The first terminal is grounded, and the second terminal is connected to the input terminal of the fourth inverter INV4. It is used to turn on when the second input voltage is greater than the second threshold voltage. The second threshold voltage is greater than the first threshold voltage. The discharge speed of the first discharge branch 51 is less than the discharge speed of the second discharge branch 52.

[0176] The third discharge branch 53 has its control terminal connected to the second output terminal of the frequency and phase detector 11, its first terminal connected to the power supply, its second terminal grounded, and its third terminal connected to the input terminal of the fifth inverter INV5. It is used to turn on when the second pulse is present and the level changes.

[0177] The fourth discharge branch 54 has its control terminal connected to the second output terminal of the frequency and phase detector 11, its first terminal grounded, and its second terminal connected to the input terminal of the fifth inverter INV5. It is used to turn on when the first input voltage is greater than the second threshold voltage. The discharge speed of the third discharge branch 53 is less than that of the fourth discharge branch 54.

[0178] It is easy to understand that this embodiment amplifies the edge delay difference between two pulses by employing a design with multiple discharge branches. The first discharge branch 51 and the third discharge branch 53 serve as slow discharge branches, while the second discharge branch 52 and the fourth discharge branch 54 serve as fast discharge branches. When a discharge branch is turned on, it discharges the first or second input voltage connected to it. The entire amplification module 5 is implemented using a differential symmetrical structure, with the two fast discharge branches cross-coupled. Taking the identification of the high level of the clock signal as an example, the level transition between the first pulse and the second pulse corresponds to the rising edge, such as... Figure 6 As shown, if the output clock signal leads the reference clock signal, the first pulse output by the frequency and phase detector 11 changes from low to high level first, and the second pulse changes from low to high level afterward. Therefore, the signals I input to the first discharge branch 51 and the second discharge branch 52 are... UP First, the voltage level changes to high, controlling both the first discharge branch 51 and the second discharge branch 52 to conduct, thus affecting the first input voltage V at the input terminal of the fourth inverter INV4. INTP Rapid discharge; input signals I to the third discharge branch 53 and the fourth discharge branch 54 DN The voltage then goes high, turning on both the third discharge branch 53 and the fourth discharge branch 54, thus controlling the second input voltage V at the input terminal of the fifth inverter INV5. INTN Rapid discharge; however, because the first discharge branch 51 and the second discharge branch 52 are turned on first, the discharge causes V to... INTP The voltage drops rapidly when V INTP Once the voltage falls below the second threshold voltage, the fourth discharge branch 54 will stop conducting, and the first input voltage V will... INTP It will first be connected to the second input voltage V INTNThe voltage drops to the second threshold voltage, therefore the first discharge branch 51 and the second discharge branch 52 corresponding to the first pulse will continue to discharge rapidly until the first input voltage V drops. INTP When the voltage drops below the first preset threshold, the fourth inverter INV4 will output a high level to represent the first pulse; while the second input voltage V... INTN It will now discharge rapidly under the action of the third discharge branch 53 and the fourth discharge branch 54 until the first input voltage V... INTP After the voltage drops below the second threshold voltage, only the third discharge branch 53 will discharge the second input voltage V. INTN Discharge proceeds, but the discharge rate decreases significantly until the second input voltage V is reached. INTN After the discharge rate falls below the first preset threshold, the fifth inverter INV5 will output a high level to represent the second pulse. Due to the reduced discharge speed, the high-level output of the fifth inverter INV5 will be significantly later than the high-level output of the fourth inverter INV4. This amplifies the time difference between the rising edge of the amplified first pulse and the rising edge of the second pulse, thus reducing the original... Time difference magnified to The amplification process when the output clock signal lags behind the reference clock signal is similar and will not be described in detail here. To ensure the correctness of the time difference amplification function, the second threshold voltage needs to be greater than the first threshold voltage. Furthermore, the discharge rate of the first discharge branch 51 can be set to be less than the discharge rate of the second discharge branch 52, and the discharge rate of the third discharge branch 53 can be set to be less than the discharge rate of the fourth discharge branch 54, to further amplify this time difference. This application does not impose any special limitations on the specific types and implementation methods of the fourth inverter INV4, the fifth inverter INV5, and each discharge branch. This application does not impose any special limitations on the specific values ​​of the first and second threshold voltages; the first threshold voltage can be directly implemented using the switching threshold of the inverters (fourth inverter INV4 and fifth inverter INV5).

[0179] Specifically, by setting up symmetrically coupled discharge branches, the time difference is amplified by utilizing the difference in discharge speed, and an inverter is used to realize the output of the amplified first pulse and the second pulse, which effectively improves the signal edge time difference between the two pulse signals output by the frequency and phase detector 11, thereby improving the phase detection gain.

[0180] As an optional embodiment, the first discharge branch 51 includes:

[0181] The fourth PMOS transistor, MP4, has its source connected to the power supply.

[0182] The gate of the first NMOS transistor MN1 is connected to the gate of the fourth PMOS transistor MP4 and the first output terminal of the frequency and phase detector 11, respectively, and the drain is connected to the drain of the fourth PMOS transistor MP4 and the input terminal of the fourth inverter INV4, respectively.

[0183] The drain of the second NMOS transistor is connected to the source of the first NMOS transistor MN1, the gate is connected to a preset power supply, and the source is grounded.

[0184] The third discharge branch 53 includes:

[0185] The source of the fifth PMOS transistor, MP5, is connected to the power supply.

[0186] The gate of the third NMOS transistor MN3 is connected to the gate of the fifth PMOS transistor MP5 and the second output terminal of the frequency and phase detector 11, respectively, and the drain is connected to the drain of the fifth PMOS transistor MP5 and the input terminal of the fifth inverter INV5, respectively.

[0187] The drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor MN3, the gate is connected to the preset power supply, and the source is grounded.

[0188] Understandably, a circuit built using MOS transistors can be used to implement the discharge branch. Taking the high level of the pulse signal to characterize the phase sequence as an example, for the first discharge branch 51 and the second discharge branch 52, which are slow discharge branches, the second NMOS transistor and the fourth NMOS transistor, whose gates are connected to the power supply, can be directly used for discharge. At the same time, the fourth PMOS transistor MP4, the first NMOS transistor MN1, the fifth PMOS transistor MP5, and the third NMOS transistor MN3 are set to receive the pulse signal. When the first pulse is high, the corresponding first NMOS transistor MN1 is turned on, and when the second pulse is high, the corresponding third NMOS transistor MN3 is turned on.

[0189] Specifically, the discharge branch is implemented using a circuit built with MOSFETs, which is simple, effective, and easy to implement. The components used are low-cost and small in size, which is conducive to the low power consumption and small area implementation of the entire phase-locked circuit and phase-locked loop.

[0190] As an optional embodiment, the second discharge branch 52 includes:

[0191] The gate of the fifth NMOS transistor MN5 is connected to the first output terminal of the frequency and phase detector 11;

[0192] The drain of the sixth NMOS transistor MN6 is connected to the source of the fifth NMOS transistor MN5, and the source is grounded.

[0193] The fourth discharge branch 54 includes:

[0194] The gate of the seventh NMOS transistor MN7 is connected to the second output terminal of the frequency and phase detector 11, and the drain is connected to the input terminal of the fifth inverter INV5 and the gate of the sixth NMOS transistor MN6, respectively.

[0195] The drain of the eighth NMOS transistor MN8 is connected to the source of the seventh NMOS transistor MN7, and the source is grounded. The gate is connected to the input of the fourth inverter INV4 and the drain of the fifth NMOS transistor MN5, respectively.

[0196] It's easy to understand that the fast discharge branches can be directly implemented using coupled NMOS transistors. The second discharge branch 52 uses the sixth NMOS transistor MN6 for discharge, and the fourth discharge branch 54 uses the eighth NMOS transistor MN8 for discharge. The input of the fifth inverter INV5 is connected to the gate of the sixth NMOS transistor MN6, and the input of the fourth inverter INV4 is connected to the gate of the eighth NMOS transistor MN8, thus achieving coupling between the two fast discharge branches. Simultaneously, the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 are used to receive pulse signals. When the first pulse is high, the corresponding fifth NMOS transistor MN5 is turned on; when the second pulse is high, the corresponding seventh NMOS transistor MN7 is turned on. Based on this, the second threshold voltage can be implemented using the turn-on threshold voltages of the sixth NMOS transistor MN6 and the eighth NMOS transistor MN8.

[0197] Specifically, the discharge branch is implemented using a circuit built with MOSFETs, which is simple, effective, and easy to implement. The components used are low-cost and small in size, which is conducive to the low power consumption and small area implementation of the entire phase-locked circuit and phase-locked loop.

[0198] As an optional embodiment, the second discharge branch 52 further includes:

[0199] Several first sub-transistors are connected in series, and the first end of the series circuit is connected to the source of the sixth NMOS transistor MN6. The second end of the series circuit is grounded. The control terminals of the several first sub-transistors are all connected to the first drive signal. The first drive signal is configured to control the number of first sub-transistors connected to the second discharge branch 52.

[0200] And / or,

[0201] The fourth discharge branch 54 also includes:

[0202] Several second sub-transistors are connected in series, and the first end of the series circuit is connected to the source of the eighth NMOS transistor MN8. The second end of the series circuit is grounded. The control terminals of the several second sub-transistors are all connected to the second drive signal. The second drive signal is configured to control the number of second sub-transistors connected to the fourth discharge branch 54.

[0203] Furthermore, to achieve the discharge speed difference between the first discharge branch 51 and the second discharge branch 52, as well as the discharge speed difference between the third discharge branch 53 and the fourth discharge branch 54, the second NMOS transistor in the first discharge branch 51 and the fourth NMOS transistor in the third discharge branch 53 can both be implemented using n MOS transistors connected in series, such as... Figure 5 The second NMOS transistor is implemented using n MOSFETs connected in series, from MN21 to MN2n, and the fourth NMOS transistor is implemented using n MOSFETs connected in series, from MN41 to MN4n. In the second discharge branch 52, m more MOSFETs connected in series can be added as the first sub-transistor based on the sixth NMOS transistor MN6. In the fourth discharge branch 54, m more MOSFETs connected in series can be added as the second sub-transistor based on the eighth NMOS transistor MN8. Figure 5 The amplification module 5 incorporates m series-connected MOS transistors, MN11 to MN1m, and m series-connected MOS transistors, MN31 to MN3m. When all NMOS transistors are of the same specification, the amplification gain of the amplification module 5 is m / n, which is the ratio of the discharge speed of the fast discharge branch to the discharge speed of the slow discharge branch. Multiple series-connected MOS transistors can reduce the width-to-length ratio of the equivalent NMOS transistors used in the discharge branch, thereby increasing the on-resistance of the discharge branch and reducing the discharge current. Therefore, by setting n > m, the difference in discharge speed between the discharge branches can be ensured, further improving the amplification of the time difference. Alternatively, different discharge speeds can be achieved by directly using NMOS transistors with different width-to-length ratios to implement the NMOS transistors in the fast discharge branch and the NMOS transistors in the slow discharge branch; this application does not impose any particular limitation here.

[0204] Based on this, the discharge speed in the fast discharge branch is adjustable by controlling the on / off state of the sub-tube through a specific drive signal. This application does not specifically limit the specific types and implementation methods of the first and second drive signals; in particular, a numerical control word D composed of m-bit binary numbers can be used. KTA This controls the number of sub-transistors connected in the fast discharge branch. When a bit of the binary number is 1, the corresponding sub-transistor is turned on and participates in the discharge; when a bit of the binary number is 0, the corresponding sub-transistor is turned off and does not participate in the discharge. This is equivalent to m being adjustable, thereby achieving the amplification gain K. TA Adjustable functionality. In this case, it is necessary to ensure that the equivalent width-to-length ratio of the NMOS transistors participating in the discharge in the slow discharge branch is less than the equivalent width-to-length ratio corresponding to the simultaneous conduction of m sub-transistors in the fast discharge branch.

[0205] Furthermore, the amplification gain K can also be achieved by configuring the corresponding drive signal to make n adjustable, and by coordinating with the adjustment of m. TAAdjustable function. The second NMOS transistor in the first discharge branch 51 is implemented using n series-connected third sub-transistors (NMOS transistors), and the gate of the third sub-transistor is connected to the third drive signal; the third drive signal is configured to control the number of third sub-transistors connected to the first discharge branch 51; the fourth NMOS transistor in the third discharge branch 53 is implemented using n series-connected fourth sub-transistors (NMOS transistors), and the gate of the third sub-transistor is connected to the fourth drive signal; the fourth drive signal is configured to control the number of fourth sub-transistors connected to the third discharge branch 53. Specifically, the third and fourth drive signals can be implemented using a numerical control word composed of n-bit binary numbers. To ensure the symmetry of the circuit, the first drive signal of the second discharge branch 52 and the second drive signal of the fourth discharge branch 54 use the same numerical control word D. KTA This is achieved by using the same numerical control word to implement the third drive signal of the first discharge branch 51 and the fourth drive signal of the third discharge branch 53. This allows for a more flexible amplification module 5.

[0206] Specifically, by designing the series MOSFET and the corresponding drive signal, the gain of the amplifier module 5 can be effectively adjusted, which is beneficial for fine calibration of the PLL performance.

[0207] It should be further noted that the loop bandwidth f of the phase-locked loop implemented in this application is... BW The expression is:

[0208] f BW =(K TA / 2π)×I P ×K CCO / N;

[0209] Among them, K TA K represents the gain of amplifier module 5. CCO This represents the current tuning gain of oscillator 4. When the PLL is locked, the frequency f of oscillator 4 is... CCO It can be represented as:

[0210] f CCO =I I ×K CCO =I P ×K CCO / α=Nf REF ;

[0211] Where N represents the division ratio of frequency divider 6 in the PLL, f REF The frequency of the input reference clock signal, α=I P / I I Combining the two expressions above, we can obtain:

[0212] f BW =(KTA / 2π)α×f REF ;

[0213] Therefore, it can be seen that the loop bandwidth of the PLL provided in this application is only related to the frequency of the reference clock signal, the scaling factor α, and K. TA Correlation, α and K TA The bandwidth of the PLL in this design is determined by the size ratio of the components and remains largely unchanged regardless of the PVT. Therefore, the bandwidth of the PLL can track PVT fluctuations and remain relatively constant. The loop bandwidth is approximately equal to the frequency of the input reference clock signal, thereby improving the PVT immunity of the PLL, achieving higher loop bandwidth, better suppressing the phase noise of oscillator 4, and reducing PLL jitter and power consumption.

[0214] As can be seen from the preceding text, the first voltage V H Second voltage V L The selection is based on Decision made, and C S And C I This determines the gain of the integration path. Therefore, it is necessary to determine the gain based on the tuning gain K of oscillator 4. CCO The selected appropriate C S and C I and conduct The determination of the tuning gain K; CCO A relatively large gain indicates that the oscillator 4 has a wide adjustable frequency range and is more sensitive to fluctuations. In this case, to avoid excessive fluctuations in the voltage signal output by the integrator module 2, the gain of the integrator module 2 needs to be appropriately increased. To avoid increasing the circuit area, this can be achieved by adjusting... This is to achieve gain adjustment of the integrator module 2. On the one hand, it ensures that the loop is stable enough. On the other hand, under the premise that the loop stability can be guaranteed, the gain of the integrator module 2 is increased as much as possible, thereby significantly suppressing the phase noise with a roll-off of -30dBc / dec contributed by the flicker noise of the oscillator 4, and thus optimizing the PLL output clock jitter. This is especially important for low-jitter, low-power, ultra-small area PLLs based on the ring oscillator 4 and advanced technology.

[0215] As mentioned earlier, considering that the loop bandwidth of the PLL is f BW =(K TA / 2π)α×f REF Here, it is necessary to combine the gain K of amplification module 5. TA To select the proportional coefficient α, the smaller α is, the stronger the I when the PLL is locked. P The smaller, I P The smaller the contribution of phase noise, the more important it is to reduce α, but this requires increasing K. TA To achieve, K TAExcessive values ​​not only increase the noise of amplifier module 5 itself, but also reduce its linear input range, introducing nonlinearity into the loop, which in turn worsens the overall phase noise and even jitter performance of the PLL. Therefore, α and K TA A comprehensive consideration and a compromise value are needed. The specific value can be determined by combining the simulation process. K TA The adjustability can be achieved through the method described in the previous embodiment, while leaving a certain adjustability margin for performance correction. In addition, in order to reduce the impact of the PMOS transistor noise in the current output module 3 on the phase noise of the oscillator 4, it is necessary to reduce the transconductance of the PMOS transistor in the current output module 3, that is, to increase the overdrive voltage of the PMOS transistor in the current output module 3 as much as possible while meeting the voltage margin.

[0216] See Figure 7 As shown, Figure 7 This is a schematic diagram of a phase-locked loop (PLL) provided in an embodiment of the present invention. To solve the above-mentioned technical problems, the present invention also provides a PLL, including a frequency divider 6 and the aforementioned PLL circuit. The input terminal of the frequency divider 6 is connected to the output terminal of the oscillator 4 in the PLL circuit, and the output terminal is connected to the second input terminal of the phase detection module 1 in the PLL circuit.

[0217] It is understood that, based on the phase-locked loop circuit provided in this application, a frequency divider 6 can be further added to realize a phase-locked loop. This application does not specifically limit the specific type or implementation method of the frequency divider 6. Ultimately, an ultra-small area, low-jitter, low-power phase-locked loop integrated circuit is realized. Simultaneously, by utilizing the cooperative design of the current output module 3 and the integrator module 2, loop bandwidth tracking can be achieved, significantly reducing the power consumption and area of ​​the PLL while maintaining low jitter performance. Building upon this foundation, a PLL can be configured for each transceiver channel in a SerDes transceiver, providing a local clock multiplication function for each channel. This allows the input reference clock to be implemented using a low-frequency clock signal. Only long-distance clock transmission and distribution of the low-frequency reference clock are required. After the low-frequency reference clock is allocated to the corresponding transceiver channel, the PLL multiplies the frequency to provide a high-frequency clock for the channel. This significantly reduces the power consumption of the clock circuit in a multi-channel SerDes transceiver, avoids the distribution and long-distance transmission of high-frequency clocks, and achieves the goal of reducing the power consumption of high-channel-density SerDes transceivers for D2D interconnects. Furthermore, it improves the overall integration of the transceiver, enabling the integration of more transceiver channels onto a single chip, thereby increasing the total transceiver bandwidth of D2D interconnects, improving the energy efficiency of multi-channel SerDes transceivers, and meeting the demand for higher data interaction bandwidth for enhanced AI computing power.

[0218] For a description of the features in the phase-locked loop provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the phase-locked circuit, which will not be repeated here.

[0219] See Figure 8 As shown, Figure 8 This is a schematic diagram of a clock circuit provided in an embodiment of the present invention. To solve the above-mentioned technical problems, this embodiment of the present invention also provides a clock circuit applied to a transceiver; including a clock distribution buffer U0 and several of the aforementioned phase-locked loops connected one-to-one with several transceiver channels in the transceiver;

[0220] The input of the clock distribution buffer U0 is connected to the reference clock signal; the phase-locked loop is used to provide the clock signal for the corresponding transceiver channel based on the reference clock signal.

[0221] It is not difficult to understand that this application does not impose any special restrictions on the specific type and configuration method of the clock distribution buffer U0, and can be implemented as follows: Figure 8 The setup shown includes several clock distribution buffers U0 connected one-to-one with several transmit and receive channels.

[0222] For a description of the features in the clock circuit provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the phase-locked circuit and the phase-locked loop, which will not be repeated here.

[0223] The phase-locked circuit, phase-locked loop, and clock circuit provided by the embodiments of the present invention have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0224] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0225] The phase-locked circuit, phase-locked loop, and clock circuit provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A phase-locked loop circuit, characterized in that, include: The phase detection module has a first input terminal connected to a reference clock signal and a second input terminal connected to the output clock signal of a phase-locked loop circuit. It is used to detect the phase sequence relationship between the reference clock signal and the output clock signal, and output a pulse signal based on the phase sequence relationship. An integration module, with its input end connected to the output end of the phase detection module, is used to integrate the pulse signal to generate a corresponding voltage signal. The current output module has its input terminals connected to the output terminals of the phase detection module and the integration module, respectively, and is used to output a current signal based on the pulse signal and the voltage signal. The current signal is linearly correlated with the phase difference between the reference clock signal and the output clock signal; The oscillator's control terminal is connected to the output terminal of the current output module. The output terminal serves as the output terminal of the phase-locked loop circuit, used to output the output clock signal of the phase-locked loop circuit, and adjusts the frequency of the output clock signal based on the current signal to control the phase of the output clock signal to remain synchronized with the reference clock signal. The integration module includes: The first capacitor has its first terminal grounded. The second capacitor has its first terminal grounded. The first control module has its output terminal connected to the second terminal of the first capacitor and the second terminal of the second capacitor, respectively, and serves as the output terminal of the integration module. It is used to control the transfer of charge from the second capacitor to the first capacitor when the output clock signal leads the reference clock signal, and to control the transfer of charge from the first capacitor to the second capacitor when the output clock signal lags the reference clock signal. The current output module includes: The first PMOS transistor has its source connected to the power supply and its gate connected to the output terminal of the integration module. The second PMOS transistor has its source connected to the power supply and its gate connected to the output terminal of the integration module. The third PMOS transistor has its source connected to the power supply and its gate connected to the output of the integration module. The seventh switch has its first terminal connected to the drain of the second PMOS transistor; The eighth switch has its first end connected to the drain of the third PMOS transistor, and its second end connected to the second end of the seventh switch and the drain of the first PMOS transistor, and serves as the output terminal of the current output module. When the phase of the output clock signal leads the reference clock signal, both the seventh switch and the eighth switch are turned off. When the phase of the output clock signal lags the reference clock signal, both the seventh switch and the eighth switch are turned on. When the phase of the output clock signal is synchronized with the reference clock signal, either the seventh switch or the eighth switch is turned on.

2. The phase-locked circuit according to claim 1, characterized in that, The phase detection module includes a binary phase detector, the first input terminal of which is connected to a reference clock signal, and the second input terminal of which is connected to the output clock signal of a phase-locked loop circuit; the input terminal of the first control module is connected to the output terminal of the binary phase detector. The binary phase detector is used to output a first level when the phase of the output clock signal leads the reference clock signal; When the phase of the output clock signal lags behind the reference clock signal, a second level is output; The first voltage level and the second voltage level are opposite.

3. The phase-locked circuit according to claim 2, characterized in that, The first control module includes: The step size configuration module has its input end connected to the output end of the integration module, and is used to generate a first voltage and a second voltage based on the voltage signal output by the integration module; the voltage value of the first voltage is greater than the voltage across the first capacitor, and the voltage across the first capacitor is greater than the voltage value of the second voltage. The selector has a first input terminal connected to the first output terminal of the step size configuration module, a second input terminal connected to the second output terminal of the step size configuration module, and a control terminal connected to the output terminal of the binary phase detector. It is used to output the first voltage when the binary phase detector outputs a first level and output the second voltage when the binary phase detector outputs a second level.

4. The phase-locked circuit according to claim 3, characterized in that, The step size configuration module includes: The voltage divider circuit has a first input terminal connected to the power supply and a second input terminal grounded, and is used to output a preset voltage based on the power supply. Third capacitor; The first switch, with its first end connected to the output end of the integration module, is used to turn on when the voltage of the third capacitor reaches the preset voltage. The second switch has its first end connected to the output end of the voltage divider circuit and its second end connected to the first end of the third capacitor. It also serves as the first output end of the step size configuration module. The switch is turned on when a charging signal is received and turned off when the voltage of the third capacitor reaches the preset voltage. The third switch has a first terminal grounded and a second terminal connected to the second terminal of the first switch and the second terminal of the third capacitor, respectively. It is used to turn on when a charging signal is received and turn off when the voltage of the third capacitor reaches the preset voltage. Fourth capacitor; The fourth switch, with its first end connected to the output end of the integration module, is used to turn on when the voltage of the fourth capacitor reaches the preset voltage. The fifth switch has its first end connected to the output terminal of the voltage divider circuit, and its second end connected to the first end of the fourth capacitor and the second end of the fourth switch, respectively. It is used to turn on when a charging signal is received and turn off when the voltage of the fourth capacitor reaches the preset voltage. The sixth switch has its first end grounded, its second end connected to the second end of the fourth capacitor, and serves as the second output terminal of the step configuration module. It is used to turn on when a charging signal is received and turn off when the voltage of the third capacitor reaches the preset voltage.

5. The phase-locked circuit according to claim 4, characterized in that, The voltage divider circuit includes: A fixed resistor, with its first end connected to the power supply; The variable resistor has its first end grounded and its second end connected to the second end of the fixed resistor, serving as the output terminal of the voltage divider circuit.

6. The phase-locked circuit according to claim 4, characterized in that, The step size configuration module also includes: The first follower has its non-inverting input terminal connected to the output terminal of the integral module, and its output terminal connected to the inverting input terminal of the first follower and the first terminal of the first switch, respectively. The second follower has its non-inverting input connected to the output of the integral module, and its output connected to the inverting input of the second follower and the first terminal of the fourth switch.

7. The phase-locked circuit according to claim 1, characterized in that, The oscillator includes: The first inverter has its control terminal connected to the output terminal of the current output module, and its ground terminal grounded. The second inverter has its control terminal connected to the output terminal of the current output module, its ground terminal grounded, and its input terminal connected to the output terminal of the first inverter. The third inverter has its control terminal connected to the output terminal of the current output module, its ground terminal grounded, its input terminal connected to the output terminal of the second inverter, its output terminal connected to the input terminal of the first inverter, and serves as the output terminal of the oscillator.

8. The phase-locked circuit according to any one of claims 1 to 7, characterized in that, The phase detection module includes a frequency and phase detector, and the pulse signal includes a first pulse and a second pulse. The first input terminal of the frequency and phase detector is connected to a reference clock signal, the second input terminal is connected to the output clock signal of the phase-locked loop circuit, the first output terminal is used to output a first pulse, and the second output terminal is used to output a second pulse. The first pulse is configured to indicate that the phase of the output clock signal leads the reference clock signal, the second pulse is configured to indicate that the phase of the output clock signal lags the reference clock signal, and the pulse width difference between the first pulse and the second pulse is configured to indicate the phase difference between the reference clock signal and the output clock signal; the control terminal of the seventh switch is connected to the second output terminal of the frequency and phase detector; the control terminal of the eighth switch is connected to the first output terminal of the frequency and phase detector.

9. The phase-locked circuit according to claim 8, characterized in that, Also includes: The amplification module has a first input terminal connected to the first output terminal of the frequency and phase detector, a second input terminal connected to the second output terminal of the frequency and phase detector, a first output terminal connected to the control terminal of the eighth switch, and a second output terminal connected to the control terminal of the seventh switch. The amplification module is used to amplify the signal edge time difference between the first pulse and the second pulse.

10. The phase-locked circuit according to claim 9, characterized in that, The amplification module includes: The fourth inverter, whose output terminal serves as the first output terminal of the amplification module, is used to output a low level when the first input voltage of the fourth inverter's input terminal is greater than the first threshold voltage, and to output a high level when the first input voltage of the fourth inverter's input terminal is less than or equal to the first threshold voltage. The fifth inverter, whose output terminal serves as the second output terminal of the amplification module, is used to output a low level when the second input voltage of the fifth inverter's input terminal is greater than the first threshold voltage, and to output a high level when the second input voltage of the fifth inverter's input terminal is less than or equal to the first threshold voltage. The first discharge branch has its control terminal connected to the first output terminal of the frequency and phase detector, its first terminal connected to the power supply, its second terminal grounded, and its third terminal connected to the input terminal of the fourth inverter. It is used to turn on when the first pulse has a level shift. The second discharge branch has its control terminal connected to the first output terminal of the frequency and phase detector, the first terminal being grounded, and the second terminal connected to the input terminal of the fourth inverter. It is used to conduct when the second input voltage is greater than the second threshold voltage; the second threshold voltage is greater than the first threshold voltage; and the discharge rate of the first discharge branch is less than the discharge rate of the second discharge branch. The third discharge branch has its control terminal connected to the second output terminal of the frequency and phase detector, its first terminal connected to the power supply, its second terminal grounded, and its third terminal connected to the input terminal of the fifth inverter. It is used to turn on when the second pulse has a level transition. The fourth discharge branch has its control terminal connected to the second output terminal of the frequency and phase detector, its first terminal grounded, and its second terminal connected to the input terminal of the fifth inverter. It is used to conduct when the first input voltage is greater than the second threshold voltage. The discharge speed of the third discharge branch is less than that of the fourth discharge branch.

11. The phase-locked circuit according to claim 10, characterized in that, The first discharge branch includes: The fourth PMOS transistor has its source connected to the power supply. The gate of the first NMOS transistor is connected to the gate of the fourth PMOS transistor and the first output terminal of the frequency and phase detector, respectively, and the drain is connected to the drain of the fourth PMOS transistor and the input terminal of the fourth inverter, respectively. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, the gate is connected to a preset power supply, and the source is grounded. The third discharge branch includes: The fifth PMOS transistor has its source connected to the power supply. The gate of the third NMOS transistor is connected to the gate of the fifth PMOS transistor and the second output terminal of the frequency and phase detector, respectively, and the drain is connected to the drain of the fifth PMOS transistor and the input terminal of the fifth inverter, respectively. The fourth NMOS transistor has its drain connected to the source of the third NMOS transistor, its gate connected to a preset power supply, and its source grounded.

12. The phase-locked circuit according to claim 10, characterized in that, The second discharge branch includes: The fifth NMOS transistor has its gate connected to the first output terminal of the frequency and phase detector; The drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, and the source is grounded. The fourth discharge branch includes: The seventh NMOS transistor has its gate connected to the second output terminal of the frequency and phase detector, and its drain connected to the input terminal of the fifth inverter and the gate of the sixth NMOS transistor, respectively. The eighth NMOS transistor has its drain connected to the source of the seventh NMOS transistor, with the source grounded. Its gate is connected to the input of the fourth inverter and the drain of the fifth NMOS transistor, respectively.

13. The phase-locked circuit according to claim 12, characterized in that, The second discharge branch also includes: A plurality of first sub-transistors are connected in series, and the first end of the series circuit is connected to the source of the sixth NMOS transistor, the second end of the series circuit is grounded, and the control terminals of the plurality of first sub-transistors are all connected to a first drive signal; the first drive signal is configured to control the number of first sub-transistors connected to the second discharge branch. And / or, The fourth discharge branch also includes: A plurality of second sub-transistors are connected in series, and the first end of the series circuit is connected to the source of the eighth NMOS transistor. The second end of the series circuit is grounded. The control terminals of the plurality of second sub-transistors are all connected to a second drive signal. The second drive signal is configured to control the number of second sub-transistors connected to the fourth discharge branch.

14. A phase-locked loop, characterized in that, It includes a frequency divider and a phase-locked loop (PLL) circuit as described in any one of claims 1 to 13, wherein the input terminal of the frequency divider is connected to the output terminal of the oscillator in the PLL circuit, and the output terminal is connected to the second input terminal of the phase detection module in the PLL circuit.

15. A clock circuit, characterized in that, Applications in transceivers; It includes a clock distribution buffer and several phase-locked loops as described in claim 14, which are connected one-to-one with several transceiver channels in the transceiver; The input of the clock distribution buffer is connected to a reference clock signal; the phase-locked loop is used to provide a clock signal for the corresponding transceiver channel based on the reference clock signal.

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