Data receiving device and method with data efficient window extension mechanism
By using data delay circuits, AND gates, OR gates and data multiplexers to perform logical operations in a data receiving device, the problem of data sampling errors caused by channel divergence in a double data rate memory is solved, and the data valid window is expanded and the sampling accuracy is improved.
Patent Information
- Application Number
- CN202410395210.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-02
- Publication Date
- 2025-10-14
AI Technical Summary
In double data rate memory, as the memory speed increases, channel divergence makes it difficult for the data receiving device to accurately adjust the sampling timing, resulting in data sampling errors.
Data delay circuits, AND gates, OR gates, positive-edge data multiplexers, and negative-edge data multiplexers are used for logic operations. Combined with sampling circuits, the correct data signal is selected for sampling through AND and OR logic operations to expand the data valid window.
The accuracy of data sampling is improved, the error sampling caused by insufficient signal transition amplitude is reduced, and the accuracy of data reception is improved.
Smart Images
Figure CN120785358A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to data receiving technology, and more particularly to a data receiving device and method with a data valid window expansion mechanism. Background Art
[0002] Double data rate (DDR) memory transmits data using both the rising and falling edges of the system clock signal, resulting in a transmission speed twice as fast as the system clock signal. Traditionally, the data receiving device in DDR memory oversamples multiple clock signals, dynamically adjusting the sampling timing based on the relationship between the multiple sampling results to ensure sampling accuracy.
[0003] However, as memory speeds increase, channel dispersion becomes increasingly severe. Using only oversampling to sample data can lead to errors in some data sequences due to insufficient signal transition amplitudes. This can prevent the oversampling mechanism from accurately adjusting the sampling timing, leading to errors in the final sampling result. Summary of the Invention
[0004] In view of the problems of the prior art, one object of the present invention is to provide a data receiving device and method with a data valid window expansion mechanism to improve the prior art.
[0005] The present invention includes a data receiving device with a data valid window expansion mechanism, comprising: a data delay circuit, an AND gate, an OR gate, a positive-edge data multiplexer, a negative-edge data multiplexer, and a sampling circuit. The data delay circuit is configured to receive an input data signal and delay it to generate a delayed data signal. The AND gate is configured to perform an AND logic operation on the input data signal and the delayed data signal to generate an AND gate-processed signal. The OR gate is configured to perform an OR logic operation on the input data signal and the delayed data signal to generate an OR gate-processed signal. The positive-edge data multiplexer is configured to select the OR gate-processed signal as the current positive-edge data when the previous negative-edge sampling result is in a low state, and to select the AND gate-processed signal as the current positive-edge data when the previous negative-edge sampling result is in a high state. The negative-edge data multiplexer is configured to select the OR gate-processed signal as the current negative-edge data when the previous positive-edge sampling result is in a low state, and to select the AND gate-processed signal as the current negative-edge data when the previous positive-edge sampling result is in a high state. The sampling circuit is configured to sample current positive edge data according to the sampling positive edge of the data strobe signal to generate a current positive edge sampling result, and to sample current negative edge data according to the sampling negative edge of the data strobe signal to generate a current negative edge sampling result, wherein the previous positive edge sampling result is adjacent to and precedes the current negative edge sampling result, and the previous negative edge sampling result is adjacent to and precedes the current positive edge sampling result.
[0006] The present invention also includes a data receiving method with a data valid window expansion mechanism, comprising: causing a data delay circuit to receive an input data signal and delay it to generate a delayed data signal; causing an AND gate to perform an AND logic operation on the input data signal and the delayed data signal to generate an AND gate processing signal; causing an OR gate to perform an OR logic operation on the input data signal and the delayed data signal to generate an OR gate processing signal; causing a positive edge data multiplexer to select the OR gate processing signal to output as the current positive edge data when the previous negative edge sampling result is in a low state, and to select the AND gate processing signal to output as the current positive edge data when the previous negative edge sampling result is in a high state. Current positive edge data; the negative edge data multiplexer selects the OR gate processing signal output as the current negative edge data when the previous positive edge sampling result is in a low state, and selects the AND gate processing signal output as the current negative edge data when the previous positive edge sampling result is in a high state; and the sampling circuit samples the current positive edge data according to the sampling positive edge of the data flash signal to generate the current positive edge sampling result, and samples the current negative edge data according to the sampling negative edge of the data flash signal to generate the current negative edge sampling result, wherein the previous positive edge sampling result is adjacent to the current negative edge sampling result, and the previous negative edge sampling result is adjacent to the current positive edge sampling result.
[0007] The features, implementation and effects of the present invention are described in detail below with reference to the drawings for preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] [Figure 1 ] shows a block diagram of a data receiving device with a data valid window expansion mechanism according to one embodiment of the present invention;
[0009] [ Figure 2 ] shows waveform diagrams of multiple signals related to the operation of a data receiving device according to one embodiment of the present invention;
[0010] [ Figure 3A ] shows an embodiment of the present invention, corresponding to Figure 2 A schematic diagram of a first data sequence of an input data signal and a delayed data signal in a first position in FIG.
[0011] [ Figure 3B ] shows an embodiment of the present invention, corresponding to Figure 2 A schematic diagram of a second data sequence of an input data signal and a delayed data signal in a second position in FIG.
[0012] [ Figure 4 ] shows a block diagram of a data receiving device with a data valid window expansion mechanism according to another embodiment of the present invention;
[0013] [ Figure 5 ] shows a flow chart of a data receiving method with a data valid window expansion mechanism in one embodiment of the present invention. DETAILED DESCRIPTION
[0014] An object of the present invention is to provide a data receiving device and method with a data valid window expansion mechanism. The device and method perform AND and OR logic operations on an input data signal and a delayed data signal to generate an AND gate processing signal and an OR gate processing signal. One of the AND gate processing signal and the OR gate processing signal is selected based on a previous sampling result to output as the current data for sampling. This achieves a data valid window expansion mechanism and improves the accuracy of data sampling.
[0015] Please also refer to Figure 1 as well as Figure 2 . Figure 1 A block diagram of a data receiving device 100 with a data valid window extension mechanism according to an embodiment of the present invention is shown. Figure 2 The waveform diagram of multiple signals related to the operation of the data receiving device 100 in one embodiment of the present invention is shown. Figure 2 In the figure, the horizontal axis represents time and the vertical axis represents signal size.
[0016] The data receiving device 100 may be disposed in, for example but not limited to, a double data rate (DDR) memory, and includes a data delay circuit 110 , an AND gate 120 , an OR gate 130 , a positive edge data multiplexer 140 , a negative edge data multiplexer 150 , and a sampling circuit 160 .
[0017] The data delay circuit 110 is configured to receive an input data signal DQ and delay the input data signal DQ to generate a delayed data signal DDL.
[0018] like Figure 2 As shown, in one embodiment, the data delay circuit 110 delays the input data signal DQ by the data delay time TD, so that the delayed data signal DDL lags behind the input data signal DQ by the time corresponding to the data delay time TD.
[0019] The AND gate 120 is configured to perform an AND logic operation on the input data signal DQ and the delayed data signal DDL to generate an AND-processed signal DAN.
[0020] like Figure 2 As shown, the AND gate processing signal DAN is low as long as either the input data signal DQ or the delayed data signal DDL is low. Conversely, the AND gate processing signal DAN is high only when the corresponding input data signal DQ and the delayed data signal DDL are both high.
[0021] The OR gate 130 is configured to perform an OR logic operation on the input data signal DQ and the delayed data signal DDL to generate an OR gate processed signal DOR.
[0022] like Figure 2 As shown, as long as either the input data signal DQ or the delayed data signal DDL is high, the OR gate processing signal DOR is high. Conversely, only when the corresponding input data signal DQ and the delayed data signal DDL are both low, the OR gate processing signal DOR is low.
[0023] It should be noted that in practice, due to the time required for circuit processing, the timing of the AND gate processing signal DAN and the OR gate processing signal DOR is actually slightly later than the input data signal DQ. However, in order to facilitate the visualization of the relative relationship between different signals, Figure 2 The AND gate processing signal DAN and the OR gate processing signal DOR are aligned with the input data signal DQ.
[0024] The positive edge data multiplexer 140 is configured to select the OR processing signal DOR to output as the current positive edge data DCP when the previous negative edge sampling result SPN is at a low state, and to select the AND processing signal DAN to output as the current positive edge data DCP when the previous negative edge sampling result SPN is at a high state.
[0025] The negative edge data multiplexer 150 is configured to select the OR gate processing signal DOR to output as the current negative edge data DCN when the previous positive edge sampling result SPP is at a low state, and to select the AND gate processing signal DAN to output as the current negative edge data DCN when the previous positive edge sampling result SPP is at a high state.
[0026] In one embodiment, the sampling circuit 160 includes a rising edge sampling circuit 170 and a falling edge sampling circuit 180 .
[0027] The positive edge sampling circuit 170 is configured to sample the current positive edge data DCP according to the sampling positive edge of the data strobe signal DQS to generate a current positive edge sampling result DQP, wherein the previous negative edge sampling result SPN is adjacent to the current positive edge sampling result DQP.
[0028] like Figure 2 As shown, time points TP1-TP6 correspond to the sampling edges of the data strobe signal DQS. The edge sampling circuit 170 samples the current edge data DCP according to the sampling edges of the data strobe signal DQS at these time points to generate the current edge sampling results DQP.
[0029] The falling edge sampling circuit 180 samples the current falling edge data DCN according to the sampling falling edge of the data strobe signal DQS to generate the current falling edge sampling result DQN, wherein the previous rising edge sampling result SPP is adjacent to the current falling edge sampling result DQN.
[0030] like Figure 2 As shown, time points TN1-TN6 correspond to the sampling falling edge of the data strobe signal DQS. The falling edge sampling circuit 180 samples the current falling edge data DCN according to the sampling falling edge of the data strobe signal DQS at these time points to generate the current falling edge sampling result DQN.
[0031] The following will take the current DCP generation of Zhengyuan Data as an example, with Figure 2 、 Figure 3A as well as Figure 3B The data valid window expansion mechanism is described in more detail.
[0032] Please also refer to Figure 2 as well as Figure 3A . Figure 3A In one embodiment of the present invention, the corresponding Figure 2 Schematic diagram of a first data sequence of an input data signal DQ and a delayed data signal DDL in a first position PO1 in FIG.
[0033] In this embodiment, the first data sequence is (0, 1, 0). Figure 3AIn FIG, the high state of the input data signal DQ is depicted by a forward-slashed block and is labeled with a value of 1. The low state of the input data signal DQ is depicted by a blank area and is labeled with a value of 0. On the other hand, the high state of the delayed data signal DDL is depicted by a backslashed block and is labeled with a value of 1. The low state of the delayed data signal DDL is depicted by a blank area and is labeled with a value of 0.
[0034] correspond Figure 2 At the first position PO1 in the data strobe signal, the rising edge sampling circuit 170 samples the data at time point TP5 based on the rising edge of the data strobe signal DQS. At this time, the rising edge of the sampling at time point TP5 corresponds to the high state of the input data signal DQ and the delayed data signal DDL, that is, the "1" in the first data sequence (0, 1, 0).
[0035] Since the previous falling edge sampling result SPN is adjacent to the current rising edge sampling result DQP, for the current rising edge sampling result DQP to be generated at time point TP5, the previous falling edge sampling result SPN is the sampling result generated by the falling edge sampling circuit 180 according to the sampling falling edge of the data strobe signal DQS at time point TN4, and the previous falling edge sampling result SPN is low, that is, the "0" before the 1 in the first data sequence (0, 1, 0).
[0036] According to the previous negative edge sampling result SPN which is low, the positive edge data multiplexer 140 selects the OR gate processing signal DOR to output as the current positive edge data DCP. The current positive edge data DCP will be the union of the high state of the input data signal DQ and the delayed data signal DDL, and includes Figure 3A All forward slashes and backslashes in the block.
[0037] By selecting the OR processing signal DOR to generate the current rising edge data DCP, the original high state range of the input data signal DQ is expanded through a logical OR operation with the delayed data signal DDL. This increases the probability that the rising edge sampling circuit 170 will sample the correct data content based on the sampling edge of the data strobe signal DQS. Therefore, the OR processing signal DOR is configured to expand the data valid window for the first data sequence (0, 1, 0).
[0038] Please also refer to Figure 2 as well as Figure 3B . Figure 3B In one embodiment of the present invention, the corresponding Figure 2 Schematic diagram of a second data sequence of the input data signal DQ and the delayed data signal DDL at the second position PO2 in FIG.
[0039] In this embodiment, the second data sequence is (1, 0, 1). Figure 3BIn FIG, the low state of the input data signal DQ is depicted by a forward-slashed block and is labeled with a value of 0. The high state of the input data signal DQ is depicted by a blank area and is labeled with a value of 1. On the other hand, the low state of the delayed data signal DDL is depicted by a backslashed block and is labeled with a value of 0. The high state of the delayed data signal DDL is depicted by a blank area and is labeled with a value of 1.
[0040] correspond Figure 2 At the second position PO2 in FIG, the rising edge sampling circuit 170 performs sampling at time point TP3 based on the rising sampling edge of the data strobe signal DQS. At this time, the rising sampling edge at time point TP3 corresponds to the low state of the input data signal DQ and the delayed data signal DDL, i.e., the "0" in the second data sequence (1, 0, 1).
[0041] Since the previous falling edge sampling result SPN is adjacent to the current rising edge sampling result DQP, for the current rising edge sampling result DQP to be generated at time point TP3, the previous falling edge sampling result SPN is the sampling result generated by the falling edge sampling circuit 180 according to the sampling falling edge of the data strobe signal DQS at time point TN2, and the previous falling edge sampling result SPN is high, that is, the "1" before the 0 in the second data sequence (1, 0, 1).
[0042] According to the previous negative edge sampling result SPN which is high, the positive edge data multiplexer 140 selects the OR gate processing signal DOR to output as the current positive edge data DCP. The current positive edge data DCP will be the intersection of the low state of the input data signal DQ and the delayed data signal DDL, and includes Figure 3B All forward slashes and backslashes in the block.
[0043] By selecting the current rising edge data DCP generated by the AND gate processing signal DAN, the low state range of the original input data signal DQ is expanded through an AND logic operation with the delayed data signal DDL. This increases the probability that the rising edge sampling circuit 170 will sample the correct data content based on the sampling edge of the data strobe signal DQS. Therefore, the AND gate processing signal DAN is configured to expand the data valid window for the second data sequence (1, 0, 1).
[0044] Based on the above, the positive edge data multiplexer 140 can select one of the AND gate processing signal DAN and the OR gate processing signal DOR to output according to the state of the previous negative edge sampling result SPN, so as to expand the data valid window for the data sequences (0, 1, 0) and (1, 0, 1), respectively, thereby increasing the probability of sampling the correct data content according to the sampling positive edge of the data strobe signal DQS.
[0045] It should be noted that Figure 2Only the current positive edge data DCP is shown as an example, and the current negative edge data DCN is not shown. However, the current negative edge data DCN can have the same data valid window expansion mechanism as the current positive edge data DCP, which will not be described in detail here.
[0046] Ideally, the data delay time TD applied by the data delay circuit 110 to the input data signal DQ may be as large as possible when the input data signal DQ and the delayed data signal DDL continue to intersect.
[0047] In e.g. Figure 2 For the data sequence (0, 0, 1) corresponding to the third position PO3, the rising edge sampling at time point TP2 is to be sampled in a low state. The rising edge data multiplexer 140 selects the OR gate processing signal DOR based on the previous falling edge sampling result SPN, which is in a low state, and outputs it as the current rising edge data DCP. The low state at which the data strobe signal DQS is sampled is therefore limited by the severity of the intersymbol interference (ISI) of the input data signal DQ, limiting the expansion of the data valid window. Similarly, the data sequence (1, 1, 0) corresponding to the fourth position PO4 is subject to the same limitation. This limitation places an upper limit on the data delay time TD, preventing it from being continuously increased.
[0048] However, in the absence of intersymbol interference (ISI), the data sequences (0, 0, 1) and (1, 1, 0) coincide with the boundary of the aforementioned data sequences (0, 1, 0) and (1, 0, 1). Even if the data sequences (0, 1, 0) and (1, 0, 1) are ANDed or ORed with the delayed data signal DDL, the extent of the expansion is still limited to the boundary of the data sequences (0, 0, 1) and (1, 1, 0). However, in the presence of severe ISI (intersymbol interference), the data valid window of the data sequences (0, 1, 0) and (1, 0, 1) becomes significantly smaller than that of the data sequences (0, 0, 1) and (1, 1, 0). Through the aforementioned ANDed or ORed operations, the data valid window of the data sequences (0, 1, 0) and (1, 0, 1) can be extended to the boundary of the data sequences (0, 0, 1) and (1, 1, 0).
[0049] In some technologies, the data receiving device in a double data rate memory uses oversampling with multiple clock signals to dynamically adjust the sampling timing based on the relationship between the multiple sampling results. However, as memory speeds increase, channel dispersion becomes increasingly severe. Using only oversampling for data sampling, for example, data sequences (0, 1, 0) and (1, 0, 1) can easily produce erroneous results due to insufficient signal transition amplitudes (for example, in the data sequence (0, 1, 0), the signal returns to a low state before fully transitioning from a low state to a high state, or in the data sequence (1, 0, 1), the signal returns to a high state before fully transitioning from a high state to a low state). This can prevent the oversampling mechanism from accurately adjusting the sampling timing, resulting in errors in the final sampling result.
[0050] The data receiving device of the present invention can generate an AND gate processing signal and an OR gate processing signal by performing an AND logic operation and an OR logic operation on an input data signal and a delayed data signal, and select one of the AND gate processing signal and the OR gate processing signal to output as the current data for sampling based on the previous sampling result, thereby achieving a mechanism for expanding the data effective window and improving the accuracy of data sampling.
[0051] Please refer to Figure 4 . Figure 4 A block diagram of a data receiving device 400 with a data valid window expansion mechanism is shown in another embodiment of the present invention. Figure 1 The data receiving device 100 is similar to the data receiving device 100, and includes a data delay circuit 110, an AND gate 120, an OR gate 130, a positive edge data multiplexer 140, a negative edge data multiplexer 150, and a sampling circuit 160. The functions and operations of the above-mentioned common components will not be described in detail here.
[0052] In this embodiment, the data receiving device 400 further includes a data strobe delay circuit 410A and a data strobe delay circuit 410B. The data strobe delay circuit 410A and the data strobe delay circuit 410B are respectively configured to receive an original data strobe signal DQSO corresponding to the input data signal DQ and delay it to generate a data strobe signal DQS.
[0053] In one embodiment, the data receiving device 100 receives an input data signal DQ and a raw data strobe signal DQSO from an external device (not shown). However, the input data signal DQ must be processed by multiple circuits to generate the current positive-edge data DCP and the current negative-edge data DCN. Therefore, the data strobe delay time of the data strobe delay circuit 410A and the data strobe delay circuit 410B is equivalent to the time it takes for the data delay circuit 110 to receive the input data signal DQ and transmit it to the positive-edge data multiplexer 140 and the negative-edge data multiplexer 150 to generate the current positive-edge data DCP and the current negative-edge data DCN.
[0054] After being processed by the data strobe delay circuit 410A and the data strobe delay circuit 410B, the positive edge sampling circuit 170 and the negative edge sampling circuit 180 can sample the current positive edge data DCP and the current negative edge data DCN through the data strobe signal DQS according to the correct timing.
[0055] In practice, the data strobe delay circuit 410A and the data strobe delay circuit 410B can be selectively set to have the same data strobe delay time or two slightly different data strobe delay times depending on application requirements, but the present invention is not limited thereto.
[0056] Please refer to Figure 5 . Figure 5 A flow chart of a data receiving method 500 with a data valid window extension mechanism according to an embodiment of the present invention is shown.
[0057] In addition to the aforementioned apparatus, the present invention further discloses a data receiving method 500 with a data valid window extension mechanism, which is applied to, for example, but not limited to Figure 1 In the data receiving device 100. One embodiment of the data receiving method 500 is as follows: Figure 5 As shown, it includes the following steps.
[0058] In step S510 , the data delay circuit 110 receives the input data signal DQ and delays it to generate a delayed data signal DDL.
[0059] In step S520 , the AND gate 120 performs an AND logic operation on the input data signal DQ and the delayed data signal DDL to generate an AND gate processed signal DAN.
[0060] In step S530 , the OR gate 130 performs an OR logic operation on the input data signal DQ and the delayed data signal DDL to generate an OR gate processed signal DOR.
[0061] In step S540 , the positive edge data multiplexer 140 selects the OR processing signal DOR to output as the current positive edge data DCP when the previous negative edge sampling result SPN is at a low state, and selects the AND processing signal DAN to output as the current positive edge data DCP when the previous negative edge sampling result SPN is at a high state.
[0062] In step S550 , the negative edge data multiplexer 150 selects the OR gate processing signal DOR to output as the current negative edge data DCN when the previous positive edge sampling result SPP is at a low state, and selects the AND gate processing signal DAN to output as the current negative edge data DCN when the previous positive edge sampling result SPP is at a high state.
[0063] In step S560, the sampling circuit 160 samples the current positive edge data DCP according to the sampling rising edge of the data strobe signal DQS to generate the current positive edge sampling result DQP, and samples the current negative edge data DCN according to the sampling falling edge of the data strobe signal DQS to generate the current negative edge sampling result DQN, wherein the previous positive edge sampling result SPP is adjacent to the current negative edge sampling result DQN, and the previous negative edge sampling result SPN is adjacent to the current positive edge sampling result DQP.
[0064] It should be noted that the above-mentioned implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.
[0065] In summary, the data receiving device and method of the present invention with a data valid window expansion mechanism performs AND logic operations and OR logic operations on the input data signal and the delayed data signal to generate an AND gate processing signal and an OR gate processing signal, and selects one of the AND gate processing signal and the OR gate processing signal to output as the current data for sampling based on the previous sampling result, thereby achieving a data valid window expansion mechanism and improving the accuracy of data sampling.
[0066] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art may modify the technical features of this case based on the explicit or implicit content of this case. All such modifications may fall within the scope of the patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application defined in this specification.
[0067]
Explanation of symbols
[0068] 100: Data receiving device
[0069] 110: Data delay circuit
[0070] 120: AND gate
[0071] 130: OR gate
[0072] 140: Positive edge data multiplexer
[0073] 150: Negative edge data multiplexer
[0074] 160: Sampling circuit
[0075] 170: Positive edge sampling circuit
[0076] 180: Negative edge sampling circuit
[0077] 400: Data receiving device
[0078] 410A: Data flash delay circuit
[0079] 410B: Data flash delay circuit
[0080] 500: Data receiving method
[0081] S510~S560: Steps
[0082] DAN: AND gate processing signal
[0083] DCN: Current negative edge data
[0084] DCP: Current Data
[0085] DDL: Delayed Data Signal
[0086] DOR: OR gate processing signal
[0087] DQ: input data signal
[0088] DQN: Current negative edge sampling results
[0089] DQP: Current positive edge sampling result
[0090] DQS: data strobe signal
[0091] DQSO: Raw Data Strobe Signal
[0092] PO1: First position
[0093] PO2: Second position
[0094] PO3: third position
[0095] PO4: fourth position
[0096] SPN: Previous negative edge sampling results
[0097] SPP: Previous positive edge sampling results
[0098] TD: Data delay time
[0099] TN1~TN6: Time point
[0100] TP1~TP6: time points.
Claims
1. A data receiving device with a data valid window expansion mechanism, comprising: A data delay circuit is configured to receive an input data signal and delay it to generate a delayed data signal. an AND gate configured to perform an AND logic operation on the input data signal and the delayed data signal to generate an AND gate processed signal; an OR gate configured to perform an OR logic operation on the input data signal and the delayed data signal to generate an OR gate processed signal; a positive edge data multiplexer configured to select the OR gate processed signal output as a current positive edge data when a previous negative edge sampling result is in a low state, and to select the AND gate processed signal output as the current positive edge data when the previous negative edge sampling result is in a high state; a negative edge data multiplexer configured to select the OR gate processed signal output as a current negative edge data when a previous positive edge sampling result is in the low state, and to select the AND gate processed signal output as the current negative edge data when the previous positive edge sampling result is in the high state; and A sampling circuit is configured to generate a current positive edge sampling result for the current positive edge data sample according to a sampling positive edge of a data strobe signal, and to generate a current negative edge sampling result for the current negative edge data sample according to a sampling negative edge of the data strobe signal, wherein the previous positive edge sampling result is adjacent to and precedes the current negative edge sampling result, and the previous negative edge sampling result is adjacent to and precedes the current positive edge sampling result.
2. The data receiving device according to claim 1, further comprising a data strobe delay circuit configured to receive an original data strobe signal corresponding to the input data signal and delay the received data strobe signal to generate the data strobe signal.
3. The data receiving device according to claim 2, wherein a data flash delay time of the data flash delay circuit is equivalent to the time taken for the data delay circuit to receive the input data signal to the positive edge data multiplexer and the negative edge data multiplexer to generate the current positive edge data and the current negative edge data.
4. The data receiving device according to claim 1 , wherein the sampling circuit comprises: a positive edge sampling circuit configured to sample the current positive edge data according to the sampling positive edge to generate the current positive edge sampling result; and A negative edge sampling circuit is configured to sample the current negative edge data according to the sampling negative edge to generate the current negative edge sampling result.
5. The data receiving device according to claim 1, wherein the OR gate processing signal is configured to perform a data valid window extension on a first data sequence of (0, 1, 0), and the AND gate processing signal is configured to perform the data valid window extension on a second data sequence of (1, 0, 1).
6. A data receiving method with a data valid window expansion mechanism, comprising: A data delay circuit receives an input data signal and delays the signal to generate a delayed data signal; enabling an AND gate to perform an AND logic operation on the input data signal and the delayed data signal to generate an AND gate processed signal; enabling an OR gate to perform an OR logic operation on the input data signal and the delayed data signal to generate an OR gate processed signal; A positive edge data multiplexer selects the OR gate processing signal output as a current positive edge data when a previous negative edge sampling result is in a low state, and selects the AND gate processing signal output as the current positive edge data when the previous negative edge sampling result is in a high state; enabling a negative edge data multiplexer to select the OR gate processing signal output as a current negative edge data when a previous positive edge sampling result is in the low state, and to select the AND gate processing signal output as the current negative edge data when the previous positive edge sampling result is in the high state; and A sampling circuit generates a current positive edge sampling result for sampling the current positive edge data according to a sampling positive edge of a data strobe signal, and generates a current negative edge sampling result for sampling the current negative edge data according to a sampling negative edge of the data strobe signal, wherein the previous positive edge sampling result is adjacent to and precedes the current negative edge sampling result, and the previous negative edge sampling result is adjacent to and precedes the current positive edge sampling result.
7. The data receiving method according to claim 6, further comprising: A data strobe delay circuit receives an original data strobe signal corresponding to the input data signal and delays the signal to generate the data strobe signal.
8. The data receiving method according to claim 7, wherein a data flash delay time of the data flash delay circuit is equivalent to the time taken for the data delay circuit to receive the input data signal to the positive edge data multiplexer and the negative edge data multiplexer to generate the current positive edge data and the current negative edge data.
9. The data receiving method according to claim 6, further comprising: A positive edge sampling circuit included in the sampling circuit samples the current positive edge data according to the sampling positive edge to generate the current positive edge sampling result; and A negative edge sampling circuit included in the sampling circuit samples the current negative edge data according to the sampling negative edge to generate the current negative edge sampling result.
10. The data receiving method according to claim 6, wherein the OR gate processing signal is configured to perform a data valid window extension on a first data sequence of (0, 1, 0), and the AND gate processing signal is configured to perform the data valid window extension on a second data sequence of (1, 0, 1).