Interference cancellation circuit and method for operating channel impulse response estimation circuit

Abstract

Methods of operation of an interference cancellation circuit and a channel impulse response estimation circuit are disclosed. The interference cancellation circuit includes: a finite impulse response (FIR) filter configured to set a channel impulse response (CIR) coefficient for each transmission path of a transmission signal, and to obtain a CIR-adapted transmission signal by applying the CIR coefficient to the transmission signal; a kernel generation circuit configured to generate an interference model based on the CIR-adapted transmit signal; an adaptive filter configured to estimate an interference signal for each reception path by estimating an interference model coefficient of an interference model, and to generate an interference-cancelled signal by filtering the interference signal from the reception signal; and a CIR estimation circuit configured to estimate a CIR coefficient in a next sampling period by using a back propagation method based on the interference-cancelled signal, and transmit the estimated CIR coefficient to the FIR filter.

Description

[0001] This application is based on and claims priority under one or more of Korean Patent Application Nos. 10-2024-0046221, filed on April 4, 2024, and 10-2024-0092577, filed on July 12, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entireties by reference. TECHNICAL FIELD

[0002] One or more embodiments of the present disclosure relate to an interference cancellation circuit and an operation method thereof, and more particularly, to an interference cancellation circuit configured to cancel intermodulation interference based on a relative delay between transmit signals and an operation method of the interference cancellation circuit. BACKGROUND

[0003] Various methods can be employed in a wireless communication system to increase throughput. These methods can include carrier aggregation (CA), evolved universal terrestrial radio access (E-UTRA) new radio (NR) dual connectivity (EN-DC), multiple input multiple output (MIMO), etc., and increase communication capacity by using multiple antennas. When a throughput enhancement technique is employed, a transmit end can need to process a complex transmit signal, while a receive end is capable of processing a receive signal with high complexity.

[0004] Interference signals can interfere with a receive end, preventing correct processing of a signal received through an antenna. These interference signals can take various forms. For example, inter-cell interference can be caused by a neighboring base station at a boundary of a serving base station, and intra-cell interference can occur due to a wireless signal from another terminal within a coverage area of the serving base station. Other types of interference, such as channel interference, can also be encountered.

[0005] In addition to interference signals received through an antenna, there can also be interference signals that occur when a transmit signal leaks or couples onto a receive path within a terminal when the transmit signal passes through a transmit path. For self-interference signals that occur in a terminal, a transmit signal is fed back as an interference signal, and thus can significantly affect degradation of receive sensitivity. Recently, technology development has been actively conducted to remove interference signals caused by intermodulation distortion (IMD) between transmit signals received through multiple transmit paths. More specifically, as bandwidth for data transmission increases, a memory term can be introduced during processing when there is frequency selectivity according to an increase in bandwidth for data transmission in a transmit path, and the memory term can be generated in processing in the transmit path. These memory terms can occur before a non-linear model (e.g., a kernel generation circuit) and after interference cancellation processing. Therefore, in order to effectively cancel interference signals, a solution that includes a memory term for each transmit path in an interference model can be needed. SUMMARY

[0006] One or more embodiments provide a channel impulse response (CIR) estimation circuit configured to estimate a CIR coefficient for each transmission path, an interference cancellation circuit including the CIR estimation circuit, and an operation method thereof.

[0007] According to one aspect of the disclosure, there is provided an interference cancellation circuit including a finite impulse response (FIR) filter configured to set a channel impulse response (CIR) coefficient for each transmission path of a transmission signal and to obtain a CIR-adapted transmission signal by applying the CIR coefficient to the transmission signal, a kernel generation circuit configured to generate an interference model based on the CIR-adapted transmission signal, an adaptive filter configured to estimate an interference signal for each reception path by estimating an interference model coefficient of the interference model and to generate a cancellation-interference signal by filtering out the interference signal from a reception signal, and a CIR estimation circuit configured to estimate a CIR coefficient in a next sampling period based on the cancellation-interference signal by a backpropagation method and to transmit the estimated CIR coefficient to the FIR filter.

[0008] According to another aspect of the disclosure, there is provided an interference cancellation circuit including a finite impulse response (FIR) filter configured to set a channel impulse response (CIR) coefficient for each transmission path of a transmission signal and to obtain a CIR-adapted transmission signal by applying the CIR coefficient to the transmission signal, a kernel generation circuit configured to generate an interference model based on the CIR-adapted transmission signal, a cancellation circuit configured to generate a subtraction-interference signal by subtracting an interference signal estimated based on the interference model from a reception signal, and a CIR estimation circuit configured to estimate a CIR coefficient in a next sampling period based on the subtraction-interference signal by using a backpropagation method and to transmit the estimated CIR coefficient to the FIR filter.

[0009] According to another aspect of the disclosure, there is provided an operation method of a channel impulse response (CIR) estimation circuit, the operation method including generating a target delay signal for updating a CIR coefficient among a plurality of delay signals based on a transmission path index and a delay index, performing a backpropagation process on the target delay signal, estimating the CIR coefficient of the target delay signal based on a result of performing the backpropagation process, and transmitting the estimated CIR coefficient to a finite impulse response (FIR) filter to update the estimated CIR coefficient as the CIR coefficient of the target delay signal in a next sampling period. BRIEF DESCRIPTION OF DRAWINGS

[0010] The embodiments will become more fully understood from the detailed description and accompanying drawings, given below.

[0011] Figure 1 A wireless communication device subject to self-interference caused by a transmit signal is shown in accordance with one or more embodiments.

[0012] Figure 2 An example of a wireless communication device in accordance with one or more embodiments is shown.

[0013] Figure 3 An example of an interference cancellation circuit in accordance with one or more embodiments is shown.

[0014] Figure 4 An example of a channel impulse response (CIR) estimation circuit in accordance with another embodiment is shown.

[0015] Figure 5 is a diagram that describes the operation of an interference cancellation circuit in accordance with one or more embodiments.

[0016] Figure 6 is a diagram that describes the operation of a CIR estimation circuit in accordance with one or more embodiments.

[0017] Figure 7 is a diagram that describes the operation of a CIR estimation circuit in accordance with one or more embodiments.

[0018] Figure 8 An example of a configuration of a CIR estimation circuit in accordance with one or more embodiments is shown.

[0019] Figure 9 An example of a configuration of an interference cancellation circuit in accordance with one or more embodiments is shown.

[0020] Figure 10 Another example of a configuration of an interference cancellation circuit in accordance with one or more embodiments is shown.

[0021] Figure 11 Another example of an interference cancellation circuit in accordance with one or more embodiments is shown.

[0022] Figure 12 is a flowchart for describing a method of operation of an interference cancellation circuit in accordance with one or more embodiments.

[0023] Figure 13 is a flowchart for describing a method of operation of a CIR estimation circuit in accordance with one or more embodiments.

[0024] Figure 14 is a block diagram of a wireless communication device in accordance with one or more embodiments. DETAILED DESCRIPTION

[0025] Embodiments will be described in detail with reference to accompanying drawings. Although the embodiments are illustrated in the accompanying drawings and are described herein in detail, it is not intended to restrict various embodiments in specific forms. For example, it will be apparent to those skilled in the art that various modifications can be made to the embodiments.

[0026] One or more embodiments provide a wireless communication device (e.g., a terminal) including interference cancellation circuitry or channel impulse response (CIR) estimation circuitry to perform wireless communication through at least one transmission path such as an antenna.

[0027] In this specification, BPP can indicate a back propagation process.

[0028] Figure 1 A wireless communication device subject to self-interference caused by a transmission signal according to one or more embodiments is illustrated.

[0029] Referring to Figure 1 The wireless communication device 10 can include a transmission antenna and a reception antenna. The wireless communication device 10 can be implemented to have a single antenna connected to both a transmission radio frequency (RF) chain and a reception RF chain through a duplexer. For example, the wireless communication device 10 can be configured to receive a wireless signal through the reception RF chain in a reception mode and to transmit a baseband signal to an external device through the transmission RF chain in a transmission mode.

[0030] According to various embodiments, in the wireless communication device 10 including a transmission antenna and a reception antenna connected through a duplexer, feedback of a transmission signal can occur based on the transmission antenna and the reception antenna being adjacent to each other. However, since the duplexer is connected to both the transmission RF chain and the reception RF chain, at least a portion of the transmission signal can be leaked from the transmission RF chain to the reception RF chain. When the leaked transmission signal is input to the reception RF chain, self-interference can occur.

[0031] According to various embodiments, the reception antenna can be configured to receive a wireless signal transmitted from the transmission antenna as well as a wireless signal transmitted from an external device. For example, when the transmission antenna and the reception antenna correspond to non-directional antennas and the transmission antenna and the reception antenna are arranged adjacent to each other, some of the transmitted wireless signal can be fed back through the reception antenna. Self-interference can also occur based on the fed-back wireless signal.

[0032] Figure 2 An example of the wireless communication device 10 according to one or more embodiments is illustrated.

[0033] Referring to Figure 2 The wireless communication device 10 can include two antennas for transmitting a first transmission signal TX1 and a second transmission signal TX2, respectively. Each of the two antennas can include an antenna for transmitting and receiving a signal.

[0034] For example, the first transmit filter 110 can filter an input signal to output a first transmit signal TX1 having only a desired frequency band. The first digital-to-analog converter (DAC) 111 can convert the first transmit signal TX1 in a digital signal form into an analog signal form. Thereafter, the first mixer 112 can perform up-conversion on a transmission frequency of the first transmit signal TX1 by mixing the first transmit signal TX1 with a (high frequency) LO frequency received from a local oscillator (LO). The first power amplifier (PA) 113 can amplify the up-converted first transmit signal TX1 and then transmit it to an external device (e.g., a base station) through an antenna. The second transmit filter 120 filters an input signal to output a second transmit signal TX2 having only a desired frequency band. The second DAC 121 can convert the second transmit signal TX2 in a digital signal form into an analog signal form. Thereafter, the second mixer 122 performs up-conversion on a transmission frequency of the second transmit signal TX2 by mixing the second transmit signal TX2 with a (high frequency) LO frequency. The second PA 123 can amplify the up-converted second transmit signal TX2 and then can transmit it to an external device through an antenna.

[0035] According to various embodiments, the wireless communication device 10 can be configured to perform carrier aggregation or dual connectivity in a case where the first transmit filter 110, the second transmit filter 120, and the receive filter 210 are all in an active state. Here, when self-interference occurs, the first transmit signal TX1 amplified through the first PA 113 can be coupled to an adjacent receive RF chain. For example, the first transmit signal TX1 can be input to a low noise amplifier (LNA) 211 of the receive RF chain as a receive signal. Also, the second transmit signal TX2 can leak from the transmit RF chain connected through the duplexer 124. That is, the second transmit signal TX2 can be input to the LNA 211 through the duplexer 124 as a receive signal. The first transmit signal TX1 and the second transmit signal TX2 can generate an interference signal around a receive frequency due to a non-linear characteristic of the receive RF chain. The interference signal can undergo down-conversion again through an LO frequency received by the third mixer 212 and then can be converted into a digital signal form through an analog-to-digital converter (ADC) 213. Thereafter, the interference signal generated by the first transmit signal TX1 and the second transmit signal TX2 can be cancelled through the interference cancellation circuit 300.

[0036] The interference cancellation circuit 300 can further include a pre-processing circuit 310, a finite impulse response (FIR) filter 320, a kernel generation circuit 330, a post-processing circuit 340, and an adaptive filter 350. Details thereof will be described below with reference to FIG. 4. Figure 3

[0037] Aspects are described in the following Figure 2 ​The interference cancellation circuit 300 shown in FIG. 1A generates an interference signal by modeling the first transmission signal TX1 and the second transmission signal TX2 received by the interference cancellation circuit 300 and cancels the interference based on the generated interference signal, and describes the function of canceling various interferences Figure 3 The interference cancellation circuit 300 shown in FIG. 1B.

[0038] Figure 3 An example of the interference cancellation circuit 300 according to one or more embodiments is shown.

[0039] Referring to Figure 3 , the interference cancellation circuit 300 can include a pre-processing circuit 310, an FIR filter 320, a kernel generation circuit 330, a post-processing circuit 340, an adaptive filter 350, and a CIR estimation circuit 360.

[0040] The pre-processing circuit 310 can be configured to receive transmission signals from at least one transmission path, and perform at least one pre-processing on the transmission signals transmitted through different transmission paths. The at least one pre-processing can include an operation regarding at least one of delay matching between the transmission signals, delay matching between the interference signals in the transmission paths, adjustment of a sampling rate, and / or a combination thereof.

[0041] The FIR filter (e.g., a linear model) 320 can be configured to set CIR coefficients corresponding to the transmission signals (or the pre-processed transmission signals) with respect to the transmission signals (or the pre-processed transmission signals).

[0042] In one or more embodiments, the FIR filter 320 can include a plurality of buffers. The FIR filter 320 can be configured to generate first to nth delay signals (see Figure 5 ) by delaying the transmission signals by each of delay periods set with respect to the plurality of buffers (or, buffer circuits, delay circuits) using the plurality of buffers (e.g., the sampling period of the interference signal can include Z -0 , Z -1 , Z -2 , …, Z -(n-1) ). For example, the FIR filter 320 can be configured to generate a first delay signal by delaying the transmission signals by a zeroth delay period set with respect to a first buffer based on the first buffer (wherein the zeroth delay period can indicate "sampling period of interference signal x 0 (e.g., Z -0 )", generate a second delay signal by delaying the transmission signals by a first delay period set with respect to a second buffer based on the second buffer (wherein the first delay period can indicate "sampling period of interference signal x 1 (e.g., Z -1generate a second delay signal by delaying the transmit signal based on the third buffer by a second delay period set for the third buffer (where the second delay period can indicate "a sampling period of the interference signal x 2 (i.e., Z -2 )"), generate a third delay signal by delaying the transmit signal based on the third buffer by a third delay period set for the third buffer (where the third delay period can indicate "a sampling period of the interference signal x 3 (i.e., Z -(n-1) )"), and generate an n-th delay signal by delaying the transmit signal based on the n-th buffer (n is a natural number greater than or equal to 1) by an (n-1)-th delay period set for the n-th buffer (where the (n-1)-th delay period can indicate "a sampling period of the interference signal x (n-1) (e.g., Z

[0043] In one or more embodiments, for the first delay signal to the n-th delay signal, the FIR filter 320 can set CIR coefficients corresponding to the first delay signal to the n-th delay signal, respectively (see Figure 5 ).

[0044] The kernel generation circuit (e.g., a non-linear model) 330 can include a circuit configured to generate (or reproduce) an interference model (see Figure 8 ) by receiving the interference signals (e.g., the first transmit signal TX1 and the second transmit signal TX2). The reproduced interference model can include both active interference signals and passive interference signals.

[0045] In one or more embodiments, the kernel generation circuit 330 can be configured to receive the transmit signals (e.g., the aggregated signals STS#0 to STS#1 generated by aggregating the first delay signal to the n-th delay signal set with the CIR coefficients) from the FIR filter 320, and generate (or reproduce) the interference model based on the aggregated signals (see Figure 8 ).

[0046] The post-processing circuit 340 can be configured to perform at least one post-processing on the interference model received from the kernel generation circuit 330. The at least one post-processing can include an operation on at least one of a delay matching between the transmit signals and the receive signals, an adjustment of a frequency offset, an adjustment of a sampling rate, and / or a combination thereof.

[0047] The adaptive filter (e.g., a linear model) 350 can estimate (or generate) an interference signal by estimating coefficients of the kernel generation circuit 330 (e.g., estimating interference model coefficients of an interference model generated by the kernel generation circuit 330), and perform filtering on the interference signal by filtering out the interference signal from the received signal. For example, the adaptive filter 350 can be configured to generate an interference- canceled signal by filtering out the interference signal from the received signal. For example, the adaptive filter 350 can operate based on one of adaptive filter algorithms (e.g., a least mean square (LMS) algorithm using a stochastic gradient descent method, a recursive least square (RLS) algorithm, and a dichotomous coordinate descent (DCD)-RLS algorithm). The adaptive filter 350 can transmit the interference-canceled signal to the CIR estimation circuit 360.

[0048] The interference cancellation circuit according to embodiments can include a cancellation circuit instead of the adaptive filter 350. Here, the cancellation circuit can be configured to estimate an interference signal based on the interference model, and generate an interference-subtracted signal by subtracting the estimated interference signal from the received signal. The cancellation circuit can be configured to transmit the interference-subtracted signal to the CIR estimation circuit 360. Details thereof will be described below with reference to Figure 10 and Figure 12 .

[0049] The CIR estimation circuit 360 can be configured to estimate CIR coefficients in a next sample period by using a back propagation method based on any one of the interference-canceled signal (received from the adaptive filter 350) and the interference-subtracted signal (received from the cancellation circuit), and can transmit the estimated CIR coefficients to the FIR filter to update the CIR coefficients.

[0050] In one or more embodiments, the CIR estimation circuit 360 can be configured to estimate CIR coefficients corresponding to the first to nth delay signals in the next sample period by using the back propagation method based on the interference-canceled signal. The CIR estimation circuit 360 can be configured to transmit the CIR coefficients corresponding to the first to nth delay signals in the next sample period to the FIR filter 320, and the FIR filter 320 can be configured to update the CIR coefficients received from the CIR estimation circuit 360 as the CIR coefficients corresponding to the first to nth delay signals in the next sample period.

[0051] In one or more embodiments, the CIR estimation circuit 360 can be configured to estimate the CIR coefficients corresponding to the first to nth delay signals in the next sampling period by using a back propagation method. The CIR estimation circuit 360 can be configured to transmit the CIR coefficients corresponding to the first to nth delay signals in the next sampling period to the FIR filter 320, and the FIR filter 320 can be configured to update the CIR coefficients received from the CIR estimation circuit 360 as the CIR coefficients corresponding to the first to nth delay signals in the next sampling period.

[0052] In one or more embodiments, the CIR estimation circuit 360 can be configured to estimate the CIR coefficients corresponding to the first to nth delay signals in the next sampling period by using a back propagation method based on a Wirtinger derivative method and / or a chain rule. Details thereof will be described below with reference to Figures 5 to 8

[0053] According to the CIR estimation circuit 360, the interference cancellation circuit 300, and the operation method thereof in the embodiments, estimating the CIR coefficients of each transmission path and reflecting the CIR coefficients to interference modeling can allow effective cancellation of intermodulation distortion (IMD) interference without a significant change in the structure of the interference cancellation circuit. In addition, the system can be more compactly configured, and the inventive concept can be implemented with low system complexity.

[0054] According to the CIR estimation circuit 360, the interference cancellation circuit 300, and the operation method thereof in the embodiments, even when transmission / reception delays occur due to analog elements or digital elements of a wireless communication device, IMD interference can be effectively cancelled by reflecting the delays of each transmission path.

[0055] Figure 4 A CIR estimation circuit 360 according to another embodiment is illustrated.

[0056] Referring to Figure 4 , the CIR estimation circuit 360 can include a selector 361, a pre-processing circuit 362, and a back propagation processing (BPP) circuit 365 including a first BPP circuit 363 and a second BPP circuit 364.

[0057] The selector 361 can be configured to select a plurality of delay signals (e.g., Figure 3 ​The selector 361 can determine a target delay signal for updating the CIR coefficient among the first to nth delay signals (e.g., the first to nth delay signals illustrated in FIG. 3). The selector 361 can include a first selector and a second selector. The first selector can be configured to calculate / select a transmit (Tx) path index t for determining the target delay signal, and the second selector can be configured to calculate / select a delay index m (see Figure 6 ). For example, referring to Figure 5 , when "0" is selected as the Tx path index t and "1" is selected as the delay index m, the selector 361 can determine the second delay signal TS#01 as the target delay signal, the second delay signal TS#01 being a transmit signal delayed by a first delay period (e.g., (a sampling period) x 1) in a zeroth transmit path Tx0.

[0058] The pre-processing circuit 362 can be configured to perform at least one pre-processing on each of a plurality of transmit signals transmitted through a transmit path selected by the selector 361 (e.g., a transmit signal TS#0 of the zeroth transmit path or a transmit signal TS#1 of the first transmit path). The at least one pre-processing can include an operation on at least one of a delay matching between transmit signals respectively received through different transmit paths, a delay matching between interference signals in a transmit path, an adjustment of a sampling rate, and / or a combination thereof.

[0059] The BPP circuit 365 can be configured to estimate CIR coefficients for delay signals of transmit paths in a next sampling period based on interference-eliminated signals by using back propagation, and effectively eliminate interference signals by reflecting the estimated CIR coefficients to interference modeling. Here, the back propagation method can be based on a Wirtinger derivative method and a chain rule.

[0060] The BPP circuit 365 can be configured to estimate CIR coefficients for delay signals of transmit paths in a next sampling period based on Equation 1 below (where t indicates a Tx path index, and m indicates a delay index)

[0061] [Equation 1]

[0062]

[0063] Here, H(t, m) can indicate a CIR coefficient for a delay signal of each transmit path in a previous sampling period, μ can indicate a step size, and may indicate a loss function with respect to a CIR coefficient for a delay signal of each transmit path

[0064] ​​In [Formula 1], it can be difficult to directly calculate the loss function due to complexity in actual calculation processing CIR coefficients with respect to a delay signal for each transmission path Wirtinger derivative

[0065] Therefore, the BPP circuit 365 of the CIR estimation circuit 360 according to the embodiment can be configured to calculate the Wirtinger derivative for the adaptive filter 350 and the kernel generation circuit 330 by using a backpropagation method based on the Wirtinger derivative and the chain rule from the pre-processing (performed by the pre-processing circuit 310) to the loss function (performed by the CIR estimation circuit 360) in the interference cancellation circuit 300 processing. In one or more embodiments, the BPP circuit 365 can include a first BPP circuit 363 configured to calculate the Wirtinger derivative for the adaptive filter 350 and the kernel generation circuit 330 by using the backpropagation method. In one or more embodiments, the BPP circuit 365 can include a second BPP circuit 364 configured to calculate the Wirtinger derivative for at least one circuit configured to perform the post-processing (see Figure 5 the post-processing circuit 340 in the interference cancellation circuit 300) by using the backpropagation method.

[0066] In the processing of calculating the Wirtinger derivative, the processing of calculating the derivative of the conjugate term (e.g., conjugate path) and the processing of calculating the derivative of the original term (e.g., non-conjugate path) are respectively performed, and thus the BPP circuit 365 according to the embodiment can include a BPP circuit for the conjugate path and a BPP circuit for the non-conjugate path. For example, referring to Figure 6 , the first BPP circuit #1 363-1 can include a BBP circuit for the non-conjugate path in calculating the Wirtinger derivative for the adaptive filter 350 and the kernel generation circuit 330, and the first BPP circuit #2 363-2 can include a BPP circuit for the conjugate path in calculating the Wirtinger derivative for the adaptive filter 350 and the kernel generation circuit 330. For example, referring to Figure 6 , the second BPP circuit #1 364-1 can include a BPP circuit for the non-conjugate path in calculating the Wirtinger derivative for at least one circuit configured to perform the post-processing in the interference cancellation circuit 300, and the second BPP circuit #2 364-2 can include a BPP circuit for the conjugate path in calculating the Wirtinger derivative for at least one circuit configured to perform the post-processing.

[0067] More specifically, the BPP circuit 365 estimates the CIR coefficients in the next sampling period by calculating the Wirtinger derivative ​The operation of the above is as follows.

[0068] The BPP circuit 365 can be configured to calculate the error signal e r，n (i.e., an interference-eliminated signal).

[0069] [Equation 2]

[0070] e r,n = (d r，n - Z rADo,n )

[0071] Here, Z r，ADo，n may indicate an interference signal value (or an estimated value of an interference signal), and d r，n may indicate an actually received reception signal (or a downlink signal).

[0072] In one or more embodiments, when a plurality of reception signals is received through a plurality of reception paths, the BPP circuit 365 can generate a plurality of error signals (i.e., a plurality of interference-eliminated signals) in the plurality of reception paths and calculate a loss function The BPP circuit 365 can be configured to calculate the loss function based on the following [Equation 3]. (where the loss function corresponds to an interference-eliminated signal) by calculating the loss function using a backpropagation method via a Wirtinger derivative of the CIR coefficient of the delayed signal with respect to each transmission path. (see Equation 1).

[0073] [Equation 3]

[0074]

[0075] Here, w r (i.e., a weight of the r-th reception path) can be defined by an equal combination or various combination methods. Here, even when the loss function is calculated with respect to all of the plurality of reception signals, the BPP circuit 365 according to an embodiment can be more widely implemented in a simple structure (e.g., an aggregation structure) by calculating the loss function with respect to all of the plurality of reception signals in a magnitude and phase method.

[0076] In one or more embodiments, when the plurality of received signals is received through the plurality of reception paths, the BPP circuit 365 can generate a plurality of error signals (i.e., a plurality of interference- canceled signals) in the plurality of reception paths, and identify a reception path in which an interference is strongest (i.e., an interference signal having a greatest strength) from among the plurality of error signals (i.e., the plurality of interference-canceled signals). The BPP circuit 365 can be configured to calculate a loss function of the reception path in which the interference is strongest (i.e., the interference signal having the greatest strength) based on [Equation 4] below The BPP circuit 365 can be configured to calculate the loss function based on [Equation 4] below The BPP circuit 365 can be configured to calculate the loss function based on [Equation 4] below (where the loss function corresponding to the interference-canceled signal) by calculating the loss function through the use of a backpropagation method with respect to the CIR coefficient of the delay signal for each transmission path of the Wirtinger derivative to estimate the CIR coefficient in the next sampling period (see Equation 1).

[0077] [Equation 4]

[0078]

[0079] Here, R can indicate the reception path in which the interference is strongest (i.e., the interference signal having the greatest strength).

[0080] In one or more embodiments, when the BPP circuit 365 calculates the Wirtinger derivative based on a plurality of loss functions , the sum of the loss functions may be used instead of the loss function Here, the BPP circuit 365 can be configured to calculate the sum of the loss functions based on [Equation 5] below

[0081] [Equation 5]

[0082]

[0083] Here, n can indicate a sample index of the interference signal. Here, since the sum of the loss functions is a linear combination of the loss function , the BPP circuit 365 according to an embodiment can be configured to calculate the sum of the loss functions using an amplitude and phase method ​​And can be effectively implemented in a simplified structure (e.g., an aggregation structure).

[0084] The first BPP circuit 363 can be configured to receive the interference- canceled signal from the adaptive filter 350 (see Figure 5 ) based on the interference-canceled signal. Here, the first backpropagation process can indicate a backpropagation process of the adaptive filter 350 configured to generate the interference-canceled signal and the kernel generation circuit 330 configured to generate an interference model corresponding to the interference signal.

[0085] The first BPP circuit 363 can be configured to receive the interference- canceled signal from the adaptive filter 350 (see Figure 5 ) based on the interference-canceled signal. Here, the first backpropagation process can indicate a backpropagation process of the adaptive filter 350 configured to generate the interference-canceled signal and the kernel generation circuit 330 configured to generate an interference model corresponding to the interference signal. Figure 8 The first backpropagation process or the third backpropagation process will be described below with reference to a representative von Neumann derivative (e.g., the kernel generation circuit 330 or the filter (e.g., the adaptive filter 350)).

[0086] The second BPP circuit 364 can be configured to perform a second backpropagation process for the target delay signal based on a result of performing the first backpropagation process. Here, the second backpropagation process can indicate a backpropagation process of at least one circuit configured to perform a post-processing (see Figure 5 ) for the interference signal. The first backpropagation process and the second backpropagation process can include a backpropagation process based on a von Neumann derivative method (and a chain rule).

[0087] The second BPP circuit 364 can be configured to perform a fourth backpropagation process for the target delay signal based on a result of performing the third backpropagation process. Here, the fourth backpropagation process can indicate a backpropagation process of at least one circuit configured to perform a post-processing (see Figure 5 ) for the interference signal. The third backpropagation process and the fourth backpropagation process can include a backpropagation process based on a von Neumann derivative method (and a chain rule).

[0088] The interference cancellation circuit 300 according to an embodiment can be implemented in various methods. In one or more embodiments, when there is no hardware limitation, the interference cancellation circuit 300 can be configured to calculate a von Neumann derivative r，n (i.e., the interference-canceled signal) for each error signal e to estimate the CIR coefficients of the next sampling period In this case, the interference cancellation circuit 300 can be configured to estimate the CIR coefficients by sharing a hardware module having a high operation processing rate or estimate the CIR coefficients based on hardware modules corresponding to the delay signals, respectively That is, the interference cancellation circuit 300 can be configured to estimate the CIR coefficients in all sampling periods and update the CIR coefficients (first case).

[0089] In one or more embodiments, according to a setting, the interference cancellation circuit 300 can be configured to calculate the Wirtinger derivative only for a specific interference signal (i.e., a specific interference signal sample) and can estimate the CIR coefficients in the next sampling period and update the CIR coefficients (second case).

[0090] In one or more embodiments, according to a setting, the interference cancellation circuit 300 can be configured to calculate the Wirtinger derivative only in a specific sampling period and can estimate the CIR coefficients in the next sampling period and update the CIR coefficients (third case).

[0091] Here, when the adaptive filter 350 is present in each transmission path in the second case and the third case, the interference cancellation performance of the apparatus can not be significantly impaired. However, in this case, the CIR coefficients of the delay signals for each transmission path are updated by time division and a separate memory in which data of a transmission signal and data of a reception signal can be stored can be required.

[0092] Figure 5 is a diagram describing the operation of the interference cancellation circuit 300 according to one or more embodiments.

[0093] More specifically, Figure 5 is a diagram describing the operation of a wireless communication apparatus estimating the CIR coefficients of a delay signal (e.g., TS#00, TS#01, TS#02, …, TS#1(M-1)) for a corresponding transmission path (e.g., a zeroth transmission path Tx path#0 or a first transmission path Tx path#1).

[0094] In Figure 5 , the first pre-processing circuit 310-1 and the second pre-processing circuit 310-2 can correspond to the pre-processing circuit 310 shown in Figure 3 , and the first FIR filter 320-1 and the second FIR filter 320-2 can correspond to the FIR filter 320 shown in Figure 3The interference cancellation circuit 300 according to the embodiment may be implemented in a Hammerstein structure.

[0095] Reference Figure 5 The first pre-processing circuit 310-1 may be configured to receive a zeroth transmit signal TS#0 via a zeroth transmit path Tx path #0. The first pre-processing circuit 310-1 may be configured to perform at least one pre-processing on the zeroth transmit signal TS#0 and output the pre-processed zeroth transmit signal TS#0 to the first FIR filter 320-1. The second pre-processing circuit 310-2 may be configured to receive a first transmit signal TS#1 via a first transmit path Tx path #1. The second pre-processing circuit 310-2 may be configured to perform at least one pre-processing on the first transmit signal TS#1 and output the pre-processed first transmit signal TS#1 to the second FIR filter 320-2. The at least one pre-processing may include at least one of delay matching between transmit signals (e.g., the zeroth transmit path Tx path #0 and the first transmit path Tx path #1) received via different transmit paths (e.g., the zeroth transmit path Tx path #0 and the first transmit path Tx path #1), delay matching between interfering signals in the transmit paths, sampling rate adjustment, and / or a combination thereof.

[0096] The first FIR filter 320-1 may be configured to delay the pre-processed zeroth transmit signal TS#0 by a delay period (eg, Z ) preset in the plurality of buffer circuits by using the plurality of buffer circuits. -0 , Z -1 , Z -2 , ...) to generate the first delayed signal TS#00 to the Lth delayed signal TS#0(L-1). Here, the preset delay period (for example, Z -1 ) may include a sampling period of the interference signal. For example, the first delayed signal TS#00 may include delaying the zeroth transmission signal TS#0 by the zeroth delay period (eg, Z -0 ) signal (ie, the first delayed signal TS#00 is not delayed), the second delayed signal TS#01 may include a signal obtained by delaying the zeroth transmission signal TS#0 by a first delay period (eg, Z -1 ), ..., and the L-th delayed signal TS#0(L-1) may include delaying the zero-th transmission signal TS#0 by the L-1 delay period (eg, Z -(L-1) ) and the signal generated.

[0097] The first FIR filter 320-1 may be configured to filter the CIR coefficient corresponding to each delayed signal (or each delayed tap) by convolve each of the first delayed signal TS#00 to the Lth delayed signal TS#0(L-1) to set a CIR coefficient corresponding to each of the delayed signals In the CIR coefficients , t can indicate a transmission path index, and m can indicate a delay index. For example, the first FIR filter 320-1 can be configured to set a first CIR coefficient corresponding to the first delayed signal TS#00 by convolving the first CIR coefficient with the first delayed signal TS#00 set a second CIR coefficient corresponding to the second delayed signal TS#01 by convolving the second CIR coefficient with the second delayed signal TS#01 …, and set an Lth CIR coefficient corresponding to the Lth delayed signal TS#0(L-1) by convolving the Lth CIR coefficient with the Lth delayed signal TS#0(L-1)

[0098] The second FIR filter 320-2 can be configured to set first delayed signals TS#10 to Mth delayed signals TS#1(M-1) by delaying the pre-processed first transmission signal TS#1 by each of preset delay periods (e.g., Z -0 , Z -1 , Z -2 , …) for a plurality of buffer circuits using a plurality of buffer circuit. Here, the preset delay periods (e.g., Z -1 ) can include a sampling period of an interference signal. For example, the first delayed signal TS#10 can include a signal generated by delaying the first transmission signal TS#1 by a zeroth delay period (e.g., Z -0 ) in a first delay tap, the second delayed signal TS#11 can include a signal generated by delaying the first transmission signal TS#1 by a first delay period (e.g., Z -1 ) in a second delay tap, …, and the Mth delayed signal TS#1(M-1) can include a signal generated by delaying the first transmission signal TS#1 by an M-1th delay period (e.g., Z -(M-1) ) in an Mth delay tap.

[0099] The second FIR filter 320-2 can be configured to set CIR coefficients corresponding to the first delayed signal TS#10 to the Mth delayed signal TS#1(M-1), respectively, by convolving the CIR coefficients corresponding to the respective ones of the delayed signals with the first delayed signal TS#10 to the Mth delayed signal TS#1(M-1) In the CIR coefficients In the middle, t can indicate a transmit path index, and m can indicate a delay index. For example, the second FIR filter 320-2 can be configured to set a first CIR coefficient by convolving a first delay signal TS#10 with the first CIR coefficient by convolving a second delay signal TS#11 with the second CIR coefficient by convolving a second delay signal TS#11 with the second CIR coefficient …, and by convolving an Mth delay signal TS#1(M-1) with the Mth CIR coefficient by convolving an Mth delay signal TS#1(M-1) with the Mth CIR coefficient

[0100] The first FIR filter 320-1 can be configured to generate a zeroth aggregated signal STS#0 by aggregating the first delay signal TS#00 to the Lth delay signal TS#0(L-1) with the set CIR coefficients , and transmit the zeroth aggregated signal STS#0 to the kernel generation circuit 330. The first delay signal TS#00 to the Lth delay signal TS#0(L-1) with the set CIR coefficients may be referred to as a CIR adapted signal obtained by applying the CIR coefficients to the first delay signal TS#00 to the Lth delay signal TS#0(L-1) or by convolving the first delay signal TS#00 to the Lth delay signal TS#0(L-1) with the CIR coefficients corresponding thereto. The zeroth aggregated signal STS#0 can be an aggregated signal of the CIR adapted signals. The second FIR filter 320-2 can be configured to generate a first aggregated signal STS#1 by aggregating the first delay signal TS#10 to the Mth delay signal TS#1(M-1) with the set CIR coefficients , and transmit the first aggregated signal STS#1 to the kernel generation circuit 330. Similarly, the first delay signal TS#10 to the Mth delay signal TS#1(M-1) with the set CIR coefficients may be referred to as a CIR adapted signal obtained by applying the CIR coefficients to the first delay signal TS#10 to the Mth delay signal TS#1(M-1) or by convolving the first delay signal TS#10 to the Mth delay signal TS#1(M-1) with the CIR coefficients corresponding thereto. The first aggregated signal STS#1 can be an aggregated signal of the CIR adapted signals.

[0101] The kernel generation circuit 330 can be configured to generate / reproduce a kernel, i.e., an interference model (or an interference basis), based on the zeroth aggregated signal STS#0 and the first aggregated signal STS#1. The generated / reproduced interference model can include both an active interference signal and a passive interference signal. The kernel generation circuit 330 can be configured to transmit the generated / reproduced interference model to the post-processing circuit 340.

[0102] The post-processing circuit 340 can be configured to perform at least one post-processing with respect to the received interference model, and transmit the post-processed interference model to the adaptive filter 350. The at least one post-processing can include an operation of at least one of a delay matching between a transmit signal and a receive signal, an adjustment of a frequency offset, an adjustment of a sampling rate, and / or a combination thereof.

[0103] The adaptive filter 350 can be configured to estimate / generate an interference signal based on the post-processed interference model, and generate an interference-canceled signal (ICS) by filtering out the interference signal from a receive signal (e.g., Rx data). The adaptive filter 350 can be configured to transmit the interference-canceled signal ICS to the CIR estimation circuit 360. The interference cancellation circuit according to an embodiment can include a cancellation circuit instead of the adaptive filter 350. The cancellation circuit can be configured to estimate an interference signal according to the interference model, and generate a subtracted interference signal by simply subtracting the interference signal from the receive signal. The cancellation circuit can be configured to transmit the subtracted interference signal to the CIR estimation circuit 360.

[0104] The CIR estimation circuit 360 can be configured to estimate CIR coefficients corresponding to the delay signals of each transmit path in a next sampling period by using a backpropagation method based on the interference-canceled signal ICS (or the subtracted interference signal) For example, the CIR estimation circuit 360 can be configured to estimate CIR coefficients corresponding to the delay signals of each transmit path in a next sampling period by using a backpropagation method based on a Wirtinger derivative method and / or a chain rule

[0105] For updating the CIR coefficients corresponding to the delay signals of each transmit path in a next sampling period The CIR estimation circuit 360 can transmit the estimated CIR coefficients to the first FIR filter 320-1 or the second FIR filter 320-2.

[0106] The CIR estimation circuit 360 according to an embodiment is configured to estimate CIR coefficients of a transmit signal (or each delay signal generated from the transmit signal) of each transmit path by using a backpropagation method and a system having a relatively low complexity can be implemented.

[0107] The interference cancellation circuit 300 according to the embodiments can be configured to estimate CIR coefficients of a transmission signal (or each delayed signal generated from the transmission signal) of each transmission path by using the CIR estimation circuit 360 and reflect the CIR coefficients to interference modeling, and by doing so, the IMD interference can be efficiently removed.

[0108] For ease of explanation, reference is made to Figure 5 the operation of estimating CIR coefficients based on two transmission paths (e.g., a zeroth transmission path Tx path#0 and a first transmission path Tx path#1) is described, but the embodiments are not limited thereto, and the interference cancellation circuit 300 (or the CIR estimation circuit 360) according to the embodiments can be configured to estimate CIR coefficients

[0109] Figure 6 is a diagram describing the operation of the CIR estimation circuit 360 according to one or more embodiments.

[0110] More specifically, Figure 6 is a diagram describing CIR coefficients of a delayed signal of each transmission path (e.g., a zeroth transmission path Tx path#0 or a first transmission path Tx path#1) of the CIR estimation circuit 360. Unlike Figure 8 , Figure 6 shows an example of a configuration of the CIR estimation circuit 360 including a block (e.g., hardware) configured to sequentially estimate CIR coefficients of a delayed signal of each transmission path.

[0111] Referring to Figure 6 , the CIR estimation circuit 360 can include a first selector 361-1, a pre-processing circuit 362, a second selector 361-2, a first BPP circuit #1 363-1, a first BPP circuit #2 363-2, a second BPP circuit #1 364-1, and a second BPP circuit #2 364-2.

[0112] The first selector 361-1 can be configured to select any one of at least one transmission path (e.g., a zeroth transmission path Tx path#0 and a first transmission path Tx path#1) based on a first index (e.g., a transmission path index t). For example, when t=0, the zeroth transmission path Tx path#0 can be selected, and when t=1, the first transmission path Tx path#1 can be selected.

[0113] The pre-processing circuit 362 can be configured to perform at least one pre-processing for the transmission signals received through the transmission path selected by the first selector 361-1 (e.g., any one of the zeroth transmission path Tx path#0 and the first transmission path Tx path#1). The at least one pre-processing can include at least one of delay matching between the transmission signals, delay matching between interference signals in the transmission path, adjustment of a sampling rate, and / or a combination thereof. For example, when the zeroth transmission path Tx path#0 is selected by the first selector 361-1, the pre-processing circuit 362 can perform at least one pre-processing for the zeroth transmission signal TS#0 received through the zeroth transmission path Tx path#0.

[0114] The transmission signal for which at least one pre-processing is performed can be delayed for each of delay time periods (e.g., Z -0 , Z -1 , Z -2 ,...) preset for the plurality of buffers, and can be input to the second selector 361-2.

[0115] The second selector 361-2 can be configured to select any one of the plurality of delay signals (e.g., the first delay signal TS#00 to the Lth delay signal TS#0(L-1) when the zeroth transmission path Tx path#0 is selected by the first selector 361-1) based on a second index (e.g., a delay index m). For example, in the case of t=0 and m=0, the first delay signal TS#00 can be selected, and in the case of t=0 and m=1, the second delay signal TS#01 can be selected.

[0116] Referring to Figure 4 and Figure 6 , the BPP circuit 365 according to an embodiment can include a first BPP circuit#1 363-1, a first BPP circuit#2 363-2, a second BPP circuit#1 364-1, and a second BPP circuit#2 364-2.

[0117] When performing the backward propagation process based on the interference- canceled signal (i.e., based on the adaptive filter 350), the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 can perform a first backward propagation process, and the second BPP circuit #1 364-1 and the second BPP circuit #2 364-2 can perform a second backward propagation process based on a result of performing the first backward propagation process. The first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 can be configured to perform the first backward propagation process based on a first index (e.g., a transmit path index t). The first backward propagation process can indicate a process of calculating the Wirtinger derivatives for the adaptive filter 350 and the kernel generation circuit 330 in the selected transmit path based on the interference-canceled signal received from the adaptive filter 350 by using a backward propagation method (e.g., a chain rule, etc.). The first BPP circuit #1 363-1 can include a BPP circuit for a non-conjugate path in calculating the Wirtinger derivatives for the adaptive filter 350 and the kernel generation circuit 330, and the first BPP circuit #2 363-2 can include a BPP circuit for a conjugate path in calculating the Wirtinger derivatives for the adaptive filter 350 and the kernel generation circuit 330. The operations of calculating the Wirtinger derivatives for the adaptive filter 350 and the kernel generation circuit 330 in the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 will be described below with reference to Figure 7 The operations of calculating the Wirtinger derivatives for the adaptive filter 350 and the kernel generation circuit 330 in the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 will be described below with reference to Figure 6 The second backward propagation process can indicate a process of calculating the Wirtinger derivatives for at least one circuit configured to perform the post-processing in the selected transmit path based on the result of performing the first backward propagation process (i.e., the output values of the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2) by using a backward propagation method (e.g., a chain rule, etc.). The second BPP circuit #1 364-1 can include a BPP circuit for a non-conjugate path in calculating the Wirtinger derivatives for at least one circuit configured to perform the post-processing, and the second BPP circuit #2 364-2 can include a BPP circuit for a conjugate path in calculating the Wirtinger derivatives for at least one circuit configured to perform the post-processing. The operations of calculating the Wirtinger derivatives for at least one circuit configured to perform the post-processing in the second BPP circuit #1 364-1 and the second BPP circuit #2 364-2 will be described below with reference to Figure 7 The operations of calculating the Wirtinger derivatives for at least one circuit configured to perform the post-processing in the second BPP circuit #1 364-1 and the second BPP circuit #2 364-2 will be described below with reference to

[0118] When the backward propagation process is performed based on the interference- subtracted signal (i.e., based on the cancellation circuit), the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 can perform a third backward propagation process, and the second BPP circuit #1 364-1 and the second BPP circuit #2 364-2 can perform a fourth backward propagation process based on a result of performing the third backward propagation process. The first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 can be configured to perform the third backward propagation process based on the first index (e.g., a transmission path index t). The third backward propagation process can indicate a process of calculating the Windinger derivative for the cancellation circuit and the kernel generation circuit 330 in the selected transmission path by using a backward propagation method (e.g., a chain rule, etc.) based on the interference-subtracted signal received from the cancellation circuit. The first BPP circuit #1 363-1 can include a BPP circuit for a non-conjugate path in calculating the Windinger derivative for the cancellation circuit and the kernel generation circuit 330, and the first BPP circuit #2 363-2 can include a BPP circuit for a conjugate path in calculating the Windinger derivative for the cancellation circuit and the kernel generation circuit 330. The operation of calculating the Windinger derivative for the cancellation circuit and the kernel generation circuit 330 in the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 will be described below with reference to FIG. 13. Figure 7 The operation of calculating the Windinger derivative for the cancellation circuit and the kernel generation circuit 330 in the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2 will be described below with reference to FIG. 13. Figure 6 The fourth backward propagation process can indicate a process of calculating the Windinger derivative for at least one circuit configured to perform the post-processing in the selected transmission path by using a backward propagation method (e.g., a chain rule, etc.) based on the result of performing the third backward propagation process (i.e., the output values of the first BPP circuit #1 363-1 and the first BPP circuit #2 363-2). The second BPP circuit #1 364-1 can include a BPP circuit for a non-conjugate path in calculating the Windinger derivative for at least one circuit configured to perform the post-processing, and the second BPP circuit #2 364-2 can include a BPP circuit for a conjugate path in calculating the Windinger derivative for at least one circuit configured to perform the post-processing. The operation of calculating the Windinger derivative for at least one circuit configured to perform the post-processing in the second BPP circuit #1 364-1 and the second BPP circuit #2 364-2 will be described below with reference to FIG. 14. Figure 7 The operation of calculating the Windinger derivative for at least one circuit configured to perform the post-processing in the second BPP circuit #1 364-1 and the second BPP circuit #2 364-2 will be described below with reference to FIG. 14.

[0119] The BPP circuit 365 can be configured to generate a signal based on the error signal (e.g., −conj(e n ) and -e n The Wildinger derivative is calculated by multiplying the output values ​​of the second BPP circuit #1 364-1 and the second BPP circuit #2 364-2, respectively, and aggregating the values ​​obtained by the multiplication. (See Figure 4 ).

[0120] The BPP circuit 365 can be configured to pass the Wildinger derivative Substitute into the above [Formula 1] to estimate the CIR coefficient in the next sampling period The BPP circuit 365 may be configured to convert the estimated CIR coefficient Sent to FIR filter 320 to filter the estimated CIR coefficients Update the CIR coefficient of the delayed signal of each transmission path.

[0121] exist Figure 6 In the embodiment, the first selector 361-1 and the second selector 361-2 may be implemented in a number smaller than the total number of actual delay signals (or delay taps of the FIR filter 320) for reuse when using the time-sharing method.

[0122] Figure 7 is a diagram describing the operation of the CIR estimation circuit 360 according to one or more embodiments.

[0123] More specifically, Figure 7 1 is a diagram describing the operation of calculating Wildinger derivatives for the BPP circuits 365 (e.g., first BPP circuit #1 363-1, first BPP circuit #2 363-2, second BPP circuit #1 364-1, and second BPP circuit #2 364-2) of the CIR estimation circuit 360 and various FIR filter-type circuits (e.g., the FIR filter 320, the adaptive filter 350 (or cancellation circuit), filters in post-processing, etc.).

[0124] Reference Figure 7 The BPP circuit 365 may be configured to calculate the Wildinger derivative (non-conjugate path) of the kernel generation circuit 330 for each transmit path by using a back-propagation method. and the Wildinger derivative (conjugate path) exist Figure 7 In the example, the interference model g corresponding to the type of interference is n (e.g., mathematical model) can be "g n =f(y 0，n ,y 1，n )". Here, y0，n may indicate the output of the FIR filter 320 in the zeroth transmit path Tx path#0 (e.g., an aggregated signal obtained by aggregating the first delay signal through the Lth delay signal), and y 1，n may indicate the output of the FIR filter 320 in the first transmit path Tx path#1 (e.g., an aggregated signal obtained by aggregating the first delay signal through the Mth delay signal).

[0125] In the following, the case where the aggressor TX path number is 1 will be described.

[0126] In one or more embodiments, when the interference type is the 2nd harmonic model (2nd Har.), the interference model can be Here, for the mth delay signal in the zeroth transmit path Tx path#0 (where the transmit path index t = 0, and the delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 may be “2y 0， n x 0，n-m ”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 may be “zero”.

[0127] In one or more embodiments, when the interference type is the 2nd harmonic model (2nd Har.), the interference model can be In this case, for the mth delay signal in the first transmit path Tx path#1 (where the transmit path index t = 1, and the delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 may be “N / A”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 may be “N / A”.

[0128] In one or more embodiments, when the interference type is the 3rd harmonic model (3rd Har.), the interference model can be Here, for the mth delay signal in the zeroth transmit path Tx path#0 (where the transmit path index t = 0, and the delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 may be and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 may be “zero”.

[0129] In one or more embodiments, when the interference type is the 3rd harmonic model (3rd Har.), the interference model can be In this case, for the mth delayed signal in the first transmit path Tx path#1 (where the transmit path index t = 1 and the delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 may be “N / A”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 may be “N / A”.

[0130] In one or more embodiments, when the interference type is the 3rd harmonic model (3 rd rd Har.), the interference model can be Here, for the mth delayed signal in the zeroth transmit path Tx path#0 (where the transmit path index t = 0 and the delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 may be “zero”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 may be “x 0，n-m ”.

[0131] In one or more embodiments, when the interference type is the 3rd harmonic model (3 rd rd Har.), the interference model can be In this case, for the mth delayed signal in the first transmit path Tx path#1 (where the transmit path index t = 1 and the delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 may be “N / A”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 may be “N / A”.

[0132] In one or more embodiments, when the interference type is the 5th harmonic model (5 th th Har.), the interference model can be “g n = y 0，n ”. Here, for the mth delayed signal in the zeroth transmit path Tx path#0 (where the transmit path index t = 0 and the delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 may be “x 0，n-m ”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 may be “zero”.

[0133] In one or more embodiments, when the interference type is the 5th harmonic model (5 th) when the interference type is IM2 of aggressor TX path #1, the interference model can be n = y 0，n ”. In this case, for the mth delayed signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be “N / A”, and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be “N / A”.

[0134] In one or more embodiments, when the interference type is IM2 of aggressor TX path #1, the interference model can be Here, for the mth delayed signal in the zeroth transmit path Tx path#0 (where transmit path index t = 0, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be

[0135] In one or more embodiments, when the interference type is IM2 of aggressor TX path #1, the interference model can be In this case, for the mth delayed signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be “N / A”, and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be “N / A”.

[0136] Hereinafter, a case where the aggressor TX path number is 2 will be described.

[0137] In one or more embodiments, when the interference type is second-order intermodulation distortion (IMD2) of aggressor TX path #2, the interference model can be g n = y 0，n y 1，n ”. Here, for the mth delayed signal in the zeroth transmit path Tx path#0 (where transmit path index t = 0, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be “y 1，n x 0，n-m ” and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be “zero”.

[0138] In one or more embodiments, when the interference type is aggressor TX path #2 IMD2, the interference model can be g n = y 0，n y 1，n Here, for the mth delayed signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be “y 0，n x 1，n-m ” and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be “zero”.

[0139] In one or more embodiments, when the interference type is aggressor TX path #2 IMD2, the interference model can be Here, for the mth delayed signal in the zeroth transmit path Tx path#0 (where transmit path index t = 0, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be “zero”.

[0140] In one or more embodiments, when the interference type is aggressor TX path #2 IMD2, the interference model can be Here, for the mth delayed signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be “zero”, and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be

[0141] In one or more embodiments, when the interference type is aggressor TX path #2 third-order intermodulation distortion (IMD3), the interference model can be Here, for the mth delayed signal in the zeroth transmit path Tx path#0 (where transmit path index t = 0, delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be “zero”.

[0142] In one or more embodiments, when the interference type is IMD3 aggressor TX path number 2, the interference model can be Here, for the mthdelayed signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be “zero”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be

[0143] In one or more embodiments, when the interference type is IMD3 aggressor TX path number 2, the interference model can be Here, for the mthdelayed signal in the zeroth transmit path Tx path#0 (where transmit path index t = 0, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be “zero”.

[0144] In one or more embodiments, when the interference type is IMD3 aggressor TX path number 2, the interference model can be Here, for the mthdelayed signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be “2y 0，n y 1，n x 1，n-m ”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be “zero”.

[0145] In one or more embodiments, when the interference type is IMD3 aggressor TX path number 2, the interference model can be Here, for the mthdelayed signal in the zeroth transmit path Tx path#0 (where transmit path index t = 0, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be “zero”.

[0146] ​​​In one or more embodiments, when the interference type is IMD3 aggressor TX path number 2, the interference model can be Here, in the mth delay signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be “zero”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be

[0147] In one or more embodiments, when the interference type is IMD3 aggressor TX path number 2, the interference model can be Here, in the mth delay signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be “2y 0,n y 1,n x 0,n-m ”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be “zero”.

[0148] In one or more embodiments, when the interference type is IMD3 aggressor TX path number 2, the interference model can be Here, in the mth delay signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be “(y 0，n ) 2 x 1，n-m ”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be “zero”.

[0149] In one or more embodiments, when the interference type is fifth-order intermodulation distortion (IMD5) aggressor TX path number 2, the interference model can be Here, in the mth delay signal in the first transmit path Tx path#1 (where transmit path index t = 1, delay index m = m): the Wirtinger derivative (non-conjugate path) computed by the BPP circuit 365 can be “2y ”, and the Wirtinger derivative (conjugate path) computed by the BPP circuit 365 can be “2y ​

[0150] In one or more embodiments, when the interference type is IMD5 aggressor TX path #2, the interference model can be Here, for the mth delay signal in the first transmit path Tx path #1 (where the transmit path index t = 1, the delay index m = m): the Wirtinger derivative (non-conjugate path) calculated by the BPP circuit 365 can be “zero”, and the Wirtinger derivative (conjugate path) calculated by the BPP circuit 365 can be

[0151] In Figure 7 , “N / A” can indicate the Wirtinger derivative (non-conjugate path or conjugate path) unnecessary for estimating the CIR coefficient, but embodiments are not limited thereto. The BPP circuit 365 of the CIR estimation circuit 360 according to embodiments is not limited to the above-described interference types and the interference models corresponding to the interference types, and can be configured to calculate the Wirtinger derivative (non-conjugate path or conjugate path) for various interference types not disclosed in the present specification and the interference models corresponding to the various interference types.

[0152] The BPP circuit 365 can be configured to calculate the Wirtinger derivative for the output O n of the circuit for various FIR filter types (e.g., the FIR filter 320, the adaptive filter 350 (or cancellation circuit), the filter in post-processing, etc.) by using a backpropagation method. Here, the circuit for the FIR filter type (including the circuit in the interference cancellation circuit 300) can indicate a circuit in which the relationship between the input I n and the output O n is the relationship in Equation 6 below.

[0153] [Equation 6]

[0154]

[0155] Here, h FIR，l may indicate a filter coefficient.

[0156] The BPP circuit 365 can be configured to calculate the Wirtinger derivative for the circuit for the FIR filter type (e.g., the FIR filter 320, the adaptive filter 350 (or cancellation circuit), the filter in post-processing, etc.) based on Equations 7 and 8 below.

[0157] [Equation 7]

[0158]

[0159] [Equation 8] ​​

[0160]

[0161] For example, the first BPP circuit #1 363-1 can be configured to calculate the Wirtinger derivative (non-conjugate path) for the adaptive filter 350 (or cancellation circuit) based on the above [Equation 7] and the backpropagation method. For example, the first BPP circuit #2 363-2 can be configured to calculate the Wirtinger derivative (conjugate path) for the adaptive filter 350 (or cancellation circuit) based on the above [Equation 8] and the backpropagation method.

[0162] For example, the second BPP circuit #1 364-1 can be configured to calculate the Wirtinger derivative (non-conjugate path) for the filter for post-processing based on the above [Equation 7] and the backpropagation method. For example, the second BPP circuit #2 364-2 can be configured to calculate the Wirtinger derivative (conjugate path) for the filter for post-processing based on the above [Equation 8] and the backpropagation method.

[0163] When the above Equation 7 and Equation 8 are and I n-l are the outputs of the previous block of the circuit of the FIR filter type, the BPP circuit 365 can calculate the final Wirtinger derivative and by using the backpropagation method and the chain rule. (i.e., as described above, the Wirtinger derivative can also be calculated for the remaining processing of the interference cancellation circuit 300 by using the backpropagation method and the chain rule).

[0164] Accordingly, the CIR estimation circuit 360 according to an embodiment can be configured to estimate / calculate the CIR coefficient in the next sampling period by substituting the final Wirtinger derivative

[0165] Figure 8 An example of a configuration of the CIR estimation circuit 360 according to one or more embodiments is illustrated.

[0166] More specifically, Figure 8 An example of a configuration of the CIR estimation circuit 360 including a plurality of blocks (e.g., hardware) configured to estimate CIR coefficients of a delayed signal of a respective transmission path in parallel is illustrated.

[0167] In Figure 8 , the pre-processing circuit #1 362-1 and the pre-processing circuit #2 362-2 correspond to the pre-processing circuit 362 illustrated in Figure 6 , the pre-processing circuit 362, Figure 8The first BPP circuit #1-0 363-1-0 and the first BPP circuit #1-1 363-1-1 in FIG. 36 correspond to the first BPP circuit #1 363-1 illustrated in FIG. 36, and Figure 6 The first BPP circuit #1-0 363-1-0 and the first BPP circuit #1-1 363-1-1 in FIG. 36 correspond to the first BPP circuit #1 363-1 illustrated in FIG. 36, and Figure 8 The first BPP circuit #2-0 363-2-0 and the first BPP circuit #2-1 363-2-1 in FIG. 36 correspond to the first BPP circuit #2 363-2 illustrated in FIG. 36, and Figure 6 The first BPP circuit #2-0 363-2-0 and the first BPP circuit #2-1 363-2-1 in FIG. 36 correspond to the first BPP circuit #2 363-2 illustrated in FIG. 36, and Figure 8 The second BPP circuit #1-0 364-1-0 and the second BPP circuit #1-1 364-1-1 in FIG. 36 correspond to the second BPP circuit #1 364-1 illustrated in FIG. 36, and Figure 6 The second BPP circuit #1-0 364-1-0 and the second BPP circuit #1-1 364-1-1 in FIG. 36 correspond to the second BPP circuit #1 364-1 illustrated in FIG. 36, and Figure 8 The second BPP circuit #2-0 364-2-0 and the second BPP circuit #2-1 364-2-1 in FIG. 36 correspond to the second BPP circuit #2 364-2 illustrated in FIG. 36, and Figure 6 The second BPP circuit #2-0 364-2-0 and the second BPP circuit #2-1 364-2-1 in FIG. 36 correspond to the second BPP circuit #2 364-2 illustrated in FIG. 36, and

[0168] Hereinafter, it is assumed that the transmission signal of the zeroth transmission path Tx path#0 is generated as L delay signals by the L buffers of the FIR filter 320, and the transmission signal of the first transmission path Tx path#1 is generated as M delay signals by the M buffers of the FIR filter 320.

[0169] Referring to FIG. 36, Figure 6 According to an embodiment, the CIR estimation circuit 360 can be configured to estimate CIR coefficients of the delay signals of the respective transmission paths in parallel. To this end, the CIR estimation circuit 360 can be implemented as blocks for the respective transmission paths including a plurality of sub-blocks (for example, a zeroth block Block#0 for the zeroth transmission path Tx path#0 and a first block Block#1 for the first transmission path Tx path#1). Here, the number of the plurality of sub-blocks included in the CIR estimation circuit 360 can be {the total number of transmission paths (i.e., transmission antennas) × (the total number of delay signals (or delay taps) of the respective transmission paths)}.

[0170] In one or more embodiments, each of the blocks (e.g., the zeroth block Block#0 for the zeroth transmit path Tx path#0 and the first block Block#1 for the first transmit path Tx path#1) of the CIR estimation circuit 360 can include sub-blocks for estimating CIR coefficients of a delay signal (or delay taps generating a delay signal) for each transmit path. In one or more embodiments, the zeroth block Block#0 for the zeroth transmit path Tx path#0 can include: a 0-0 sub-block Sub-block#0-0 for estimating CIR coefficients of a first delay signal (or a first delay tap for generating a first delay signal), a 0-1 sub-block Sub-block#0-1 for estimating CIR coefficients of a second delay signal (or a second delay tap for generating a second delay signal), …, and a 0-L-1 sub-block Sub-block#0-L-1 for estimating CIR coefficients of an Lth delay signal (or an Lth delay tap for generating an Lth delay signal). Here, each of the 0-0 sub-block Sub-block#0-0 to the 0-L-1 sub-block Sub-block#0-L-1 can include a pre-processing circuit, a first BPP circuit, a second BPP circuit, etc. (see FIG. 3B). Figure 9 For example, the 0-0 sub-block Sub-block#0-0 can include a pre-processing circuit#1 362-1, a first BPP circuit#1-0 363-1-0, a first BPP circuit#2-0 363-2-0, a second BPP circuit#1-0 364-1-0, and a second BPP circuit#2-0 364-2-0. For example, the 0-1 sub-block Sub-block#0-1 can include a pre-processing circuit#2 362-2, a first BPP circuit#1-1 363-1-1, a first BPP circuit#2-1 363-2-1, a second BPP circuit#1-1 364-1-1, and a second BPP circuit#2-1 364-2-1.

[0171] In one or more embodiments, the first block Block#1 for the first transmit path Tx path#1 can include: a 1-0 sub-block Sub-block#1-0 for estimating CIR coefficients of a first delay signal (or a first delay tap generating the first delay signal), a 1-1 sub-block Sub-block#1-1 for estimating CIR coefficients of a second delay signal (or a second delay tap generating the second delay signal), …, and a 1-M-1 sub-block Sub-block#1-M-1 for estimating CIR coefficients of an Mth delay signal (or an Mth delay tap generating the Mth delay signal). Here, each of the 1-0 sub-block Sub-block#1-0 to the 1-M-1 sub-block Sub-block#1-M-1 can include a pre-processing circuit, a first BPP circuit, a second BPP circuit, and the like (see Figure 9 ).

[0172] Figure 3 An example of a configuration of the interference cancellation circuit 300 according to one or more embodiments is shown.

[0173] Figure 9 The FIR filter in Figure 3 may correspond to the FIR filter 320 in Figure 9 The kernel generation circuit in Figure 3 may correspond to the kernel generation circuit 330 in Figure 9 The post-processing circuit in Figure 3 may correspond to the post-processing circuit 340 in Figure 9 The adaptive filter #1 to the adaptive filter #4 in Figure 3 may correspond to the adaptive filter 350 in Figure 9 The CIR estimation circuit in Figure 9 may correspond to the CIR estimation circuit 360 in

[0174] In Figure 9 , it is assumed that each of a zeroth receive signal RS#0 to a third receive signal RS#3 is received through a zeroth receive path Rx path#0 to a third receive path Rx path#3, respectively.

[0175] Referring to Figure 10According to the embodiment, the interference cancellation circuit 300 can include a common FIR filter, a kernel generation circuit, a post-processing circuit, a CIR estimation circuit, and a plurality of adaptive filters corresponding to respective ones of the plurality of reception paths. For example, the interference cancellation circuit 300 can include a common FIR filter, a kernel generation circuit, a post-processing circuit, a CIR estimation circuit, an adaptive filter #1 corresponding to the zeroth reception path Rx path #0, an adaptive filter #2 corresponding to the first reception path Rx path #1, an adaptive filter #3 corresponding to the second reception path Rx path #2, and an adaptive filter #4 corresponding to the third reception path Rx path #3.

[0176] Figure 10 The CIR estimation circuit shown in FIG. 3 can be configured to receive the interference-canceled signals #0 ICS #0 to #3 ICS #3, and estimate CIR coefficients of the delay signals of the respective transmission paths by using a back propagation method based on the interference-canceled signals #0 ICS #0 to #3 ICS #3. Here, the CIR estimation circuit can use the back propagation method based on [Equation 3] or [Equation 4] described above.

[0177] Figure 3 Another example of a configuration of an interference cancellation circuit according to one or more embodiments is shown.

[0178] Figure 10 The FIR filter #1 shown in FIG. 3 can correspond to Figure 3 The FIR filter 320 shown in FIG. 3, Figure 10 The kernel generation circuit #1 shown in FIG. 3 can correspond to Figure 3 The kernel generation circuit 330 shown in FIG. 3, Figure 10 The post-processing circuit #1 shown in FIG. 3 can correspond to Figure 3 The post-processing circuit 340 shown in FIG. 3, and Figure 4 The CIR estimation circuit #1 shown in FIG. 3 can correspond to Figure 10 and Figure 3 The CIR estimation circuit 360 shown in FIG. 3. In the description regarding the FIR filter #1, the kernel generation circuit #1, the post-processing circuit #1, and the CIR estimation circuit #1 shown in FIG. 3, Figure 4 the same description as the description with reference to Figure 3 and Figure 3 may be replaced with the description regarding the FIR filter 320, the kernel generation circuit 330, the post-processing circuit 340, and Figure 4 The CIR estimation circuit 360 shown in FIG. 3. Figure 10 and Figure 10 In the description regarding the FIR filter #1, the kernel generation circuit #1, the post-processing circuit #1, and the CIR estimation circuit #1 shown in FIG. 3,

[0179] In the description regarding the FIR filter #1, the kernel generation circuit #1, the post-processing circuit #1, and the CIR estimation circuit #1 shown in FIG. 3, Figure 10In the interference cancellation circuit 300 shown in FIG. 1, the FIR filter #1 can be configured to generate the first delayed signal to the n-th delayed signal by delaying the received signal by a delay period set for the plurality of buffers, and set the CIR coefficients corresponding to the first delayed signal to the n-th delayed signal for the first delayed signal to the n-th delayed signal, respectively.

[0180] Referring to Figure 10 , the interference cancellation circuit 300 according to the embodiment can include a plurality of blocks corresponding to a plurality of reception paths, respectively. Here, each of the plurality of blocks can be configured to include the FIR filter, the kernel generation circuit, the post-processing circuit, the CIR estimation circuit, and the cancellation circuit. Here, the cancellation circuit (instead of the adaptive filter) can be configured to estimate the interference signal based on the interference model, and generate the interference-canceled signal by subtracting the interference signal from the received signal. In some cases, in the interference cancellation circuit 300 shown in Figure 10 , the CIR estimation circuit can perform some functions of the adaptive filter (e.g., a function of estimating a channel between the interference model and the reception path). For example, in the interference cancellation circuit 300, the block corresponding to the zero-th reception path Rx path #0 can be configured to include the FIR filter #1, the kernel generation circuit #1, the post-processing circuit #1, the CIR estimation circuit #1, the cancellation circuit #1. The cancellation circuit #1 can be configured to generate the interference-canceled signal #0 ISS #0 by subtracting the interference signal from the zero-th received signal RS #0, and transmit the generated interference-canceled signal #0 ISS #0 to the CIR estimation circuit #1.

[0181] The FIR filter #1 can further include a plurality of buffers. For example, the FIR filter #1 can be configured to generate the first delayed signal to the n-th delayed signal by delaying the received signal by a delay period set for the plurality of buffers by using the plurality of buffers, and set the CIR coefficients corresponding to the first delayed signal to the n-th delayed signal for the first delayed signal to the n-th delayed signal, respectively.

[0182] The kernel generation circuit #1 can be configured to generate the interference model based on an aggregated signal generated by aggregating the first delayed signal to the n-th delayed signal to which the CIR coefficients are set.

[0183] The CIR estimation circuit #1 can be configured to estimate the CIR coefficients corresponding to the first delayed signal and the n-th delayed signal in the next sampling period by using the backpropagation method based on the interference-canceled signal #0 ISS #0, and transmit the CIR coefficients corresponding to the first delayed signal to the n-th delayed signal in the next sampling period to the FIR filter #1. Here, the FIR filter #1 can be configured to update the CIR coefficients corresponding to the first delayed signal to the n-th delayed signal based on the CIR coefficients in the next sampling period received from the CIR estimation circuit #1. Here, the backpropagation method can indicate a backpropagation method based on the Wirtinger derivative method.

[0184] As described above, the CIR estimation circuit (e.g., CIR estimation circuit #1) included in each of the plurality of blocks in Figure 11 may be configured to estimate CIR coefficients of a delay signal of a corresponding transmission path by using a back propagation method based on an interference-subtracted signal (e.g., interference-subtracted signal ISS#0) received from the cancellation circuit (e.g., cancellation circuit #1) in the same block. Although Figure 11 the interference cancellation circuit 300 shown inmay be designed to have a higher complexity, when each reception path includes an adaptive filter, the accuracy of the estimation of the CIR coefficients can be improved.

[0185] Figure 3 Another example of an interference cancellation circuit according to one or more embodiments is shown.

[0186] Figure 11 The FIR filter #1 shown inmay correspond to the FIR filter 320 shown in Figure 3 Figure 11 The kernel generation circuit #1 shown inmay correspond to the kernel generation circuit 330 shown in Figure 3 Figure 11 The post-processing circuit #1 shown inmay correspond to the post-processing circuit 340 shown in Figure 3 Figure 11 The adaptive filter #1 shown inmay correspond to the adaptive filter 350 shown in Figure 3 Figure 11 The CIR estimation circuit #1 shown in may correspond to the CIR estimation circuit 360 shown in Figure 11

[0187] In Figure 11 , it is assumed that a zeroth reception signal RS#0 to a third reception signal RS#3 are received through a zeroth reception path Rx path#0 to a third reception path Rx path#3, respectively.

[0188] Referring to Figure 12 , the interference cancellation circuit 300 according to an embodiment can include a plurality of blocks corresponding to a plurality of reception paths, respectively. Here, each of the plurality of blocks can be configured to include a FIR filter, a kernel generation circuit, a post-processing circuit, a CIR estimation circuit, and an adaptive filter. For example, in the interference cancellation circuit 300, a block corresponding to the zeroth reception path Rx path#0 can be configured to include a FIR filter #1, a kernel generation circuit #1, a post-processing circuit #1, a CIR estimation circuit #1, and an adaptive filter #1.

[0189] included in Figure 12The CIR estimation circuit (e.g., CIR estimation circuit #1) in each of the plurality of blocks in the CIR estimation circuit 300 can be configured to estimate CIR coefficients of a delay signal of a corresponding transmission path by using a back propagation method based on an interference-canceled signal (e.g., interference-canceled signal ICS #0) received from an adaptive filter (e.g., adaptive filter #1) of the same block.

[0190] Figure 12 is a flowchart for describing an operation method of the interference cancellation circuit 300 according to one or more embodiments.

[0191] Referring to Figures 1 to 11 The method of estimating CIR coefficients of a delay signal of a corresponding transmission path by the interference cancellation circuit 300 can include operations S100 to S150. In the description of Figures 1 to 11 , the same description as the description of Figure 13 will be replaced with the description of Figure 13 .

[0192] In operation S100, the interference cancellation circuit 300 can set CIR coefficients for each transmission path of a transmission signal. For example, the interference cancellation circuit 300 can be configured to generate first to nth delay signals by delaying the transmission signal by each preset delay period. For the first to nth delay signals, the interference cancellation circuit 300 can set CIR coefficients corresponding to the first to nth delay signals, respectively.

[0193] In operation S110, the interference cancellation circuit 300 can generate an interference model based on the transmission signal for which the CIR coefficients are set. For example, the interference cancellation circuit 300 can generate an aggregated signal by aggregating the first to nth delay signals for which the CIR coefficients are set, and generate the interference model based on the aggregated signal.

[0194] In operation S120, the interference cancellation circuit 300 can estimate an interference signal of each reception path based on the interference model. In operation S130, the interference cancellation circuit 300 (e.g., including an adaptive filter) can generate an interference-canceled signal by filtering out the interference signal from a reception signal. For another example, in operation S130, the interference cancellation circuit 300 (e.g., including a cancellation circuit) can generate a subtraction interference signal by subtracting the interference signal from the reception signal instead of operation S130 (e.g., generating an interference-canceled signal based on the adaptive filter).

[0195] In operation S140, the interference cancellation circuit 300 can estimate CIR coefficients in a next sampling period based on the interference cancelled signal (or the interference subtracted signal) by using a back propagation method. In operation S150, the interference cancellation circuit 300 can update the estimated CIR coefficients as CIR coefficients of the respective transmission paths. For example, the interference cancellation circuit 300 can estimate CIR coefficients corresponding to the first delayed signal to the nth delayed signal in the next sampling period based on the interference cancelled signal (or the interference subtracted signal) by using a back propagation method. The interference cancellation circuit 300 can update each of the estimated CIR coefficients in the next sampling period as a CIR coefficient corresponding to each of the first delayed signal to the nth delayed signal.

[0196] In one or more embodiments, when a plurality of reception signals is received through a plurality of reception paths, the interference cancellation circuit 300 can generate a plurality of interference cancelled signals by filtering out an interference signal from each of the plurality of reception signals. The interference cancellation circuit 300 can estimate CIR coefficients based on the plurality of interference cancelled signals to which a preset weight is applied (see Equation 3) by using a back propagation method.

[0197] In one or more embodiments, when a plurality of reception signals is received through a plurality of reception paths, the interference cancellation circuit 300 can identify a reception signal having the strongest interference from among the plurality of reception signals, and generate a target interference cancelled signal by filtering out an interference signal from the reception signal having the strongest interference. The interference cancellation circuit 300 can estimate CIR coefficients based on the target interference cancelled signal (see Equation 4) by using a back propagation method.

[0198] In one or more embodiments, when a plurality of reception signals is received through a plurality of reception paths, the interference cancellation circuit 300 can include an FIR filter, a kernel generation circuit, a plurality of adaptive filters corresponding to the plurality of reception paths, respectively, and a CIR estimation circuit.

[0199] In one or more embodiments, when a plurality of reception signals is received through a plurality of reception paths, the interference cancellation circuit 300 can include a plurality of blocks corresponding to the plurality of reception paths, respectively, and each of the plurality of blocks can include an FIR filter, a kernel generation circuit, a cancellation circuit, and a CIR estimation circuit that estimates CIR coefficients based on an interference subtracted signal by using a back propagation method. In this case, the cancellation circuit can generate the interference subtracted signal by subtracting an interference signal from a reception signal received from any one path among the plurality of reception paths.

[0200] In one or more embodiments, when a plurality of reception signals is received through a plurality of reception paths, the interference cancellation circuit 300 can include a plurality of blocks corresponding to the plurality of reception paths, respectively, and each of the plurality of blocks can include a FIR filter, a kernel generation circuit, an adaptive filter, and a CIR estimation circuit.

[0201] In one or more embodiments, the backpropagation method can include a backpropagation method based on the Viterbi derivative method (and the chain rule).

[0202] According to various embodiments, according to the CIR estimation circuit 360, the interference cancellation circuit 300, and the operation method thereof, the IMD interference can be effectively cancelled by estimating the CIR coefficients of each transmission path and reflecting the CIR coefficients to interference modeling, the structure can be simply constructed and can be implemented with low system complexity.

[0203] Figure 13 is a flowchart for describing an operation method of the CIR estimation circuit 360 according to one or more embodiments.

[0204] Referring to Figures 1 to 12 , the method of estimating the CIR coefficients of the delayed signals of each transmission path by the CIR estimation circuit 360 can include operations S200 to S230. In the description with reference to Figures 1 to 12 , the same description as the description with reference to Figure 14 will be replaced with the description with reference to Figure 14 .

[0205] In operation S200, the CIR estimation circuit 360 can determine a target delayed signal for updating the CIR coefficients among a plurality of delayed signals based on a transmission path index and a delay index.

[0206] In operation S210, the CIR estimation circuit 360 can perform a backpropagation process with respect to the target delayed signal.

[0207] In one or more embodiments, the CIR estimation circuit 360 can perform a backpropagation process with respect to the target delayed signal based on a signal from which the interference is cancelled. For example, the CIR estimation circuit 360 can perform a first backpropagation process with respect to an adaptive filter configured to filter out an interference signal from a reception signal and a kernel generation circuit configured to generate an interference model corresponding to the interference signal. The CIR estimation circuit 360 can perform a second backpropagation process with respect to at least one circuit configured to perform post-processing with respect to the interference signal based on a result of performing the first backpropagation process.

[0208] In one or more embodiments, the CIR estimation circuit 360 can perform a back propagation process for a target delay signal based on the signal from which the interference is subtracted. For example, the CIR estimation circuit 360 can perform a third back propagation process for a cancellation circuit configured to subtract the interference signal from the received signal and a kernel generation circuit configured to generate an interference model corresponding to the interference signal. The CIR estimation circuit 360 can perform a fourth back propagation process for at least one circuit configured to perform post-processing for the interference signal based on a result of performing the third back propagation process.

[0209] In operation S220, the CIR estimation circuit 360 can estimate the CIR coefficient of the target delay signal based on a result of performing the back propagation process. Here, the back propagation process can indicate a process by using a back propagation method based on the Wirtinger derivative method.

[0210] In one or more embodiments, when the back propagation process is performed based on the signal from which the interference is cancelled, the CIR estimation circuit 360 can estimate the CIR coefficient of the target delay signal based on a result of performing the second back propagation process.

[0211] In one or more embodiments, when the back propagation process is performed based on the signal from which the interference is subtracted, the CIR estimation circuit 360 can estimate the CIR coefficient of the target delay signal based on a result of performing the fourth back propagation process.

[0212] In operation S230, the CIR estimation circuit 360 can transmit the estimated CIR coefficient to the FIR filter to update the estimated CIR coefficient as the CIR coefficient of the target delay signal in the next sampling period.

[0213] Figure 14 is a block diagram of a wireless communication apparatus 1000 according to one or more embodiments.

[0214] Referring to Figure 2 The wireless communication apparatus 1000 can include a modem and a radio frequency integrated circuit (RFIC) 1060, and the modem can include an application specific integrated circuit (ASIC) 1010, an application specific instruction set processor (ASIP) 1030, a memory 1050, a main processor 1070, and a main memory 1090. Figure 3 The wireless communication apparatus 1000 shown in FIG.

[0215] The wireless communication device (e.g., modem) 1000 according to the embodiments can be configured to estimate CIR coefficients for a delay signal of each transmission path using a back propagation method (e.g., a back propagation method based on a Viterbi derivative and a chain rule), and effectively remove an interference signal by reflecting the estimated CIR coefficients to interference modeling. For example, the main processor 1070 can include an interference cancellation circuit 300 shown in FIGS. 1, 2, 3, 4, 5, and 6 to estimate CIR coefficients by a back propagation method. ​ and ​ The main processor 1070 can include the interference cancellation circuit 300 shown in FIGS. 1, 2, 3, 4, 5, and 6 to estimate CIR coefficients by a back propagation method.

[0216] The RFIC 1060 can be connected to the antenna Ant, and configured to receive / transmit a signal from / to the outside by using a wireless communication network. The ASIP 1030, which is an integrated circuit customized for a specific purpose, can be configured to support a dedicated instruction set for a specific application and execute instructions included in the instruction set. The memory 1050 can be configured to communicate with the ASIP 1030, and can also be configured to store a plurality of instructions executed by the ASIP 1030 as a non-transitory storage device. For example, the memory 1050 can include any type of memory device accessible by the ASIP 1030, such as a random access memory (RAM), a read only memory (ROM), a tape, a disk, an optical disk, a volatile memory, a non-volatile memory, and combinations thereof, by way of non-limiting example.

[0217] The main processor 1070 can be configured to control the wireless communication device 1000 by executing a plurality of instructions. For example, the main processor 1070 can be configured to control the ASIC 1010 and the ASIP 1030, and can also be configured to process data received through a wireless communication network or a user input to the wireless communication device 1000.

[0218] The main memory 1090 can be configured to communicate with the main processor 1070, and can also be configured to store a plurality of instructions executed by the main processor 1070 as a non-transitory storage device. For example, the main memory 1090 can include any type of memory device accessible by the main processor 1070, such as a random access memory (RAM), a read only memory (ROM), a tape, a disk, an optical disk, a volatile memory, a non-volatile memory, and combinations thereof, by way of non-limiting example.

[0219] As described above, example embodiments have been disclosed in the drawings and specification. Although the embodiments are described herein with the use of specific terms, the terms are used only in describing the inventive concept and not in limiting the meaning or the scope of the inventive concept written in the claims. Those skilled in the art will understand that various modifications and other equivalent embodiments can be made from the embodiments. Therefore, the technical scope of the inventive concept will be determined by the technical spirit of the appended claims.

[0220] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An interference cancellation circuit, comprising: a finite impulse response filter configured to set a channel impulse response coefficient for each transmission path of a transmission signal and obtain a channel impulse response-adapted transmission signal by applying the channel impulse response coefficient to the transmission signal; a core generation circuit configured to generate an interference model based on a transmit signal adapted to a channel impulse response; an adaptive filter configured to estimate an interference signal for each reception path by estimating interference model coefficients of an interference model, and to generate an interference-canceled signal by filtering the interference signal from the reception signal; as well as The channel impulse response estimation circuit is configured to estimate a channel impulse response coefficient in a next sampling period by using a back propagation method based on the interference-eliminated signal and transmit the estimated channel impulse response coefficient to the finite impulse response filter.

2. The interference elimination circuit according to claim 1, wherein: The finite impulse response filter includes a plurality of buffers and is further configured to: generating first to nth delayed signals by delaying a transmit signal using the plurality of buffers, wherein the plurality of buffers are provided with different delay periods, and A channel impulse response coefficient is set for each of the first to nth delayed signals, and Here, n is a natural number greater than or equal to 2.

3. The interference elimination circuit according to claim 2, wherein: The kernel generation circuit is further configured to generate an interference model based on an aggregate signal generated by aggregating the first to nth delayed signals to which the channel impulse response coefficients are applied.

4. The interference elimination circuit according to claim 3, wherein: The channel impulse response estimation circuit is further configured to: estimating channel impulse response coefficients corresponding to the first to nth delayed signals, respectively, in the next sampling period by using a back propagation method based on the interference-eliminated signal; and Sending the channel impulse response coefficients corresponding to the first to nth delayed signals in the next sampling period to the finite impulse response filter, and The finite impulse response filter is further configured to update existing channel impulse response coefficients corresponding to the first to nth delayed signals respectively to channel impulse response coefficients estimated by the channel impulse response estimation circuit for the next sampling period.

5. The interference cancellation circuit according to any one of claims 1 to 4, wherein: When a plurality of reception signals are received through a plurality of reception paths, the interference cancellation circuit includes a finite impulse response filter, a kernel generation circuit, a plurality of adaptive filters respectively corresponding to the plurality of reception paths, and a channel impulse response estimation circuit.

6. The interference cancellation circuit according to any one of claims 1 to 4, wherein: When a plurality of reception signals are received through a plurality of reception paths, the interference cancellation circuit includes a plurality of blocks respectively corresponding to the plurality of reception paths, and Each of the plurality of blocks includes a finite impulse response filter, a kernel generation circuit, an adaptive filter, and a channel impulse response estimation circuit.

7. The interference cancellation circuit according to any one of claims 1 to 4, wherein: The back-propagation method is performed based on the Wildinger derivative method.

8. An interference cancellation circuit comprising: a finite impulse response filter configured to set a channel impulse response coefficient for each transmission path of a transmission signal and obtain a channel impulse response-adapted transmission signal by applying the channel impulse response coefficient to the transmission signal; a core generation circuit configured to generate an interference model based on a transmit signal adapted to a channel impulse response; a cancellation circuit configured to generate an interference-subtracted signal by subtracting an interference signal estimated based on an interference model from a received signal; as well as The channel impulse response estimation circuit is configured to estimate a channel impulse response coefficient in a next sampling period by using a back propagation method based on the interference-subtracted signal and send the estimated channel impulse response coefficient to the finite impulse response filter.

9. The interference elimination circuit according to claim 8, wherein: The finite impulse response filter includes a plurality of buffers and is further configured to: generating first to nth delayed signals by delaying a transmit signal using the plurality of buffers, wherein the plurality of buffers are provided with different delay periods, and setting a channel impulse response coefficient for each of the first to nth delayed signals, Here, n is a natural number greater than or equal to 2.

10. The interference cancellation circuit according to claim 9, wherein: The kernel generation circuit is further configured to generate an interference model based on an aggregate signal generated by aggregating the first to nth delayed signals to which the channel impulse response coefficients are applied.

11. The interference cancellation circuit according to claim 10, wherein: The channel impulse response estimation circuit is further configured to: estimating channel impulse response coefficients corresponding to the first to nth delayed signals, respectively, in the next sampling period by using a back propagation method based on the interference-subtracted signal; sending the channel impulse response coefficients corresponding to the first to nth delayed signals respectively in the next sampling period to the finite impulse response filter; and The finite impulse response filter is configured to update existing channel impulse response coefficients corresponding to the first to nth delayed signals respectively to channel impulse response coefficients estimated by the channel impulse response estimation circuit for the next sampling period.

12. The interference cancellation circuit according to any one of claims 8 to 11, wherein: When a plurality of reception signals are received through a plurality of reception paths, the interference cancellation circuit includes a plurality of blocks respectively corresponding to the plurality of reception paths, and Each of the plurality of blocks includes a finite impulse response filter, a kernel generation circuit, a cancellation circuit, and a channel impulse response estimation circuit.

13. The interference cancellation circuit according to any one of claims 8 to 11, wherein: The back-propagation method is performed based on the Wildinger derivative method.

14. A method for operating a channel impulse response estimation circuit, the method comprising: generating a target delay signal for updating a channel impulse response coefficient among a plurality of delay signals based on a transmission path index and a delay index; performing back-propagation processing on the target delayed signal; estimating a channel impulse response coefficient of the target delayed signal based on a result of performing the back-propagation process; as well as The estimated channel impulse response coefficients are sent to a finite impulse response filter to update the estimated channel impulse response coefficients to channel impulse response coefficients of a target delayed signal in a next sampling period.

15. The operating method according to claim 14, wherein: The step of performing the back propagation process includes performing the back propagation process based on the interference-eliminated signal.

16. The operating method according to claim 14, wherein: The step of performing the back propagation process includes performing the back propagation process based on the signal from which the interference is subtracted.

17. The operating method according to claim 15, wherein: The steps of performing back propagation processing based on the interference-eliminated signal include: performing a first back-propagation process on an adaptive filter configured to filter out an interference signal from a received signal and a kernel generation circuit configured to generate an interference model corresponding to the interference signal, and performing a second back-propagation process on at least one circuit based on a result of performing the first back-propagation process, the at least one circuit being configured to perform post-processing on the interference signal, and The step of estimating the channel impulse response coefficient includes estimating the channel impulse response coefficient of the target delayed signal based on a result of performing the second back propagation process.

18. The operating method according to claim 16, wherein: The steps of performing back propagation processing based on the interference-subtracted signal include: performing a third back-propagation process on a cancellation circuit configured to subtract the interference signal from the received signal and a kernel generation circuit configured to generate an interference model corresponding to the interference signal, performing a fourth back-propagation process on at least one circuit based on a result of performing the third back-propagation process, the at least one circuit being configured to perform post-processing on the interference signal, and Here, the step of estimating the channel impulse response coefficient is performed based on a result of performing the fourth back propagation process.

19. The operating method according to any one of claims 14 to 18, wherein: The plurality of delay signals indicate delay signals generated by delaying a transmission signal by a delay period set in each of a plurality of delay circuits.

20. The operating method according to any one of claims 14 to 18, wherein: The back-propagation process is performed based on the Wildinger derivative method.

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