A method of manufacturing a semiconductor device and a semiconductor device

Abstract

The present application relates to a semiconductor device manufacturing method and a semiconductor device, the semiconductor device manufacturing method comprising: providing a substrate, the substrate comprising at least two regions separated by an isolation trench, a functional trench being formed in at least one region; performing ion implantation for doping on the region where the functional trench is formed to form a MOS region; forming a strain-enhanced trench in the functional trench; growing a strain material in the strain-enhanced trench, so that the upper surface of the strain material is higher than the upper surface of the substrate; filling an isolation medium in the isolation trench and the strain-enhanced trench; and forming a dummy gate structure in a preset gate region by taking the height difference between the upper surface of the strain material and the upper surface of the substrate as a self-alignment reference. By forming the MOS region first and then forming the dummy gate structure, the dummy gate structure can be uniformly polished by using a chemical mechanical polishing process when the dummy gate structure is removed, thereby solving the problem of Loading.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a manufacturing method of a semiconductor device and the semiconductor device. BACKGROUND

[0002] In the current metal gate process, a process flow of first forming a dummy polysilicon gate, then epitaxially growing SiGe in the trench in the MOS region, and then removing the dummy polysilicon gate and filling a metal layer is usually adopted. However, in the prior art, before the dummy polysilicon gate is removed, the oxide on the dummy polysilicon gate is used as a hard mask to epitaxially grow a layer of strain material in the trench in the MOS region, which inevitably causes the oxide thickness to become uneven. Further, in the process of removing the dummy polysilicon, the chemical mechanical polishing (CMP) process will be affected by the difference in the thickness of the oxide hard mask (PolyHM) of different dummy polysilicon gates, causing a "Loading" problem, which further affects the subsequent etching process and the performance of the entire device. SUMMARY

[0003] To solve the above problems, the present application provides a manufacturing method of a semiconductor device and the semiconductor device.

[0004] The technical scheme of the present application is as follows:

[0005] In one aspect, the present application provides a manufacturing method of a semiconductor device, comprising:

[0006] providing a substrate, the substrate comprising at least two regions separated by an isolation trench, and at least one of the regions being formed with a functional trench;

[0007] performing ion implantation on the region formed with the functional trench to form a MOS region;

[0008] forming a strain-enhanced trench in the functional trench;

[0009] growing a strain material in the strain-enhanced trench, so that the upper surface of the strain material is higher than the upper surface of the substrate;

[0010] filling an isolation medium in the isolation trench and the strain-enhanced trench;

[0011] forming a dummy gate structure in a preset gate region by taking the height difference between the upper surface of the strain material and the upper surface of the substrate as a self-alignment reference;

[0012] The preset gate region is a spacing region between adjacent strain materials on the substrate of the MOS region. Preferably, the forming process of the isolation trench and the functional trench comprises:

[0013] The substrate is pretreated so that a first pad oxide layer and a first pad nitride layer are formed on the substrate, and a well region is formed in the substrate, the well region extending from the surface of the substrate to the inside of the substrate;

[0014] The isolation trench extending to the inside of the substrate and the functional trench extending to the inside of the well region are etched synchronously on the substrate;

[0015] The isolation trench is subjected to deepening treatment.

[0016] Preferably, the step of deepening the isolation trench comprises:

[0017] The first pad nitride layer surface of the functional trench and the adjacent part is covered with a first protective material;

[0018] The isolation trench is subjected to deepening treatment.

[0019] Preferably, the region where the functional trench is formed is subjected to doping ion implantation, and the step of forming the MOS region comprises:

[0020] The isolation trench is filled with a second protective material until the surface of the first protective material is covered;

[0021] The first protective material and the second protective material are etched until the functional trench is completely exposed;

[0022] The region where the functional trench is formed is subjected to doping ion implantation to form the MOS region.

[0023] Preferably, the step of growing strain material in the strain-enhanced trench comprises:

[0024] The strain material is epitaxially grown in the strain-enhanced trench;

[0025] The residual second protective material is removed.

[0026] Preferably, the step of filling the isolation medium in the isolation trench and the strain-enhanced trench comprises:

[0027] The isolation medium is filled in the isolation trench and the strain-enhanced trench until the isolation medium covers the first pad nitride layer;

[0028] The isolation medium is subjected to planarization treatment until the isolation medium is flush with the first pad nitride layer;

[0029] removing the first pad nitride layer;

[0030] performing thinning treatment on the isolation medium and the first pad oxide layer until the isolation medium covering the strained material reaches a preset thickness.

[0031] Preferably, the height difference between the upper surface of the strained material and the upper surface of the substrate is taken as a self-alignment reference to form a dummy gate structure in the preset gate region of the MOS region, which specifically comprises:

[0032] forming a polysilicon layer, a medium protection layer and a carbon-based mask layer on the isolation medium and the first pad oxide layer in sequence;

[0033] planarizing the carbon-based mask layer to the surface of the medium protection layer, and the carbon-based mask layer after planarization treatment is located on both sides of the strained material;

[0034] taking the carbon-based mask layer after planarization treatment as a hard mask to etch and form a stack structure in all regions;

[0035] removing the excess carbon-based mask layer;

[0036] patterning the stack structure to form a dummy gate structure.

[0037] Preferably, when all the regions are formed into MOS regions, the step of patterning the stack structure to form a dummy gate structure comprises:

[0038] selectively protecting the stack structure of the MOS region, and removing the unprotected part of the stack structure;

[0039] taking the remaining stack structure as a hard mask to etch the polysilicon layer and form a dummy gate structure on the MOS region;

[0040] removing the hard mask to expose the dummy gate structure.

[0041] Preferably, when part of the regions are formed into the MOS region, the step of patterning the stack structure to form a dummy gate structure comprises:

[0042] selectively protecting the stack structure on the MOS region, and patterning the stack structure outside the MOS region;

[0043] removing the unprotected part of the stack structure;

[0044] taking the remaining stack structure as a hard mask to etch the polysilicon layer and form a dummy gate structure in the MOS region and the remaining region without the functional trench;

[0045] removing the hard mask to expose the dummy gate structure.

[0046] In another aspect, the application also provides a semiconductor device manufactured by the above-mentioned method.

[0047] The application has the following unexpected advantages:

[0048] Since the MOS region is formed first and the dummy gate structure is formed later, there is no need to reserve the oxide hard mask above the dummy gate structure after the formation of the dummy gate structure; in the subsequent dummy gate structure removal process, the chemical mechanical polishing process can be uniformly polished, avoiding the polishing rate difference caused by the uneven thickness of the oxide hard mask, thereby solving the "Loading" problem, improving the uniformity of the thickness of the protective layer of the dummy gate structure after polishing, and further improving the electrical performance and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 A schematic diagram of forming a well region on a substrate in an embodiment of the application;

[0050] Figure 2 A schematic diagram of simultaneously forming a first opening and a second opening in an embodiment of the application;

[0051] Figure 3 A schematic diagram of simultaneously forming an isolation trench and a functional trench in an embodiment of the application;

[0052] Figure 4 A schematic diagram of using a first protective material to protect the functional trench in an embodiment of the application;

[0053] Figure 5 A schematic diagram of deepening the isolation trench in an embodiment of the application;

[0054] Figure 6 A schematic diagram of using a second protective material to protect the isolation trench in an embodiment of the application;

[0055] Figure 7 A schematic diagram of etching the protective material and ion implantation in an embodiment of the application;

[0056] Figure 8 A schematic diagram of forming a strain-enhanced trench in an embodiment of the application;

[0057] Figure 9 A schematic diagram of epitaxial growth of a strain material in an embodiment of the application;

[0058] Figure 10 A schematic diagram of removing the second protective material in an embodiment of the application;

[0059] Figure 11 A schematic diagram of filling the isolation medium in an embodiment of the application;

[0060] Figure 12 FIG. 13 is a schematic diagram of the isolation medium after grinding in an embodiment of the present application;

[0061] Figure 13 FIG. 14 is a schematic diagram of the isolation medium and the first pad oxide layer after thinning in an embodiment of the present application;

[0062] Figure 14 FIG. 15 is a schematic diagram of the polysilicon layer, the second pad oxide layer, the second pad nitride layer, and the carbon-based mask layer after formation in an embodiment of the present application;

[0063] Figure 15 FIG. 16 is a schematic diagram of the stack structure after formation in an embodiment of the present application;

[0064] Figure 16 FIG. 17 is a schematic diagram of the carbon-based mask layer after removal in an embodiment of the present application;

[0065] Figure 17 FIG. 18 is a schematic diagram of the pseudo-gate structure pattern after formation in an embodiment of the present application;

[0066] Figure 18 FIG. 19 is a schematic diagram of the hard mask after formation in an embodiment of the present application;

[0067] Figure 19 FIG. 20 is a schematic diagram of the pseudo-gate structure after formation in an embodiment of the present application;

[0068] Figure 20 FIG. 21 is a schematic diagram of the medium protection layer after removal in an embodiment of the present application;

[0069] Figure 21 FIG. 22 is a schematic diagram of the protection layer of the pseudo-gate structure after formation in an embodiment of the present application;

[0070] Figure 22 FIG. 23 is a schematic diagram of the pseudo-gate structure after grinding in an embodiment of the present application. DETAILED DESCRIPTION

[0071] In order to make the objects, advantages and features of the present application clearer, the following will further describe the present application in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn according to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0072] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. As used in the present application, the term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. As used in the present application, the term "several" is generally employed in its sense of "at least one" unless the content clearly dictates otherwise. As used in the present application, the term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used merely to describe a particular feature and do not imply or suggest a relative importance or imply a number of the indicated technical features. Thus, features qualified with "first," "second," "third," etc. can expressly or implicitly include one or at least two of the features.

[0073] The embodiment of the present application provides a manufacturing method of a semiconductor device, comprising:

[0074] S101, providing a substrate 100, the substrate 100 comprises at least two regions separated by an isolation groove 105, and at least one region is formed with a functional groove 106;

[0075] S102, performing ion implantation on the region formed with the functional groove 106 to form a MOS region;

[0076] S103, forming a strain enhancement groove 109 in the functional groove 106;

[0077] S104, growing a strain material 110 in the strain enhancement groove 109, so that the upper surface of the strain material 110 is higher than the upper surface of the substrate 100;

[0078] S105, filling an isolation medium 111 in the isolation groove 105 and the strain enhancement groove 109;

[0079] S106, taking the height difference between the upper surface of the strain material 110 and the upper surface of the substrate 100 as a self-aligned reference to form a dummy gate structure in a preset gate region; the preset gate region is a spacing region on the substrate 100 of the MOS region between adjacent strain materials 110.

[0080] In some embodiments, the substrate 100 is a single crystal or a single crystal silicon substrate 100. The substrate 100 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), germanium silicon (GeSi), sapphire, silicon wafer, or other III / V compound semiconductor material, and also includes a laminated structure of these semiconductor materials, or a silicon-on-insulator, a silicon-on-laminated insulator, a silicon germanium-on-insulator, and a germanium-on-insulator, etc. More specifically, the substrate 100 is a silicon wafer semiconductor substrate 100.

[0081] In step S101, the formation of the isolation trench 105 and the functional trench 106 includes:

[0082] The substrate 100 is pre-processed so that the first pad oxide layer 101 and the first pad nitride layer 103 are formed on the substrate 100, and the well region 1011 is formed in the substrate 100 and extends from the surface of the substrate 100 to the inside of the substrate 100. The isolation trench 105 extending to the inside of the substrate 100 and the functional trench 106 extending to the inside of the well region 1011 are simultaneously etched on the substrate 100. The isolation trench 105 is deepened.

[0083] Optionally, in some embodiments, referring to Figure 1 The first pad oxide layer 101 can be formed on the substrate 100 first, then the well region 1011 is formed on the substrate 100, and finally the first pad nitride layer 103 is formed on the first pad oxide layer 101.

[0084] First, the first pad oxide layer 101 is formed on the substrate 100. The function of the first pad oxide layer 101 is to protect the surface of the substrate 100 from being contaminated or damaged in subsequent processes, and also to serve as a barrier layer for ion implantation to prevent dopants from penetrating the surface of the substrate 100. The thickness of the first pad oxide layer 101 is usually between tens of nanometers and hundreds of nanometers, and the specific thickness depends on the process requirements.

[0085] In some embodiments, the first pad oxide layer 101 is, for example, a dense silicon oxide, and the first pad oxide layer 101 can be formed by any one of the following methods, for example, dry oxygen oxidation, wet oxygen oxidation, or in-situ steam generation (ISSG). For example, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900-1000°C, oxygen is introduced, and the surface of the substrate 100 reacts with the oxygen at high temperature to form the first pad oxide layer 101, and the first pad oxide layer 101 formed has good quality. In some embodiments, the first pad oxide layer 101 is, for example, silicon oxide, and the thickness of the first pad oxide layer 101 is, for example, 30-60 nm, for example, 30 nm, 40 nm, 45 nm, or 50 nm.

[0086] Next, the first photoresist layer 102 is formed on the first pad oxide layer 101. The photoresist is uniformly coated on the surface of the first pad oxide layer 101 by using a spin coating method, and the solvent in the photoresist is removed by soft baking, and the photoresist is solidified. A mask pattern on a mask is transferred to the first photoresist layer 102 using a photoetching machine; the first photoresist layer 102 is irradiated by ultraviolet light or other light sources, so that the area on the substrate 100 where the well region 1011 needs to be formed is exposed, and the exposed first photoresist layer 102 is developed to remove the photoresist in the exposed area, thereby forming the desired pattern.

[0087] Finally, the well region 1011 with controllable doping concentration gradient is formed in the substrate 100 by ion implantation and annealing. The well region 1011 formed can be an N-type well region, a P-type well region, or both an N-type well region and a P-type well region. The corresponding type of impurities is directly implanted into the exposed area using an ion implanter, and after the implantation of the doping ions is completed, the substrate 100 after ion implantation is annealed by, for example, a rapid thermal processing (RTA) process or a process of repeatedly heating in a furnace tube, thereby forming the well region 1011 on the substrate 100. The dose and energy of the ion implantation can be adjusted according to the required depth and doping concentration of the well region 1011.

[0088] After the ion implantation and high-temperature annealing are completed, the first photoresist layer 102 is removed by a suitable process, thereby obtaining the desired well region 1011. Figure 1 In some embodiments, the well region 1011 formed is an N-type well region.

[0089] After the well region 1011 is obtained, the first pad nitride layer 103 is deposited on the first pad oxide layer 101.

[0090] The first pad nitrided layer 103 is, for example, silicon nitride SiNx or a stack of silicon nitride and silicon oxide. The first pad oxide layer 101 can improve the stress between the substrate 100 and the first pad nitrided layer 103 as a buffer layer. The first pad nitrided layer 103 can be formed on the first pad oxide layer 101 by, for example, a low pressure chemical vapor deposition (LPCVD) method. Specifically, the substrate 100 with the first pad oxide layer 101 is placed in a furnace tube filled with dichlorosilane and ammonia, and reacts at a pressure of, for example, 2-10 Torr and a temperature of, for example, 700-800 °C to deposit the first pad nitrided layer 103. The thickness of the first pad nitrided layer 103 can be adjusted by controlling the heating time.

[0091] The first pad nitrided layer 103 can protect the substrate 100 from the chemical mechanical polishing process involved in the manufacturing process of the shallow trench isolation structure. In the subsequent trench forming process, the first pad nitrided layer 103 can act as a mask to protect other parts of the substrate 100 from being damaged during etching of the substrate 100.

[0092] In other embodiments, the first pad oxide layer 101 and the first pad nitrided layer 103 can also be formed by first forming the well region 1011 in the substrate 100. For example, a first photoresist layer 102 is first formed on the substrate 100, an opening is formed in the first photoresist layer 102, and ion implantation is then performed at the opening to form the well region 1011. After removing the first photoresist layer 102, the first pad oxide layer 101 and the first pad nitrided layer 103 are sequentially formed on the substrate 100.

[0093] To simultaneously etch the isolation trench 105 and the functional trench 106, the etching opening of the isolation trench 105 and the functional trench 106 needs to be defined on the first pad nitrided layer 103 by a single photolithography process. In combination with Figure 2 , a second photoresist layer 104 is coated on the first pad nitrided layer 103 by spin coating, and the photoresist layer is cured by soft baking to remove the solvent in the photoresist layer. Then, the shallow trench isolation region pattern and the MOS region pattern on the mask plate are transferred to the second photoresist layer 104 by a photolithography machine. The second photoresist layer 104 is irradiated by ultraviolet light or other light sources to expose the region where the opening needs to be formed. After exposure, the photoresist layer in the exposed region is removed by a developing process to form the first opening 1041 defining the isolation trench 105 and the second opening 1042 defining the functional trench 106. The second opening 1042 is opposite to the well region 1011 on the substrate 100.

[0094] The above steps can form the first opening 1041 defining the isolation trench 105 and the second opening 1042 defining the functional trench 106 simultaneously through a single photolithography process, thereby reducing the photolithography steps and saving a mask.

[0095] After the etching opening is formed, the first pad nitride layer 103 is used as an etching stop layer to synchronously etch the exposed region of the etching opening, for example, through dry etching, wet etching or other etching methods, to form the isolation trench 105 extending into the substrate 100 and the functional trench 106 extending into the well region 1011.

[0096] More specifically, the isolation trench 105 and the functional trench 106 can be formed through dry etching, and the etching gas can be one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), or a combination of the above and oxygen (O2); for reference Figure 3 The first pad nitride layer 103, the first pad oxide layer 101 and part of the substrate 100 exposed by the first opening 1041 are removed through dry etching with the second photoresist layer 104 as a mask to form the isolation trench 105; the first pad nitride layer 103, the first pad oxide layer 101 and part of the well region 1011 exposed by the second opening 1042 are removed to form the functional trench 106.

[0097] The etching depth of the isolation trench 105 is set to be between several hundred nanometers and several microns, and the specific depth depends on the design requirements of the device; the shape of the isolation trench 105 is, for example, rectangular or trapezoidal, to ensure good planarization when filling the isolation medium 111 later. The etching depth of the functional trench 106 is the same as that of the isolation trench 105, to ensure that the depths of the two trenches are consistent; the functional trench 106 extends into the well region 1011, for forming the source and drain regions of the MOS region later; the shape and size of the functional trench 106 are also optimized according to the design requirements of the MOS region, to ensure the electrical performance of the device.

[0098] The simultaneous formation of the isolation trench 105 and the functional trench 106 reduces the process steps, improves the efficiency, and ensures the accurate alignment of the MOS region and the shallow trench isolation region.

[0099] After the isolation trench 105 and the functional trench 106 are formed simultaneously, the substrate 100 is divided into at least two regions by the isolation trench 105, and the functional trench 106 is formed in part or all of the regions.

[0100] After the isolation trench 105 and the functional trench 106 are etched, the second photoresist layer 104 is removed, for example, using a wet removal process, exposing the surface of the first pad nitride layer 103 and the formed trenches. The isolation trench 105 and the functional trench 106 are formed through a single photolithography process and simultaneous etching, reducing one photolithography step, simplifying the process flow, improving the alignment accuracy of the two trenches, and avoiding alignment deviations caused by multiple etching steps.

[0101] After the isolation trench 105 and the functional trench 106 are formed, the process of deepening the isolation trench 105 includes:

[0102] refer to Figure 4 First, a first protective material 107 is used to cover the functional trench 106 and the surface of the adjacent portion of the first pad nitride layer 103 to protect the MOS region to be formed. The first protective material 107 is, for example, photoresist (PR), to ensure good protective performance in subsequent processing; more specifically, the photoresist is precisely applied to the surface of the functional trench 106 and the surface of the first pad nitride layer 103 on both sides of the functional trench 106 through coating, exposure, and development processes.

[0103] In this embodiment, the photomask used during the exposure process to form the first protective material 107 can be used with... Figure 1 The photomasks used in the exposure process that forms the first photoresist layer 102 share the same solid photomask; the only difference is between the first protective material 107 and... Figure 1 The first photoresist layer 102 in the process uses different types of photoresist. For example, positive photoresist development is used in the process of forming the first photoresist layer 102, and negative photoresist development is used in the process of forming the first protective material 107, thereby reducing process costs.

[0104] Because the first pad nitride layer 103 has high resistance to etching processes, it can protect areas that do not need to be etched during subsequent etching processes. After photoresist patterning, the areas not covered by the first protective material 107 will use the first pad nitride layer 103 as a hard mask during etching.

[0105] Reference Figure 5 Using the first pad nitride layer 103 as a mask, the area not covered by the first protective material 107 is etched. The etching process removes part of the first pad nitride layer 103 and part of the substrate 100 inside the isolation trench 105 until the isolation trench 105 reaches the required depth to form a trench isolation area. These formed trench isolation areas will be used to isolate different device areas to prevent electrical interference.

[0106] More specifically, when etching, a suitable dry etching process is selected to further deepen the isolation trench 105, for example, using plasma etching to ensure uniformity and consistency of etching. According to design requirements, parameters such as etching time, gas flow, pressure and power are set to ensure that the depth of the isolation trench 105 reaches a predetermined value. For example, one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), or a combination of them and oxygen (O2) are used.

[0107] After completing the deepening of the isolation trench 105, step S102 is performed.

[0108] In step S102, the second protective material 108 is used to fill the isolation trench 105 until the surface of the first protective material 107 is covered. For example, a UL material (Under Layer) or a SOC material (Spin-On Carbon) with high flowability is selected as the second protective material 108; these materials have good flowability and uniformity, and can effectively cover the entire wafer surface; then, the UL material or the SOC material is uniformly coated on the entire wafer surface using a spin coating method; the spin coating method can ensure uniform distribution of the material, especially on the trench and other complex structures; and by controlling and adjusting the spin coating parameters (such as spin coating speed, time, etc.), it is ensured that the UL material or the SOC material can sufficiently fill the isolation trench 105 and cover the first protective material 107 and the remaining portion of the first pad nitride layer 103 that is not covered by the first protective material 107, such as Figure 6 The coated UL material or SOC material is subjected to a curing process; the curing process includes baking at a specific temperature to remove solvents and solidify the material. The cured UL material or SOC material should have good adhesion and chemical stability to effectively protect the trench isolation area and other areas.

[0109] After the second protective material 108 is protected, referring to Figure 7 The first protective material 107 and the second protective material 108 are etched until the functional trench 106 is completely exposed. Alternatively, an etch-back process (EBP) is used to etch the isolation trench 105 and the functional trench 106; the etch-back gas is selected from chlorine (Cl2), nitrogen trifluoride (NF3) and trifluoromethane (CHF3), etc.

[0110] After the etch-back of the first protective material 107 and the second protective material 108 is completed, the upper surface of the second protective material 108 is lower than the upper surface of the first pad oxide layer 101; the first protective material 107 is completely etched back to expose the functional trench 106.

[0111] After the surface of the functional trench 106 is completely exposed, the region where the functional trench 106 is formed is subjected to a doping ion implantation to form a MOS region. By directly performing the doping ion implantation using the first pad nitride layer 103 that has been formed as a natural mask without an additional photoresist mask, damage to the first pad oxide layer 101 in a photoresist ashing process can be avoided, and the integrity of the first pad oxide layer 101 is protected.

[0112] When the doping ion implantation is performed in the functional trench 106, the doping ion implantation process is, for example, a Lightly Doped Drain (LDD) ion implantation process. The purpose of the ion implantation is to form a lightly doped drain region to improve the electrical performance of the device; by selecting appropriate ion implantation parameters (such as ion species, energy, dose, etc.), the ion implantation is ensured to be performed only in the predetermined region.

[0113] In S103, the functional trench 106 is etched to form a trench profile with strain enhancement characteristics, and a strain-enhanced trench 109 is obtained.

[0114] For example, the functional trench 106 is etched using a wet TMAH etching process. Since the crystal orientation of the substrate 100 is 100, a V-shaped profile shape as shown in the figure is formed. Figure 8

[0115] In step S103, as shown in the figure, Figure 9 The strain material 110 is epitaxially grown in the processed strain-enhanced trench 109. The strain material 110 is composed of, for example, silicon germanium (SiGe) or other materials with strain characteristics, which can introduce strain without changing the lattice structure of the substrate 100, thereby improving the performance of the device. Alternatively, a layer of Ge is epitaxially grown in the strain-enhanced trench 109, for example, using chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable epitaxial growth techniques, so that the Ge epitaxy forms a layer of SiGe material at the exposed Si location.

[0116] After the growth of the strain material 110 is completed, the excess second protective material 108 is removed, for example, using a dry etching process, as shown in the figure. Figure 10

[0117] In step S104, the isolation trench 105 and the strain-enhanced trench 109 are first filled with an isolation medium 111. For example Figure 11 ​​In the present embodiment, the isolation medium 111 is filled in the isolation trench 105 and the functional trench 106 by using oxide (OX), silicon dioxide (SiO2) or other suitable insulating material as the insulating medium, and by using plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD) until the surface of the first pad nitride layer 103 is completely covered.

[0118] Then, the excess isolation medium 111 is removed by using chemical mechanical polishing technology. Since the polishing rate of the first pad nitride layer 103 is slow, the polishing of the isolation medium 111 will eventually stop at the surface of the first pad nitride layer 103, i.e. the isolation medium 111 will eventually cover the surface of the first pad nitride layer 103.

[0119] Next, the first pad nitride layer 103 is removed, for example, by using a wet etching process or a dry etching process, as shown in FIG. 1C. Figure 12 .

[0120] After the first pad nitride layer 103 is removed, the isolation medium 111 and the first pad oxide layer 101 are thinned until the isolation medium 111 covering the surface of the strain material 110 reaches a predetermined thickness, so that a height difference is formed between the upper surface of the isolation medium 111 above the strain material 110 and the upper surface of the first pad oxide layer 101 above the substrate 100, and the height difference is equal to the height difference formed between the upper surface of the strain material 110 and the upper surface of the substrate 100. Specifically, the first pad oxide layer 101 and the isolation medium 111 are etched by using a dry etching process, and the thickness of the remaining first pad oxide layer 101 is adjusted according to the etching amount, and the remaining isolation medium 111 is able to protect the surface of the strain material 110, and since the etching rate is the same at different positions, the height difference left by the previous process will be retained after etching, as shown in FIG. 1D. Figure 13 .

[0121] By retaining the partial thickness of the isolation medium 111 and the first pad oxide layer 101, a height difference is formed between the upper surface of the isolation medium 111 above the strain material 110 and the upper surface of the first pad oxide layer 101 above the substrate 100 as a self-alignment reference, and this design enables the subsequent stack structure to be accurately aligned with this height difference as the reference.

[0122] In step S105, as shown in FIG. 1E, a polysilicon layer 112, a medium protection layer and a carbon-based mask layer 115 are sequentially formed on the thinned first pad oxide layer 101 and the isolation medium 111, with the height difference formed between the upper surface of the isolation medium 111 above the strain material 110 and the upper surface of the first pad oxide layer 101 above the substrate 100 as the self-alignment reference. Figure 14 .

[0123] Optionally, the medium protection layer comprises, for example, a second pad oxide layer 113 and a second pad nitride layer 114 deposited on the polysilicon layer 112 in sequence. The polysilicon layer 112 is deposited on the thinned first pad oxide layer 101 and the isolation medium 111 using, for example, a low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition technique, the second pad oxide layer 113 is deposited on the polysilicon layer 112 using a chemical vapor deposition technique, the second pad nitride layer 114 is deposited on the second pad oxide layer 113 using a low-pressure chemical vapor deposition technique, and the carbon-based mask layer 115 is deposited on the second pad nitride layer 114 using a chemical vapor deposition technique.

[0124] Next, the carbon-based mask layer 115 is subjected to a planarization process until it is flush with the medium protection layer, and the planarized carbon-based mask layer 115 is located on both sides of the strained material 110. For example, the carbon-based mask layer 115 is ground using chemical mechanical grinding until the carbon-based mask layer 115 and the medium protection layer are flush.

[0125] The carbon-based mask layer 115 after grinding can be used as a mask, and the position of this mask is directly aligned on both sides of the strained material 110, which can reduce the etching deviation caused by uneven mask material.

[0126] Thereafter, referring to Figure 15 The carbon-based mask layer 115 after planarization is used as a mask to define the etching amount of the polysilicon layer 112, and part of the medium protection layer and part of the polysilicon layer 112 are etched away using, for example, a dry etching process to form a stack structure. The carbon-based mask layer 115 has high hardness and uniformity, which can provide more precise control during etching.

[0127] By using a self-alignment technique, the stack structure is formed on both sides of the MOS region from the most accurate, avoiding the problem of abnormal electron migration caused by abnormal alignment of the pseudo-gate structure in the process of first forming the MOS region and then forming the pseudo-gate structure; and this self-alignment technique ensures the accuracy and consistency of etching, while reducing the process steps. Moreover, by using the carbon-based mask layer 115 as a mask, etching can be directly performed on the existing structure without the need for additional photolithography steps, further reducing the use of one photomask.

[0128] Next, the excess carbon-based mask layer 115 is removed. For example, the excess carbon-based mask layer 115 is removed using dry etching, such as Figure 16 .

[0129] Finally, the stack structure is patterned to form a pseudo-gate structure.

[0130] Optionally, when all the regions separated by the isolation groove 105 are formed with the functional groove 106, all the regions will form MOS regions after the ion implantation. At this time, in order to form the pseudo-gate structure, it is necessary to selectively protect the stack structure of each MOS region, for example, coating photoresist on the surface of the stack structure adjacent to the strain-enhanced groove 109, and defining the position of the pseudo-gate structure on the photoresist through a photolithography process.

[0131] Optionally, when part of the regions separated by the isolation groove 105 are formed with the functional groove 106, the part of the regions will form MOS regions after the ion implantation. It is necessary to coat photoresist on the surface of the stack structure adjacent to the strain-enhanced groove 109 in the MOS region, so as to selectively protect the stack structure of the MOS region; at the same time, it is also necessary to coat photoresist on the specific position in the remaining region, so as to pattern the stack structure of the remaining region; and it is also necessary to coat photoresist on the surface of part of the polysilicon layer 112 corresponding to the isolation groove 105, so as to protect the structure of the formed isolation groove 105. After these operations, the third photoresist layer 116 in Figure 17 is formed.

[0132] Next, the excess stack structure is etched to form a hard mask. Specifically, referring to Figure 18 , the excess stack structure is etched by dry etching, so that the remaining dielectric protection layer forms a hard mask.

[0133] Then, the polysilicon layer 112 is etched to form a pseudo-gate structure. For example, referring to Figure 19 , the pseudo-gate structure is formed by using the dielectric protection layer as a hard mask and using dry etching for pseudo-gate cutting etching; wherein the cutting position of the pseudo-gate is perpendicular to the direction of the pseudo-gate.

[0134] Next, the dielectric protection layer as a hard mask is removed, and the pseudo-gate structure is released. Specifically, referring to Figure 20 , at this time, the second pad nitride layer 114 and the second pad oxide layer 113 at the top position of the pseudo-gate structure are removed by using a wet etching process or a dry etching process.

[0135] Since the MOS region has been formed in step S103 in the present application, after the pseudo-gate structure is formed in S106, it is not necessary to use the material layer on the pseudo-gate structure as a hard mask for the strain material epitaxial growth of the trench in the MOS region; therefore, before the pseudo-gate structure is removed, the second pad nitride layer 114 and the second pad oxide layer 113 on the pseudo-gate structure can be removed first, so that the subsequent chemical mechanical polishing process can be uniformly polished, and the polishing rate difference caused by the uneven thickness of the hard mask on the pseudo-gate structure can be avoided, thereby avoiding the “Loading” effect and improving the performance of the device.

[0136] After the dummy gate structures are formed in S106, the following steps are performed. Figure 21 A protective layer is formed on the dummy gate structures. For example, a layer of oxide (e.g., silicon dioxide SiO2) is deposited on the surface of the dummy gate structures using chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) technology, and a layer of nitride (e.g., silicon nitride SiN) is deposited on the surface of the dummy gate structures using low pressure chemical vapor deposition (LPCVD) technology to form a sidewall spacer.

[0137] Then, ion implantation is performed on the regions other than the MOS regions, so that the regions other than the MOS regions also form MOS regions. After all the regions on the substrate 100 form MOS regions, a chemical mechanical polishing process is performed. Referring to Figure 22 After the other MOS regions are formed, the chemical mechanical polishing process is performed, and the dummy gate structures are uniformly polished, so that the subsequent dummy gate structure removal process is easier.

[0138] The embodiments of the present application also provide a semiconductor device manufactured by the method for manufacturing a semiconductor device as described above.

[0139] The above description of the disclosed embodiments (including that in the summary) is not meant to limit or restrict the scope of the application, but is to provide examples for the practice of the application. The scope of the application is defined by the claims. The description of the embodiments of the application is merely exemplary in nature and, thus, variations that do not depart from the essence of the application are intended to be within the scope of the application. Such variations are not to be regarded as a departure from the spirit and scope of the application.

[0140] The above description is merely exemplary of the application and the application is not limited to the specific examples described. The application is intended to cover any variations within the scope of the application, which is defined by the claims. The claims are intended to cover the equivalent of the specific examples described, and modifications that do not depart from the spirit and scope of the application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate (100), the substrate (100) comprising at least two regions separated by an isolation trench (105), a functional trench (106) being formed in at least one of the regions; performing ion implantation on the region where the functional trench (106) is formed to form a MOS region; forming a strain-enhanced trench (109) in the functional trench (106); growing a strain material (110) in the strain-enhanced trench (109), so that the upper surface of the strain material (110) is higher than the upper surface of the substrate (100); filling an isolation medium (111) in the isolation trench (105) and the strain-enhanced trench (109); forming a dummy gate structure in a preset gate region by using the height difference between the upper surface of the strain material (110) and the upper surface of the substrate (100) as a self-aligned reference; the preset gate region is a spacing region between adjacent strain materials (110) on the substrate (100) of the MOS region; forming a dummy gate structure in the preset gate region of the MOS region by using the height difference between the upper surface of the strain material (110) and the upper surface of the substrate (100) as a self-aligned reference specifically comprises: forming a polycrystalline silicon layer (112), a medium protection layer and a carbon-based mask layer (115) on the isolation medium (111) and the substrate (100) after thinning treatment in sequence on the first pad oxide layer (101) after thinning treatment; planarizing the carbon-based mask layer (115) to the surface of the medium protection layer, and the carbon-based mask layer (115) after planarization treatment is located on both sides of the strain material (110); using the carbon-based mask layer (115) after planarization treatment as a hard mask to etch and form a stack structure in all regions; removing the excess carbon-based mask layer (115); patterning the stack structure to form a dummy gate structure.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The forming process of the isolation trench (105) and the functional trench (106) comprises: preprocessing the substrate (100) so that a first pad oxide layer (101) and a first pad nitride layer (103) are formed on the substrate (100), and a well region (1011) is formed in the substrate (100) and extends from the surface of the substrate (100) to the inside of the substrate (100); simultaneously etching the isolation trench (105) extending to the inside of the substrate (100) and the functional trench (106) extending to the inside of the well region (1011) on the substrate (100); deepening the isolation trench (105).

3. The method of manufacturing a semiconductor device according to claim 2, wherein The step of deepening the isolation trench (105) comprises: covering the functional trench (106) and the surface of the first pad nitride layer (103) adjacent to the functional trench (106) with a first protection material (107); deepening the isolation trench (105).

4. The method of manufacturing a semiconductor device according to claim 3, wherein The step of performing ion implantation on the region where the functional trench (106) is formed to form a MOS region comprises: filling the isolation trench (105) with a second protective material (108) until the surface of the first protective material (107) is covered; etching the first protective material (107) and the second protective material (108) until the functional trench (106) is completely exposed; forming MOS regions by ion implantation in the regions where the functional trench (106) is formed.

5. The method of manufacturing a semiconductor device according to claim 4, wherein The step of growing a strain material (110) in the strain enhancement trench (109) includes: epitaxially growing a strain material (110) in the strain enhancement trench (109); removing the residual second protective material (108).

6. The method of manufacturing a semiconductor device according to claim 2 or 5, wherein The step of filling the isolation trench (105) and the strain enhancement trench (109) with an isolation medium (111) includes: filling the isolation trench (105) and the strain enhancement trench (109) with an isolation medium (111) until the isolation medium (111) covers the first pad nitridation layer (103); planarizing the isolation medium (111) until the isolation medium (111) is flush with the first pad nitridation layer (103); removing the first pad nitridation layer (103); thinning the isolation medium (111) and the first pad oxidation layer (101) until the isolation medium (111) covering the strain material (110) reaches a preset thickness.

7. The method of manufacturing a semiconductor device according to Claim 1, wherein When all the regions are formed into MOS regions, the step of patterning the stack structure to form a pseudo-gate structure includes: selectively protecting the stack structure of the MOS regions and removing the unprotected part of the stack structure; using the remaining stack structure as a hard mask to etch the polysilicon layer (112) to form a pseudo-gate structure on the MOS regions; removing the hard mask to expose the pseudo-gate structure.

8. The method of manufacturing a semiconductor device according to Claim 1, wherein When part of the regions are formed into the MOS regions, the step of patterning the stack structure to form a pseudo-gate structure includes: selectively protecting the stack structure on the MOS regions and patterning the stack structure outside the MOS regions; removing the unprotected part of the stack structure; using the remaining stack structure as a hard mask to etch the polysilicon layer (112) to form a pseudo-gate structure outside the MOS regions; removing the hard mask to expose the pseudo-gate structure.

9. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by using the manufacturing method of the semiconductor device according to any one of claims 1-8. The semiconductor device is manufactured by using the manufacturing method of the semiconductor device according to any one of claims 1-8.

Images