Flexible SRAM precharging system and method

Abstract

Embodiments of the present disclosure include techniques for pre-charging an SRAM. The pre-charge signal may be used to apply the pre-charge signal to a bit line in an SRAM memory bank. Features and advantages of the present disclosure include receiving a pre-charge signal in an SRAM and storing the pre-charge signal. The pre-charge signal may be received and stored during a period in which the SRAM is performing memory access. The stored pre-charge signal may be applied during a later period. In some embodiments, the SRAM is divided into a plurality of sub-banks, and a plurality of pre-charge signals are received and stored for different sub-banks. For example, the stored pre-charge signal may be applied individually to different sub-banks.

Description

BACKGROUND

[0001] The present disclosure relates generally to computing, and in particular, to flexible static random access memory (SRAM) precharge systems and methods.

[0002] SRAM memory typically precharges its bit lines to a high voltage state before read or write accesses can proceed. When the bit lines of an SRAM are in a precharge state, the SRAM will typically exhibit higher leakage power compared to a non-precharge state. In addition, a number of large drivers within the SRAM, such as word line drivers, contribute a significant amount of the overall SRAM leakage power. To improve power consumption in designs that use SRAM, it is desirable to minimize the time that the SRAM is in a high leakage state. BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 An SRAM is shown in accordance with an embodiment.

[0004] Figure 2 A method of precharging an SRAM is shown in accordance with an embodiment.

[0005] Figure 3 SRAM precharge is shown in accordance with another embodiment.

[0006] Figure 4 An SRAM circuit arrangement is shown in accordance with an embodiment.

[0007] Figure 5 An SRAM layout is shown in accordance with an embodiment.

[0008] Figure 6 An SRAM timing diagram is shown.

[0009] Figure 7 Another SRAM timing diagram is shown.

[0010] Figure 8 Yet another SRAM timing diagram is shown. DETAILED DESCRIPTION

[0011] Techniques for precharging an SRAM are described herein. In the following description, for the purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of some embodiments. Embodiments as defined by the appended claims can individually, or in combination with other features described below, include some or all of the features in these examples, and can also include modifications and equivalents of the features and concepts described herein.

[0012] Features and advantages of the present disclosure include a dynamic explicit precharge scheme for use on SRAM while allowing the system to initiate a precharge request to the SRAM while a previous access is currently in progress within the SRAM. This results in reduced leakage power without adding additional latency to the SRAM access. The techniques described herein can be used with or without grouping the SRAM into "banks" to enable parallelism as described below.

[0013] In some embodiments, the SRAM includes circuitry to (1) pipeline the precharge / SRAM access cycle and (2) determine whether to place the SRAM in a low leakage state after the current access or to keep the SRAM in a precharged state in preparation for the next access. A precharge request can be provided to the SRAM for one or more cycles prior to the SRAM access. However, during the SRAM access, a new precharge request for the next access can be provided to the SRAM (e.g., pipelined precharge feature). In some embodiments, the SRAM can also determine whether to keep the head / tail voltages on and precharge the bitlines after the current access or to turn off the head / tail voltages and not precharge the bitlines after the current access in order to place the SRAM in a low leakage state. These techniques provide a flexible solution in that the SRAM can dynamically keep the precharge input active at all times or explicitly precharge as needed without incurring additional performance loss due to precharge.

[0014] Additionally, in some embodiments, the SRAM allows for dynamic precharge of select memory sub-banks of the SRAM, enabling finer grained precharge. Further, for example, a precharge reset input (e.g., precharge reset all) can be provided in the SRAM that clears the SRAM bitlines of precharge for all sub-banks, and in some embodiments, the pipelined precharge request within the SRAM is also so cleared.

[0015] Figure 1An SRAM 101 according to an embodiment is shown. The SRAM 101 includes an SRAM memory bank 111 and an SRAM access control circuit 110. The SRAM memory bank 111 is configured to store data bits 120 (e.g., using CMOS transistors configured as latches) and includes a plurality of bit lines 121 (e.g., typically 2 bit lines - BL and BL*). The SRAM access control circuit 110 is configured with digital logic circuitry for performing operations on the SRAM memory bank 111, such as reading and writing data to and from the array of bit cells in the memory bank 111. Advantageously, the SRAM access control circuit 110 is coupled to the plurality of bit lines 121 of the SRAM memory bank 111 to pre-charge the plurality of bit lines 121 to access the stored data bits 120. The SRAM access control circuit 110 receives and stores a pre-charge signal 112. This pre-charge signal 112 can be stored to pre-charge the bit lines for a subsequent cycle while the SRAM access control circuit 110 is accessing the stored data bits 120 in the SRAM memory bank in a current cycle.

[0016] Accordingly, the SRAM circuit can include a pre-charge request input (pre-charge input) that receives a pre-charge signal. For example, the pre-charge signal can be a digital signal and, in various embodiments, can include one bit or multiple bits. For example, using the pre-charge signal, the SRAM can issue a pre-charge request when an SRAM access (e.g., a read or write) is in progress.

[0017] For example, the SRAM access control circuit 110 can receive and store the pre-charge signal 112 to implement any of the following scenarios. The pre-charge signal can cause the plurality of bit lines to be pre-charged when the SRAM access control circuit is not accessing the stored data bits in the SRAM memory bank in a current cycle. Similarly, the pre-charge signal can be stored in the SRAM access control circuit when the SRAM access control circuit is accessing the stored data bits in the SRAM memory bank in a current cycle to automatically pre-charge the plurality of bit lines when the current memory access is completed. Alternatively, the SRAM access control circuit does not pre-charge the bit lines when the pre-charge signal indicates that there is no pre-charge for a subsequent cycle when the current memory access is completed. Further, the SRAM access control circuit can also turn off one or more head switches that provide power to the plurality of word lines when the pre-charge signal indicates that there is no pre-charge for a subsequent cycle when the current memory access is completed. Examples of head switches are also described below.

[0018] Figure 2A method of precharging SRAM is shown, according to an embodiment. At 201, data bits are stored in an SRAM bank comprising a plurality of bit lines. At 202, a precharge signal for a subsequent cycle is received and stored by the SRAM access control circuit while the SRAM access control circuit is accessing the stored data bits in the SRAM bank in a current cycle. At 203, based on the precharge signal, the bit lines are precharged by the SRAM access control circuit to access the stored data bits of the SRAM bank.

[0019] Figure 3 SRAM precharge is shown, according to another embodiment. During cycle 0 301, upstream logic 302 in the system can cause a precharge signal to be generated, at 303. For example, the upstream logic can correspond to an upcoming memory read or write. The precharge signal 304 is coupled to the SRAM 309, which indicates that a precharge will occur in a subsequent cycle. The SRAM 309 can perform a process of another read or write at the same time that the precharge signal is received. For example, the SRAM 309 can store the precharge signal for use in a later cycle. For example, during cycle 1 305, information for performing an operation, such as an address, a write command (for a write), read / write control signals, and a memory enable signal, can be provided to the SRAM. During cycle 2, the memory access operation is performed in the current cycle (cycle 2) using the precharge signal received in the previous cycle.

[0020] Figure 4 SRAM circuitry is shown, according to an embodiment. The example schematic shows an SRAM access control circuit 401, a word line driver portion 490, and a column 491 of a memory bank comprising bit line pairs (BL / BL*) and corresponding bit cells 460a-460x. In this example, the precharge signal comprises a 4-bit digital signal (“precharge<3:0>”) for precharging 4 respective sub-banks of a 4-partition memory, as will be explained below. It will be understood that other memory partitions can be used in other embodiments. For example, the precharge bits can be stored in flip-flops (e.g., set-reset flip-flops) 430-433 and coupled to precharge outputs (“precharge outputs*”, active low) that are coupled to specific bit lines.

[0021] This example shows two bit lines 450 to 451 coupled to a plurality of bit cells 460a to 460x. For example, bit cell 460a includes cross-coupled inverters 410 to 411, which are coupled to bit lines 450 to 451 through NMOS transistors 412 to 413, which are controlled by word line inputs wL0 to wLx. Each inverter may include two transistors. Thus, Figure 4 The bit cell in FIG4 is an example of a 6-transistor (6T) bit cell. In this example, the precharge output of the SRAM access control circuit 401 is coupled to the gates of PMOS transistors 420 to 421, which are coupled between the bit lines 450 to 451 and the power supply voltage Vdd. When the precharge output *499 is high (not activated), the PMOS transistors 420 to 422 are turned off and the bit lines are floating. However, during precharge, the precharge output *499 is low (activated) and the PMOS transistors 420 to 422 are turned on to connect the bit lines 450 to 451 together and to Vdd, thereby precharging the bit lines before applying the word line input (when precharge is turned off).

[0022] Figure 4 Another aspect of the present disclosure is also shown. The SRAM may include a wordline driver section 490 that includes inverter-configured transistors for each wordline (e.g., 403 / 404 and 405 / 406), which are coupled to Vdd via the header switch transistor 402. Advantageously, the header switch can be turned off when access is not occurring to further reduce leakage and power consumption. Thus, the same precharge signal used to control precharge can be used to control the header switch to further improve the performance of the memory circuit.

[0023] exist Figure 4 In the example in FIG, the SRAM access control circuit 401 also includes a precharge reset input. The precharge reset can be used to clear the precharge on multiple bit lines. In some embodiments, the precharge reset input can also clear the precharge signal stored in the SRAM access control circuit (e.g., in FF). In some embodiments, the precharge reset input also turns off one or more head switches that provide power to multiple word lines (e.g., deactivates "head enable").

[0024] Figure 5 An SRAM layout according to an embodiment is shown. In various embodiments, an SRAM memory bank may be partitioned into multiple sub-banks. Figure 5A partition is shown that includes four (4) sub-banks 510, 511, 512, and 513. A local data input / output bus (LDIO) runs between sub-banks 510 and 511, and an LDIO bus runs between sub-banks 512 and 513. Thus, these banks are shown as 510a to 510b, 511a to 511b, 512a to 512b, and 513a to 513b (on either side of each LDIO). SRAM access control circuitry can be configured at 550, for example. Word line drivers and head switches can be configured in the layout shown at 520 and 521, for example. In this example, the control circuitry can include a 4-bit digital pre-charge signal and 4 pre-charge output signals to activate bit lines in different sub-banks 510 to 513, for example. In some embodiments, multiple pre-charge voltages can be independently applied within a sub-bank.

[0025] Figure 6 An SRAM timing diagram is shown. The following example uses a 6-transistor (6T) bitcell shown above. A 6T SRAM memory can use column multiplexing, such as 4-to-l or 8-to-l. Typically, only one set of bit lines (such as 1 of 4 or 1 of 8) is being used during a memory operation for a given I / O column of the memory. The other unused bit line sets with corresponding active word lines will have the true or complementary side of the bit line (BL, BL*) discharged by the bitcell, but the values for these bit lines can not be used (e.g., referred to as “dummy reads”). Prior to an SRAM memory access, the bit lines are pre-charged before the word lines are activated. During the SRAM idle / ready state, all word lines are inactive, and the bit lines can be pre-charged in preparation for the next memory operation. However, the bit lines can also be floating in the idle state to reduce leakage, as long as the bit lines are pre-charged prior to the next memory access. During a memory access, the word lines are activated, and the bit lines are driven to a logic 0 state or a logic 1 state. For a read or dummy read, the true or complementary bit line is driven to logic “0” by the memory bitcell. The other bit lines start from a pre-charged logic “1” state, and then are initially held at logic “1” state by the bit line capacitance, and then are held at a “weak 1” state by the bitcell, as the bitcell only drives a “weak 1” through the NMOS access transistor. For a write operation, the bit lines are driven to a logic 0 or logic 1 state by a write driver (not shown) coupled to the bit line.

[0026] Referring to Figure 6 Pre-charge set bank <x>The input remains valid. In idle, the bit line is pre-charged (valid pre-charge sets the bank <x>Enabling internal precharge on a row address latch library <x>Will be effective). When SRAM is being accessed (e.g. wordline is open), bitline precharge is turned off, and bitlines are being driven to logic 0 / 1. After access, bitlines are precharged because internal precharge enable row address latches <x>are valid.

[0027] Figure 7 Another SRAM timing diagram is shown. In this example, precharge occurs at least one cycle before a memory access. For example, precharge can occur 2, 3, or 1 cycle before a memory access cycle, or more generally, precharge can occur N cycles before a memory enable cycle, where N is any integer greater than or equal to 1. After precharge is set bank valid using the rising edge of the clock (clk), the corresponding bit line is precharged. At the clk rising edge, because precharge is not set bank valid at these cycles, the bit line is not precharged. At the clk falling edge, because precharge is set bank valid at these cycles, the bit line is precharged. At the clk rising edge, because precharge is not set bank valid at these cycles, the bit line is not precharged. At the clk falling edge, because precharge is set bank valid at these cycles, the bit line is precharged. <x>effective, and the memory enables an effective internal precharge enable row address latch library <x>Reset to logic 0. When SRAM is active (e.g., when the word line is open), the bit line is being driven to logic 0 / 1. After access, the internal pre-charge enable row address latch bank <x>fail, and the bit line is floating.

[0028] Figure 8 Another SRAM timing diagram is shown. This example shows precharge for two consecutive memory accesses. For example, 3 time periods 801, 802, and 803 show input (clk, memory enable, address <11:10>, and precharge set bank <x>) how to affect the output of the internal flip-flops (internal precharge enable row address latch bank <x>), the trigger can be a reset / set trigger. In this particular example, each memory access takes two cycles. Thus, there are three ways to make the "precharge set bank" input valid while a memory access is occurring. At the clock rising edge with memory enable active, if the precharge set bank <x>Also valid, the corresponding internal precharge enable row address latch library <x>maintained active (801 and 803); otherwise the corresponding internal precharge enable row latch bank will be made inactive <x>Failure (802; failure between two clock cycles with valid memory enable).

[0029] Advantageously, in this illustrative example, the timing of the precharge signal (here "precharge set bank <3>" controls the timing of the application of the precharge voltage to the bit lines in the bank, which shows the flexibility of the technology presented herein. During the time period labeled 801, the clk rising edge occurs with address Al valid, and precharge set bank <3> remains valid for two clock cycles. Thus, the bit line voltage internal precharge enable row address latch bank <3> remains valid until the clk rise with address Bl valid. Thus, the first clock cycle of precharge set bank <3> is associated with access Al, while the second clock cycle of precharge set bank <3> is associated with access Bl. Time period 801 is an example of how the second clock cycle of precharge set bank <3> associated with access Bl occurs simultaneously with the memory enable for ongoing access Al.

[0030] During the time period labeled 802, the clk rising edge has valid address A2 due to precharge set bank <3> being invalid, thus, the internal precharge enable row address latch bank <3> is invalid when the word line (A2) is valid. However, during the clk rising edge with precharge set bank <3> valid (between addresses A2 and B2), the internal precharge enable row address latch bank <3> becomes valid and the bit lines are precharged in preparation for B2 memory access. Thus, the first clock cycle of precharge set bank <3> is associated with access A2, while the second clock cycle of precharge set bank <3> is associated with access B2. Time period 802 is an example of how the second clock cycle of precharge set bank <3> associated with access B2 occurs simultaneously with the SRAM bit cell access for ongoing access A2.

[0031] During the time period labeled 803, the precharge set bank <3> input is made valid for 3 clock cycles. However, the internal precharge enable row address latch bank <3> has the same behavior. Time period 803 shows a combination of 801 and 802. The first clock cycle of precharge set bank <3> is associated with access A3, while the second and third clock cycles of precharge set bank <3> are associated with access B3. Time period 803 also shows pipelining of 801 and 802 (precharge for B3 is valid during the memory enable period of A3 and the SRAM bit cell access period of A3), and also shows how the technology can keep the precharge input activated for multiple cycles if necessary for a given request (in this case, B3).

[0032] Feature Examples

[0033] Each of the following restrictive features in the following examples can exist alone, or can be combined with one or more of the other features in the following examples in various permutations or combinations. In various embodiments, the present disclosure can be implemented as a processor or a method.

[0034] Embodiments of the present disclosure include a static random access memory (SRAM) circuit, comprising: an SRAM memory bank configured to store data bits, the SRAM memory bank comprising a plurality of bit lines; and an SRAM access control circuit coupled to the plurality of bit lines of the SRAM memory bank, the SRAM access control circuit configured to pre-charge the plurality of bit lines to access the stored data bits, wherein the SRAM access control circuit receives and stores a pre-charge signal for a subsequent cycle when the SRAM access control circuit is accessing the stored data bits in the SRAM memory bank in a current cycle.

[0035] In another example, the present disclosure includes a method of pre-charging an SRAM circuit, comprising: storing data bits in an SRAM memory bank, the SRAM memory bank comprising a plurality of bit lines; receiving and storing, by an SRAM access control circuit, a pre-charge signal for a subsequent cycle when the SRAM access control circuit is accessing the stored data bits in the SRAM memory bank in a current cycle; and pre-charging, by the SRAM access control circuit, the plurality of bit lines to access the stored data bits of the SRAM memory bank based on the pre-charge signal.

[0036] In one embodiment, the pre-charge signal causes the plurality of bit lines to be pre-charged when the SRAM access control circuit is not accessing the stored data bits in the SRAM memory bank in the current cycle.

[0037] In one embodiment, the pre-charge signal is stored in the SRAM access control circuit to automatically pre-charge the plurality of bit lines when the current memory access is completed when the SRAM access control circuit is accessing the stored data bits in the SRAM memory bank in the current cycle.

[0038] In one embodiment, the SRAM access control circuit does not pre-charge the bit lines when the pre-charge signal indicates that there is no pre-charge for the subsequent cycle when the current memory access is completed.

[0039] In one embodiment, the SRAM access control circuit also turns off one or more head switches that provide power to the plurality of word lines when the pre-charge signal indicates that there is no pre-charge for the subsequent cycle when the current memory access is completed.

[0040] In one embodiment, the precharge signal includes one or more bits.

[0041] In one embodiment, the SRAM memory bank includes a plurality of memory sub-banks, and the precharge signal includes a corresponding number of bits to individually precharge the plurality of memory sub-banks.

[0042] In one embodiment, the number of bits is equal to the number of memory sub-banks.

[0043] In one embodiment, the SRAM access control circuit includes a plurality of precharge signal inputs equal to the number of memory sub-banks.

[0044] In one embodiment, the SRAM access control circuit includes a plurality of flip-flops to store a plurality of precharge signal inputs equal to the number of memory sub-banks.

[0045] In one embodiment, the SRAM access control circuit includes a precharge reset input to clear precharge on the plurality of bit lines.

[0046] In one embodiment, the precharge reset input also clears the precharge signal stored in the SRAM access control circuit.

[0047] In one embodiment, the precharge reset input also turns off one or more head switches that provide power to the plurality of word lines.

[0048] The above description illustrates various embodiments and examples of how aspects of some embodiments can be implemented. The above examples and embodiments should not be considered to be exclusive of other embodiments and examples that can be implemented in light of the above disclosure. Other arrangements, embodiments, implementations, and equivalents can be employed without departing from the scope of the claims as defined below.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A static random access memory (SRAM) circuit comprising: an SRAM memory bank configured to store data bits, the SRAM memory bank comprising a plurality of bit lines; as well as an SRAM access control circuit coupled to the plurality of bit lines of the SRAM memory bank, the SRAM access control circuit configured to precharge the plurality of bit lines to access the stored data bits, When the SRAM access control circuit is accessing the data bits stored in the SRAM memory bank in a current cycle, the SRAM access control circuit receives and stores a precharge signal for a subsequent cycle.

2. The SRAM circuit of claim 1, wherein the precharge signal causes the plurality of bit lines to be precharged when the SRAM access control circuit does not access the data bits stored in the SRAM memory bank in the current cycle.

3. The SRAM circuit according to claim 1 , wherein when the SRAM access control circuit is accessing the data bits stored in the SRAM memory bank in the current cycle, the precharge signal is stored in the SRAM access control circuit to automatically precharge the plurality of bit lines when the current memory access is completed.

4. The SRAM circuit of claim 1 , wherein when the precharge signal indicates that there is no precharge for the subsequent cycle, the SRAM access control circuit does not precharge the bit line when the current memory access is completed.

5. The SRAM circuit of claim 4 , wherein when the precharge signal indicates that there is no precharge for the subsequent cycle, the SRAM access control circuit further turns off one or more head switches that provide power to a plurality of word lines when the current memory access is completed. The SRAM circuit according to claim 1 , wherein the precharge signal comprises one or more bits. 7 . The SRAM circuit of claim 1 , wherein the SRAM memory bank comprises a plurality of memory sub-banks, and the precharge signal comprises a corresponding number of bits to precharge the plurality of memory sub-banks individually.

8. The SRAM circuit of claim 7, wherein the number of bits is equal to the number of the plurality of memory sub-banks.

9. The SRAM circuit of claim 7, wherein the SRAM access control circuit comprises a number of precharge signal inputs equal to the number of the plurality of memory sub-banks. 10 . The SRAM circuit according to claim 9 , wherein the SRAM access control circuit comprises a plurality of flip-flops for storing a number of the plurality of precharge signal inputs equal to the number of the plurality of memory sub-banks.

11. The SRAM circuit of claim 1, wherein the SRAM access control circuit comprises a precharge reset input to clear the precharge on the plurality of bit lines.

12. The SRAM circuit of claim 11, wherein the precharge reset input also clears a precharge signal stored in the SRAM access control circuit.

13. The SRAM circuit of claim 12, wherein the precharge reset input also turns off one or more header switches that provide power to the plurality of word lines.

14. A method for precharging an SRAM circuit, comprising: storing data bits in an SRAM memory bank, the SRAM memory bank comprising a plurality of bit lines; When the SRAM access control circuit is accessing the data bits stored in the SRAM memory bank in a current cycle, the SRAM access control circuit receives and stores a precharge signal for a subsequent cycle; as well as Based on the precharge signal, the SRAM access control circuit precharges the plurality of bit lines to access the stored data bits of the SRAM memory bank. 15 . The method of claim 14 , wherein the precharge signal causes the plurality of bit lines to be precharged when the SRAM access control circuit does not access the data bits stored in the SRAM memory bank in the current cycle.

16. The method of claim 14 , wherein the precharge signal is stored in the SRAM access control circuit when the SRAM access control circuit is accessing the data bits stored in the SRAM memory bank in the current cycle to automatically precharge the plurality of bit lines when the current memory access is completed.

17. The method of claim 14, wherein when the precharge signal indicates that there is no precharge for the subsequent cycle, then the SRAM access control circuit does not precharge the bit line when the current memory access is completed. The method of claim 14 , wherein the precharge signal comprises one or more bits.

19. The method of claim 14, wherein the SRAM memory bank comprises a plurality of memory sub-banks, and the precharge signal comprises a corresponding number of bits to precharge the plurality of memory sub-banks individually.

20. The method of claim 14, wherein the SRAM access control circuit comprises a precharge reset input to clear the plurality of bit lines and clear the precharge signal stored in the SRAM access control circuit.

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