Current mirror circuit single-particle transient error automatic detection and suppression method

Abstract

The invention relates to an automatic detection and suppression method for a single-particle transient error of a current mirror circuit, and belongs to the technical field of radiation resistance of an electronic system. The circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube MR serving as a root node of a current mirror, a plurality of leaf node PMOS tubes ML1-MLn, an inverter and a single-particle transient suppression NMOS (N-channel Metal Oxide Semiconductor) transistor Ndn, the grid electrode and the drain electrode of the PMOS tube MR are connected and are simultaneously connected to the grid electrodes of the plurality of PMOS tubes ML1-MLn, and the drain electrodes of the plurality of PMOS tubes are current output ends; substrates and source electrodes of the PMOS tube MR and the plurality of PMOS tubes are connected with VDD; an N-well contact of an N-type doped region is placed beside the PMOS tube MR, the N-well contact is not connected with a power supply and serves as the input end of the phase inverter, and the output end of the phase inverter serves as the grid electrode of the single-particle transient suppression NMOS transistor Ndn; the drain electrode of the transistor Ndn is connected with the drain electrode of the PMOS tube MR, and the source electrode and the substrate are connected with the VSS. The method can be realized based on the circuit. The device has the advantages of simple structure, simplicity and convenience in operation, easiness in implementation, good reinforcing effect and the like.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of anti-radiation of electronic systems, and particularly relates to a current mirror circuit single event transient error automatic detection and suppression method. BACKGROUND

[0002] Electronic systems used in the field of aerospace and aviation are easily affected by radiation effects, which may cause system failure. Electronic systems working in a radiation environment mainly need to consider two radiation effects, single event effect (SEE) and total ionizing dose effect (TID). With the continuous improvement of technology, the influence of total dose effect on chips is gradually decreasing, but the influence of single event effect on electronic devices in space equipment is becoming increasingly serious. Compared with digital circuits, analog circuits are more sensitive to radiation effects, and it is more difficult to design against single event effects. Therefore, high-performance analog circuits have become the focus and difficulty of radiation effect research.

[0003] Single event effect is usually caused by high-energy particles such as cosmic rays, solar particle events, natural decay of super-uranium materials, or nuclear weapon explosions, which bombard the circuit, causing sudden changes in circuit function. When a semiconductor device is bombarded by a single particle, the energy of the high-energy particle will cause ionization collision in the circuit, and the charge will move under the action of concentration gradient and electric field, resulting in transient changes in current and voltage at the bombarded junction in the circuit.

[0004] Current mirror circuit is one of the most important elements in electronic system design, and various analog and mixed signal systems need to use current mirror circuit. It provides accurate and stable output current for various sub-circuit systems (such as ADC, DAC, etc.). Since the current mirror has a significant impact on other circuits, it is of great significance to understand the behavior of the current mirror when it is affected by the irradiation environment and to study its anti-single event transient effect for electronic systems working in extreme environments.

[0005] As shown in Figure 1 The traditional current mirror circuit is usually composed of a current input terminal Iref and multiple current output terminals Iout1 to Ioutn. The input current passes through the diode-biased field effect transistor MR, which generates a bias voltage Vg as the root node, and provides bias for each leaf node transistor ML1 to MLn, thereby generating output currents Iout1 to Ioutn.

[0006] Ignoring the channel length modulation effect of the transistor, the output current of the nth stage of the current mirror is:

[0007]

[0008] where W Rand L R W and L are width and length of the root node transistor MR Ln and L Ln W and L are width and length of the nth level leaf node transistor MLn. Iref is input reference current, I outn is the nth level output current.

[0009] It can be seen that the root node transistor MR of the current mirror is the most sensitive transistor because it generates the bias voltage Vg to provide bias for all the leaf node transistors. Once MR is hit by a single particle, the Vg signal is disturbed, and all the output currents will be affected. SUMMARY

[0010] (1) Technical problem to be solved

[0011] The technical problem to be solved by the present application is how to design a reinforced current mirror circuit and a single particle transient error automatic detection and suppression method which are simple in structure, easy to operate, easy to implement and good in reinforcement effect.

[0012] (2) Technical solution

[0013] In order to solve the above technical problem, the present application provides a current mirror circuit, which is a single particle transient pulse resistant reinforced current mirror circuit, has one current input end and multiple current output ends; the current input end is a reference current input end Iref, and the multiple current output ends are Iout1 to Ioutn; the current mirror circuit comprises:

[0014] a PMOS transistor MR as a root node of the current mirror, PMOS transistors ML1-MLn as leaf nodes, an inverter F and a single particle transient suppression NMOS transistor Ndn;

[0015] The gate of the PMOS transistor MR is connected to the drain, and is connected to the current input end Iref and the gates of the PMOS transistors ML1-MLn at the same time; the drains of the PMOS transistors ML1-MLn are the current output ends; the substrates and the sources of the PMOS transistor MR and the PMOS transistors ML1-MLn are connected to the power supply VDD;

[0016] An N-well contact of N-type doping region is placed beside the PMOS transistor MR, the N-well contact can provide a trigger signal, is not connected to the power supply VDD, and is connected to the input end of the inverter F, and the output end of the inverter F is the gate of the single particle transient suppression NMOS transistor Ndn; the drain of the transistor Ndn is connected to the drain of the PMOS transistor MR, and the source and the substrate are connected to the power supply ground VSS.

[0017] Preferably, the voltage of the N-well contact is Vb, and Vb=Vdd when the reinforced current mirror circuit is not hit by a single particle.

[0018] Preferably, the N-well contact is arranged next to the PMOS tube MR at the nearest distance satisfying the process rule.

[0019] Preferably, the PMOS tube MR is grown in the P-type doped region of the N-well; and another N-well contact of N-type doped region is also arranged in the N-well, and the another N-well contact is connected to the power supply VDD to control the N-well potential.

[0020] Preferably, the N-well is high through the another N-well contact.

[0021] The application also provides a single particle transient error automatic detection and suppression method based on the current mirror circuit. During the normal operation of the current mirror circuit, the voltage Vb is kept at a high level, the inverter F outputs at a low level, the single particle transient suppression NMOS transistor Ndn is kept in the off state, and the bias signal generated by the PMOS tube MR is propagated from the root node to each leaf node to provide a bias voltage Vg for each PMOS tube of the leaf node. When a single particle strikes the root node PMOS tube MR, the PN junction of the drain and body region of the struck PMOS tube MR will collapse, the N-well potential will be temporarily biased, the voltage Vb will be temporarily changed to a low level, the output voltage of the inverter F will be temporarily changed to a high level, and the single particle transient suppression NMOS transistor Ndn will be opened, thereby suppressing the disturbance (i.e. single particle transient error) generated by the single particle striking the drain of the PMOS tube MR, and further reducing the fluctuation of the current output end.

[0022] The application also provides an anti-radiation method for an electronic system based on the current mirror circuit.

[0023] The application also provides an anti-radiation method for an electronic system based on the method.

[0024] The application also provides an electronic system based on the design of the current mirror circuit.

[0025] (III) Beneficial effects

[0026] The reinforced current mirror circuit and the single particle transient error automatic detection and suppression method of the application can achieve reinforcement of the root node transistor of the current mirror circuit, the error signal generated by the root node transistor after being struck by a single particle can be greatly attenuated, thereby reducing the interference on each leaf node transistor, and reducing the single particle radiation disturbance of the output current. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a non-reinforced current mirror circuit (taking a PMOS tube as an example) in the prior art;

[0028] Figure 2is a schematic diagram of the circuit principle of the current mirror circuit of the present application in a specific application example;

[0029] Figure 3 is a layout schematic diagram of the current mirror circuit of the present application in a specific application example;

[0030] Figure 4 is a schematic diagram of the Vb signal jump result obtained by modeling and simulating the single particle hitting the drain of the MR transistor in the TCAD simulation software of the present application;

[0031] Figure 5 is a schematic diagram of the Vg signal result obtained by modeling and simulating the single particle hitting the drain of the MR transistor in the TCAD simulation software of the present application in the hardened and unhardened circuits;

[0032] Figure 6 is a schematic diagram of the output current change result obtained by modeling and simulating the single particle hitting the drain of the MR transistor in the TCAD simulation software of the present application in the hardened and unhardened circuits. DETAILED DESCRIPTION

[0033] In order to make the purpose, content and advantages of the present application clearer, the specific embodiments of the present application are described in further detail below in combination with the drawings and examples.

[0034] As Figure 2 shown, the hardened current mirror circuit of the present application is a current mirror circuit resistant to single particle transient pulses, which comprises a normal current mirror circuit, an N-well contact not connected with the power supply ground, an inverter circuit and a single particle transient suppression NMOS transistor Ndn. Among them: the current mirror circuit has one current input end and multiple current output ends. One input end is a reference current input end Iref; the multiple current output ends are Iout1 to Ioutn.

[0035] The current mirror circuit of the present application comprises multiple PMOS tubes, an inverter and a single particle transient suppression NMOS transistor Ndn; wherein:

[0036] One PMOS tube MR serves as the root node of the current mirror, the gate and the drain of which are connected, connected to the input end Iref, and connected to the gates of multiple PMOS tubes ML1 to MLn at the same time, and the drains of the multiple PMOS tubes ML1 to MLn are the current output ends Iout1 to Ioutn.

[0037] The substrate and the source of the PMOS tube MR and the multiple PMOS tubes ML1 to MLn are connected to VDD.

[0038] Referring to Figure 3The shown layout diagram takes the current mirror circuit composed of PMOS transistors as an example, and the PMOS transistors are grown in the P-doped region of the N-well. In addition to the N-well contact (N-well contact 1) of the normal N-type doped region in the N-well, which is normally connected to the power supply Vdd to control the N-well potential, another N-well contact (N-well contact 2) of the N-type doped region is placed beside the root node transistor MR at the nearest distance to meet the process rules. The N-well contact 2 is not connected to the power supply. The voltage of the N-well contact 2 is Vb, and Vb = VDD when the circuit is not subjected to single particle bombardment.

[0039] That is, the present application arranges an additional N-well contact (N-well contact 2) beside the PMOS transistor MR on the layout at the nearest distance to meet the rule file, Figure 3 and the potential of the N-well contact 2 is Vb, which is connected to the input end of the inverter as a trigger signal, and the output end of the inverter is connected to the gate of the single particle transient suppression NMOS transistor Ndn.

[0040] The present application further provides a single particle transient error automatic detection and suppression method. Since the root node transistor MR is the most sensitive transistor, the most critical innovation of the present application is to carry out reinforcement design for it. The reinforcement method of the present application includes:

[0041] The transistor MR (such as a PMOS transistor) is grown in the P-doped region of the N-well. In addition to the N-well contact (N-well contact 1) of the normal N-type doped region in the N-well, which is normally connected to the power supply Vdd to control the N-well potential, another N-well contact (N-well contact 2) of the N-type doped region is placed beside the root node transistor MR at the nearest distance to meet the process rules. The N-well contact 2 is not connected to the power supply. The voltage of the N-well contact 2 is Vb, and Vb = VDD when the circuit is not subjected to single particle bombardment.

[0042] In a specific application example, the N-well contact 2 is directly connected to the input of an inverter as a trigger signal, and the output of the inverter is connected to the gate of an NMOS transistor Ndn as a single event transient suppression transistor. In the normal operation of the circuit, the Vb signal remains high, and the output of the inverter is low, and the Ndn transistor remains off, and the bias signal generated by the MR can be normally propagated from the root node to each leaf node to provide a bias voltage Vg for each leaf node transistor. If a single particle strikes the root node transistor MR, the PN junction between the drain and the body region (the N-well region for the PMOS transistor) of the struck transistor will collapse, and the N-well potential will be temporarily positively biased, so that the Vb voltage is temporarily lowered to low, and the MR drain voltage is temporarily raised to high; the output of the inverter is high, driving the single event transient suppression NMOS transistor Ndn to turn on. Therefore, the disturbance of the MR drain signal caused by the single particle strike will be greatly suppressed by the single event transient suppression NMOS transistor Ndn, and the disturbance of the Vg signal caused by the single particle strike will be reduced (suppressing the disturbance caused by the single particle strike at the Vg node, i.e., the single event transient error), and the current output end will be less fluctuated, thereby achieving the effect of resisting single event transients.

[0043] As can be seen from the above, after the above design is adopted, in the process of particle striking the PMOS tube MR root node, the PN junction between the body region and the drain of the PMOS tube MR collapses, the body region potential drops, and the drain voltage rises. The input Vb of the inverter is affected by the single particle and jumps from high to low, and the output jumps from low to high, and the NMOS switch tube Ndn changes from the normal cut-off state to the on state, so that the bias signal generated by the PMOS tube MR is quickly dissipated by the Ndn after being affected by the single particle, and the gate voltage Vg of the plurality of PMOS tubes ML1 to MLn jumps and decreases. In this way, the influence of the single particle striking the PMOS tube MR root node on the output current signal is suppressed.

[0044] Figure 4 To utilize Figure 3 The Vb signal jump result caused by the single particle striking the drain of the MR transistor is modeled and simulated in the TCAD simulation software.

[0045] The simulation adopts Figure 2 and Figure 3 The circuit schematic diagram and layout schematic diagram shown in the figures. The current mirror circuit layout of the application is modeled and simulated in the TCAD software, and the LET=10 MeV·cm 2A single particle of / mg hits the drain center of the MR transistor at t = 1ns. When not hit by a single particle, the Vb signal remains high. If a single particle hits the root node transistor MR, the PN junction between the drain of MR and the N-well region will collapse, and the N-well potential will be temporarily positive, causing the Vb voltage to temporarily jump to a low level. Taking half of the power supply voltage (Vdd = 0.9V, half of the power supply voltage is 0.45V) as the threshold voltage, TCAD simulation results show that Vb is subject to LET = 10MeV·cm 2 The pulse width generated by the single particle impact of / mg is 0.1ns. This result shows that the drain of MR is subjected to LET = 10MeV·cm 2 After a single-particle bombardment of 1000 Å / mg, the Ndn transistor will turn on for 0.1 ns.

[0046] Figure 5 To utilize Figure 3 Modeling and simulating the Vg signal of a single-particle impact on the drain of an MR transistor in TCAD software. The results for reinforced and unreinforced circuits are shown in Figure 1. Line I in the figure represents unreinforced circuits, while line II in the figure represents reinforced circuits.

[0047] The simulation uses Figure 2 and Figure 3 The layout and circuit diagram are shown. For the sake of convenience, n=1 is used as an example, that is, there is only one output current. At the same time, for the sake of simplicity, the width and length of the MR and ML1 transistors are the same, so the output current Iout1 is equal to the input reference current Iref. The current mirror circuit of the present invention is laid out and simulated in TCAD software. LET=10MeV·cm 2 A single particle of / mg bombards the drain center of the MR transistor at time t = 1ns. For both reinforced and unreinforced circuits, the Vg voltage is 0.41V when not affected by the single particle. The SET pulse width of the Vg signal of the unreinforced current mirror circuit after the MR transistor is bombarded by the single particle is 97ps (taking 0.5V as the threshold voltage). Using the reinforced current mirror circuit of the present invention, the SET width of the Vg signal after the MR transistor is bombarded by the single particle is 41ps (taking 0.5V as the threshold voltage). Comparing the reinforced and unreinforced circuits, the present invention can reduce the SET pulse disturbance of the Vg signal to 42.2%.

[0048] Figure 6 To utilize Figure 3 Modeling and simulating the output current of a single-particle impact on the drain of an MR transistor in TCAD software. The results for reinforced and unreinforced circuits are shown in Figure 1. Line I in the figure represents unreinforced circuits, while line II in the figure represents reinforced circuits.

[0049] The simulation uses Figure 2 and Figure 3The layout and circuit schematic are shown. For the convenience of analysis, take n = 1 as an example, that is, there is only one output current. At the same time, in order to simplify the analysis, the width and length of MR and ML1 transistors are the same, so the output current Iout1 is equal to the input reference current Iref. The layout of the current mirror circuit of the application is simulated in the TCAD software, and LET = 10 MeV·cm 2 / mg of single particles hit the center of the drain of the MR transistor at t = 1 ns. For the hardened and unhardened circuits, the output current is 417 pA when not affected by single particles. The output current of the unhardened current mirror circuit is at least 61 pA after the MR transistor is hit by single particles, and the SET-induced current change is 356 pA. The output current of the hardened current mirror circuit of the application is at least 224 pA after the MR transistor is hit by single particles, and the SET-induced current change is 193 pA. Compared with the hardened and unhardened circuits, the SET pulse amplitude of the output current can be reduced to 54.2% by using the application.

[0050] The above only describes the preferred embodiments of the application, and it should be noted that those skilled in the art can make several improvements and modifications without departing from the technical principles of the application, and these improvements and modifications should also be considered as within the protection scope of the application.

Claims

1. A current mirror circuit, characterized in that: The current mirror circuit is a reinforced current mirror circuit resistant to single-particle transient pulses, having a current input terminal and multiple current output terminals; The current input terminal is a reference current input terminal Iref, and the multiple current output terminals are Iout1 to Ioutn; the current mirror circuit includes: PMOS transistor MR as the root node of the current mirror, PMOS transistors ML1 to MLn as leaf nodes, inverter F and single event transient suppression NMOS transistor Ndn; The gate and drain of the PMOS transistor MR are connected to the current input terminal Iref and the gates of the PMOS transistors ML1 to MLn. The drains of the PMOS transistors ML1 to MLn are the current output terminals. The substrates and sources of the PMOS transistors MR and ML1 to MLn are connected to the power supply VDD. An N-well contact of an N-type doped region is placed next to the PMOS transistor MR. The N-well contact can provide a trigger signal, is not connected to the power supply VDD, and is connected to the input end of the inverter F. The output end of the inverter F is the gate of the single-event transient suppression NMOS transistor Ndn. The drain of the transistor Ndn is connected to the drain of the PMOS transistor MR, and the source and substrate are both connected to the power ground VSS.

2. The current mirror circuit according to claim 1, wherein: The voltage of the N-well contact is Vb, and when the reinforced current mirror circuit is not bombarded by a single event, Vb=Vdd.

3. The current mirror circuit according to claim 1, wherein: The N-well contact is arranged at the closest distance to the PMOS transistor MR that meets the process rules.

4. The current mirror circuit according to claim 1, wherein: The PMOS transistor MR is grown in the P-type doping region of the N-well. Another N-well contact of the N-type doping region is also arranged in the N-well. The other N-well contact is connected to the power supply VDD to control the N-well potential.

5. The current mirror circuit according to claim 4, wherein: The N-well contacts the other N-well so that the entire well potential is high.

6. A method for automatically detecting and suppressing single-event transient errors based on the current mirror circuit according to any one of claims 1 to 5.

7. The method according to claim 6, wherein During normal operation of the current mirror circuit, the voltage Vb remains at a high level, the output of the inverter F is at a low level, the single-particle transient suppression NMOS transistor Ndn remains in the off state, and the bias signal generated by the PMOS tube MR propagates from the root node to each leaf node, providing a bias voltage Vg for the PMOS tubes of each leaf node; when a single particle bombards the root node PMOS tube MR, the PN junction between the drain and body of the bombarded PMOS tube MR will collapse, and the N-well potential will be forward biased, causing the voltage Vb to jump to a low level, and the output voltage of the inverter F to jump to a high level, driving the single-particle transient suppression NMOS transistor Ndn to turn on, thereby suppressing the disturbance caused by the single particle bombardment on the drain of the PMOS tube MR.

8. An anti-radiation method for an electronic system implemented based on the current mirror circuit according to any one of claims 1 to 5.

9. An anti-radiation method for an electronic system implemented based on the method according to claim 7.

10. An electronic system based on the current mirror circuit design according to any one of claims 1 to 5.

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