Low-temperature drift coefficient voltage reference source with load driving capability

Abstract

The invention discloses a low-temperature-drift-coefficient voltage reference source with load driving capacity. The low-temperature-drift-coefficient voltage reference source comprises a temperature negative correlation circuit, an unbalanced amplifier, a time domain amplifier and a voltage superposition main branch. According to the invention, the temperature negative correlation circuit and the improved unbalanced amplifier are combined, so that the nonlinear term related to the temperature in the output voltage is greatly reduced, a very small temperature coefficient is achieved, and an additional starting circuit is not needed. In addition, by adopting the stacked NMOS structure, the output voltage is effectively reduced along with process deviation; by adopting the time domain amplifier, high gain, low power consumption and 20mA load driving capability are realized under the lowest low power supply voltage of 0.9 V.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of low-power consumption voltage reference source, and particularly relates to a low-temperature drift coefficient voltage reference source with load driving capability. BACKGROUND

[0002] As a key building block of analog integrated circuit system, voltage reference source can provide stable voltage which is not affected by process, power voltage and temperature change. In recent years, with the rapid development of self-powered Internet of Things system and implantable devices, long-term operation and miniaturization application have put forward strict requirements on voltage reference source, such as low power supply voltage, small area and ultra-low power consumption, and integrated driving capability has also become an important additional requirement.

[0003] The minimum power supply voltage of the traditional bandgap reference source based on triode is limited by the base-emitter voltage of bipolar transistor. In order to minimize power consumption, it usually needs to use a large resistance, which leads to excessive area overhead. In contrast, CMOS voltage reference source has the advantages of low power consumption, small area and low power supply. However, most of the existing CMOS voltage reference sources often have difficulty in achieving low temperature drift coefficient, such as the literature [P. Luong, C. Christoffersen, C. Rossi-Aicardi and C. Dualibe. CMOS voltage reference source with nW power consumption and below 1V voltage using digitally trimmed temperature drift coefficient, IEEE Journal of Circuits and Systems, April 2017, Vol. 64, No. 4, pp. 787-798] and the literature [M. Eberlein and S. Ruping. A 0.6V supply and small area voltage reference using MOS threshold voltage relationship, Custom Integrated Circuits Conference, Boston, USA, 2025, pp. 1-3]. At the same time, the CMOS voltage reference source has no load driving capability, so additional driving circuit needs to be added to power the circuit module, which brings sacrifice in power consumption and accuracy. SUMMARY

[0004] In view of the above, the application provides a low-temperature drift coefficient voltage reference source with load driving capability, which greatly reduces the nonlinear term about temperature in the output voltage by combining the temperature negative correlation circuit of stacked NMOS tube structure and the improved unbalanced amplifier, so as to achieve very small temperature coefficient without additional starting circuit.

[0005] A low-temperature drift coefficient voltage reference source with load driving capability, comprising a temperature negative correlation circuit, a time domain amplifier, an unbalanced amplifier and a voltage superposition main branch, wherein: The unbalanced amplifier generates an output voltage V OUT and a feedback voltage VFB The differential output voltage is amplified by an unbalanced differential amplifier to generate a pair of differential output voltages, while V OUT is generated between V FB , which has a positive first-order temperature coefficient and a negative second-order temperature coefficient. The temperature negative correlation circuit generates a temperature positive correlation current bias using the differential output voltage, thereby generating a voltage V CTAT with a negative first-order temperature coefficient and a positive second-order temperature coefficient. The time domain amplifier is used to amplify the differential output voltage to generate a driving voltage V G to drive the load tube in the main branch. The voltage superposition main branch is used to superimpose the input offset voltage after amplification with the voltage V CTAT to generate a high-order temperature compensation output voltage V OUT to drive the load, and V OUT is divided by V CTAT to obtain a feedback voltage V FB .

[0006] Further, the temperature negative correlation circuit includes PMOS tubes M6 and M7 and NMOS tubes M0 and M1, wherein the source of M6 is connected to the source of M7 and connected to the power supply voltage, the gate of M6 is connected to the positive output voltage V CP generated by the unbalanced amplifier, the gate of M7 is connected to the negative output voltage V CN generated by the unbalanced amplifier, the drain of M6 is connected to the drain of M7, the gate of M0, the gate of M1, and the drain of M1, the source of M0 is connected to ground, the drain of M0 is connected to the source of M1 and generates a voltage V CTAT , and M0 is an HVT (high threshold voltage) NMOS tube.

[0007] Further, the unbalanced amplifier includes NMOS tubes M2 and M3, PMOS tubes M4 and M5, and a resistor R B , wherein the gate of M2 is connected to the output voltage V OUT , the drain of M2 is connected to the drain of M4 and the gate of M4 to generate a positive output voltage V CP , the source of M2 is connected to the source of M3 and one end of R B , the other end of R B is connected to ground, the source of M4 is connected to the power supply voltage, the gate of M3 is connected to the feedback voltage V FB , the drain of M3 is connected to the drain of M5 and the gate of M5 to generate a negative output voltage V CN , and the source of M5 is connected to the power supply voltage.

[0008] Further, the time domain amplifier comprises a voltage-time conversion circuit and a charge pump, the voltage-time conversion circuit is used to convert the differential output voltage into a pair of pulse signals, and then the pulse signals are used to control the charge pump to generate the driving voltage V G .

[0009] Further, the voltage-time conversion circuit comprises four NMOS tubes M9~M 12 , two PMOS tubes M 13 and M 14 , two capacitors C1 and C2, two skew inverters I0 and I1, seven inverters I2~I7 and I 10 , and two NAND gates I8 and I9, wherein the gate of M9 is connected to the non-inverted output voltage V CP generated by the unbalanced amplifier, the gate of M 10 is connected to the inverted output voltage V CN generated by the unbalanced amplifier, the source of M9 is connected to the source of M 10 and the drain of M 11 , the gate of M 11 is connected to an external clock, the source of M 11 is connected to the drain of M 12 , the gate of M 12 is connected to an external bias voltage, the source of M 12 is connected to ground, the drain of M9 is connected to one end of C1, the drain of M 13 and the input of I0, the drain of M 10 is connected to one end of C2, the drain of M 14 and the input of I1, the gate of M 13 is connected to the gate of M 14 and connected to an external clock, the source of M 13 is connected to the source of M 14 , the other end of C1 and the other end of C2 and connected to a power supply voltage, the output of I0 is connected to the input of I2, the output of I2 is connected to the input of I4, the output of I4 is connected to the input of I6 and the first input of I9, the output of I6 is connected to the first input of I8, the output of I8 generates a pulse signal UP, the output of I1 is connected to the input of I3, the output of I3 is connected to the input of I5, the output of I5 is connected to the input of I7 and the second input of I8, the output of I7 is connected to the second input of I9, the output of I9 is connected to the input of I 10 , and the output of I 10 generates a pulse signal DN.

[0010] Further, the skew inverters I0 and I1 are the same structure, comprising a PMOS tube M I0 and an NMOS tube M I1wherein the gate of M I0 is connected to the gate of M I1 and serves as the input of the skew inverter, the source of M I0 is connected to the power supply voltage, the source of M I1 is connected to ground, the drain of M I0 is connected to the drain of M I1 and serves as the output of the skew inverter, and M I1 is an HVT NMOS transistor.

[0011] Further, the charge pump comprises two PMOS transistors M 15 and M 16 and two NMOS transistors M 17 and M 18 , wherein the gate of M 15 is connected to an external bias voltage, the source of M 15 is connected to the power supply voltage, the drain of M 15 is connected to the source of M 16 , the gate of M 16 is connected to the pulse signal UP, the drain of M 16 is connected to the drain of M 17 to generate the driving voltage V G , the gate of M 17 is connected to the pulse signal DN, the source of M 17 is connected to the drain of M 18 , the gate of M 18 is connected to an external bias voltage, and the source of M 18 is connected to ground.

[0012] Further, the voltage superposition main branch comprises a PMOS transistor M P , a capacitor C C and two resistors R0 and R1, wherein M P is a load transistor, the gate of M P is connected to one end of C C and is connected to the driving voltage V G , the drain of M P is connected to the other end of C C and one end of R0 to generate the output voltage V OUT , the source of M P is connected to the power supply voltage, the other end of R0 and one end of R1 are connected to generate the feedback voltage V FB , and the other end of R1 is connected to the voltage V CTAT .

[0013] Compared to existing technologies, the low-drift voltage reference of this invention significantly reduces the temperature-dependent nonlinearity of the output voltage by combining a negative temperature-dependent circuit with an improved unbalanced amplifier, achieving a very low temperature coefficient (1.86ppm / °C in the -40°C to 140°C temperature range) while eliminating the need for an additional startup circuit. Furthermore, by utilizing a stacked NMOS structure, the invention effectively reduces process variations in output voltage. By employing a time-domain amplifier, the invention achieves high gain, low power consumption, and a 20mA load drive capability at a minimum supply voltage of 0.9V. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the overall structure of the low temperature drift coefficient voltage reference source of the present invention.

[0015] Figure 2 Schematic diagram of the structure of the voltage-time conversion circuit in the present invention.

[0016] Figure 3 Schematic diagram of the working sequence of the voltage-to-time conversion circuit in the present invention.

[0017] Figure 4 Schematic diagram of the structure of the CMOS skew inverter in the present invention.

[0018] Figure 5 Schematic diagram of the internal structure of the charge pump in the present invention.

[0019] Figure 6 Schematic diagram of the temperature drift coefficient of the low-temperature drift coefficient voltage reference source of the present invention.

[0020] Figure 7 Schematic diagram of the load transient response of the low-temperature drift coefficient voltage reference source of the present invention. DETAILED DESCRIPTION

[0021] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1 As shown, this embodiment provides a low-temperature drift coefficient voltage reference source with load driving capability, including a temperature negative correlation circuit, an unbalanced amplifier, a time domain amplifier, and a voltage superposition main branch, wherein: The temperature negative correlation circuit includes a PMOS transistor M6, a PMOS transistor M7, a high threshold NMOS transistor M0, and an NMOS transistor M1. The source of the PMOS transistor M6 and the source of the PMOS transistor M7 are connected to the power supply voltage VDD, and the gate of the PMOS transistor M6 is connected to the positive phase output voltage V CP The gate of the PMOS tube M7 is connected to the inverting output voltage V of the unbalanced amplifier.CN , the drain of PMOS transistor M6, the drain of PMOS transistor M7, the gate of high threshold NMOS transistor M0, the gate and the drain of NMOS transistor M1 are connected together, the source of high threshold NMOS transistor M0 is connected to ground GND, the drain of high threshold NMOS transistor M0 and the source of NMOS transistor M1 are connected together and generate voltage V CTAT .

[0023] wherein PMOS transistor M6 and PMOS transistor M7 mirror the bias current from the unbalanced amplifier, high threshold NMOS transistor M0 and NMOS transistor M1 form a stacked NMOS structure for generating voltage V with a first order temperature coefficient being negative and a second order temperature coefficient being positive CTAT to an input terminal of the voltage superposition main branch; the output V CTAT of the temperature negative correlation circuit wherein: m1, m0 are the sub-threshold slope factors of M1, M0 respectively, V TH0 , V TH1 are the threshold voltages of M1, M0 respectively, V T is the thermal voltage, I D1 , I D0 are the currents flowing through M1, M0 respectively, μ1, μ0 are the carrier mobilities of M1, M0 respectively, C OX1 , C OX2 are the unit gate oxide capacitances of M1, M0 respectively, W1, L1, W0, L0 are the width and length of M1, M0 respectively, V GS0 is the gate-source voltage of M0. In application, the value of the first term in which the two threshold voltages are subtracted is dominant, V CTAT exhibits a temperature negative correlation characteristic, and the second order coefficient with respect to temperature is greater than zero.

[0024] The unbalanced amplifier comprises NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, PMOS transistor M5 and resistor R B , wherein the gate of NMOS transistor M2 is connected to output voltage V OUT and forms a non-inverting input terminal of the unbalanced amplifier, the drain of NMOS transistor M2, the drain of PMOS transistor M4 and the gate of PMOS transistor M4 are connected together and generate non-inverting output voltage V CP as a non-inverting output terminal of the unbalanced amplifier, the source of NMOS transistor M2 and the source of NMOS transistor M3 are connected together and are connected to one end of resistor R B , the other end of resistor R B is connected to ground GND, the source of PMOS transistor M4 is connected to power voltage VDD, and the gate of NMOS transistor M3 is connected to feedback voltage V FBThe drain of NMOS tube M3, the drain of PMOS tube M5 and the gate of PMOS tube M5 are connected together and serve as the inverting output terminal of the unbalanced amplifier to generate an inverting output voltage V CN , the source of the PMOS tube M5 is connected to the power supply voltage VDD.

[0025] The NMOS transistors M2 and M3 both operate in the subthreshold region and have different width-to-length ratios. When the currents flowing through the NMOS transistors M2 and M3 and the drain-source voltages are equal, the input offset voltage of the amplifier is expressed as: Where: m is the subthreshold slope factor of NMOS, V T is the thermal voltage, and S3 and S2 are the width-to-length ratios of M3 and M2, respectively. This input offset voltage exhibits a positive correlation with temperature. Due to the slight difference in current flowing through M3 and M2, the second-order temperature coefficient of this input offset voltage with respect to temperature is less than zero, enabling high-order temperature compensation for the negatively correlated voltage.

[0026] The time-domain amplifier, which includes a voltage-to-time conversion circuit and a charge pump, amplifies the differential output voltage generated by the unbalanced amplifier and drives the load transistor. Using negative feedback, the time-domain amplifier ensures that the current flowing through NMOS transistors M2 and M3 in the amplifier, which contains a temperature-dependent offset voltage, and the drain-source voltage are equal, ensuring proper operation.

[0027] like Figure 2 As shown, the voltage-time conversion circuit includes four NMOS tubes M9~M 12 , 2 PMOS tubes M 13 ~M 14 , 2 capacitors C1~C2, 2 CMOS skew inverters I0~I1, 7 CMOS inverters I2~I7 and I 10 And two CMOS NAND gates I8~I9, where the gate of NMOS tube M9 serves as the positive phase input terminal of the voltage-time conversion circuit. 10 The gate of the NMOS tube M9 is used as the inverting input terminal of the voltage-time conversion circuit, and the source of the NMOS tube M 10 The source of NMOS tube M 11 The drain of NMOS tube M is connected in common. 11 The gate of the NMOS tube is connected to the external clock CLK, 11 The source of the NMOS tube M 12 The drain of NMOS tube M 12 The gate is connected to an external bias voltage V BN , NMOS tube M 12source GND, the drain of NMOS transistor M9, one end of capacitor C1, the drain of PMOS transistor M 13 , the drain of NMOS transistor M 10 , one end of capacitor C2, the drain of PMOS transistor M 14 , the drain of PMOS transistor M 13 , the gate of PMOS transistor M 14 , the gate of PMOS transistor M 13 , the source of PMOS transistor M 14 , the other end of capacitor C1, the other end of capacitor C2 are connected together and connected to power voltage VDD. The output end of CMOS skew inverter I0 is connected to the input end of CMOS inverter I2, the output end of CMOS inverter I2 is connected to the input end of CMOS inverter I4, the output end of CMOS inverter I4 is connected to the input end of CMOS inverter I6 and the first input end of CMOS NAND gate I9, the output end of CMOS inverter I6 is connected to the second input end of CMOS NAND gate I8, the output end of CMOS NAND gate I8 generates pulse signal UP as the positive phase output end of voltage time conversion circuit, the output end of CMOS skew inverter I1 is connected to the input end of CMOS inverter I3, the output end of CMOS inverter I3 is connected to the input end of CMOS inverter I5, the output end of CMOS inverter I5 is connected to the input end of CMOS inverter I7 and the first input end of CMOS NAND gate I8, the output end of CMOS inverter I7 is connected to the second input end of CMOS NAND gate I9, the output end of CMOS NAND gate I9 is connected to the input end of CMOS inverter I 10 , the output end of CMOS inverter I 10 generates pulse signal DN as the inverse phase output end of voltage time conversion circuit.

[0028] The working timing of voltage time conversion circuit is shown in Figure 3 , when the external clock signal CLK is low, M 13 , M 14 are turned on, the voltage time conversion circuit is reset; when the external clock signal CLK is high, M 11 are turned on, the input differential pair composed of M9, M 10 starts to work, the difference between input voltage V CP and V CN causes the falling speed of voltage V TP , V TN from VDD to be different, thus the flip time of CMOS skew inverters is different, the digital circuit converts it into pulses UP and DN with different width and as two output ends of voltage time conversion circuit.

[0029] As shown in Figure 4 , the CMOS skew inverter comprises a PMOS transistor M I0 and a high threshold NMOS transistor M I1 , wherein the gate of the PMOS transistor M I0 and the gate of the high threshold NMOS transistor M I1 are connected in common and serve as the input terminal of the CMOS skew inverter, the source of the PMOS transistor M I0 is connected to the power supply voltage VDD, the source of the high threshold NMOS transistor M I1 is connected to the ground GND, the drain of the PMOS transistor M I0 and the drain of the high threshold NMOS transistor M I1 are connected in common and serve as the output terminal of the CMOS skew inverter; the flip voltage of the CMOS skew inverter is adjusted by setting the width-length ratio, for comparing the voltages V TP , V TN and the flip voltage.

[0030] As shown in Figure 5 , the charge pump comprises two PMOS transistors M 15 ~M 16 and two NMOS transistors M 17 ~M 18 , wherein the gate of the PMOS transistor M 15 is connected to the external bias voltage V BP , the source of the PMOS transistor M 15 is connected to the power supply voltage VDD, the drain of the PMOS transistor M 15 is connected to the source of the PMOS transistor M 16 , the gate of the PMOS transistor M 16 serves as the non-inverted input terminal of the charge pump and is connected to the pulse signal UP, the drain of the PMOS transistor M 16 and the drain of the NMOS transistor M 17 are connected in common and serve as the output terminal V G of the charge pump, the gate of the NMOS transistor M 17 serves as the inverted input terminal of the charge pump and is connected to the pulse signal DN, the source of the NMOS transistor M 17 is connected to the drain of the NMOS transistor M 18 , the gate of the NMOS transistor M 18 is connected to the external bias voltage V BN , and the source of the NMOS transistor M 18 is connected to the ground GND. The gate of the PMOS transistor M 16 and the gate of the NMOS transistor M 17 are respectively connected to the output UP and DN of the voltage time conversion circuit, to control the on or off of the upper and lower current sources, so as to output or input the current to drive the load transistor M P and the Miller capacitor CC .

[0031] The voltage superposition main branch comprises a PMOS transistor M P , a capacitor C C and two resistors R0 and R1, wherein the gate of the PMOS transistor M P , one end of the capacitor C C are connected in common and connected to the driving voltage V G output by the time domain amplifier, the drain of the PMOS transistor M P , the other end of the capacitor C C , one end of the resistor R0 and the non-inverting input end of the unbalanced amplifier are connected in common and generate an output voltage V OUT as an output end of the voltage reference source, the source of the PMOS transistor M P is connected to the power voltage VDD, the other end of the resistor R0 and one end of the resistor R1 are connected in common and connected to the inverting input end of the unbalanced amplifier to generate a feedback voltage V FB , and the other end of the resistor R1 is connected to the voltage V CTAT output by the temperature negative correlation circuit.

[0032] The gate of the load transistor M P is connected to the output of the time domain amplifier, thereby driving the external load; the two ends V OUT and V FB of the resistor R0 are connected to the two input ends of the unbalanced amplifier, respectively, and an input offset voltage is applied to the resistor R0 through loop negative feedback; the temperature negative correlation voltage V CTAT and the temperature positive correlation offset voltage are superimposed according to the resistance ratio to be the output voltage, and the expression is: As shown in Figure 6 , the temperature drift coefficient of the low-temperature drift coefficient voltage reference source is 1.86ppm / ℃ in the temperature range of-40℃ to 140℃ after resistance adjustment, and the effect of high-order temperature compensation is very significant.

[0033] As shown in Figure 7 , the load current of the low-temperature drift coefficient voltage reference source is switched between 1mA and 20mA, the conversion time is 10ns, the clock frequency is 1MHz, and the load capacitance and the Miller capacitance C C are both 10pF, and the undershoot voltage of 177mV and the recovery time of 4.4us and the undershoot voltage of 220mV and the recovery time of 6.4us are obtained, which proves that the voltage reference source has a load driving capacity of 20mA and a fast transient response.

[0034] The above description of the embodiments is for the purpose of enabling one of ordinary skill in the art to make and use the application and is not intended to limit the application as construed in the broadest scope possible. Inasmuch as modifications to the above described embodiments can readily be made by persons of ordinary skill in the art, it is intended that the application not be limited to the embodiments described above but should be construed in the broadest scope possible.

Claims

1. A low-temperature drift coefficient voltage reference source with load driving capability, characterized in that: It includes a temperature negative correlation circuit, a time domain amplifier, an unbalanced amplifier, and a voltage superposition main branch, wherein: The unbalanced amplifier adds the voltage to the output voltage V generated by the main branch. OUT and feedback voltage V FB After the unbalanced differential pair tube is amplified, a pair of differential output voltages are generated. OUT With V FB An input offset voltage with a positive first-order temperature coefficient and a negative second-order temperature coefficient is generated between them; The temperature negative correlation circuit uses the differential output voltage to generate a current bias that is positively correlated with temperature, thereby generating a voltage V with a negative first-order temperature coefficient and a positive second-order temperature coefficient. CTAT ; The time domain amplifier is used to amplify the differential output voltage to generate a driving voltage V G Used to drive the load tube in the voltage superposition main branch; The voltage superposition main branch is used to amplify the input offset voltage and the voltage V CTAT Superposition generates a high-order temperature compensated output voltage V OUT To drive the load, and V OUT With V CTAT After voltage division, the feedback voltage V FB .

2. The low-temperature drift coefficient voltage reference source with load driving capability according to claim 1, characterized in that: The temperature negative correlation circuit includes PMOS transistors M6 and M7 and NMOS transistors M0 and M1, wherein the source of M6 is connected to the source of M7 and connected to the power supply voltage, and the gate of M6 is connected to the positive phase output voltage V generated by the unbalanced amplifier. CP The gate of M7 is connected to the inverting output voltage V generated by the unbalanced amplifier. CN , the drain of M6 is connected to the drain of M7, the gate of M0, the gate of M1 and the drain of M1, the source of M0 is grounded, the drain of M0 is connected to the source of M1 and generates a voltage V CTAT , M0 uses HVT NMOS tube.

3. The low-temperature drift coefficient voltage reference source with load driving capability according to claim 1, characterized in that: The unbalanced amplifier includes NMOS tubes M2 and M3, PMOS tubes M4 and M5, and a resistor R B , where the gate of M2 is connected to the output voltage V OUT , the drain of M2 is connected to the drain of M4 and the gate of M4 to generate a positive output voltage V CP , the source of M2 and the source of M3 and R B One end is connected to R B The other end of M4 is connected to the ground, the source of M4 is connected to the power supply voltage, and the gate of M3 is connected to the feedback voltage V FB , the drain of M3 is connected to the drain of M5 and the gate of M5 to generate an inverted output voltage V CN , the source of M5 is connected to the power supply voltage.

4. The low-temperature drift coefficient voltage reference source with load driving capability according to claim 1, characterized in that: The time domain amplifier includes a voltage-time conversion circuit and a charge pump. The voltage-time conversion circuit is used to convert the differential output voltage into a pair of pulse signals, and then use the pulse signals to control the charge pump to generate a driving voltage V G .

5. The low-temperature drift coefficient voltage reference source with load driving capability according to claim 4, characterized in that: The voltage-time conversion circuit includes four NMOS tubes M9~M 12 , two PMOS tubes M 13 and M 14 , two capacitors C1 and C2, two skew inverters I0 and I1, seven inverters I2~I7 and I 10 And two NAND gates I8 and I9, where the gate of M9 is connected to the positive phase output voltage V generated by the unbalanced amplifier CP , M 10 The gate of the unbalanced amplifier generates the inverting output voltage V CN , the source of M9 and M 10 The source and M 11 The drain of M 11 The gate is connected to the external clock, M 11 The source and M 12 The drain of M 12 The gate is connected to the external bias voltage, M 12 The source of M9 is grounded, the drain of M9 is connected to one end of C1, M 13 The drain of M is connected to the input of I0. 10 The drain of C2 and one end of M 14 The drain of I1 is connected to the input terminal of M 13 The gate and M 14 The gate of the M 13 The source and M 14 The source of C1, the other end of C2 and the other end of C2 are connected and connected to the power supply voltage, the output end of I0 is connected to the input end of I2, the output end of I2 is connected to the input end of I4, the output end of I4 is connected to the input end of I6 and the first input end of I9, the output end of I6 is connected to the first input end of I8, the output end of I8 generates a pulse signal UP, the output end of I1 is connected to the input end of I3, the output end of I3 is connected to the input end of I5, the output end of I5 is connected to the input end of I7 and the second input end of I8, the output end of I7 is connected to the second input end of I9, the output end of I9 is ​​connected to I 10 The input terminal is connected to I 10 The output end generates a pulse signal DN.

6. The low-temperature drift coefficient voltage reference source with load driving capability according to claim 5, characterized in that: The skew inverters I0 and I1 have the same structure, including a PMOS transistor M I0 And NMOS tube M I1 , where M I0 The gate and M I1 The gate of the skew inverter is connected to the input terminal, M I0 The source is connected to the power supply voltage, M I1 The source is grounded, M I0 The drain and M I1 The drain of M is connected to the output of the skew inverter. I1 Use HVT NMOS tube.

7. The low-temperature drift coefficient voltage reference source with load driving capability according to claim 5, characterized in that: The charge pump includes two PMOS tubes M 15 and M 16 And two NMOS tubes M 17 and M 18 , where M 15 The gate is connected to the external bias voltage, M 15 The source is connected to the power supply voltage, M 15 The drain and M 16 The source of M 16 The gate is connected to the pulse signal UP, M 16 The drain and M 17 The drain is connected to generate the driving voltage V G , M 17 The gate is connected to the pulse signal DN, M 17 The source and M 18 The drain of M 18 The gate is connected to the external bias voltage, M 18 The source is grounded.

8. The low-temperature drift coefficient voltage reference source with load driving capability according to claim 1, characterized in that: The voltage superposition main branch includes a PMOS tube M P , capacitor C C And two resistors R0 and R1, where M P is the load tube, M P The gate and C C One end is connected to the drive voltage V G , M P The drain and C C The other end of R0 is connected to generate the output voltage V OUT , M P The source of R0 is connected to the power supply voltage, and the other end of R0 is connected to one end of R1 to generate a feedback voltage V FB , the other end of R1 is connected to voltage V CTAT .

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