NVME low-delay data transmission control system and method based on FPGA

Abstract

According to the NVME low-delay data transmission control system and method based on the FPGA, multi-disk control over the NVME is achieved by adopting a CPU + FPGA mode, and meanwhile SQ and CQ doorbell operation and interrupt operation of the CPU are transplanted into the FPGA to be processed through the PCIE DMA technology, so that high-speed data transmission of the NVME is achieved; compared with a traditional NVME control system, a part of an NVME protocol stack of a CPU is achieved in an FPGA, the behavior that DDR is frequently read and written when the CPU interacts with the NVME in a traditional architecture is broken through, in addition, it needs to be explained that due to the fact that the CPU depends on execution of interruption when executing commands, interruption storm is faced when multiple disks exist, the CPU cannot be free to execute effective commands, and the CPU cannot be used for executing the effective commands. And the FPGA does not need to execute interruption, so that the interruption pressure of the CPU is reduced to a great extent, and the low-delay effect is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of computer storage systems and hardware acceleration, and particularly relates to an NVMe (Non-Volatile Memory Express) multi-disk control system based on FPGA (Field Programmable Gate Array), which is particularly suitable for data centers, edge computing and high-performance storage scenarios that require high throughput, low latency and multi-disk parallel management. BACKGROUND

[0002] NVMe is a high-performance communication protocol specially designed for flash storage (such as SSD). With the rapid development of NAND flash technology, the physical performance of SSD (such as read / write speed and latency) has been greatly improved. However, the traditional SATA interface and AHCI protocol have become a performance bottleneck. With the rapid iteration of PICE, its high bandwidth and low latency characteristics, combined with NVMe, are deeply loved by consumers.

[0003] In traditional NVMe data transmission, the delay of the data transmission path mainly comes from the following aspects:

[0004] 1. Software protocol stack overhead: I / O requests need to go through multiple layers of processing (system call, memory copy, queue management, etc.) of the operating system kernel driver (such as Linux NVMe driver), introducing microsecond-level delay.

[0005] 2. Interrupt processing delay: Each I / O completion triggers an interrupt (MSI / MSI-X), and in high-concurrency scenarios, interrupt storms cause CPU resource contention.

[0006] 3. Multi-core synchronization overhead: Multi-queue management requires cross-CPU core lock contention and cache consistency maintenance, adding additional delay.

[0007] 4. PCIe transmission limitation: Traditional DMA engine relies on CPU configuration descriptors, and the preparation time for batch data transmission cannot be ignored.

[0008] In order to break through the above bottlenecks, we have implemented an NVMe host control method based on FPGA. This method takes advantage of high-speed serdes technology to expand the PCIe port, enabling multi-disk control. Additionally, we handle some driver overheads in FPGA, greatly reducing the CPU pressure in handling multi-queue parallel IO processing, thereby reducing system latency. SUMMARY

[0009] Therefore, the purpose of the present application is to provide an FPGA-based NVME low-latency data transmission control system and method.

[0010] The FPGA-based NVME low-delay data transmission control system includes logical modules divided by an FPGA chip, which are a downlink SQ queue, an uplink CQ queue, an SQ message processing module, a CQ message processing module, a doorbell control module, a data buffer processing module, and data uplink and downlink channels.

[0011] The downlink SQ queue is configured to form an SQ message by a CPU, transmit the SQ message to the downlink SQ queue of the FPGA through DMA, and transmit complete and valid SQ information to the SQ message processing module after the downlink SQ queue performs DMA packet disassembly on the downlink information.

[0012] The uplink CQ queue is configured to pack a CQ message processed by the CQ message processing module into a DMA message format, and then send the CQ message to a CPU through PCIe.

[0013] The SQ message processing module is configured to analyze an SQ message received from the downlink SQ queue, extract a command type, a tag_id, a data address, a data size, and disk position information from the SQ message, package a new SQ message, store the new SQ message in a specified RAM according to disk position information, and perform a write Doorbell operation to prompt a specified NVME disk to execute the new message.

[0014] The CQ message processing module is configured to send a CQ instruction to indicate that a task is completed after an NVME disk processes a command, send the CQ instruction to the Q message processing module through the data buffer processing module, convert a hard disk CQ message into a specified CQ format in the Q message processing module, and send the CQ message to the uplink CQ queue.

[0015] The doorbell control module is configured to receive prompt information of the SQ message processing module and the CQ message processing module to form a Doorbell instruction for the NVME disk, and each hard disk corresponds to one doorbell control module.

[0016] The data buffer processing module is configured to:

[0017] First, the data buffer processing module receives commands of various hard disks, stores the commands in corresponding buffer areas, analyzes command formats of the NVME according to a scheduling function, and extracts a command type, a read-write address, a read-write size, and hard disk information.

[0018] Second: process new SQ instructions from the SQ message processing module, package them into PCIE format, and send them to the specified hard disk according to the previously parsed hard disk information;

[0019] Third: receive CQ information from the hard disk and pass it to the CQ message processing module;

[0020] Fourth: receive read and write commands from the hard disk, and according to the address and length in them, initiate DMA operation on the CPU through data upload and download channels to read the data cached in the CPU or write it into the CPU buffer.

[0021] A data transmission control method of an NVME low-latency data transmission control system based on FPGA, including a write data operation, specifically:

[0022] Step 1, the CPU writes data in its internal buffer, then forms an SQ instruction, which includes the CPU-recognized tag_id, command type for write operation, data address, data size, disk position information and command sequence number information;

[0023] Step 2, notify the SQ queue that there is a command to take, the SQ queue will take the SQ message formed by the CPU through DMA operation, then disassemble the DMA package, and send the effective SQ information to the SQ message processing module;

[0024] Step 3, the SQ message processing module first parses the SQ message to parse the data address and data size, as well as the disk position information, then forms a new SQ message, writes the SQ message into the specified RAM according to the disk position information of the SQ, and sends the updated SQ queue command to the specified doorbell control module;

[0025] Step 4, the corresponding doorbell control module receives the updated SQ queue command, forms a PCIE format, and sends the updated SQ queue command to the corresponding NVME disk, at this time, the corresponding NVME disk knows that there is a new command to process;

[0026] Step 5, the NVME disk initiates a read instruction, which is recognized by the data buffer processing module through the NVME interface and stored in the buffer area corresponding to its disk position, then sequentially reads the read instruction sent by the NVME disk from the buffer area through internal scheduling, identifies the disk position information according to the scheduling function, then transmits it to the SQ message processing module according to the disk position information to read the SQ message previously stored in the RAM, then assembles the SQ command into PCIE format and sends it to the specified hard disk;

[0027] Step 6, the hard disk receives the read SQ message for write operation instruction, and then initiates a read command again, the read command is to read the data content to be written into the hard disk;

[0028] Step 7, the read command is written into the received command buffer area of the data buffer processing module, and then the current NVME disk command is processed through scheduling, the data address and data size in the read command are recognized by the module, the read DMA command format is constructed, the read DMA operation is initiated, and then the CPU sends the data to the data buffer processing module through the data delivery channel;

[0029] Step 8, after the data buffer processing module receives the read data, the effective data content is parsed by first resolving the DMA package, and then the data is assembled into the PCIE format, and the data to be written into the hard disk is sent to the specified hard disk through the scheduling function;

[0030] Step 9, after the hard disk receives the data to be written, a CQ instruction is sent to indicate that the command has been executed, the instruction is processed by the data buffer processing module, and the CQ message is uploaded to the CQ message processing module, the CQ message processing module converts the CQ message into a specified format, and reports the CQ queue to form a DMA package, and reports the CQ message to the CPU, at the same time, sends an update CQ doorbell operation to the specified doorbell control module, the doorbell control module converts the update CQ queue instruction into PCIE format and sends it to the specified NVME disk, thus a complete write data operation is completed.

[0031] It also includes read data operation, specifically:

[0032] Step 1, the CPU prepares a buffer area to receive read data, and then constructs an SQ instruction, which includes tag_id recognized by the CPU, command type for read operation, prepared data address, data size to be read, disk position number and command sequence number information;

[0033] Step 2, notify the SQ queue to issue, there is a command to take, the SQ queue will take away the SQ message constructed by the CPU through DMA operation, and send the effective SQ message to the SQ message processing module after resolving the read DMA package;

[0034] Step 3, the SQ message processing module first parses the SQ message to parse the data address and data size, as well as the disk position information, then constructs a new SQ message, writes the SQ message into the specified RAM buffer according to the disk position information of the SQ message, and sends the update SQ queue command to the specified doorbell control module;

[0035] Step 4, after the corresponding doorbell control module receives the command of updating the SQ queue, the PCIE format is formed, the updating SQ queue command is sent to the corresponding NVME disk, at this time, the corresponding NVME disk knows that there is a new command to be processed;

[0036] Step 5, the NVME disk initiates a read instruction, through the NVME interface, is recognized by the data buffer processing module, is stored in the buffer area corresponding to the disk position, then is read out from the buffer area by the internal scheduling, the read instruction sent by the NVME disk is recognized according to the scheduling function to identify the disk position information, then is transmitted to the SQ message processing module according to the disk position information to read the SQ message previously stored in the RAM, and then the SQ command is assembled into the PCIE format and is sent to the specified hard disk;

[0037] Step 6, the hard disk receives the read-out SQ message as a read operation instruction, and then prepares to read out the data, and then initiates a write instruction to the data buffer processing module;

[0038] Step 7, after the data buffer processing module receives the write operation instruction, the write operation instruction is first written into the buffer area, then the command of the current NVME disk is processed through scheduling, the data address and the data size in the write instruction are recognized by the module, the write DMA command format is formed, the write DMA operation is initiated through the data uploading channel, and the data to be written by the hard disk is written into the CPU;

[0039] Step 8, after the hard disk reads out the data, a CQ instruction is sent to indicate that the command has been executed, the CQ message is uploaded to the CQ message processing module through the data buffer processing module scheduling processing, the CQ message processing module converts the CQ message into a specified format, a DMA package is formed through the reporting CQ queue, the CQ message is reported to the CPU, at the same time, an updating CQ doorbell operation is sent to the specified doorbell control module, the doorbell control module converts the updating CQ queue instruction into the PCIE format and then sends it to the NVME disk, and thus a complete read data operation is completed.

[0040] The application has the following beneficial effects:

[0041] The application adopts the CPU+FPGA mode, realizes the multi-disk control of the NVME, and transplants the SQ and CQ doorbell operations and the interrupt operation of the CPU into the FPGA for processing through the PCIE DMA technology, so that the high-speed data transmission of the NVMe is realized.

[0042] With Figure 1Compared with the traditional NVME control system architecture shown, the part of the CPU NVME protocol stack of the application is implemented in the FPGA, and the innovation of the application is that the frequent reading and writing of DDR when the CPU interacts with the NVME in the traditional architecture is broken, in addition, it should be noted that since the CPU executes the command by relying on the execution of the interrupt, when multiple disks are used, an interrupt storm will be faced, which causes the CPU to be unable to idle to execute effective commands, and the FPGA does not need to execute the interrupt, therefore, the interrupt pressure of the CPU is greatly reduced, thereby realizing the effect of low delay. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 For the traditional NVME data transmission control system architecture;

[0044] Figure 2 For the NVME low-delay data transmission control system architecture of the application. DETAILED DESCRIPTION

[0045] The application will be described in detail below with reference to the drawings and examples.

[0046] The application provides an FPGA-based NVME low-delay data transmission control system, which uses an FPGA chip to avoid the multi-queue synchronization overhead and interrupt storm faced by the CPU when multiple disks are used.

[0047] When the CPU faces the processing of small data blocks of multiple disks, the DDR data buffer will be frequently read and written, which will be a relatively large time overhead, when the hard disk completes the command, an interrupt instruction will be sent to prompt the CPU to end the current process, if the small data block reading and writing are executed, a large number of interrupts will be faced, which causes the CPU to be busy in processing the interrupts and unable to idle to process new commands.

[0048] Figure 2 As shown, the application provides an FPGA chip-based NVMe low-delay data transmission method, and the logic modules of the FPGA chip mainly include: a downward SQ queue, an upward CQ queue, an SQ message processing module, a CQ message processing module, a doorbell control module, a data buffer processing module, and a data upward channel and a downward channel.

[0049] The application realizes the data communication between the CPU and the FPGA based on the PCIE DMA technology, and the functions of each module are described below.

[0050] The downward SQ queue: the CPU forms the SQ message, and transmits it to the downward SQ queue of the FPGA through the DMA, in the queue, since the effective information is encapsulated in the DMA package, the module first performs the DMA package on the downward effective information, and then transmits the complete effective SQ information to the SQ message processing module.

[0051] Report CQ queue: when the NVME disk processes the data, a completed CQ message is returned, and the module packs the CQ message processed by the CQ message processing module into a DMA message format, and then sends it to the CPU through PCIe.

[0052] SQ message processing module: after receiving the SQ message transmitted from the SQ queue, the module analyzes the SQ message and extracts the command type, tag_id, data address, data size, disk position information (including disk position number and instruction sequence number) and other information. Then, through processing, the new SQ message is packaged and stored in the specified RAM according to its disk position information, and at the same time, the write Doorbell operation is executed to prompt the specified NVME disk that a new message needs to be executed. After receiving the Doorbell instruction, the NVME disk sends a read instruction to read the SQ message stored in the RAM through the data buffer processing module.

[0053] CQ message processing module: when the NVME disk processes a command, it sends a CQ instruction to indicate that the task is completed. After the CQ instruction passes through the data buffer processing module, it is sent to the module. In this module, the CQ message of the hard disk is converted into the specified CQ format, and then sent to the report CQ queue. At the same time, the doorbell control module is used to update the CQ queue of the specified NVME disk to indicate that the current CQ processing is completed.

[0054] Doorbell control module: this module mainly receives the prompt information of the SQ message processing module and the CQ message processing module to form the Doorbell instruction of the NVME disk. Each hard disk corresponds to a doorbell control module.

[0055] Data buffer processing module: this module has three functions, first: receiving commands from various hard disks and storing them in the corresponding buffer area, according to the scheduling function, analyzing the command format sent by the NVME, extracting the command type, read / write address, read / write size, and hard disk information (including disk position number and instruction sequence number); second: processing new SQ instructions from the SQ message processing module, packaging them into PCIE format, and sending them to the specified hard disk according to the previously analyzed hard disk information; third: receiving CQ information from the hard disk and transmitting it to the CQ message processing module; fourth: receiving read and write commands from the hard disk, and according to the address and length, initiating DMA operation to the CPU through data upload and download channels to read the data cached in the CPU or write it to the CPU buffer area.

[0056] The working process of the present application will be described below through the read / write flow.

[0057] Taking the write data operation as an example, the working process is as follows:

[0058] Step 1, the CPU writes data in its internal buffer, and then forms an SQ instruction, which includes the tag_id recognized by the CPU, the command type, the data address, the data size, the disk position information of the disk to which the command is sent, and the command sequence number, etc.

[0059] Step 2, the SQ queue is notified that a command needs to be taken, and the SQ queue will take the SQ message formed by the CPU through DMA operation, then disassemble the DMA package, and send the effective SQ information to the SQ message processing module.

[0060] Step 3, the SQ message processing module first parses the SQ message to parse the data address and data size, and disk position information, etc., and then forms a new SQ message, writes the SQ message into the specified RAM cache according to the disk position information of the SQ, and sends the command to update the SQ queue to the specified doorbell control module.

[0061] Step 4, the corresponding doorbell control module receives the command to update the SQ queue, forms a PCIE format, and sends the command to update the SQ queue to the corresponding NVME disk. At this time, the corresponding NVME disk knows that a new command needs to be processed.

[0062] Step 5, the NVME disk initiates a read instruction through the NVME interface, which is recognized by our data buffer and stored in the buffer corresponding to its disk position. Then, through internal scheduling, the read instruction sent by the NVME disk is read out from the buffer in order. We can identify the disk position information according to the scheduling function, and then transmit it to the SQ message processing module according to the disk position information to read the SQ message previously stored in the RAM, and then assemble the SQ command into a PCIE format and send it to the specified hard disk.

[0063] Step 6, the hard disk receives the read SQ message as a write operation instruction, and then initiates a read command again. The read command at this time is to read the data content to be written into the hard disk (the data address and data size are contained in the SQ message package, so the NVME disk knows where to read the data and how much data to read).

[0064] Step 7, the read command is written into the received command buffer of the data buffer processing module, and then through scheduling, the current NVME disk command is processed. This module identifies the data address and data size in the read command, forms a read DMA command format, initiates a read DMA operation, and then the CPU sends the data to the data buffer processing module through the data delivery channel.

[0065] Step 8, after receiving the read data, the data buffer processing module first unpacks the DMA package, parses the valid data content, and then assembles the data into the format of PCIE. The data to be written by the hard disk is sent to the specified hard disk through the scheduling function.

[0066] Step 9, after receiving the data to be written, the hard disk sends a CQ instruction to indicate that the command has been executed. The instruction is processed by the data buffer processing module and uploaded to the CQ message processing module. The CQ message processing module converts the CQ message into the specified format and reports the CQ queue to form a DMA package. The CQ message is reported to the CPU, and at the same time, the CQ doorbell update operation is sent to the specified doorbell control module. The doorbell control module converts the CQ queue update instruction into PCIE format and sends it to the specified NVME disk. Thus, a complete write operation is completed.

[0067] Taking the read data operation as an example, the workflow is as follows:

[0068] Step 1, the CPU prepares a buffer area to receive read data, and then constructs an SQ instruction, which includes the tag_id recognized by the CPU, the command type for read operation, the prepared data address, the data size to be read, the disk position number and the command sequence number, etc.

[0069] Step 2, notify the SQ queue that there is a command to be taken. The SQ queue will take the SQ message constructed by the CPU through DMA operation, unpack the read DMA package, and send the valid SQ message to the SQ message processing module.

[0070] Step 3, the SQ message processing module first parses the SQ message to obtain the data address, data size, disk position information, etc. Then it constructs a new SQ message, writes the SQ message into the specified RAM buffer according to the disk position information of the SQ, and sends the update SQ queue command to the specified doorbell control module.

[0071] Step 4, after receiving the update SQ queue command, the corresponding doorbell control module constructs PCIE format and sends the update SQ queue command to the corresponding NVME disk. At this time, the corresponding NVME disk knows that there is a new command to be processed.

[0072] Step 5, the NVME disc initiates a read instruction, which is recognized by our data buffer through the NVME interface and stored in the buffer corresponding to the disc position, and then read out in order from the buffer through internal scheduling, and the disc position information can be identified according to the scheduling function, and then transmitted to the SQ message processing module according to the disc position information to read the SQ message previously stored in the RAM, and then the SQ command is assembled into a PCIE format and sent to the specified hard disk.

[0073] Step 6, the hard disk receives the read SQ message as a read operation instruction, and then prepares to read the data, and then initiates a write instruction to the data buffer processing module (the data address and data size are included in the SQ message packet, so the NVME disc knows where to write the data and how much data to write).

[0074] Step 7, after receiving the write operation instruction, the data buffer processing module writes to the buffer first, and then schedules the current NVME disc command, and the module identifies the data address and data size in the write instruction to form the write DMA command format, and initiates the write DMA operation through the data upload channel to write the data to be written by the hard disk into the CPU.

[0075] Step 8, after the hard disk reads the read data, it will send a CQ instruction to indicate that the command has been executed. The instruction is scheduled and processed by the data buffer processing module, and the CQ message is uploaded to the CQ message processing module, and the CQ message processing module converts the CQ message into the specified format, and uploads the CQ message to the CPU through the reporting CQ queue to form a DMA packet, and sends an update CQ doorbell operation to the specified doorbell control module, and the doorbell control module converts the update CQ queue instruction into a PCIE format and sends it to the NVME disc. Thus, a complete read operation is completed.

[0076] With Figure 1 Compared with the traditional NVME control system architecture as shown in the figure, the application implements part of the NVME protocol stack of the CPU in the FPGA, and the innovation of the application is to break the frequent read and write of DDR when the CPU interacts with the NVME in the traditional architecture. In addition, it should be noted that since the CPU executes commands by relying on interrupts, when multiple discs are used, an interrupt storm will occur, which will cause the CPU to be unable to idle to execute effective commands. Therefore, the FPGA does not need to execute interrupts, thereby greatly reducing the interrupt pressure of the CPU, thereby achieving a low delay effect.

[0077] In summary, the above is only a preferred embodiment of the application, and is not used to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. FPGA-based NVME low-latency data transmission control system, characterized by: The logic modules divided by the FPGA chip include: downlink SQ queue, uplink CQ queue, SQ message processing module, CQ message processing module, doorbell control module, data buffer processing module, and data uplink and downlink channels; The sending SQ queue is used for: the CPU forms an SQ message and transmits it to the sending SQ queue of the FPGA through DMA; the sending SQ queue first de-DMAs the valid information sent, and then transmits the complete valid SQ information to the SQ message processing module; The reporting CQ queue is used to: when the NVME disk finishes processing the data, it will reply with a completed CQ message. This module packages the CQ message processed by the CQ message processing module according to the DMA message format, and then sends it to the CPU through PCIe; The SQ message processing module is used to: after receiving the SQ message from the SQ queue, this module parses the SQ message and extracts the command type, tag_id, data address, data size, and disk location information; then, through processing, the new SQ message is packaged and stored in the specified RAM according to its disk location information. At the same time, a write doorbell operation is performed to prompt the specified NVME disk that there is a new message to be executed. After receiving the doorbell instruction, the NVME disk will send a read instruction to read the SQ message stored in the RAM through the data buffer processing module; The CQ message processing module is used to: when the NVME disk completes processing a command, it will send a CQ instruction to indicate that the task is completed. After the CQ instruction passes through the data buffer processing module, it is sent to the Q message processing module. In this module, the CQ message of the hard disk is converted into a specified CQ format and then sent to the reporting CQ queue. At the same time, the CQ queue of the specified NVME disk will be updated through the doorbell control module to indicate that the current CQ processing is completed; The doorbell control module is used to receive prompt information from the SQ message processing module and the CQ message processing module to form a Doorbell instruction to write to the NVME disk. Each hard disk corresponds to a doorbell control module. The data buffer processing module is used for: First: Receive commands from each hard drive and store them in the corresponding buffer. According to the scheduling function, parse the command format sent by NVME and extract the command type, read and write address, read and write size, and hard drive information. Second: Process the new SQ instruction from the SQ message processing module, package it into PCIE format, and send it to the specified hard disk according to the previously parsed hard disk information; Third: Receive CQ information from the hard disk and transparently transmit it to the CQ message processing module; Fourth: Receive the read and write commands from the hard disk, and according to the address and length, initiate DMA operations on the CPU through the data upload and download channels to read the data cached in the CPU or write it to the CPU buffer.

2. A data transmission control method for the NVME low-latency data transmission control system based on FPGA according to claim 1, characterized in that, Including write data operations, specifically: Step 1: The CPU writes the data into its internal buffer and then forms an SQ instruction, which includes the tag_id recognized by the CPU, the command type (write operation), the data address, the data size, the disk slot information, and the command sequence number information; Step 2: Notify the SQ queue that there is a command to be taken. The SQ queue will take the SQ message formed by the CPU through DMA operation, then decompress the DMA package and send the valid SQ information to the SQ message processing module. Step 3: The SQ message processing module first parses the SQ message to obtain its data address, data size, and disk location information, then constructs a new SQ message, writes the SQ message to the designated RAM cache based on the SQ disk location information, and sends the command to update the SQ queue to the designated doorbell control module; Step 4: After receiving the command to update the SQ queue, the corresponding doorbell control module forms a PCIE format and sends the command to the corresponding NVME disk. At this time, the corresponding NVME disk knows that there is a new command to be processed; Step 5: The NVME disk initiates a read command, which is recognized by the data buffer processing module through the NVME interface and stored in the buffer corresponding to its disk position. Then, after internal scheduling, the read command sent by the NVME disk is read out from the buffer in an orderly manner. The disk position information is identified according to the scheduling function. Then, the SQ message processing module is transparently transmitted to read the SQ message previously stored in RAM according to the disk position information. The SQ command is then assembled into PCIE format and sent to the designated hard disk. Step 6: The hard disk receives the read SQ message as a write operation instruction, and then initiates a read command again. This read command is to read the data to be written to the hard disk; Step 7: The read command is written into the receive command buffer of the data buffer processing module, and then the command of the current NVME disk is processed after scheduling. This module identifies the data address and data size in the read command, constitutes the command format of the read DMA, initiates the read DMA operation, and then the CPU sends the data to the data buffer processing module through the data delivery channel; Step 8: After receiving the read data, the data buffer processing module first unpacks the DMA package, parses the valid data content, and then assembles the data into the PCIE format. The data to be written to the hard disk is sent to the designated hard disk through the scheduling function; Step 9. After the hard disk receives the data to be written, it sends a CQ instruction to indicate that the command has been executed. The instruction is scheduled and processed by the data buffer processing module, and the CQ message is uploaded to the CQ message processing module. The CQ message processing module converts the CQ message into a specified format, forms a DMA packet by reporting the CQ queue, and reports the CQ message to the CPU. At the same time, the operation of updating the CQ doorbell is sent to the specified doorbell control module. The doorbell control module converts the update CQ queue instruction into PCIE format and sends it to the specified NVME disk. At this point, a complete data write operation is completed.

3. The data transmission control method according to claim 2, wherein: It also includes data read operations, specifically: Step 1: The CPU prepares a buffer to receive the read data, and then constructs an SQ instruction, which includes the tag_id recognized by the CPU, the command type is a read operation, the prepared data address, the size of the data to be read, the disk location number, and the command sequence number information; Step 2: Notify the SQ queue that a command needs to be retrieved. The SQ queue will take the SQ message formed by the CPU through DMA operation, decapsulate the read DMA packet, and send the valid SQ message to the SQ message processing module; Step 3: The SQ message processing module first parses the SQ message to obtain its data address, data size, and disk location information, then constructs a new SQ message. Based on the disk location information of the SQ message, the SQ message is written to the designated RAM cache and the command to update the SQ queue is sent to the designated doorbell control module. Step 4: After receiving the command to update the SQ queue, the corresponding doorbell control module forms a PCIE format and sends the command to the corresponding NVME disk. At this time, the corresponding NVME disk knows that there is a new command to be processed; Step 5: The NVME disk initiates a read command, which is recognized by the data buffer processing module through the NVME interface and stored in the buffer corresponding to its disk position. Then, after internal scheduling, the read command sent by the NVME disk is read from the buffer, and the disk position information is identified according to the scheduling function. Then, the SQ message processing module is transparently transmitted to read the SQ message previously stored in RAM according to the disk position information. The SQ command is then assembled into PCIE format and sent to the specified hard disk. Step 6: The hard disk receives the read SQ message as a read operation instruction, prepares the data to be read, and then issues a write instruction to the data buffer processing module; Step 7: After receiving the write operation instruction, the data buffer processing module first writes it into the buffer, and then processes the command of the current NVME disk through scheduling. This module identifies the data address and data size in the write instruction, forms the command format of the write DMA, and initiates the write DMA operation through the data upload channel to write the data to the hard disk into the CPU; Step 8. After the hard disk finishes reading the read data, it sends a CQ instruction to indicate that the command has been executed. The instruction is scheduled and processed by the data buffer processing module, and the CQ message is uploaded to the CQ message processing module. The CQ message processing module converts the CQ message into a specified format, forms a DMA packet by reporting the CQ queue, and reports the CQ message to the CPU. At the same time, the operation of updating the CQ doorbell is sent to the specified doorbell control module. The doorbell control module converts the update CQ queue instruction into PCIE format and sends it to the NVME disk. At this point, a complete data read operation is completed.

Images