A modular multiplication circuit suitable for various modular multiplication algorithms

Abstract

The application relates to the field of information security hardware circuit, in particular to a modular multiplication circuit suitable for various modular multiplication algorithms. The modular multiplication circuit comprises a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a Wallace compression tree adder, a modulus correction unit and a first MUX selector. Data is first split into byte data, then 4 2^8 ordinary modular multiplication results are obtained through the 16-way parallel 8-bit multiplier, then 2 2^16 ordinary modular multiplication results are obtained through the 4-way parallel 32-bit adder, then 1 2^32 ordinary modular multiplication result is obtained through the Wallace compression tree adder, the ordinary modular multiplication results are corrected by the modulus correction unit to obtain special modular multiplication results, and finally the final result is output through the first MUX selector. The modular multiplication circuit structure is proposed in the form of hardware multiplexing, different numbers and bit width types of modular multiplication operations are supported, and the resource utilization rate of the hardware circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of information security hardware circuit, and particularly relates to a modular multiplication circuit suitable for multiple modular multiplication algorithms. BACKGROUND

[0002] With the development of information technology, people pay more and more attention to information security. By encrypting and decrypting information data, information can be protected from being leaked, and information security can be protected. In many cryptographic algorithms, bit operation, S-box lookup table, data cyclic shift, modular addition operation and modular multiplication operation are needed in the encryption and decryption process. Modular multiplication operation, as a module that occupies a large resource, needs to be optimized and improved in the case of on-chip resource shortage. Modular multiplication operation appears in multiple algorithms, and different types of modular multiplication are used in different algorithms. For example, ordinary modular multiplication is used in MARS algorithm, RC6 algorithm and E2 algorithm, and special modular multiplication is used in IDEA algorithm and MMB algorithm.

[0003] 2^8, 2^16 and 2^32 type modular multiplication are called ordinary modular multiplication, and 2^8+1, 2^16+1 and 2^32-1 type modular multiplication are called special modular multiplication, which are based on the multiplication of 2^8, 2^16 and 2^32 type modular multiplication and then perform a modular correction operation. The modular multiplication circuits existing on the market are as follows: 1. Traditional modular multiplication circuit, which realizes single type of modular multiplication for single cryptographic algorithm. 2. Large bit width modular multiplication circuit, which is compatible with small bit width and can realize modular multiplication of the same type with different bit widths. 3. Reconfigurable modular multiplication circuit, which integrates circuits of different types of modular multiplication. 4. Special modular multiplication circuit, which adds a modular correction unit based on the ordinary modular multiplication circuit.

[0004] The traditional modular multiplication circuit is only suitable for fixed algorithms and cannot realize multiple types of modular multiplication. When the cryptographic algorithm is switched, the current modular multiplication circuit cannot be adapted. The circuit is fast, but has poor compatibility. The large bit width modular multiplication circuit is a hardware optimized modular multiplication circuit to reduce the resource area of the modular multiplication circuit. By implementing a large bit width modular multiplication circuit, small bit width modular multiplication operations can be compatible. However, when small bit width operations are performed, part of the hardware is idle, resulting in low resource utilization. The reconfigurable modular multiplication circuit is adapted to different cryptographic algorithms by integrating different types of modular multiplication to match different cryptographic algorithms. The compatibility is good, but the resource occupation rate is high. The special modular multiplication circuit performs modular correction operation based on the ordinary modular multiplication. Currently, the circuit supporting special modular multiplication generally adopts the circuit form of ordinary modular multiplication cascaded with ordinary addition and subtraction, which has poor compatibility and slow speed. SUMMARY

[0005] In view of the defects of the prior art, the application relates to a modular multiplication circuit suitable for various modular multiplication algorithms, which can be compatible with different types of modular multiplication operations in commonly used cryptographic algorithms, and optimizes hardware circuits in the form of hardware multiplexing, proposes a serial-parallel modular multiplication circuit structure, supports modular multiplication operations of different quantities and bit widths, and improves the resource utilization rate of hardware circuits.

[0006] In order to solve the technical problem, the application adopts the technical scheme of a modular multiplication circuit suitable for various modular multiplication algorithms, which comprises a 4-way parallel 32-bit adder, a Wallace compression tree adder and a first MUX selector, the input end of a 16-way parallel 8-bit multiplier is connected with the operation number of the modular multiplication algorithm, the output end of the 16-way parallel 8-bit multiplier is connected with the input end of the 4-way parallel 32-bit adder or the input end of the first MUX selector, the input end of the 4-way parallel 32-bit adder is connected with the output end of the 16-way parallel 8-bit multiplier, the output end of the 4-way parallel 32-bit adder is connected with the input end of the Wallace compression tree adder or the input end of the first MUX selector, the input end of the Wallace compression tree adder is connected with the output end of the 4-way parallel 32-bit adder, the output end of the Wallace compression tree adder is connected with the input end of the first MUX selector, the gating end of the first MUX selector is connected with the modular multiplication type instruction, the modular multiplication result is obtained at the output end of the first MUX selector according to the modular multiplication type instruction; when the modular multiplication operation is performed, the two operation numbers of the modular multiplication algorithm are split into byte data, the 16-way parallel 8-bit multiplier completes the multiplication of the byte data two by two, the 4-way parallel 32-bit adder, the Wallace compression tree adder and the first MUX selector complete the combination of the two-by-two multiplication results, so that the modular multiplication results of different types are obtained.

[0007] Further, the module correction unit comprises a second MUX selector, a third MUX selector, a 32-bit inversion circuit, a fourth MUX selector and a module addition and subtraction circuit, the input end of the second MUX selector is connected with the high 32-bit data output by the 16-way parallel 8-bit multiplier, the high 32-bit data output by the 4-way parallel 32-bit adder and the high 32-bit data output by the Wallace compression tree adder, the input end of the third MUX selector is connected with the low 32-bit data output by the 16-way parallel 8-bit multiplier, the low 32-bit data output by the 4-way parallel 32-bit adder and the low 32-bit data output by the Wallace compression tree adder, the 32-bit inversion circuit is connected between the output end of the second MUX selector and one input end of the fourth MUX selector, the other input end of the fourth MUX selector is connected with the output end of the second MUX selector, the input end of the module addition and subtraction circuit is connected with the output end of the fourth MUX selector and the output end of the third MUX selector respectively, and the output end of the module addition and subtraction circuit is connected with the input end of the first MUX selector; the gating end of the second MUX selector and the third MUX selector is connected with the operation type instruction link, the gating end of the fourth MUX selector is connected with the operation type instruction type, the correction end of the module addition and subtraction circuit is connected with the operation type instruction link and the operation type instruction type, the operation type instruction link indicates the operation way, if the link indicates that the 4-way operation is to be performed, the second MUX selector outputs the high 32-bit data output by the 16-way parallel 8-bit multiplier, the third MUX selector outputs the low 32-bit data output by the 16-way parallel 8-bit multiplier, if the link indicates that the 2-way operation is to be performed, the second MUX selector outputs the high 32-bit data output by the 4-way parallel 32-bit adder, the third MUX selector outputs the low 32-bit data output by the 4-way parallel 32-bit adder, if the link indicates that the 1-way operation is to be performed, the second MUX selector outputs the high 32-bit data output by the Wallace compression tree adder, the third MUX selector outputs the low 32-bit data output by the Wallace compression tree adder, the operation type instruction type takes the value including 2^M+1 and 2^N-1, M=8 or 16, N=32, when the type=2^M+1, the fourth MUX selector outputs the inverted data of the second MUX output, when the type=2^N-1, the fourth MUX selector outputs the data of the second MUX output; the second MUX selector, the third MUX selector, the 32-bit inversion circuit, the fourth MUX selector select the corresponding data according to the operation type instruction link and the operation type instruction type, the module addition and subtraction circuit corrects the received data to obtain the special module multiplication result, and transmits the special module multiplication result to the first MUX selector, and the first MUX selector gives the module multiplication result according to the module multiplication type instruction.

[0008] Further, the modulo adder-subtracter includes a threshold correction circuit and four 8-bit correction adders, the four 8-bit correction adders are cascaded, the cin of each 8-bit correction adder is selected between the cout of the previous adder and a constant 0 according to the operation type instruction type, the high 32-bit data and the low 32-bit data are both split into byte data, the split byte data are transmitted to the four 8-bit correction adders respectively, the 8-bit correction adder obtains the output result OUT[7:0] = {H[7] ^ L[7] ^ cout, H[6:0] + L[6:0]} and the correction carry Y = (H[7] & L[7] | H[7] & cout | L[7] & cout) according to the input, H[7] represents the 8th bit of the split byte data of the high 32-bit data, H[6:0] represents the 0th to 6th bits of the split byte data of the high 32-bit data, L[7] represents the 8th bit of the split byte data of the low 32-bit data, L[6:0] represents the 0th to 6th bits of the split byte data of the low 32-bit data, | represents OR operation, ^ represents XOR operation, & represents AND operation, and cout represents the carry generated by adding H[6:0] and L[6:0] and cin, the output result and the correction carry of the four 8-bit correction adders are transmitted to the threshold correction circuit, the threshold correction circuit corrects the modulo multiplication result according to the operation type instruction link and the operation type instruction type, the correction mode is to sum the output result and the correction carry, the sum result is recorded as F, for 2^M + 1, if Y = 1, the corrected result is F + 1, otherwise the corrected result is F, for 2^N - 1, if Y = 1 or OUT is equal to all 1s, the corrected result is F + 1, otherwise the corrected result is F, M = 8 or 16, and N = 32.

[0009] Further, the 8-bit correction adder includes a Y function module, an adder, a first XOR gate, a second XOR gate and a splicer, the input of the Y function module is H[7], L[7], cout and the operation type instruction type, the Y function module performs Y function operation on the input and generates the correction carry Y = (H[7] & L[7] | H[7] & cout | L[7] & cout), the input of the adder is connected with H[6:0], L[6:0] and cin, cin is the carry input from the outside or the low bit, the output of the adder has two parts, one part is the low 7 bits of the sum of the input data, which is directly transmitted to one input end of the splicer, the other part is the carry cout of the sum of the input data, which is transmitted to the other input end of the splicer after passing through the first XOR gate and the second XOR gate and performing XOR operation with H[7] and L[7], the splicer splices the data of the two input ends into 8 bits to obtain the output result OUT[7:0] = {H[7] ^ L[7] ^ cout, H[6:0] + L[6:0]} of the 8-bit correction adder.

[0010] Further, the logical expression of the 2^8 modulo multiplication algorithm is C[7:0]=(A[7:0]*B[7:0])[7:0], which is completed by a 16-way parallel 8-bit multiplier and a first MUX selector;

[0011] The logical expression of the 2^8+1 modulo multiplication algorithm is C[7:0]=mold_and1_correct(A[7:0]*B[7:0]), which is completed by a 16-way parallel 8-bit multiplier, a modulo correction unit and a first MUX selector;

[0012] Wherein A and B are two operands of the 2^8 or 2^8+1 modulo multiplication algorithm, A[7:0] represents the 0th to 7th bits of the operand A, B[7:0] represents the 0th to 7th bits of the operand B, C[7:0] represents the modulo multiplication result, the low 8 bits of the product of A[7:0] and B[7:0] is the 2^8 modulo multiplication result, the 2^8 modulo multiplication result is obtained through the modulo correction unit to obtain the 2^8+1 modulo multiplication result, and mold_and1_correct is a 2^8+1 type modulo correction function.

[0013] Further, the circuit implements the K-way 2^8 or 2^8+1 modulo multiplication algorithm at a time, and K=1 or 2 or 3 or 4;

[0014] The implementation process of the K-way 2^8 modulo multiplication algorithm is that the operands of the K-way 2^8 modulo multiplication algorithm are split into K groups of byte data, each group of byte data includes two 8-bit numbers, the K groups of byte data are multiplied by each other through a 16-way parallel 8-bit multiplier to obtain byte multiplication results, the byte multiplication results representing 8-bit multiplication results are transmitted to a first MUX selector, and the first MUX selector outputs the 2^8 modulo multiplication result according to the modulo multiplication type instruction;

[0015] The implementation process of the K-way 2^8+1 modulo multiplication algorithm is that the operands of the K-way 2^8+1 modulo multiplication algorithm are split into K groups of byte data, each group of byte data includes two 8-bit numbers, the K groups of byte data are multiplied by each other through a 16-way parallel 8-bit multiplier to obtain byte multiplication results, the byte multiplication results representing 8-bit multiplication results are transmitted to a modulo correction unit, the modulo correction unit corrects the received data and transmits the correction result to a first MUX selector, and the first MUX selector outputs the 2^8+1 modulo multiplication result according to the modulo multiplication type instruction.

[0016] Further, the logical expression of the 2^16 modulo multiplication algorithm is C[15:0]=(A[15:0]*B[15:0])[15:0], which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder and a first MUX selector;

[0017] The logical expression of the 2^16+1 modulo multiplication algorithm is C[15:0]=mold_and1_correct(A[15:0]*B[15:0]), which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a modulo correction unit and a first MUX selector;

[0018] Wherein, A and B are two operands of the 2^16 or 2^16+1 modulo multiplication algorithm, A[15:0] represents the 0th to 15th bits of the operand A, B[15:0] represents the 0th to 15th bits of the operand B, C[15:0] represents the modulo multiplication result, the low 16 bits of the product of A[15:0] and B[15:0] is the 2^16 modulo multiplication result, the 2^16 modulo multiplication result is obtained through the modulo correction unit to obtain the 2^16+1 modulo multiplication result, and mold_and1_correct is a 2^16+1 type modulo correction function.

[0019] Further, the circuit can implement the J-way 2^16 modulo multiplication algorithm or the J-way 2^16+1 modulo multiplication algorithm at a time, and J=1 or 2;

[0020] The implementation process of the J-way 2^16 modulo multiplication algorithm is as follows: the operands of the J-way 2^16 modulo multiplication algorithm are split into 2J groups of byte data, each group of byte data includes two 8-bit numbers, the 2J groups of byte data are multiplied by each other through the 16-way parallel 8-bit multiplier to obtain byte multiplication results, the byte multiplication results representing the low 16 bits of the 16-bit multiplication results are taken, the byte multiplication results are shifted according to the carry relationship between different bits, the shifted results are transmitted to the 4-way parallel 32-bit adder, the 4-way parallel 32-bit adder adds the input data and transmits the addition result to the first selector, and the first MUX selector outputs the multiplication result according to the type of the multiplication instruction.

[0021] The implementation process of the J-way 2^16+1 modulo multiplication algorithm is as follows: the operands of the J-way 2^16+1 modulo multiplication algorithm are split into 2J groups of byte data, each group of byte data includes two 8-bit numbers, the 2J groups of byte data are multiplied by each other through the 16-way parallel 8-bit multiplier to obtain byte multiplication results, the byte multiplication results representing the low 16 bits of the 16-bit multiplication results are taken, the byte multiplication results are shifted according to the carry relationship between different bits, the shifted results are transmitted to the 4-way parallel 32-bit adder, the 4-way parallel 32-bit adder adds the input data and transmits the addition result to the modulo correction unit, the modulo correction unit corrects the received data and transmits the corrected result to the first selector, and the first MUX selector outputs the multiplication result according to the type of the multiplication instruction.

[0022] Further, the logical expression of the 2^32 modulo multiplication algorithm is C[31:0]=(A[31:0]*B[31:0])[31:0], which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a Wallace compression tree adder and a first MUX selector;

[0023] The logical expression of the 2^32-1 modulo multiplication algorithm is:

[0024] C[31:0]=mold_sub1_correct(A[31:0]*B[31:0]), which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a Wallace compression tree adder, a modulo correction unit and a first MUX selector;

[0025] Wherein A and B are two operands of the 2^32 or 2^32-1 modulo multiplication algorithm, A[31:0] represents the 0th to 31st bits of the operand A, B[31:0] represents the 0th to 31st bits of the operand B, C[31:0] represents the modulo multiplication result, the low 32 bits of the product of A[31:0] and B[31:0] is the 2^32 modulo multiplication result, the 2^32 modulo multiplication result is obtained through the modulo correction unit to obtain the 2^32-1 modulo multiplication result, and mold_sub1_correct is a 2^32-1 type modulo correction function.

[0026] Further, the circuit implements the 2^32 modulo multiplication algorithm or the 2^32-1 modulo multiplication algorithm once;

[0027] The implementation process of the 2^32 modulo multiplication algorithm is as follows: the operands of the 2^32 modulo multiplication algorithm are two 32-bit numbers A and B, A and B are both split into byte data and input into the 16-way parallel 8-bit multiplier, 16 byte multiplication results are obtained by multiplying two by two through the 16-way parallel 8-bit multiplier, the byte multiplication result representing the low 32 bits of the 32-bit multiplication result is taken, the byte multiplication result is shifted according to the carry relationship between different bits, the shifted result is transmitted to the 4-way parallel 32-bit adder and the Wallace compression tree adder, the 4-way parallel 32-bit adder and the Wallace compression tree adder add the input data and transmit the addition result to the first selector, and the first MUX selector outputs the multiplication result according to the modulo multiplication type instruction;

[0028] The implementation process of the 1-way 2^32-1 modulo multiplication algorithm is as follows: the operands of the 2^32 modulo multiplication algorithm are two 32-bit numbers A and B, A and B are both split into byte data and input into 16-way parallel 8-bit multipliers, 16 byte multiplication results are obtained by multiplying two by two through the 16-way parallel 8-bit multipliers, the byte multiplication results representing the lower 32 bits of the 32-bit multiplication result are taken, the byte multiplication results are shifted according to the carry relationship between different bits, the shifted results are transmitted to a 4-way parallel 32-bit adder and a Wallace compression tree adder, the 4-way parallel 32-bit adder and the Wallace compression tree adder add the input data and transmit the addition results to a modulo correction unit, the modulo correction unit corrects the received data and transmits the correction results to a first selector, and the first MUX selector outputs the multiplication result according to the modulo multiplication type instruction.

[0029] In the implementation process of the 2^32 or 2^32-1 modulo multiplication algorithm, the addition operation of the 4-way parallel 32-bit addition calculation and the Wallace compression tree adder is as follows:

[0030] 4-way parallel 32-bit adder:

[0031] D0=C5<<<16 + C1<<<8 + C4<<<8 + C0,

[0032] D1=C13<<<16 + C12<<<8 + C9<<<8 + C8,

[0033] D2=C7<<<16 + C3<<<8 + C6<<<8 + C2,

[0034] D3=C15<<<16 + C14<<<8 + C11<<<8 + C10,

[0035] Wallace compression tree adder:

[0036] E=D3<<<32 + D1<<<16 + D2<<<16 + D0;

[0037] Wherein A0, A1, A2, A3 are byte data split from number A, B0, B1, B2, B3 are byte data split from number B, C0=A0*B0, C1=A0*B1, C2=A0*B2, C3=A0*B3, C4=A1*B0, C5=A1*B1, C6=A1*B2, C7=A1*B3, C8=A2*B0, C9=A2*B1, C10=A2*B2, C11=A2*B3, C12=A3*B0, C13=A3*B1, C14=A3*B2, C15=A3*B3.

[0038] The beneficial effects of the present application: the modular multiplication circuit designed in the present application can realize different types of modular multiplication operations in commonly used cryptographic algorithms, and improve the compatibility of the modular multiplication circuit. The present application optimizes the hardware circuit in the form of hardware multiplexing, proposes a serial-parallel modular multiplication circuit structure, supports modular multiplication operations of different quantities and bit widths, and improves the resource utilization rate of the hardware circuit. The present application introduces an efficient modular correction unit for special modular multiplication and serial-parallel structure, compatible with different quantities, bit widths and types of special modular multiplication, and improves the circuit running speed. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The schematic diagram of the modular multiplication circuit described in Embodiment 1;

[0040] Figure 2 The schematic diagram of the modular multiplication circuit described in Embodiment 2;

[0041] Figure 3 The circuit schematic diagram of the modular correction unit;

[0042] Figure 4 The schematic diagram of the modular addition and subtraction circuit;

[0043] Figure 5 The schematic diagram of the 8-bit correction adder. DETAILED DESCRIPTION

[0044] The present application will be further described below in conjunction with the drawings and specific embodiments.

[0045] Embodiment 1

[0046] This embodiment discloses a modular multiplication circuit suitable for multiple modular multiplication algorithms, as shown in Figure 1 The input end of the 16-way parallel 8-bit multiplier is connected to the operand of the modular multiplication algorithm, the output end of the 16-way parallel 8-bit multiplier is connected to the input end of the 4-way parallel 32-bit adder or the input end of the first MUX selector, the input end of the 4-way parallel 32-bit adder is connected to the output end of the 16-way parallel 8-bit multiplier, the output end of the 4-way parallel 32-bit adder is connected to the input end of the Wallace compression tree adder or the input end of the first MUX selector, the input end of the Wallace compression tree adder is connected to the output end of the 4-way parallel 32-bit adder, the output end of the Wallace compression tree adder is connected to the input end of the first MUX selector, the gating end of the first MUX selector is connected to the modular multiplication type instruction, and the modular multiplication result is obtained at the output end of the first MUX selector according to the modular multiplication type instruction.

[0047] When performing the modular multiplication operation, the operands of the modular multiplication algorithm are split into byte data, 16-way parallel 8-bit multipliers complete the multiplication of two byte data, 4-way parallel 32-bit adders, Wallace compression tree adders and the first MUX selector complete the combination of the multiplication results of two byte data, thereby obtaining different types of modular multiplication results. The circuit described in the embodiment can complete 2^8 modular multiplication, 2^16 modular multiplication and 2^32 modular multiplication algorithms.

[0048] The modular multiplication circuit described in the embodiment further includes a control circuit. The control circuit gives a modular multiplication type instruction, which includes link[2, 0], type and inst. The link[2:0] is a one-hot code, indicating the number of operations, such as 4-way operation, 2-way operation and 1-way operation. The type indicates the operation type, which has two cases, i.e. 2^M+1 and 2^N-1, M=8 or 16, N=32. The inst indicates the specific type of the modular multiplication operation, which has six cases, i.e. 2^8, 2^8+1, 2^16, 2^16+1, 2^32 and 2^32-1.

[0049] The modular multiplication circuit described in the embodiment can achieve 4-way 2^8 modular multiplication, 2-way 2^16 modular multiplication or 1-way 2^32 modular multiplication. For 4-way 2^8 modular multiplication, 2-way 2^16 modular multiplication or 1-way 2^32 modular multiplication, the inputs of the 16-way parallel 8-bit multipliers are both two 32-bit numbers, which are denoted as A and B. First, A and B are split into byte data (8bit), and the split manner is as follows: A0[7:0]=A[7:0], A1[7:0]=A[15:8], A2[7:0]=A[23:16], A3[7:0]=A[31:24], B0[7:0]=B[7:0], B1[7:0]=B[15:8], B2[7:0]=B[23:16], B3[7:0]=B[31:24], A[7:0] and B[7:0] represent the 0th to 7th bits of A and B respectively, A[15:8] and B[15:8] represent the 8th to 15th bits of A and B respectively, A[23:16] and B[23:16] represent the 16th to 23rd bits of A and B respectively, and A[31:24] and B[31:24] represent the 24th to 31st bits of A and B respectively. The split A0, A1, A2, A3, B0, B1, B2 and B3 are input into the 16-way parallel 8-bit multipliers to perform multiplication of two byte data. The byte multiplication result is as follows:

[0050] C0=A0*B0, C1=A0*B1, C2=A0*B2, C3=A0*B3, C4=A1*B0, C5=A1*B1, C6=A1*B2, C7=A1*B3, C8=A2*B0, C9=A2*B1, C10=A2*B2, C11=A2*B3, C12=A3*B0, C13=A3*B1, C14=A3*B2, C15=A3*B3.

[0051] For 4-way 2^8 modular multiplication, only 16-way parallel 8-bit multiplication is performed. Since it is a 2^8 modular multiplication algorithm, the low 8 bits of the multiplication result are the modular multiplication result. Among the multiplication results of the above 16 bytes, A3B3, A2B2, A1B1 and A0B0 represent the results of 4-way 8-bit multiplication respectively, and the 4-way 2^8 modular multiplication results are A3B3[7:0], A2B2[7:0], A1B1[7:0] and A0B0[7:0] respectively. A0*B0, A1*B1, A2*B2, A3*B3 constitute 64-bit data, that is, the output mul_4_8[63:0] of the 16-way parallel 8-bit multiplier, A0*B0 is in bits 0 to 15, A1*B1 is in bits 16 to 31, A2*B2 is in bits 32 to 47, and A3*B3 is in bits 48 to 63. The first MUX selector outputs the modular multiplication result according to the modular multiplication type instruction. At this time, the modular multiplication type instruction is a 4-way 2^8 modular multiplication algorithm instruction, and the first MUX selector selects bits 0 to 7, bits 16 to 23, bits 32 to 39, and bits 48 to 55 to output.

[0052] For 2-way 2^16 modular multiplication, 16-way parallel 8-bit multiplication and 4-way parallel 32-bit addition calculation are required. Since it is a 2^16 modular multiplication algorithm, the low 16 bits of the multiplication result are the modular multiplication result. First, select the byte multiplication result representing the low 16 bits of the multiplication result and transmit it to the 4-way parallel 32-bit adder to sum to obtain the 2-way 2^16 modular multiplication result. The 2-way 2^16 modular multiplication result is transmitted to the first selector, and the first MUX selector outputs the modular multiplication result according to the modular multiplication type instruction.

[0053] Specifically, A0*B0 is a part of the low 16 bits of the first multiplication result, A0*B1[7:0], A1*B0[7:0] are another part of the low 16 bits of the first multiplication result (in bits 8 to 15, which need to be left shifted by 8 bits to represent the multiplication result), A2*B2 is a part of the low 16 bits of the second multiplication result, A2*B3[7:0], A3*B2[7:0] are another part of the low 16 bits of the second multiplication result (in bits 8 to 15, which need to be left shifted by 8 bits to represent the multiplication result). A0*B1[7:0], A1*B0[7:0], A2*B3[7:0], A3*B2[7:0] are left shifted by 8 bits respectively and then input into the 4-way parallel 32-bit adder, and A0B0, A2B2 are also input into the 4-way parallel 32-bit adder, the 4-way parallel 32-bit adder completes the addition operations (A3B2[7:0]<<8+A2B3[7:0]<<8+A2B2) and (A1B0[7:0]<<8+A0B1[7:0]<<8+A0B0), and the addition results are transmitted to the first selector, the first MUX selector outputs the modular multiplication result according to the modular multiplication type instruction. The 2-way addition results respectively occupy the first 32 bits and the last 32 bits, and constitute the 64-bit output mul_2_16[63:0] of the 4-way parallel 32-bit adder. At this time, the modular multiplication type instruction is a 2-way 2^16 modular multiplication algorithm instruction, and the first MUX selector selects bits 0 to 15 and bits 32 to 47 to output.

[0054] For 1-way 2^32 modular multiplication, 16-way parallel 8-bit multiplication, 4-way parallel 32-bit addition calculation and 1-way Wallace addition are required. Since it is a 2^32 modular multiplication algorithm, the low 32 bits of the multiplication result are the modular multiplication result. The expression of the 4-way parallel 32-bit addition calculation and the Wallace compression tree adder is:

[0055] (A3B0[7:0]<<24+A2B1[7:0]<<24+A1B2[7:0]<<24+A0B3[7:0]<<24+A2B0<<16+A1B1<<16+A0B2<<16+A1B0<<8+A0B1<<8+A0B0).

[0056] According to the multiplication including multiple addition operations and the carry relationship between different bits, the addition operations performed by the 4-way parallel 32-bit addition calculation and the Wallace compression tree adder are:

[0057] The 4-way parallel 32-bit adder is:

[0058] D0=C5<<<16 + C1<<<8 + C4<<<8 + C0,

[0059] D1=C13<<<16 + C12<<<8 + C9<<<8 + C8,

[0060] D2 = C7<<<16 + C3<<<8 + C6<<<8 + C2,

[0061] D3 = C15<<<16 + C14<<<8 + C11<<<8 + C10,

[0062] Wallace compression tree adder:

[0063] E = D3<<<32 + D1<<<16 + D2<<<16 + D0.

[0064] E is the 2^32 modular multiplication result, which is transmitted to the first selector. The first MUX selector outputs the modular multiplication result according to the modular multiplication type instruction.

[0065] As a backward compatible, the embodiment described can also complete 2^8 modular multiplication of 4 paths or less, i.e. 1-path 2^8 modular multiplication, 2-path 2^8 modular multiplication or 3-path 2^8 modular multiplication, the execution process is the same as that of 4-path 2^8 modular multiplication, only the number of input data bits and the number of output data paths are different. For example, for 1-path 2^8 modular multiplication, only A0 and B0 have specific data, A3, A2, A1, B3, B2 and B1 are all 0, the 16-path parallel 8-bit multiplier only performs A0*B0, and the output data is only one path, which is transmitted to the first selector, and the first MUX selector outputs the modular multiplication result according to the modular multiplication type instruction. At this time, the modular multiplication type instruction is the 1-path 2^8 modular multiplication algorithm instruction, and the first MUX selector selects the 0th to 7th bits to output. The calculation process of 2-path 2^8 modular multiplication or 3-path 2^8 modular multiplication is not repeated.

[0066] As a downward compatible, the embodiment described can also complete 1 way 2^16 modulo multiplication, the execution process is same with 2 way 2^16 modulo multiplication execution process, only the input data bit number is different, the output data way number is different. For example, executing 1 way 2^16 modulo multiplication, only A0, A1, B0, B1 have specific data, A3, A2, B3, B2 are all 0, 16 way parallel 8 bit multiplier executes A0*B0, A0*B1, A1*B0, A1*B1, A0*B0 is a part of the low 16 bits of multiplication result, A0*B1[7:0], A1*B0[7:0] are another part of the low 16 bits of multiplication result (in the 8th to 15th bit, it needs to be left shifted by 8 bits to represent the multiplication result). After A0*B1[7:0], A1*B0[7:0] are respectively left shifted by 8 bits, they are input into 4 way parallel 32 bit adder, A0B0 is also input into 4 way parallel 32 bit adder, 4 way parallel 32 bit adder completes addition operation (A3B2[7:0]<<8+A2B3[7:0]<<8+A2B2), the addition result is transmitted to the first selector, the first selector outputs the modulo multiplication result according to the modulo multiplication type instruction. At this time, the modulo multiplication type instruction is 1 way 2^16 modulo multiplication algorithm instruction, then the first MUX selector selects the 0th to 15th bit to output.

[0067] As known from the above description, the logic expression of 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0]*B[7:0])[7:0], which is completed by 16 way parallel 8 bit multiplier and first MUX selector, the data flow direction is: 16 way parallel 8 bit multiplier -> first MUX selector -> output. The logic expression of 2^16 modulo multiplication algorithm is: C[15:0]=(A[15:0]*B[15:0])[15:0], which is completed by 16 way parallel 8 bit multiplier, 4 way parallel 32 bit adder and first MUX selector, the data flow direction is: 16 way parallel 8 bit multiplier -> 4 way parallel 32 bit adder -> first MUX selector -> output. The logic expression of 2^32 modulo multiplication algorithm is: C[31:0]=(A[31:0]*B[31:0])[31:0], which is completed by 16 way parallel 8 bit multiplier, 4 way parallel 32 bit adder, Wallace compression tree adder and first MUX selector, the data flow direction is: 16 way parallel 8 bit multiplier -> 4 way parallel 32 bit adder -> Wallace compression tree adder -> first MUX selector -> output.

[0068] As known from the above description, different bit number modulo multiplication algorithms can be realized in the embodiment, and the way number of completing modulo multiplication algorithm can also be set for a certain modulo multiplication algorithm.

[0069] Embodiment 2

[0070] In order to complete the special modulo multiplication, i.e. 2^8+1, 2^16+1 and 2^32-1 modulo multiplication operation, the embodiment increases the modulo correction unit on the basis of the embodiment 1. The circuit described in the embodiment 1 realizes single 4-way 8-bit modulo multiplication, 2-way 16-bit modulo multiplication and 1-way 32-bit modulo multiplication, so 4-way 2^8+1 modulo multiplication, 2-way 2^16+1 modulo multiplication and 1-way 2^32-1 modulo multiplication are also realized in the modulo correction unit. The data source of the modulo correction unit is 4 16-bit data output by the 16-way parallel 8-bit multiplier, 2 32-bit data output by the 4-way parallel 32-bit adder and 1 64-bit data output by the Wallace compression tree adder, and the above 3 64-bit numbers are input into the operation circuit through the MUX. The 2^M+1 type modulo multiplication needs to use high-low subtraction, and the 2^N-1 type modulo multiplication needs to use high-low addition, which is realized by the addition circuit by using hardware multiplexing, M=8 or 16, N=32.

[0071] As shown in Figure 2 、 3 , the modulo correction unit comprises a second MUX selector, a third MUX selector, a 32-bit inversion circuit, a fourth MUX selector and a modulo addition and subtraction circuit, the input end of the second MUX selector is connected with high 32-bit data mul_4_8[63:32] output by the 16-way parallel 8-bit multiplier, high 32-bit data mul_2_16[63:32] output by the 4-way parallel 32-bit adder and high 32-bit data mul_1_16[63:32] output by the Wallace compression tree adder, the input end of the third MUX selector is connected with low 32-bit data mul_4_8[31:0] output by the 16-way parallel 8-bit multiplier, low 32-bit data mul_2_16[31:0] output by the 4-way parallel 32-bit adder and low 32-bit data mul_1_816[31:0] output by the Wallace compression tree adder, the 32-bit inversion circuit is connected between the output end of the second MUX selector and one input end of the fourth MUX selector, the other input end of the fourth MUX selector is connected with the output end of the second MUX selector, the input end of the modulo addition and subtraction circuit is respectively connected with the output end of the fourth MUX selector and the output end of the third MUX selector, and the output end of the modulo addition and subtraction circuit is connected with the input end of the first MUX selector.

[0072] The gating end of the second MUX selector and the third MUX selector is connected with the operation type instruction link, the gating end of the fourth MUX selector is connected with the operation type instruction type, and the correction end of the modulo addition and subtraction circuit is connected with the operation type instruction link and the operation type instruction type.

[0073] The operation type instruction link indicates the number of operations. If link indicates that 4-way operation is to be performed, the second MUX selector outputs the high 32-bit data of the 16-way parallel 8-bit multiplier output, the third MUX selector outputs the low 32-bit data of the 16-way parallel 8-bit multiplier output. If link indicates that 2-way operation is to be performed, the second MUX selector outputs the high 32-bit data of the 4-way parallel 32-bit adder output, the third MUX selector outputs the low 32-bit data of the 4-way parallel 32-bit adder output. If link indicates that 1-way operation is to be performed, the second MUX selector outputs the high 32-bit data of the Wallace compression tree adder output, the third MUX selector outputs the low 32-bit data of the Wallace compression tree adder output. The operation type instruction type takes values including 2^M+1 and 2^N-1, M=8 or 16, N=32. When type=2^M+1, the fourth MUX selector outputs the data of the second MUX output taken complement. When type=2^N-1, the fourth MUX selector outputs the data of the second MUX output. The second MUX selector, the third MUX selector, the 32-bit complement circuit and the fourth MUX selector select the data corresponding to the instruction according to the operation type instruction link and the operation type instruction type, the modulo add-subtract circuit corrects the received data to obtain a special modulo multiplication result, and transmits the special modulo multiplication result to the first MUX selector, which gives the modulo multiplication result according to the modulo multiplication type instruction.

[0074] The modulo add-subtract circuit takes 8-bit correction adder as a unit. In order to be compatible with 4-way 8-bit addition, 2-way 16-bit addition and 1-bit 32-bit addition, 4 correction adders are cascaded. The cin of each full adder selects between the cout of the previous adder and the constant 0 according to the operation type instruction type, to form a serial-parallel modulo add-subtract circuit structure. Compared with the traditional 32-bit adder, this structure improves the running speed of the circuit.

[0075] As Figure 4As shown, the modulo-addition / subtraction circuit includes a threshold correction circuit with four 8-bit corrected adders. The four 8-bit corrected adders are cascaded. The cin of each 8-bit corrected adder is selected between cout of the previous adder and the constant 0 according to the operation type instruction. The high 32-bit data and low 32-bit data of the input are split into byte data. The split byte data is transmitted to the four 8-bit corrected adders respectively. The 8-bit corrected adders obtain the output result OUT[7:0]={H[7]⊕L[7] ⊕cout, H[6:0]+L[6:0]} and the correction carry Y=(H[7]&L[7] |H[7]&cout | L[7]&cout), H[7] represents the 8th bit of the byte data split from the high 32 bits, H[6:0] represents the 0th to 6th bits of the byte data split from the high 32 bits, L[7] represents the 8th bit of the byte data split from the low 32 bits, L[6:0] represents the 0th to 6th bits of the byte data split from the low 32 bits, | represents OR operation, ⊕ represents XOR operation, & represents AND operation, cout represents the carry generated by adding H[6:0] with L[6:0] and cin; four 8-bit correction additions The output result and the correction carry of the generator are transmitted to the threshold correction circuit. The threshold correction circuit corrects the modular multiplication result according to the operation type instruction link and operation type instruction type. The correction method is to sum the output result and the correction carry. The sum is denoted as F. For 2^M+1, if Y=1, the corrected result is F+1, otherwise the corrected result is F. For 2^N-1, if Y=1 or OUT is all 1, the corrected result is F+1, otherwise the corrected result is F. M=8 or 16, N=32.

[0076] like Figure 5 As shown, the 8-bit corrected adder includes a Y function module, an adder, a first XOR gate, a second XOR gate, and a concatenator. The inputs of the Y function module are H[7], L[7], cout, and the operation type instruction type. The Y function module performs the Y function operation on the input and generates the corrected carry Y=(H[7]&L[7] |H[7]&cout | L[7]&cout), the input of the adder is connected to H[6:0], L[6:0] and cin, cin is the carry input from the outside or the low bit. The output of the adder has two parts. One part is the lower 7 bits of the sum of the input data, which is directly transmitted to one input of the splicer. The other part is the carry cout of the sum of the input data. The carry cout is XORed with H[7] and L[7] through the first XOR gate and the second XOR gate respectively. The XOR result is transmitted to the other input of the splicer. The splicer splices the data of the two inputs into an 8-bit number, and obtains the output result OUT[7:0]={H[7] ⊕L[7]⊕cout, H[6:0]+L[6:0]}.

[0077] In this embodiment, the logical expression of the 2^8+1 modular multiplication algorithm is:

[0078] C[7:0]=mold_and1_correct(A[7:0]*B[7:0]), which is completed by a 16-way parallel 8-bit multiplier, a mold correction unit and a first MUX selector;

[0079] Wherein A and B are two operands of the 2^8 or 2^8+1 modular multiplication algorithm, A[7:0] represents the 0th to 7th bits of the operand A, B[7:0] represents the 0th to 7th bits of the operand B, C[7:0] represents the modular multiplication result, the low 8 bits of the product of A[7:0] and B[7:0] is the 2^8 modular multiplication result, the 2^8 modular multiplication result is obtained through the mold correction unit to obtain the 2^8+1 modular multiplication result, and mold_and1_correct is a 2^8+1 type mold correction function.

[0080] The logical expression of the 2^16+1 modular multiplication algorithm is:

[0081] C[15:0]=mold_and1_correct(A[15:0]*B[15:0]), which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a mold correction unit and a first MUX selector;

[0082] Wherein A and B are two operands of the 2^16 or 2^16+1 modular multiplication algorithm, A[15:0] represents the 0th to 15th bits of the operand A, B[15:0] represents the 0th to 15th bits of the operand B, C[15:0] represents the modular multiplication result, the low 16 bits of the product of A[15:0] and B[15:0] is the 2^16 modular multiplication result, the 2^16 modular multiplication result is obtained through the mold correction unit to obtain the 2^16+1 modular multiplication result, and mold_and1_correct is a 2^16+1 type mold correction function.

[0083] The logical expression of the 2^32-1 modular multiplication algorithm is:

[0084] C[31:0]=mold_sub1_correct(A[31:0]*B[31:0]), which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a Wallace compression tree adder, a mold correction unit and a first MUX selector;

[0085] Wherein A, B are two operands of 2^32 or 2^32-1 modular multiplication algorithm, A[31:0] represents the 0th to 31st bit of operand A, B[31:0] represents the 0th to 31st bit of operand B, C[31:0] represents the modular multiplication result, the low 32 bits of the product of A[31:0] and B[31:0] is the 2^32 modular multiplication result, the 2^32 modular multiplication result is obtained through the modular correction unit to obtain the 2^32-1 modular multiplication result, mold_sub1_correct is a 2^32-1 type modular correction function.

[0086] The modular multiplication circuit described in the embodiment can realize 4-way 2^8 modular multiplication, 2-way 2^16 modular multiplication or 1-way 2^32 modular multiplication. For 4-way 2^8 modular multiplication, the four 8-bit correction adders operate independently, the inputs are respectively the low 8-bit data and the high 8-bit data representing 8-bit multiplication, and cin is 0. For 2-way 2^16 modular multiplication, the four 8-bit correction adders are divided into two groups averagely, and the two groups operate independently of each other. The two 8-bit correction adders in each group are cascaded and have a carry relationship. For 1-way 2^32 modular multiplication, the four 8-bit correction adders are cascaded, and the cin of each adder is Y of the previous adder.

[0087] As a downward compatible, the embodiment described can also complete 4-way or less 2^8+1 modular multiplication, i.e. 1-way 2^8+1 modular multiplication, 2-way 2^8+1 modular multiplication or 3-way 2^8+1 modular multiplication, the execution process is the same as that of 4-way 2^8+1 modular multiplication, only the number of input data bits and the number of output data are different. For example, for 1-way 2^8 modular multiplication, only A0 and B0 have specific data, A3, A2, A1, B3, B2 and B1 are all 0, the 16-way parallel 8-bit multiplier also only performs A0*B0, and the output data is only one way, which is transmitted to the modular correction unit. Only one 8-bit correction adder works, and the high 8 bits and the low 8 bits of A0*B0 are corrected to obtain the 2^8+1 modular multiplication result. The 2^8+1 modular multiplication result is transmitted to the first MUX selector, and the first MUX selector outputs the corresponding result according to the modular multiplication type instruction. At this time, the modular multiplication type instruction is the instruction of 1-way 2^8+1 modular multiplication algorithm, and the first MUX selector selects the 0th to 8th bits to output. The calculation process of 2-way 2^8 modular multiplication or 3-way 2^8 modular multiplication is not repeated. According to the different modular multiplication types, the four 8-bit correction adders form a series-parallel modular addition and subtraction circuit structure.

[0088] As a downward compatible, the embodiment described can also complete 1 way 2^16 modulo multiplication, the execution process is same with 2 way 2^16 modulo multiplication execution process, only the input data bit number is different, the output data road number is different. Such as executing 1 way 2^16 modulo multiplication, only A0, A1, B0, B1 have specific data, A3, A2, B3, B2 are all 0, 16 way parallel 8 bit multiplier executes A0*B0, A0*B1, A1*B0, A1*B1, A0*B0 is a part of the low 16 bits of multiplication result, A0*B1[7:0], A1*B0[7:0] are another part of the low 16 bits of multiplication result (in the 8th to 15th bit, it needs to be left shifted by 8 bits to represent the multiplication result). After A0*B1[7:0], A1*B0[7:0] are respectively left shifted by 8 bits, they are input into 4 way parallel 32 bit adder, A0B0 is also input into 4 way parallel 32 bit adder, 4 way parallel 32 bit adder completes addition operation (A3B2[7:0] << 8+A2B3[7:0] << 8+A2B2), the addition result is transmitted to the modulo correction unit, only two 8 bit correction adders in the modulo correction unit work, correct the received data, and the correction is transmitted to the first selector, the first selector outputs the modulo multiplication result according to the modulo multiplication type instruction. At this time, the modulo multiplication type instruction is 1 way 2^16+1 modulo multiplication algorithm instruction, then the first MUX selector selects the 0th to 16th bit output.

[0089] In summary, the new type of series-parallel high-efficiency modulo multiplication circuit can be compatible with 2^8, 2^16, 2^32, 2^8+1, 2^16+1 and 2^32-1 modulo multiplication operations in common algorithms, and adopts a series-parallel structure to improve the utilization rate of hardware resources, can realize 4-way 8-bit modulo multiplication, 2-way 16-bit modulo multiplication or 1-way 32-bit modulo multiplication at a time, introduces a high-efficiency modulo correction unit to match special modulo multiplication of different bit widths and quantities, and the improved adder circuit can improve the operation speed of the circuit.

[0090] The above description is only the basic principle and preferred embodiment of the present application, and the improvements and replacements made by the person skilled in the art according to the present application belong to the protection scope of the present application.

Claims

1. A modular multiplication circuit suitable for a plurality of modular multiplication algorithms, characterized by: The module multiplication algorithm includes 16 parallel 8-bit multipliers, 4 parallel 32-bit adders, a Wallace compression tree adder and a first MUX selector, the inputs of the 16 parallel 8-bit multipliers are connected to the operands of the module multiplication algorithm, the outputs of the 16 parallel 8-bit multipliers are connected to the inputs of the 4 parallel 32-bit adders or the inputs of the first MUX selector, the inputs of the 4 parallel 32-bit adders are connected to the outputs of the 16 parallel 8-bit multipliers, the outputs of the 4 parallel 32-bit adders are connected to the inputs of the Wallace compression tree adder or the inputs of the first MUX selector, the inputs of the Wallace compression tree adder are connected to the outputs of the 4 parallel 32-bit adders, the outputs of the Wallace compression tree adder are connected to the inputs of the first MUX selector, the gating end of the first MUX selector is connected to the module multiplication type instruction, and the module multiplication result is obtained at the output of the first MUX selector according to the module multiplication type instruction; When the module multiplication operation is performed, the two operands of the module multiplication algorithm are split into byte data, the 16 parallel 8-bit multipliers complete the multiplication of the byte data two by two, the 4 parallel 32-bit adders, the Wallace compression tree adder and the first MUX selector complete the combination of the multiplication results two by two, so that different types of module multiplication results are obtained; The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo multiplication algorithm is: C[7:0]=(A[7:0] The logical expression of the 2^8 modulo 2^16 modulo multiplication algorithm logical expression is: C[15:0]=(A[15:0] B[15:0])[15:0], which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder and a first MUX selector; the circuit realizes J-way 2^16 modulo multiplication algorithm in a single time, J=1 or 2, and the implementation process is as follows: the operands of J-way 2^16 modulo multiplication algorithm are split into 2J groups of byte data, each group of byte data including two 8-bit numbers, 2J groups of byte data are multiplied by each other through the 16-way parallel 8-bit multiplier to obtain byte multiplication results, the byte multiplication results representing the lower 16 bits of 16-bit multiplication results are taken, the byte multiplication results are shifted according to the carry relationship between different bits, the shifted results are transmitted to the 4-way parallel 32-bit adder, the 4-way parallel 32-bit adder adds the input data and transmits the addition result to the first selector, and the first MUX selector outputs the multiplication result according to the modulo multiplication type instruction. 2^32 modulo multiplication algorithm logical expression is: C[31:0]=(A[31:0] B[31:0])[31:0], which is completed by 16 parallel 8-bit multipliers, 4 parallel 32-bit adders, Wallace compression tree adder and the first MUX selector; the circuit realizes 1-way 2^32 modulo multiplication algorithm at a time, and the implementation process is as follows: the operands of 2^32 modulo multiplication algorithm are two 32-bit numbers A and B, A and B are both split into byte data and input into 16 parallel 8-bit multipliers, 16 byte multiplication results are obtained by multiplying two by two, the byte multiplication results representing the lower 32 bits of 32-bit multiplication results are taken, the byte multiplication results are shifted according to the carry relationship between different bits, the shifted results are transmitted to 4 parallel 32-bit adders and Wallace compression tree adder, 4 parallel 32-bit adders and Wallace compression tree adder add the input data and transmit the addition results to the first selector, and the first MUX selector outputs the multiplication result according to the type of modulo multiplication instruction. Wherein A and B are two operands of the module multiplication algorithm, A[7:0] represents the 0th to 7th bits of the operand A, B[7:0] represents the 0th to 7th bits of the operand B, C[7:0] represents the 2^8 module multiplication result, and the low 8 bits of the product of A[7:0] and B[7:0] are the 2^8 module multiplication result; A[15:0] represents the 0th to 15th bits of the operand A, B[15:0] represents the 0th to 15th bits of the operand B, C[15:0] represents the 2^16 module multiplication result, and the low 16 bits of the product of A[15:0] and B[15:0] are the 2^16 module multiplication result; A[31:0] represents the 0th to 31st bits of the operand A, B[31:0] represents the 0th to 31st bits of the operand B, C[31:0] represents the 2^32 module multiplication result, and the low 32 bits of the product of A[31:0] and B[31:0] are the 2^32 module multiplication result.

2. The Montgomery multiplication circuitry of claim 1 adapted to apply a plurality of Montgomery multiplication algorithms, characterized by: The module correction unit comprises a second MUX selector, a third MUX selector, a 32-bit inversion circuit, a fourth MUX selector and a module addition and subtraction circuit. The input end of the second MUX selector is connected with high 32-bit data output by the 16-way parallel 8-bit multiplier, high 32-bit data output by the 4-way parallel 32-bit adder and high 32-bit data output by the Wallace compression tree adder. The input end of the third MUX selector is connected with low 32-bit data output by the 16-way parallel 8-bit multiplier, low 32-bit data output by the 4-way parallel 32-bit adder and low 32-bit data output by the Wallace compression tree adder. The 32-bit inversion circuit is connected between the output end of the second MUX selector and one input end of the fourth MUX selector. The other input end of the fourth MUX selector is connected with the output end of the second MUX selector. The input end of the module addition and subtraction circuit is connected with the output end of the fourth MUX selector and the output end of the third MUX selector respectively. The output end of the module addition and subtraction circuit is connected with the input end of the first MUX selector. The gating end of the second MUX selector and the third MUX selector is connected with the operation type instruction link. The gating end of the fourth MUX selector is connected with the operation type instruction type. The correction end of the module addition and subtraction circuit is connected with the operation type instruction link and the operation type instruction type. The operation type instruction link indicates the operation way. If the link indicates that 4-way operation is to be performed, the second MUX selector outputs high 32-bit data output by the 16-way parallel 8-bit multiplier. The third MUX selector outputs low 32-bit data output by the 16-way parallel 8-bit multiplier. If the link indicates that 2-way operation is to be performed, the second MUX selector outputs high 32-bit data output by the 4-way parallel 32-bit adder. The third MUX selector outputs low 32-bit data output by the 4-way parallel 32-bit adder. If the link indicates that 1-way operation is to be performed, the second MUX selector outputs high 32-bit data output by the Wallace compression tree adder. The third MUX selector outputs low 32-bit data output by the Wallace compression tree adder. The operation type instruction type takes values including 2^M+1 and 2^N-1. M=8 or 16. N=32. When the type=2^M+1, the fourth MUX selector outputs inverted data of the second MUX output. When the type=2^N-1, the fourth MUX selector outputs data of the second MUX output. The second MUX selector, the third MUX selector, the 32-bit inversion circuit, the fourth MUX selector select data corresponding to the instructions according to the operation type instruction link and the operation type instruction type. The module addition and subtraction circuit corrects the received data to obtain a special module multiplication result. The special module multiplication result is transmitted to the first MUX selector. The first MUX selector gives the module multiplication result according to the module multiplication type instruction.

3. The Montgomery multiplication circuitry of claim 2 adapted to apply a plurality of Montgomery multiplication algorithms, wherein: The modulo add-subtract circuit comprises a threshold correction circuit of four 8-bit correction adders, the four 8-bit correction adders are cascaded, the carry-in cin of each 8-bit correction adder is selected between the cout of the previous adder and a constant 0 according to the operation type instruction type, the high 32-bit data and the low 32-bit data are both split into byte data, the split byte data are transmitted to the four 8-bit correction adders respectively, the 8-bit correction adder obtains the output result OUT[7:0] = {H[7] ^ L[7] ^ cout, H[6:0] + L[6:0]} and the correction carry-in Y = (H[7] & L[7] | H[7] & cout | L[7] & cout) according to the input, H[7] represents the 8th bit of the split byte data of the high 32-bit data, H[6:0] represents the 0th to 6th bits of the split byte data of the high 32-bit data, L[7] represents the 8th bit of the split byte data of the low 32-bit data, L[6:0] represents the 0th to 6th bits of the split byte data of the low 32-bit data, | represents OR operation, ^ represents XOR operation, & represents AND operation, and cout represents the carry-in generated by adding H[6:0] and L[6:0] and cin; the output result and the correction carry-in of the four 8-bit correction adders are transmitted to the threshold correction circuit, the threshold correction circuit corrects the modulo multiplication result according to the operation type instruction link and the operation type instruction type, the correction mode is to sum the output result and the correction carry-in, the sum result is recorded as F, for 2^M+1, if Y = 1, the corrected result is F+1, otherwise the corrected result is F, for 2^N-1, if Y = 1 or OUT is equal to all 1s, the corrected result is F+1, otherwise the corrected result is F, M = 8 or 16, and N = 32.

4. The Montgomery multiplication circuitry of claim 3 adapted to apply a plurality of Montgomery multiplication algorithms, characterized by: The 8-bit correction adder comprises a Y function module, an adder, a first XOR gate, a second XOR gate and a splicer, the input of the Y function module is H[7], L[7], cout and the operation type instruction type, the Y function module performs Y function operation on the input and generates the correction carry-in Y = (H[7] & L[7] | H[7] & cout | L[7] & cout), the input of the adder is connected with H[6:0], L[6:0] and cin, cin is the carry-in input from the outside or the low bit, the output of the adder has two parts, one part is the low 7 bits of the sum of the input data, which is directly transmitted to one input end of the splicer, the other part is the carry-in cout of the sum of the input data, which is transmitted to the other input end of the splicer after being subjected to XOR operation with H[7] and L[7] through the first XOR gate and the second XOR gate, the splicer splices the data of the two input ends into 8-bit data to obtain the output result OUT[7:0] = {H[7] ^ L[7] ^ cout, H[6:0] + L[6:0]} of the 8-bit correction adder.

5. The Montgomery multiplication circuitry of claim 2 adapted to apply a plurality of Montgomery multiplication algorithms, wherein: The logical expression of the 28+1 modular multiplication algorithm is: C[7:0]=mold_and1_correct(A[7:0] B[7:0]), which is completed by a 16-way parallel 8-bit multiplier, a modular correction unit and a first MUX selector. Wherein A, B are two operands of 2^8+1 modular multiplication algorithm, A[7:0] represents the 0th to 7th bits of operand A, B[7:0] represents the 0th to 7th bits of operand B, C[7:0] represents the 2^8+1 modular multiplication result, the low 8 bits of the product of A[7:0] and B[7:0] is the 2^8 modular multiplication result, the 2^8 modular multiplication result is obtained through a modulus correction unit to obtain the 2^8+1 modular multiplication result, mold_and1_correct is a 2^M+1 type modulus correction function, M=8 or 16.

6. The Montgomery multiplication circuitry of claim 5 adapted to apply a plurality of Montgomery multiplication algorithms, characterized by: The circuit implements K-way 2^8+1 modular multiplication algorithm at a time, K=1 or 2 or 3 or 4, and the implementation process is as follows: the operands of K-way 2^8+1 modular multiplication algorithm are split into K groups of byte data, each group of byte data includes two 8-bit numbers, the K groups of byte data are multiplied by each other through a 16-way parallel 8-bit multiplier to obtain byte multiplication results, the byte multiplication results representing 8-bit multiplication results are transmitted to a modulus correction unit, the modulus correction unit corrects the received data and transmits the corrected results to a first MUX selector, and the first MUX selector outputs the 2^8+1 modular multiplication result according to the modular multiplication type instruction.

7. The Montgomery multiplication circuitry of claim 2 adapted to apply a plurality of Montgomery multiplication algorithms, wherein: The logical expression of the 2<16+1> modulo multiplication algorithm is: C[15:0]=mold_and1_correct(A[15:0] B[15:0]), which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a modulo correction unit and a first MUX selector. Wherein A, B are two operands of 2^16+1 modular multiplication algorithm, A[15:0] represents the 0th to 15th bits of operand A, B[15:0] represents the 0th to 15th bits of operand B, C[15:0] represents the 2^16+1 modular multiplication result, the low 16 bits of the product of A[15:0] and B[15:0] is the 2^16 modular multiplication result, the 2^16 modular multiplication result is obtained through a modulus correction unit to obtain the 2^16+1 modular multiplication result, mold_and1_correct is a 2^M+1 type modulus correction function, M=8 or 16.

8. The Montgomery multiplication circuitry of claim 7 adapted to apply a plurality of Montgomery multiplication algorithms, characterized by: The circuit implements J-way 2^16+1 modular multiplication algorithm at a time, J=1 or 2, and the implementation process is as follows: the operands of J-way 2^16+1 modular multiplication algorithm are split into 2J groups of byte data, each group of byte data includes two 8-bit numbers, the 2J groups of byte data are multiplied by each other through a 16-way parallel 8-bit multiplier to obtain byte multiplication results, the byte multiplication results representing the low 16 bits of 16-bit multiplication results are taken, the byte multiplication results are shifted according to the carry relationship between different bits, the shifted results are transmitted to a 4-way parallel 32-bit adder, the 4-way parallel 32-bit adder adds the input data and transmits the addition result to a modulus correction unit, the modulus correction unit corrects the received data and transmits the corrected results to a first selector, and the first MUX selector outputs the modular multiplication result according to the modular multiplication type instruction.

9. The Montgomery multiplication circuitry of claim 2 adapted to apply a plurality of Montgomery multiplication algorithms, wherein: The logical expression of the 2^32-1 modulo multiplication algorithm is: C[31:0]=mold_sub1_correct(A[31:0] B[31:0]), which is completed by a 16-way parallel 8-bit multiplier, a 4-way parallel 32-bit adder, a Wallace compression tree adder, a modulo correction unit and a first MUX selector. Wherein A, B are two operands of 2^32-1 modular multiplication algorithm, A[31:0] represents the 0th to 31st bits of operand A, B[31:0] represents the 0th to 31st bits of operand B, C[31:0] represents the 2^32-1 modular multiplication result, the low 32 bits of the product of A[31:0] and B[31:0] is the 2^32 modular multiplication result, the 2^32 modular multiplication result is obtained through a modulus correction unit to obtain the 2^32-1 modular multiplication result, mold_sub1_correct is a 2^N-1 type modulus correction function, N=32.

10. The Montgomery multiplication circuitry of claim 9 adapted to apply a plurality of Montgomery multiplication algorithms, wherein: The circuit realizes 1-way 2^32-1 modular multiplication algorithm, and the implementation process is as follows: the operation number of the 2^32-1 modular multiplication algorithm is two 32-bit numbers A and B, A and B are all split into byte data and input into 16-way parallel 8-bit multipliers, 16 byte multiplication results are obtained by multiplying two by two through the 16-way parallel 8-bit multipliers, the byte multiplication result representing the lower 32 bits of the 32-bit multiplication result is taken, the byte multiplication result is shifted according to the carry relationship between different bits, the shifting result is transmitted to a 4-way parallel 32-bit adder and a Wallace compression tree adder, the 4-way parallel 32-bit adder and the Wallace compression tree adder add the input data and transmit the addition result to a modulus correction unit, the modulus correction unit corrects the received data and transmits the correction result to a first selector, and the first MUX selector outputs the modular multiplication result according to the modular multiplication type instruction.

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