FPGA configuration method and system and storage medium

Abstract

The invention relates to the technical field of computers, and discloses an FPGA configuration method and system and a storage medium, and the method comprises the steps that an upper computer generates a first-stage bit stream and a second-stage bit stream containing a configuration version based on first configuration information and the configuration version of an FPGA chip; and the upper computer synchronizes the first-stage bit stream to the FPGA chip, so that the FPGA chip starts the PCIe module and writes the configuration version of the first-stage bit stream into the PCIe module. The upper computer reads a configuration version corresponding to a first-stage bit stream of the PCIe module and reads a configuration version of a second-stage bit stream under the condition that the PCIe module is started; and if the configuration version of the first-stage bit stream is consistent with the configuration version of the second-stage bit stream, the upper computer writes the second-stage bit stream into the PCIe module so as to configure a hardware logic circuit. The problem that the FPGA chip is abnormal due to the fact that the loaded first-stage bit stream is not matched with the loaded second-stage bit stream can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an FPGA configuration method, system, and storage medium. Background Art

[0002] In related technologies, Field Programmable Gate Array (FPGA) chips primarily load FPGA configuration information bitstreams via the high-speed Peripheral Component Interconnect Express (PCIe) bus standard. The PCIe loading process is divided into two phases: the first phase, in which the FPGA chip loads the first-stage bitstream from the flash memory (Flash Memory) storing the first-stage bitstream, activating the PCIe module. Subsequently, the second-stage bitstream is loaded via the PCIe link to configure the FPGA chip's hardware logic circuits.

[0003] However, as user applications continue to evolve, the number of bitstreams of FPGA configuration information generated will increase, and it is easy for the first-stage bitstream loaded into the FPGA chip to not match the second-stage bitstream, causing FPGA chip anomalies. Summary of the Invention

[0004] In view of this, the present disclosure provides an FPGA configuration method, system, and storage medium to solve the problem of FPGA chip abnormality caused by the mismatch between the first-stage bit stream loaded by the FPGA chip and the second-stage bit stream.

[0005] In a first aspect, the present disclosure provides an FPGA configuration method applicable to a host computer, the method comprising:

[0006] Obtaining first configuration information of the FPGA chip and a configuration version corresponding to the first configuration information;

[0007] Based on the first configuration information and the configuration version, generating a first-stage bitstream and a second-stage bitstream of a PCIe module; wherein the PCIe module is deployed on the FPGA chip; the first-stage bitstream includes the configuration version; and the second-stage bitstream includes the first configuration information and the configuration version;

[0008] Synchronizing the first-stage bitstream to the FPGA chip; wherein the FPGA chip is configured to start the PCIe module based on the first-stage bitstream and write the configuration version in the first-stage bitstream into the PCIe module;

[0009] read, from the PCIe module, a configuration version corresponding to the first stage bitstream as first version information in a case where it is detected that the PCIe module is started; and load the second stage bitstream and read a configuration version in the second stage bitstream as second version information;

[0010] write the second stage bitstream into the PCIe module to configure the hardware logic circuit of the FPGA chip if the first version information is consistent with the second version information.

[0011] In a second aspect, the disclosure provides an FPGA configuration method suitable for an FPGA chip, wherein the FPGA chip is deployed with a PCIe module; the method comprises:

[0012] obtaining a first stage bitstream of the PCIe module; wherein the first stage bitstream is generated by an upper computer based on first configuration information of the FPGA chip and a configuration version of the first configuration information and is synchronized to the FPGA chip; the first stage bitstream comprises the configuration version;

[0013] starting the PCIe module based on the first stage bitstream and writing the configuration version in the first stage bitstream into the PCIe module; wherein the upper computer is configured to read, from the PCIe module, a configuration version corresponding to the first stage bitstream as first version information in a case where it is detected that the PCIe module is started, load a second stage bitstream, read a configuration version in the second stage bitstream, and take the configuration version of the second stage bitstream as second version information; the second stage bitstream is generated by the upper computer based on the first configuration information and the configuration version; the second stage bitstream comprises the first configuration information and the configuration version; and the upper computer is further configured to write the second stage bitstream into the PCIe module if the first version information is consistent with the second version information.

[0014] read the second stage bitstream in the PCIe module to configure the hardware logic circuit of the FPGA chip.

[0015] In a third aspect, the disclosure provides an FPGA configuration system, comprising:

[0016] an FPGA chip deployed with a PCIe module, wherein the FPGA chip is configured to execute the FPGA configuration method of the first aspect described above;

[0017] an upper computer connected to the FPGA chip, wherein the upper computer is configured to execute the FPGA configuration method of the second aspect described above.

[0018] In a fourth aspect, the present disclosure provides a computer readable storage medium, which stores computer instructions for causing a computer to execute the FPGA configuration method of the first aspect or the second aspect.

[0019] The FPGA configuration method provided by the embodiments of the present disclosure, the host computer generates the first stage bitstream and the second stage bitstream of the PCIe module based on the first configuration information of the FPGA chip and the configuration version thereof. Then, the host computer synchronizes the first stage bitstream to the FPGA chip, so that the FPGA chip starts the PCIe module by using the first stage bitstream, and establishes the PCIe link with the host computer. Further, the host computer can determine the matching condition of the first stage bitstream loaded by the FPGA chip and the second stage bitstream to be loaded by detecting whether the configuration version corresponding to the first stage bitstream in the PCIe module is consistent with the configuration version in the second stage bitstream, in the case of detecting that the PCIe module is started. In the case of the first stage bitstream loaded by the FPGA chip and the second stage bitstream to be loaded, the second stage bitstream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip, so as to avoid the FPGA chip from being abnormal due to the mismatch between the first stage bitstream and the second stage bitstream loaded by the FPGA chip, and ensure the normal operation of the FPGA.

[0020] The beneficial effects of the FPGA configuration system and the computer readable storage medium correspond to the beneficial effects of the FPGA configuration method, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present disclosure or the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0022] Figure 1 is a framework schematic diagram of an FPGA configuration system according to an embodiment of the present disclosure;

[0023] Figure 2 is a flowchart schematic diagram of an FPGA configuration method according to an embodiment of the present disclosure;

[0024] Figure 3 is a reconfiguration flowchart schematic diagram of an FPGA according to an embodiment of the present disclosure;

[0025] Figure 4 is a flowchart schematic diagram of another FPGA configuration method according to an embodiment of the present disclosure;

[0026] Figure 5 is an interactive schematic diagram of an FPGA configuration system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure.

[0028] As a programmable hardware platform, a field programmable gate array (FPGA) has the characteristics of general flexibility, reconfigurability and parallel computing, and is widely used in many fields such as medical treatment, computing acceleration and communication signal processing. The FPGA can reconfigure the hardware logic circuit through programming to adapt to different application scenarios and realize specific digital logic functions.

[0029] With the continuous development of FPGA technology, the capacity and performance of FPGA chips are gradually improved, and the bitstream file containing the configuration information of the FPGA chip is also larger and larger, and the requirement for the Flash capacity for storing the bitstream is also increasing, thereby increasing the application cost of the FPGA.

[0030] Therefore, the related technology loads the bitstream of the FPGA configuration information through a peripheral component interconnect express (PCIe) loading mode to obtain a faster loading mode and reduce the requirement of the bitstream loading for the Flash capacity. The loading process of the PCIe mainly includes a first stage and a second stage. In the first stage, the FPGA chip loads the first stage bitstream from the Flash storing the first stage bitstream to make the PCIe module work, and then loads the second stage bitstream through the PCIe link to realize the configuration of the hardware logic circuit of the FPGA chip. Meanwhile, online upgrading or regional reconfiguration is supported. In the process of the online upgrading or regional reconfiguration of the FPGA, it is required that the second stage bitstream must be matched with the first stage bitstream.

[0031] However, with the continuous evolution of user applications, the number of bit streams of FPGA configuration information generated is increasing, and the management requirements for user bit stream files are facing greater challenges. If the first stage bit stream and the second stage bit stream loaded by the FPGA chip do not match, the FPGA chip will work abnormally, and even the FPGA chip will be burned out.

[0032] Therefore, according to the embodiments of the present disclosure, an FPGA configuration method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] Referring to Figure 1 , Figure 1 The FPGA configuration system provided by the present disclosure includes a host computer and an FPGA board card. The FPGA board card includes an FPGA chip, a PCIe module (not shown in the figure) and a target storage medium. The FPGA chip is configured with a configuration port, specifically a CFG (Configuration) port. The target storage medium is a non-volatile storage medium, such as a programmable read-only memory PROM or a Flash. The host computer uses a bit stream loading method of PCIe, generates a first stage bit stream and a second stage bit stream based on the first configuration information of the FPGA chip and the configuration version thereof. The host computer writes the first stage bit stream into the target storage medium. When the FPGA chip is powered on, the FPGA chip obtains the first stage bit stream from the target storage medium through the configuration port to start the PCIe module, build a PCIe link with the host computer, and load the second stage bit stream from the host computer through the PCIe link to configure the hardware logic circuit of the FPGA chip.

[0034] An FPGA configuration method is provided in the present embodiment, which can be used for the above-mentioned host computer, Figure 2 The flowchart of the FPGA configuration method according to the embodiments of the present disclosure is shown in Figure 2 The flowchart includes the following steps:

[0035] In step S201, the first configuration information of the FPGA chip and the configuration version corresponding to the first configuration information are obtained.

[0036] Specifically, the FPGA development tool is deployed in the host computer, and the host computer obtains the first configuration information and the configuration version thereof through the development tool.

[0037] In practical application, a user uses a hardware description language (HDL) or a schematic input tool in a development tool to describe a logical function of an FPGA chip for a PCIe segment loading characteristic. Then, a synthesis tool in the development tool is used to optimize the design of the logical function of the FPGA chip for the PCIe segment loading characteristic, to convert the HDL code into a gate netlist, so as to generate two independent bitstreams subsequently, wherein the gate netlist includes basic logic cells. Then, the development tool is used to determine the positions of the logic cells for the PCIe segment loading characteristic, to implement the layout of the logic cells, and to connect and wire the logic cells, so as to obtain first configuration information and a configuration version of the FPGA chip.

[0038] In step S202, first-stage and second-stage bitstreams of a PCIe module are generated based on the first configuration information and the configuration version; wherein the PCIe module is deployed on the FPGA chip; the first-stage bitstream includes the configuration version; and the second-stage bitstream includes the first configuration information and the configuration version.

[0039] Specifically, the development tool converts the first configuration information and the configuration version into FPGA-loadable bitstream files for the PCIe segment loading characteristic, to obtain the first-stage and second-stage bitstreams. The first-stage bitstream has a smaller data volume and usually includes the minimum logic required for initializing the PCIe module and establishing a PCIe link.

[0040] It should be noted that the PCIe module of the FPGA chip supports mapping of a bitstream to a register of an extended configuration space of the PCIe module. That is, the configuration version can be configured into the register of the extended configuration space of the PCIe module if the configuration version is written into a first preset position of the first-stage bitstream and a second preset position of the second-stage bitstream. The first and second preset positions can be configured as needed, such as a head position or a tail position of the bitstream, without limitation.

[0041] In step S203, the first-stage bitstream is synchronized to the FPGA chip; wherein the FPGA chip is configured to start the PCIe module based on the first-stage bitstream and write the configuration version in the first-stage bitstream into the PCIe module.

[0042] Specifically, step S203 includes writing the first-stage bitstream into a target storage medium connected to the FPGA chip; wherein the FPGA chip is configured to read the first-stage bitstream from the target storage medium when powered on, to start the PCIe module based on the first-stage bitstream, and to write the configuration version in the first-stage bitstream into the PCIe module.

[0043] Optionally, the target storage medium is a PROM, and can also be a Flash, without limitation.

[0044] In practical application, the host computer writes the first-stage bit stream into the target storage medium through a Flash programming tool. When the FPGA chip is powered on, the FPGA chip loads the first-stage bit stream from the target storage medium, configures the PCIe module and starts the PCIe module. Meanwhile, the FPGA chip writes the configuration version in the first-stage bit stream into the PCIe module. The configuration version of the first-stage bit stream can be written into the extended configuration space of the PCIe module.

[0045] It can be understood that the embodiment first writes the first-stage bit stream into the target storage medium connected to the FPGA chip, and waits for the FPGA chip to be powered on to read the first-stage bit stream from the target storage medium. Therefore, the loss of the first-stage bit stream due to power failure of the FPGA chip can be avoided, thereby improving the reliability of FPGA configuration. Moreover, since the FPGA chip automatically reads the first-stage bit stream from the target storage medium when powered on, manual intervention or participation of external equipment is not required, and the FPGA configuration process can be simplified. Then, the FPGA chip starts the PCIe module based on the first-stage bit stream, writes the configuration version in the first-stage bit stream into the PCIe module, thereby being able to build a PCIe link with the host computer to obtain the second-stage bit stream containing the first configuration information through the PCIe link, and reducing the demand for Flash capacity.

[0046] In step S204, in the case where it is detected that the PCIe module is started, the configuration version corresponding to the first-stage bit stream is read from the PCIe module as first version information, and the second-stage bit stream is loaded, and the configuration version in the second-stage bit stream is read as second version information.

[0047] Specifically, the driving software deployed in the host computer reads the configuration version of the first-stage bit stream previously written into the PCIe module as first version information when the driving software detects that the PCIe module is started. The driving software loads the second-stage bit stream generated by the development tool, and reads the configuration version in the second-stage bit stream as second version information.

[0048] In step S205, if the first version information is consistent with the second version information, the second-stage bit stream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip.

[0049] Specifically, if the first version information is consistent with the second version information, the driving software writes the second-stage bit stream into the PCIe module to enable the FPGA chip to configure the hardware logic circuit based on the first configuration information of the second-stage bit stream in the PCIe module.

[0050] The FPGA configuration method provided in the embodiment is that the host computer generates the first-stage bit stream and the second-stage bit stream of the PCIe module based on the first configuration information of the FPGA chip and the configuration version thereof. Then, the host computer synchronizes the first-stage bit stream to the FPGA chip, so that the FPGA chip starts the PCIe module by using the first-stage bit stream and establishes the PCIe link with the host computer. Further, the host computer can determine the matching condition of the first-stage bit stream loaded by the FPGA chip and the second-stage bit stream to be loaded by detecting whether the configuration version corresponding to the first-stage bit stream in the PCIe module is consistent with the configuration version in the second-stage bit stream, in the case that the PCIe module is started. In the case that the first-stage bit stream loaded by the FPGA chip and the second-stage bit stream to be loaded are consistent, the second-stage bit stream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip, so that the FPGA chip does not appear abnormal due to the inconsistency between the first-stage bit stream and the second-stage bit stream loaded by the FPGA chip, and the normal operation of the FPGA is ensured.

[0051] In some optional embodiments, the step S202 includes: constructing the check information of the configuration version; and generating the first-stage bit stream and the second-stage bit stream based on the first configuration information, the configuration version and the check information. The first-stage bit stream includes the configuration version and the check information; and the second-stage bit stream includes the first configuration information, the configuration version and the check information.

[0052] It can be understood that, in order to find the configuration version that is tampered by human or has error in time in the transmission process of the configuration version, the check information of the configuration version can be constructed by using a data check algorithm to ensure the validity of the configuration version in the transmission process of the configuration version. The data check algorithm includes parity check, exclusive-OR check, cyclic redundancy check (CRC) and the like.

[0053] Further, the FPGA chip is configured to write the configuration version and the check information in the first-stage bit stream into the PCIe module. The step S204 of reading the configuration version corresponding to the first-stage bit stream from the PCIe module includes: reading the configuration version and the check information corresponding to the first-stage bit stream from the PCIe module; performing data check on the read configuration version based on the check information to obtain a data check result; and taking the read configuration version as the first version information in the case that the data check result represents that the check is passed.

[0054] Understandably, if the step S202 adds data check to the configuration version by using the data check algorithm in the process of generating the first-stage bitstream and the second-stage bitstream, the FPGA chip writes the configuration version and the check information in the first-stage bitstream to the PCIe module after starting the PCIe module based on the first-stage bitstream. The driving software of the host computer reads the configuration version and the check information corresponding to the first-stage bitstream in the PCIe module, and performs data check (such as data integrity check) on the configuration version corresponding to the first-stage bitstream read from the PCIe module based on the check information and the data check algorithm to obtain a data check result. If the data check result represents that the check passes, the version information corresponding to the first-stage bitstream read from the PCIe module is taken as the first configuration information. If the data check result represents that the check fails, error information is generated, and the error information is used to indicate that the read configuration version has error or is tampered by human.

[0055] In some optional embodiments, the FPGA configuration method of the present disclosure further includes: if the first version information and the second version information are inconsistent, generating error information; wherein the error information is used to indicate that the first-stage bitstream and the second-stage bitstream are mismatched.

[0056] It is worth noting that if the PCIe module loads the wrong second-stage bitstream, it will cause the user to waste a lot of time to analyze and locate the error bitstream, thereby affecting the development and delivery progress of the FPGA chip, and even causing the FPGA chip to be burned out. Therefore, in the present embodiment, if the driving software of the host computer detects that the first version information and the second version information are inconsistent, error information is generated to timely prompt the user that the bitstreams are mismatched.

[0057] The FPGA configuration method provided in the present embodiment can check the matching of the first version information and the second version information by the host computer in the process of loading the second-stage bitstream by the PCIe module, and if they are inconsistent, error information is generated, so that the user can be timely informed of the loading error bitstream, and the user can be prevented from wasting a lot of time to analyze and locate the error bitstream due to the loading error bitstream, thereby improving the configuration efficiency of the FPGA chip.

[0058] In some optional embodiments, the FPGA configuration method of the present disclosure further includes:

[0059] In step a1, the second configuration information is acquired in response to a configuration update instruction for the configuration version. The acquisition method of the second configuration information can refer to the acquisition method of the first configuration information, which will not be described in detail here.

[0060] Step a2, generating an updated second stage bitstream based on the second configuration information and the configuration version; wherein the updated second stage bitstream comprises the second configuration information and the configuration version. The generation manner of the updated second stage bitstream can refer to the generation manner of the second stage bitstream in step S202, and will not be repeated here.

[0061] Step a3, reading the configuration version corresponding to the first stage bitstream from the PCIe module as the third version information. The acquisition manner of the third version information can refer to the acquisition manner of the first version information in step S204, and will not be repeated here.

[0062] Step a4, loading the updated second stage bitstream and reading the configuration version in the updated second stage bitstream as the fourth version information. The acquisition manner of the fourth version information can refer to the acquisition manner of the second version information in step S204, and will not be repeated here.

[0063] Step a5, if the third version information is consistent with the fourth version information, updating the second stage bitstream in the PCIe module based on the updated second stage bitstream.

[0064] It can be understood that, as the continuous evolution of user application, the number of bitstreams generated by FPGA chip upgrade is increasing, and if the first stage bitstream and the second stage bitstream loaded by the PCIe module do not match, it will cause the FPGA chip to work abnormally, and even cause the FPGA chip to burn out. Therefore, in the online upgrade process of the FPGA chip, after the host computer obtains the updated second configuration information, the host computer generates an updated second stage bitstream according to the second configuration information and the configuration version. Before the host computer updates the second stage bitstream in the PCIe module based on the updated second stage bitstream, it is first determined whether the configuration version corresponding to the first stage bitstream in the PCIe module is consistent with the configuration version of the updated second stage bitstream. If they are consistent, it means that the first stage bitstream loaded by the FPGA chip matches the updated second stage bitstream. At this time, the host computer can update the second stage bitstream in the PCIe module based on the updated second stage bitstream, thereby ensuring the accuracy of FPGA configuration update.

[0065] In some optional embodiments, the FPGA configuration method of the present disclosure further comprises:

[0066] Step b1, in response to a reconfiguration instruction for the first configuration information, obtaining reconfiguration information for the first configuration information.

[0067] Specifically, the configuration information in the first configuration information corresponding to the target region of the FPGA chip is reconfigured by using the development tool to generate a reconfiguration instruction. In response to the reconfiguration instruction, reconfiguration information for the first configuration information is obtained. The reconfiguration information includes reconfiguration information for the target region of the FPGA chip.

[0068] Step b2, based on the reconfiguration information and the configuration version, a reconfiguration bitstream for the second stage bitstream is generated; wherein the reconfiguration bitstream includes the configuration version and the reconfiguration information. The generation method of the reconfiguration bitstream can refer to the generation method of the second stage bitstream described above, and will not be described in detail here.

[0069] Step b3, the configuration version corresponding to the first stage bitstream is read from the PCIe module as the fifth version information. The acquisition method of the fifth version information can refer to the acquisition method of the first version information in the above step S204, and will not be described in detail here.

[0070] Step b4, load the reconfiguration bitstream and read the configuration version in the reconfiguration bitstream as the sixth version information. The acquisition method of the sixth version information can refer to the acquisition method of the second version information in the above step S204, and will not be described in detail here.

[0071] Step b5, if the fifth configuration version is consistent with the sixth configuration version, the second stage bitstream in the PCIe module is updated based on the reconfiguration bitstream.

[0072] Exemplarily, referring to Figure 3 , the reconfiguration block A (i.e. the target region) in the FPGA chip includes the configuration information corresponding to the reconfiguration block A in the first configuration information, and the development tool of the host computer is used to reconfigure the configuration information to obtain the reconfiguration information, so as to obtain the reconfiguration bitstream for the reconfiguration block A, for example, the reconfiguration bitstream A1-A4, so as to update the second stage bitstream in the PCIe module by using the reconfiguration bitstream, and then reconfigure the logic of the reconfiguration block A in the FPGA chip.

[0073] It can be understood that, as the continuous evolution of user applications, the number of bit streams generated by FPGA region reconfiguration is increasing, and if the first stage bit stream and the second stage bit stream loaded by the FPGA chip do not match, the FPGA chip will work abnormally, and even the FPGA chip will be burned out. Therefore, in the process of region reconfiguration of the FPGA chip, the host computer obtains the reconfiguration information, and generates a reconfiguration bit stream according to the reconfiguration information and the configuration version. Before the host computer updates the second stage bit stream in the PCIe module based on the reconfiguration bit stream, it is determined whether the configuration version corresponding to the first stage bit stream in the PCIe module is consistent with the configuration version of the reconfiguration bit stream. If they are consistent, it means that the first stage bit stream, the second stage bit stream and the reconfiguration bit stream in the PCIe module match, and the host computer updates the second stage bit stream in the PCIe module based on the reconfiguration bit stream, thereby ensuring the accuracy of FPGA region reconfiguration.

[0074] In the embodiment, an FPGA configuration method is provided, which can be used for the FPGA chip described above, and the PCIe module is deployed on the FPGA chip. Figure 4 is a flowchart of another FPGA configuration method according to an embodiment of the present disclosure, as shown in Figure 4 The flowchart includes the following steps:

[0075] In step S401, the first stage bit stream of the PCIe module is obtained; wherein the first stage bit stream is generated by the host computer based on the first configuration information of the FPGA chip and the configuration version of the first configuration information, and is synchronized to the FPGA chip; the first stage bit stream includes the configuration version. For details, please refer to the related information of steps S201-S202 described above, which will not be repeated here.

[0076] In step S402, the PCIe module is started based on the first stage bit stream, and the configuration version in the first stage bit stream is written into the PCIe module; wherein the host computer is configured to read the configuration version corresponding to the first stage bit stream from the PCIe module as the first version information when detecting that the PCIe module is started, and load the second stage bit stream, read the configuration version in the second stage bit stream, and take the configuration version of the second stage bit stream as the second version information; the second stage bit stream is generated by the host computer based on the first configuration information and the configuration version; the second stage bit stream includes the first configuration information and the configuration version; the host computer is further configured to write the second stage bit stream into the PCIe module if the first version information is consistent with the second version information. For details, please refer to the related information of steps S203-S205 described above, which will not be repeated here.

[0077] In step S403, the second stage bit stream in the PCIe module is read to configure the hardware logic circuit of the FPGA chip.

[0078] The FPGA configuration method provided in the embodiment is characterized in that the host computer generates the first-stage bitstream and the second-stage bitstream of the PCIe module based on the first configuration information of the FPGA chip and the configuration version thereof. Then, the host computer synchronizes the first-stage bitstream to the FPGA chip, so that the FPGA chip starts the PCIe module by using the first-stage bitstream and establishes the PCIe link with the host computer. Further, the host computer can determine the matching condition of the first-stage bitstream loaded by the FPGA chip and the second-stage bitstream to be loaded by detecting whether the configuration version corresponding to the first-stage bitstream in the PCIe module is consistent with the configuration version in the second-stage bitstream. In the case that the first-stage bitstream loaded by the FPGA chip and the second-stage bitstream to be loaded are consistent, the second-stage bitstream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip, thereby avoiding the FPGA chip from being abnormal due to the inconsistency between the first-stage bitstream and the second-stage bitstream loaded by the FPGA chip and ensuring the normal operation of the FPGA.

[0079] In some optional embodiments, the FPGA chip is connected with a target storage medium. The step S401 comprises: reading the first-stage bitstream from the target storage medium at power-on; wherein the first-stage bitstream in the target storage medium is written by the host computer.

[0080] Optionally, the target storage medium is PROM, and can also be Flash, which is not limited herein.

[0081] Specifically, the host computer writes the first-stage bitstream into the target storage medium by using a Flash programming tool. When the FPGA chip is powered on, the FPGA chip loads the first-stage bitstream from the target storage medium, configures the PCIe module and starts the PCIe module. Meanwhile, the FPGA chip writes the first-stage bitstream into the PCIe module. The configuration version of the first-stage bitstream can be written into the extended configuration space of the PCIe module.

[0082] As one of the specific application examples, refer to Figure 5 The overall flow of the FPGA configuration method of the present disclosure mainly comprises: for the PCIe segment loading characteristics, the development tool of the FPGA generates the first-stage bitstream and the second-stage bitstream after the processing steps of synthesis, layout, routing and bitstream generation, and the corresponding preset positions in the first-stage bitstream and the second-stage bitstream contain the configuration version of the first configuration information. The host computer writes the first-stage bitstream into the target storage medium (such as PROM) by using a Flash programming tool. When the FPGA chip is powered on, the FPGA chip loads the first-stage bitstream from the target storage medium, configures the PCIe module and starts the PCIe module, and writes the configuration version in the first-stage bitstream into the extended configuration space of the PCIe module. Refer to Figure 5The PCIe module includes a first configuration space and a second configuration space. The first configuration space is a regular configuration space, and is used to store regular configurations of the PCIe module in the first-stage bitstream, such as startup information. The second configuration space is an extended configuration space, and is used to store differentiated configurations such as a configuration version in the first-stage bitstream and the second-stage bitstream. The host computer detects that the PCIe module is started, reads the configuration version corresponding to the first-stage bitstream in the PCIe module as first version information. The host computer loads the second-stage bitstream generated by the development tool, and reads the configuration version in the second-stage bitstream as second version information. The host computer checks whether the first version information and the second version information are consistent. If the first version information and the second version information are consistent, the host computer loads the second-stage bitstream to the PCIe module. If the first version information and the second version information are inconsistent, the host computer prompts the user that the first-stage bitstream and the second-stage bitstream are inconsistent.

[0083] The FPGA configuration method of the present disclosure supports mapping of a bitstream to a register in the extended configuration space of a PCIe module of an FPGA chip, that is, filling a configuration version in a preset position of the first-stage bitstream and the second-stage bitstream, and the configuration version can be configured to the register in the extended configuration space of the PCIe module. Moreover, when the first-stage bitstream and the second-stage bitstream are generated, the first-stage bitstream and the second-stage bitstream both contain the same configuration version. When the host computer loads the second-stage bitstream, the host computer can perform matching checking according to the configuration versions of the first-stage bitstream and the second-stage bitstream, to ensure that the first-stage bitstream and the second-stage bitstream loaded by the FPGA chip are matched. Meanwhile, data checking logic can be added to the configuration version, to ensure the integrity of the configuration version. Furthermore, in the process of loading the bitstream, online upgrading, or regional reconfiguration of the PCIe module, the FPGA configuration method of the present disclosure can timely inform the user of the error bitstream loaded by the user, improve the efficiency of the user in locating the error bitstream, and avoid abnormality of the FPGA chip due to the inconsistency between the first-stage bitstream and the second-stage bitstream.

[0084] In the present embodiment, an FPGA configuration system is also provided, as shown in Figure 1 The FPGA configuration system includes an FPGA chip and a host computer. The FPGA chip is deployed with a PCIe module, and the FPGA chip is configured to perform the FPGA configuration method suitable for the FPGA chip. The host computer is connected with the FPGA chip, and the host computer is configured to perform the FPGA configuration method suitable for the host computer.

[0085] In some optional embodiments, the FPGA configuration system further includes a target storage medium. The FPGA chip is connected with the target storage medium.

[0086] In some alternative embodiments, the target storage medium is a read-only memory or a flash memory, and other non-volatile memories can also be used, which are not limited herein.

[0087] Further function descriptions of the elements of the FPGA configuration system are the same as those of the above-mentioned corresponding embodiments, which are not described herein again.

[0088] The embodiments of the present disclosure further provide a computer readable storage medium, and the method according to the embodiments of the present disclosure can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer code stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general-purpose computer, a special-purpose processor, or programmable or special-purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, the processor, or the hardware, implements the FPGA configuration method suitable for the FPGA chip or the host computer shown in the above embodiments.

[0089] Part of the present disclosure can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present disclosure can be invoked or provided. Those skilled in the art should understand that the form of the computer program instructions in the computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way of executing the computer program instructions by the computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer obtains and executes the instructions, or the computer obtains and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0090] Although the embodiments of the present disclosure are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present disclosure, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A FPGA configuration method, characterized in that: Applicable to a host computer, the method includes: Obtaining first configuration information of the FPGA chip and a configuration version corresponding to the first configuration information; Based on the first configuration information and the configuration version, generating a first-stage bitstream and a second-stage bitstream of a PCIe module; wherein the PCIe module is deployed on the FPGA chip; the first-stage bitstream includes the configuration version; and the second-stage bitstream includes the first configuration information and the configuration version; Synchronizing the first-stage bitstream to the FPGA chip; wherein the FPGA chip is configured to start the PCIe module based on the first-stage bitstream and write the configuration version in the first-stage bitstream into the PCIe module; When detecting that the PCIe module is started, reading the configuration version corresponding to the first-stage bitstream from the PCIe module as first version information; and loading the second-stage bitstream and reading the configuration version in the second-stage bitstream as second version information; If the first version information is consistent with the second version information, the second stage bit stream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip.

2. The FPGA configuration method according to claim 1, wherein: The step of synchronizing the first-stage bit stream to the FPGA chip includes: The first-stage bitstream is written to a target storage medium connected to the FPGA chip; wherein the FPGA chip is configured to read the first-stage bitstream from the target storage medium when powered on, start the PCIe module based on the first-stage bitstream, and write the configuration version in the first-stage bitstream to the PCIe module.

3. The FPGA configuration method according to claim 2, wherein: The first stage bitstream further includes verification information of the configuration version; the FPGA chip is configured to write the configuration version and verification information in the first stage bitstream into the PCIe module; The step of reading the configuration version corresponding to the first-stage bitstream from the PCIe module as first version information includes: Reading the configuration version and verification information corresponding to the first-stage bit stream from the PCIe module; Performing data verification on the read configuration version based on the verification information to obtain a data verification result; If the data verification result indicates that the verification is passed, the read configuration version is used as the first version information.

4. The FPGA configuration method according to claim 1, wherein: The method further comprises: If the first version information is inconsistent with the second version information, an error message is generated; wherein the error message is used to indicate that the first stage bit stream is inconsistent with the second stage bit stream.

5. The FPGA configuration method according to claim 1, wherein: The method further comprises: In response to a configuration update instruction for the configuration version, obtaining second configuration information; generating an updated second-stage bitstream based on the second configuration information and the configuration version; wherein the updated second-stage bitstream includes the second configuration information and the configuration version; Reading a configuration version corresponding to the first-stage bitstream from the PCIe module as third version information; Loading the updated second-stage bitstream, and reading the configuration version in the updated second-stage bitstream as fourth version information; If the third version information is consistent with the fourth version information, the second stage bitstream in the PCIe module is updated based on the updated second stage bitstream.

6. The FPGA configuration method according to claim 1, wherein: The method further comprises: In response to a reconfiguration instruction for the first configuration information, acquiring reconfiguration information for the first configuration information; Based on the reconfiguration information and the configuration version, generating a reconfiguration bitstream for the second-stage bitstream; wherein the reconfiguration bitstream includes the configuration version and the reconfiguration information; Reading a configuration version corresponding to the first-stage bitstream from the PCIe module as fifth version information; Loading the reconfigured bitstream, and reading the configuration version in the reconfigured bitstream as sixth version information; If the fifth version information is consistent with the sixth version information, the second stage bitstream in the PCIe module is updated based on the reconfiguration bitstream.

7. A FPGA configuration method, characterized in that: Applicable to an FPGA chip, wherein a PCIe module is deployed on the FPGA chip; the method includes: Obtaining a first-stage bitstream of the PCIe module; wherein the first-stage bitstream is generated by a host computer based on first configuration information of the FPGA chip and a configuration version of the first configuration information and synchronized to the FPGA chip; the first-stage bitstream includes the configuration version; The PCIe module is started based on the first-stage bitstream, and the configuration version in the first-stage bitstream is written into the PCIe module; wherein, the host computer is configured to, upon detecting that the PCIe module is started, read the configuration version corresponding to the first-stage bitstream from the PCIe module as the first version information, and load the second-stage bitstream, read the configuration version in the second-stage bitstream, and use the configuration version of the second-stage bitstream as the second version information; the second-stage bitstream is generated by the host computer based on the first configuration information and the configuration version; the second-stage bitstream includes the first configuration information and the configuration version; the host computer is further configured to write the second-stage bitstream into the PCIe module if the first version information is consistent with the second version information; The second stage bit stream in the PCIe module is read to configure the hardware logic circuit of the FPGA chip.

8. The FPGA configuration method according to claim 7, wherein: The FPGA chip is connected to a target storage medium; and obtaining the first-stage bit stream of the PCIe module includes: The first-stage bit stream is read from the target storage medium when power is turned on; wherein the first-stage bit stream in the target storage medium is written by the host computer.

9. An FPGA configuration system, characterized in that: include: An FPGA chip having a PCIe module deployed thereon, the FPGA chip being configured to execute the FPGA configuration method according to claim 7 or 8; A host computer is connected to the FPGA chip, and the host computer is configured to execute the FPGA configuration method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the FPGA configuration method according to any one of claims 1 to 6, or to execute the FPGA configuration method according to any one of claims 7 to 8.

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