Input message signal interruption controller and method based on RISC-V architecture
By introducing the IMSIC module into the RISC-V architecture and using hardware wiring to directly access the CSR register, the problem of large bus access delay in the interrupt controller is solved, and the interrupt delay is significantly reduced and the processing efficiency is improved.
Patent Information
- Application Number
- CN202510731256.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-03
- Publication Date
- 2025-10-17
AI Technical Summary
The interrupt controller of the traditional RISC-V architecture has a large bus access delay during the interrupt response process, resulting in a long interrupt processing delay, affecting system efficiency.
An input message signal interrupt controller (IMSIC) based on the RISC-V architecture was designed. It directly accessed the CSR register through hardware wiring, reduced the number of bus accesses, and reduced the interrupt latency to 1-2 clock cycles.
The bus load and delay during interrupt processing are significantly reduced, and the interrupt response efficiency is improved.
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Figure CN120803626A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of integrated circuit processor design, and particularly relates to an input message signal interrupt controller and method based on a RISC-V architecture. BACKGROUND
[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.
[0003] The interrupt processing system is a key component in the processor, and is indispensable for guaranteeing the efficient operation of the system and optimizing resource management. With the rapid development of cloud computing, scientific computing and other fields, modern interrupt systems have higher demands for multi-core virtualization support and fast interrupt response.
[0004] The RISC-V architecture has shown great potential from power-sensitive embedded scenarios to speed-priority high-performance computing scenarios due to its open source, modularity and scalability. As an emerging instruction set architecture, the interrupt system design of RISC-V also faces similar challenges and opportunities. In combination with the current development status of the domestic and foreign semiconductor industry, RISC-V has attracted many followers and developers in China. The interrupt architecture of RISC-V has been continuously exploring new architectures from the early Platform-Level Interrupt Controller (PLIC) to the recently released Advanced Interrupt Architecture (AIA). As the early interrupt controller adopted by RISC-V, PLIC supports interrupt management and priority scheduling of multi-core processors, processes interrupt requests from multiple devices through centralized interrupt management, and supports interrupt masking and priority setting. AIA, as the new advanced interrupt architecture of RISC-V, aims to improve the efficiency and flexibility of interrupt processing, supports virtualization and multi-core processing, can efficiently manage and distribute virtual interrupts, and ensure low-latency and high-throughput interrupt processing.
[0005] After the traditional PLIC interrupt controller receives the interrupt suspension information, it accesses the priority register through the bus to obtain the interrupt information and clear the suspension information of the interrupt source (the interrupt collection valve will be released only after the interrupt response is completely finished), and then transmits the completion information to the PLIC controller through the bus after the interrupt response is finished. This process involves two uses of the bus, and the delay overhead is large. SUMMARY
[0006] In order to solve the above problems, the application provides an input message signal interrupt controller and method based on RISC-V architecture, the IMSIC module designed by the application has a direct access path between the CSR register of the RISC-V processor, and the implementation mode of hardware connection instead of bus can reduce the interrupt delay to 1-2 clock cycles, and the effect of significantly reducing the interrupt processing delay can be achieved.
[0007] According to some embodiments, the first aspect of the application provides an input message signal interrupt controller based on RISC-V architecture, which adopts the following technical solutions: The input message signal interrupt controller based on RISC-V architecture comprises a plurality of interrupt files, wherein each interrupt file comprises an interrupt receiving module, a register stack module and an external interrupt arbitrator; The interrupt receiving module receives input message signal interrupt information, stores the interrupt number corresponding to the interrupt index in the input message signal into the interrupt number register, and stores the address corresponding to the interrupt file index into the external interrupt suspension register according to the order of the interrupt number in the interrupt number register; The register stack module comprises an interrupt number register, an external interrupt enable register, an external interrupt suspension register, a highest priority register, an interrupt file opening register and an external interrupt threshold register; The external interrupt arbitrator arbitrates the suspension information in the external interrupt suspension register and the enable information in the external interrupt enable register based on the interrupt number in the interrupt number register, and determines whether it can be stored into the highest priority register.
[0008] Further, the input message signal interrupt information comprises an interrupt index and an interrupt file index; The interrupt index corresponds to the interrupt number of each interrupt in each interrupt file; The interrupt file index corresponds to the address of each interrupt file.
[0009] Further, based on the interrupt number in the interrupt number register, the suspension information in the external interrupt suspension register and the enable information in the external interrupt enable register are arbitrated to determine whether it can be stored into the highest priority register, specifically: The interrupt numbers in the interrupt number register are circularly traversed in ascending order, and it is judged whether the suspension information corresponding to each interrupt number in the external interrupt suspension register and the enable information in the external interrupt enable register are all 1; If they are all 1, the corresponding interrupt number is stored into the highest priority register; If they are not all 1, it is returned to continue to be judged.
[0010] Furthermore, the interrupt file opening register stores valid data in the lowest bit. When the lowest bit is 1, the interrupt file is opened, indicating that the content is valid.
[0011] Furthermore, the external interrupt threshold register stores an interrupt number corresponding to the external interrupt threshold. During the arbitration process, only an interrupt with a priority higher than the interrupt number corresponding to the external interrupt threshold is eligible to participate in the arbitration.
[0012] Furthermore, the external interrupt suspension register stores interrupt suspension information, that is, the interrupt corresponding to the input message signal interrupt information needs to be suspended.
[0013] Furthermore, the external interrupt enable register stores enable information, that is, enabled interrupts.
[0014] According to some embodiments, a second solution of the present invention provides an input message signal interrupt control method based on the RISC-V architecture, which adopts the following technical solutions: The input message signal interrupt control method based on the RISC-V architecture adopts the input message signal interrupt controller based on the RISC-V architecture described in the first solution, including: Receive interrupt information of an input message signal, store the interrupt number corresponding to the interrupt index in the input message signal into the interrupt number register, and store the address corresponding to the interrupt file index into the external interrupt pending register according to the interrupt number sequence in the interrupt number register; Based on the interrupt number in the interrupt number register, the suspend information in the external interrupt suspend register and the enable information in the external interrupt enable register are judged to determine whether they can be stored in the highest priority register.
[0015] According to some embodiments, a third solution of the present invention provides a chip, comprising the input message signal interrupt controller based on the RISC-V architecture described in the first solution.
[0016] According to some embodiments, a fourth embodiment of the present invention provides an electronic device, comprising the input message signal interrupt controller based on the RISC-V architecture described in the third embodiment.
[0017] Compared with the prior art, the present invention has the following beneficial effects: There is a direct access path between the IMSIC module designed in the present invention and the CSR register of the RISC-V processor. The interrupt latency can be reduced to 1-2 clock cycles by using hardware connection instead of bus, which can significantly reduce the bus load and interrupt latency during interrupt processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.
[0019] Figure 1 This is a structural diagram of an IMSIC according to an embodiment of the present invention; Figure 2 This is a flow chart of an interrupt file arbitrator according to an embodiment of the present invention; Figure 3 It is an interrupt system with IMSIC in an embodiment of the present invention. DETAILED DESCRIPTION
[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0021] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs.
[0022] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0023] In the absence of conflict, the embodiments of the present invention and the features thereof may be combined with each other.
[0024] Example 1 like Figure 1 As shown, this embodiment provides an input message signal interrupt controller based on the RISC-V architecture, including multiple interrupt files, wherein each interrupt file includes an interrupt receiving module, a register stack module and an external interrupt arbiter; The interrupt receiving module receives the interrupt information of the input message signal, stores the interrupt number corresponding to the interrupt index in the input message signal into the interrupt number register, and stores the address corresponding to the interrupt file index into the external interrupt pending register according to the interrupt number sequence in the interrupt number register; The register stack module includes the interrupt number register, external interrupt enable register, external interrupt pending register, highest priority register, interrupt file enable register and external interrupt threshold register; The external interrupt arbiter makes a decision on whether to store into the highest priority register based on the interrupt number in the interrupt number register, the pending information in the external interrupt pending register and the enable information in the external interrupt enable register.
[0025] IMSIC (Input Message Signal Interrupt Controller) is a new module added to the RISC-V instruction set to support MSI type interrupts. It is tightly coupled with the core and each core corresponds to an IMSIC. The IMSIC module receives and records incoming message signal interrupts and sends interrupt information to be responded to the core.
[0026] An IMSIC module has one or more memory-mapped registers in the address space of the machine for receiving interrupt messages. In addition to these memory-mapped registers, software can also interact with IMSIC through several RISC-V control and status registers attached to the core, which will be described in more detail in the Smaia and Ssaia extensions. Figure 1 The structure diagram of IMSIC top layer is shown, which contains two interrupt files, respectively processing machine mode and super user mode interrupt messages.
[0027] Based on the provisions of RISC-V AIA architecture, the IMSIC is designed to implement the following functions: 1) An M-level interrupt file and an S-level interrupt file are implemented in each IMSIC, and guest interrupt files are supported under virtual extension; 2) Implement a non-direct read-write channel for the registers in each interrupt file CSR; 3) Implement an AXI Lite receiving channel for MSI in each interrupt file, and record the external interrupt minor ID (eiid-priority) to the corresponding external interrupt waiting register according to the address information of MSI; 4) Implement priority arbitration logic in each interrupt file, write the highest priority enable and pending interrupt eiid to the xtopei CSR, and notify the hart that there is an interrupt to be processed. (The pending array in the interrupt file refers to the information array that stores the state of the interrupt request; the enable array in the interrupt file refers to the register array used to enable or disable interrupts) For machine mode, the relevant control and status registers (CSRs) are miselect, mireg and mtopel. When implementing the super-user mode, the set of CSRs is the same as the machine level: siselect, sireg and stopei. When implementing the virtual machine hypervisor extension, there are three corresponding virtual machine level CSRs: vsiselect, vsireg and vstopei, each level interrupt file has the same effect. For a given privilege level, the value of the xiselect CSR in the range of 0x70 to 0xFF will select these registers in the corresponding interrupt file.
[0028] The register numbers 0x71 and 0x73 to 0x7F are reserved, when the xiselect control and status register accesses one of these values, the read from the matching xireg CSR (mireg, sireg or vsireg) will return zero and the write to the xireg CSR will be ignored.
[0029] The implementation of the interrupt file mainly includes three modules: 1) MSI_channel receiving module, responsible for accepting the MSI message sent by the device or APLIC, according to its address and data information, through the setipnum (interrupt number register) is set to the corresponding eip (external interrupt pending register) bit.
[0030] The input message signal interrupt information includes interrupt index and interrupt file index; The interrupt index corresponds to the interrupt number of each interrupt in each interrupt file; The interrupt file index corresponds to the address of each interrupt file.
[0031] 2) External interrupt arbitrator (Arbitrator), after the MSI receiving module, the corresponding eip bit will be set according to the index of eiid, because the priority is higher when the eiid is smaller, that is, at this time eip[i] has been sorted according to the priority from high to low, so the interrupt priority information is completed from the MSI message to the eip register position, and the logic delay of priority arbitration is obviously improved.
[0032] Based on the interrupt number in the interrupt number register, the pending information in the external interrupt pending register and the enable information in the external interrupt enable register are arbitrated to determine whether it can be stored in the highest priority register, specifically: According to the order from small to large, the interrupt numbers in the interrupt number register are looped, and it is judged whether the pending information corresponding to each interrupt number in the external interrupt pending register and the enable information in the external interrupt enable register are all 1; If both are 1, the corresponding interrupt number is stored in the highest priority register; If not both are 1, return to continue to judge.
[0033] 3) Interrupt file register stack module, this module realizes all address mapping registers required by the interrupt file defined by AIA, which are described in the last section. The register stack module has three interface spaces: the non-direct access read-write channel between the CSR module and the regmap (register stack module), as shown in Table 1, the MSI receiving module receives setipnum and eip write channel, outputs eip (external interrupt enable register), eie (external interrupt enable register), eidelivery (interrupt file opening register) participates in the arbitrator to select the highest priority interrupt.
[0034] Table 1 Interrupt file non-direct access registers
[0035] Eithreshold (external interrupt threshold register) stores the interrupt number corresponding to the external interrupt threshold. In the arbitration process, only when the interrupt priority is higher than the interrupt number corresponding to the external interrupt threshold, it has the qualification to participate in arbitration.
[0036] The interrupt file opening register stores the lowest bit of the valid data. When the lowest bit is 1, the interrupt file is opened, indicating that the content is valid.
[0037] The external interrupt pending register stores the interrupt pending information, that is, the interrupt information corresponding to the input message signal needs to be suspended.
[0038] The external interrupt enable register stores the enable information, that is, the enabled interrupt.
[0039] MSI receiving channel: The function of the receiving channel is to receive the MSI message transmitted from the device or APLIC, and to enable the setipnum write through MSI under the condition of 128 interrupt SRC, and to write the interrupt request to the eip register.
[0040] Arbitration module, Figure 2 The design structure diagram of the arbitrator is shown. Since the MSI receiving module has written the priority information to the location information of eip, by traversing all implemented interrupt numbers, the lowest bit (bit, binary bit) enable and pending interrupt number can be arbitrated and the arbitration result can be output.
[0041] Each interrupt file corresponds to an APLIC interrupt domain, Figure 3The process of IMSIC receiving and sending interrupts is shown, csr2imsic is the direction of the processor configuration interrupt file, miselect selects which register to configure, and mireg contains the configuration information.
[0042] csr2imsic_addr, indicating the address from the csr module to the imsic module; csr2imsic_data, indicating the data from the csr module to the imsic module.
[0043] Single message signal interrupts from devices should be issued by the device in naturally aligned 32-bit write form, with both address and value configured on the device by software. Depending on the version of the standard being followed by the device or controller, the address can be limited to the lower 4GB (32-bit) range, the value written can be limited to the 16-bit range, and the upper 16 bits are always zero.
[0044] When a RISC-V processor core is equipped with IMSIC, MSI from a device is usually sent directly to a single processor core selected by software that is responsible for handling the interrupt. By receiving the corresponding interrupt file present in the IMSIC of the receiving processor core, the MSI is directed to a specific privilege level or a specific virtual processor core.
[0045] The MSI write address is the physical address of a specific word length register that is physically connected to the target interrupt file. The MSI write data is simply the identification number of the interrupt to be triggered.
[0046] Embodiment two The embodiment provides a RISC-V architecture-based input message signal interrupt control method, adopts the RISC-V architecture-based input message signal interrupt controller as described in embodiment one, and comprises the following steps of: Receiving input message signal interrupt information, storing an interrupt number corresponding to an interrupt based on an interrupt index in the input message signal into an interrupt number register, and storing an address corresponding to an interrupt file index into an external interrupt pending register in sequence according to the interrupt number in the interrupt number register; Based on the interrupt number in the interrupt number register, the enabling information in the external interrupt enable register and the pending information in the external interrupt pending register are judged to determine whether the highest priority register can be stored.
[0047] Embodiment three The embodiment provides a chip, which comprises the RISC-V architecture-based input message signal interrupt controller as described in embodiment one.
[0048] Embodiment four The embodiment provides an electronic device, including the input message signal interrupt controller based on the RISC-V architecture described in embodiment three.
[0049] Although the specific embodiments of the present application are described above with reference to the drawings, the description is not a limitation on the scope of protection of the present application, and those skilled in the art should understand that various modifications or changes made on the basis of the technical solutions of the present application without creative labor are still within the protection scope of the present application.
Claims
1. An input message signal interrupt controller based on RISC-V architecture, characterized in that: The system comprises a plurality of interrupt files, wherein each interrupt file comprises an interrupt receiving module, a register stack module and an external interrupt arbiter; The interrupt receiving module receives the interrupt information of the input message signal, stores the interrupt number corresponding to the interrupt index in the input message signal into the interrupt number register, and stores the address corresponding to the interrupt file index into the external interrupt pending register according to the interrupt number sequence in the interrupt number register; The register stack module includes the interrupt number register, external interrupt enable register, external interrupt pending register, highest priority register, interrupt file enable register and external interrupt threshold register; The external interrupt arbiter decides on the suspend information in the external interrupt suspend register and the enable information in the external interrupt enable register based on the interrupt number in the interrupt number register to determine whether the highest priority register can be stored.
2. The input message signal interrupt controller based on RISC-V architecture according to claim 1, characterized in that: The input message signal interruption information includes an interruption index and an interruption file index; The interrupt index corresponds to the interrupt number of each interrupt in each interrupt file; The interrupt file index corresponds to the address of each interrupt file.
3. The input message signal interrupt controller based on RISC-V architecture according to claim 1, characterized in that: Based on the interrupt number in the interrupt number register, the suspension information in the external interrupt suspension register and the enable information in the external interrupt enable register are judged to determine whether they can be stored in the highest priority register, specifically: Loop through the interrupt numbers in the interrupt number register in ascending order, and determine whether the suspend information corresponding to each interrupt number in the external interrupt suspend register and the enable information in the external interrupt enable register are all 1; If both are 1, the corresponding interrupt number is stored in the highest priority register; If they are not all 1, return to continue judging.
4. The input message signal interrupt controller based on RISC-V architecture according to claim 1, characterized in that: The interrupt file opening register stores valid data in the lowest bit. When the lowest bit is 1, the interrupt file is opened, indicating that the content is valid.
5. The input message signal interrupt controller based on RISC-V architecture according to claim 1, characterized in that: The external interrupt threshold register stores the interrupt number corresponding to the external interrupt threshold. During the arbitration process, only the interrupt priority level is higher than the interrupt number corresponding to the external interrupt threshold and is eligible to participate in the arbitration.
6. The input message signal interrupt controller based on RISC-V architecture according to claim 1, characterized in that: The external interrupt suspend register stores interrupt suspend information, that is, the interrupt corresponding to the input message signal interrupt information needs to be suspended.
7. The input message signal interrupt controller based on RISC-V architecture according to claim 1, characterized in that: The external interrupt enable register stores enable information, that is, enabled interrupts.
8. An input message signal interrupt control method based on RISC-V architecture, using the input message signal interrupt controller based on RISC-V architecture according to any one of claims 1 to 7, characterized in that: include: Receive interrupt information of an input message signal, store the interrupt number corresponding to the interrupt index in the input message signal into the interrupt number register, and store the address corresponding to the interrupt file index into the external interrupt pending register according to the interrupt number sequence in the interrupt number register; Based on the interrupt number in the interrupt number register, the suspend information in the external interrupt suspend register and the enable information in the external interrupt enable register are judged to determine whether they can be stored in the highest priority register.
9. A chip, characterized in that: An input message signal interrupt controller based on the RISC-V architecture comprising any one of claims 1 to 7.
10. An electronic device, characterized in that: Including the input message signal interrupt controller based on RISC-V architecture as described in claim 9.