Test board card self-checking method and system, test equipment and electronic equipment

Abstract

The embodiment of the invention discloses a test board card self-checking method and system, test equipment and electronic equipment, and the method comprises the steps: detecting the function of a target controller, generating an abnormal mark corresponding to an abnormal function when detecting that the abnormal function exists in the target controller, and when the target controller is a second controller or a third controller, generating the abnormal mark corresponding to the abnormal function; the target controller transmits the abnormal mark to the first controller through the first communication interface, the first controller stores the abnormal mark in the storage device corresponding to the abnormal mark, and the first controller inquires each abnormal storage unit; and the storage state of the abnormal storage control unit is updated when it is determined that the abnormal mark is stored in the at least one abnormal storage unit. Therefore, the target function state of each functional chip in the test board card is detected in the initialization stage and the test stage, additional operation on the test board card is not needed, the efficiency of obtaining the state of the functional chip is improved, and the reliability of the test result of the chip test equipment is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to chip testing technology, and in particular to a test board card self-checking method and system, a test device and electronic equipment. BACKGROUND

[0002] A chip testing device is used to test the function and / or performance of a chip. In the related art, the operation of the chip testing device mainly includes an initialization phase and a testing phase. In the initialization phase, the initial state of the hardware can be configured through a business scenario.

[0003] In the implementation of the present application, it is found through research that in the related art, there is a lack of active detection mechanism for the real-time state of the hardware in the chip testing device in the initialization phase and the testing phase. In the initialization phase, if the hardware state needs to be obtained, the register or peripheral device needs to be additionally operated to indirectly determine whether the hardware is normal, which results in low efficiency and increased operation complexity. In the testing phase, the hardware state can only be determined to be abnormal through experience when the chip testing device is stuck or has communication abnormalities, which not only results in poor accuracy of the determination of the hardware state, but also results in a "false PASS" phenomenon (i.e., the test result is displayed as passed due to the abnormal fault of the hardware state) because the hardware state cannot be detected in real time, which seriously affects the reliability of the test result. SUMMARY

[0004] To solve the above technical problems, the present application provides a test board card self-checking method, system, test device and electronic equipment.

[0005] In one aspect of the present application, a test board card self-checking method is provided, which is applied to a test device, the test device includes a host computer and a slave computer, the slave computer includes a test board card, the test board card includes a first controller, N second controllers and M third controllers connected in sequence, the method includes: in an initialization phase and a testing phase of the test device, the running function of a target controller is detected in real time, and when an abnormal function exists in the target controller, an abnormal flag corresponding to the abnormal function is generated, the target controller is at least one of the first controller, the N second controllers or the M third controllers; in response to the target controller being the second controller or the third controller, the abnormal flag is transmitted to the first controller by the target controller through a first communication interface; the first controller stores the abnormal flag corresponding to each target controller to an abnormal storage unit, the abnormal storage unit is used to store each abnormal flag corresponding to each target controller in a partitioned manner; the first controller queries the abnormal storage unit, and when it is determined that the abnormal flag is stored in the abnormal storage unit, the storage state of an abnormal storage control unit is updated.

[0006] In another aspect of the embodiments of the present disclosure, a test board card self-checking system is provided, which is applied to a test device, the test device comprising a host computer and a slave computer, the slave computer comprising a test board card, the test board card comprising a first controller, N second controllers and M third controllers connected in sequence, the test board card self-checking system comprising: a first detection module configured to detect a running function of a target controller in an initialization stage and a test stage of the test device, and generate an abnormal flag corresponding to an abnormal function when detecting that the target controller has the abnormal function, the target controller being one of the first controller, the N second controllers or the M third controllers; an abnormal data transmission module configured to, in response to the target controller being a second controller or a third controller, transmit the abnormal flag from the target controller to the first controller through a first communication interface; an abnormal storage module configured to store the abnormal flag corresponding to each of the target controllers in an abnormal storage unit by the first controller, the abnormal storage unit being configured to store each of the abnormal flags corresponding to each of the target controllers in a partitioned manner; and an abnormal storage control module configured to query the abnormal storage unit by the first controller, and update a storage state of an abnormal storage control unit when determining that the abnormal storage unit stores the abnormal flag.

[0007] In still another aspect of the embodiments of the present disclosure, a test device is provided, comprising: a host computer and a slave computer, the slave computer comprising at least one test board card, the test board card comprising a first controller, N second controllers and M third controllers connected in sequence, the first controller comprising an abnormal storage control unit and an abnormal storage unit, the first controller, the N second controllers and the M third controllers being connected with at least one peripheral chip respectively, the third controller being further connected with a clock chip, and the test device further comprising the test board card self-checking system described above.

[0008] In still another aspect of the embodiments of the present disclosure, an electronic device is provided, comprising: a memory configured to store a computer program; and a processor configured to execute the computer program stored in the memory, and when the computer program is executed, the test board card self-checking method described above is implemented.

[0009] In still another aspect of the embodiments of the present disclosure, a computer readable storage medium is provided, which stores a computer program, and when the computer program is executed by a processor, the test board card self-checking method described above is implemented.

[0010] In still another aspect of the embodiments of the present disclosure, a computer program product is provided, comprising computer program instructions, and when the computer program instructions are executed by a processor, the test board card self-checking method described above is implemented.

[0011] The test board card self-checking method, system, test device and electronic device in the embodiments of the present application. In the embodiments of the present application, the real-time detection of the target function state of each function core in the test board card is realized in the initialization phase and the test phase, and no additional operation is required for the test board card, which improves the efficiency of obtaining the function chip state and ensures the reliability of the test result of the chip test device. In addition, when the target function is abnormal, an abnormal flag of the corresponding abnormal type is generated. Since the abnormal flag is convenient for quickly locating the target function where the abnormality occurs, the positioning of the test board card abnormality is realized quickly.

[0012] The technical solutions of the present application will be described in further detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0014] The present application can be more clearly understood and appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a flowchart of a test board card self-checking method provided by an exemplary embodiment of the present application.

[0016] Figure 2 is a flowchart of a test board card self-checking method provided by another exemplary embodiment of the present application.

[0017] Figure 3 is a flowchart of data decoding provided by an exemplary embodiment of the present application.

[0018] Figure 4 is a flowchart of communication detection provided by an exemplary embodiment of the present application.

[0019] Figure 5 is a structural block diagram of a test board card self-checking system provided by an exemplary embodiment of the present application.

[0020] Figure 6 is a structural block diagram of a test device provided by an exemplary embodiment of the present application.

[0021] Figure 7 is a structural block diagram of a test board card provided by an exemplary embodiment of the present application.

[0022] Figure 8 is a schematic diagram of a target controller provided by an exemplary embodiment of the present application.

[0023] Figure 9 is a structural schematic diagram of an electronic device of an application embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in these embodiments are not limitations on the scope of the present application, unless otherwise specifically stated.

[0025] Those skilled in the art can understand that the terms "first", "second", and the like in the embodiments of the present application are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they represent a necessary logical sequence between them.

[0026] It should also be understood that in the embodiments of the present application, "a plurality of" can mean two or more, and "at least one" can mean one, two, or more.

[0027] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present application, it can be understood as one or more in general, unless specifically limited or the context gives a contrary indication.

[0028] In addition, the term "and / or" in the present application is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the existence of A alone, the existence of A and B together, and the existence of B alone. In addition, the character " / " in the present application generally represents an "or" relationship between the front and rear associated objects.

[0029] It should also be understood that the description of various embodiments of the present application emphasizes the differences between various embodiments, and the same or similar parts can be referred to each other, and for the sake of brevity, will not be repeated.

[0030] At the same time, it should be understood that in order to facilitate description, the size of each part shown in the drawings is not drawn in accordance with the actual proportional relationship.

[0031] The following description of at least one exemplary embodiment is merely illustrative in nature and does not in any way limit the application and its application or use.

[0032] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered part of the specification where appropriate.

[0033] It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0034] Embodiments of the present invention can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate in conjunction with numerous other general-purpose or specialized computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with terminal devices, computer systems, servers, and other electronic devices include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments including any of the above.

[0035] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system-executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media, including storage devices.

[0036] During the implementation of this application, research revealed that, during the initialization phase, if the hardware status needs to be obtained, additional register or peripheral operations are required to indirectly determine whether the hardware is functioning properly, resulting in low efficiency and increased operational complexity. During the testing phase, the only way to determine whether the hardware status is abnormal is through empirical testing, such as when the chip test equipment freezes or when communication is abnormal. This not only results in poor hardware status judgment accuracy, but also, due to the inability to detect the hardware status in real time, can lead to "false PASS" test results, seriously affecting the reliability of the test results.

[0037] Figure 1 This is a flow chart of a test board self-test method provided by an exemplary embodiment of the present application. This embodiment can be applied to test equipment, such as Figure 1 As shown, the chip testing method may include the following steps:

[0038] Step S100 , during the initialization phase and the test phase of the test device, the operating functions of the target controller are detected in real time, and when an abnormal function is detected in the target controller, an abnormal flag corresponding to the abnormal function is generated.

[0039] The test device is used to test a chip, a wafer, or other devices under test. The test device can be an automatic test equipment (ATE) for example. The test device can include an upper computer and a lower computer, and the upper computer is in communication connection with the lower computer. The upper computer can be a computer for example, and the lower computer can be a test head for testing the device under test. The lower computer can include a test board card. The test board card can include a first controller, N second controllers, and M third controllers connected in sequence, N is an integer greater than or equal to 1, and M is a natural number, for example, M can be 0, 1, 2, etc. In an embodiment, the first controller communicates with the upper computer through a backplane, and the second controllers are connected with the first controller and the third controllers respectively. The third controllers are connected with functional modules, which are arbitrary waveform generators (AWG) and waveform collectors (DIG) in this embodiment, and are used to control DAC / ADC of the functional modules. The first controller, the second controller, and the third controller can be a field programmable gate array (FPGA) for example.

[0040] The target controller can be one of the first controller, the N second controllers, or the M third controllers. The abnormal flag is used to represent an abnormal function, that is, each abnormal function corresponds to an abnormal flag.

[0041] In an embodiment, the running functions of the target controller can be detected in real time. For example, the data receiving, data sending, connection of each data interface, system clock, sampling clock, decoding function, and other functions of the target controller can be detected. When an abnormal function is detected in the target controller, an abnormal flag corresponding to the abnormal function is generated. For example, when a connection abnormality of a data interface is detected, the connection of the data interface is determined as an abnormal function, and an abnormal flag corresponding to the abnormal function is generated.

[0042] In step S110, in response to the target controller being the second controller or the third controller, the target controller transmits the abnormal flag to the first controller through the first communication interface.

[0043] The target controller is provided with a first communication interface, and the first communication interface is used to transmit the abnormal flag.

[0044] In one embodiment, the first controller, the N second controllers and the M third controllers are each provided with a first communication protocol and a first communication interface. The abnormal flag transmission can be based on the first communication protocol and the first communication interface. For example, the first communication protocol can be a Universal Asynchronous Receiver / Transmitter (UART) protocol, and the first communication interface can be a High-UART (HUART) interface.

[0045] In step S120, the first controller stores the abnormal flags corresponding to the target controllers in an abnormal storage unit. The abnormal storage unit is configured to store the abnormal flags corresponding to the target controllers in a partitioned manner.

[0046] In one embodiment, the first controller includes an abnormal storage unit and an abnormal storage control unit. The abnormal storage unit is configured to store the abnormal flags corresponding to the target controllers in a partitioned manner. In this embodiment, the abnormal storage unit includes a plurality of memories, and each memory is configured to store a type of abnormal flags. The first controller receives the abnormal flags corresponding to the target controllers, determines the memory corresponding to the abnormal flag, and stores the abnormal flag in the memory. The abnormal storage control unit and the plurality of memories can be registers. Of course, those skilled in the art can know that the abnormal storage unit is not limited to including a plurality of memories for storing the abnormal flags corresponding to the target controllers in a partitioned manner. The abnormal storage unit can also store the abnormal flags corresponding to the target controllers in a partitioned manner through a block storage manner. The method is not limited as long as the abnormal storage unit can be used to store the abnormal flags corresponding to the target controllers in a partitioned manner.

[0047] In one embodiment, when the target controller is a second controller or a third controller, the target controller transmits the abnormal flag belonging to the target controller to the first controller through the first communication interface, and the first controller stores the abnormal flag in the storage device corresponding to the abnormal flag. When the target controller is the first controller, the target controller stores the abnormal flag in the memory corresponding to the abnormal flag.

[0048] In step S130, the first controller queries the abnormal storage unit, and updates the storage state of the abnormal storage control unit when it is determined that the abnormal storage unit stores the abnormal flag.

[0049] In one embodiment, the storage state of the abnormal storage control unit includes the presence of an abnormal flag or the absence of an abnormal flag. When the storage state is the presence of an abnormal flag, it indicates that the abnormal storage unit stores the abnormal flag. When the storage state is the absence of an abnormal flag, it indicates that the abnormal storage unit does not store the abnormal flag.

[0050] For example, the first controller can query whether the exception flag is stored in each memory of the exception storage unit. When it is determined that at least one memory stores the exception flag according to the query result that the state flag bit of at least one memory is not 0, the state flag bit of the exception storage control unit is set to 0x1 to update the storage state of the exception storage control unit to store the exception flag. When it is determined that no memory stores the exception flag according to the query result that the state flag bit of each memory is 0, the state flag bit of the exception storage control unit is set to 0x0 to update the storage state of the exception storage control unit to not store the exception flag.

[0051] In one embodiment, the lower computer further comprises a state storage device, which can be a register, for example. In this embodiment, the first controller comprises a state storage device for collecting the initialization completion flags of each target controller. When the test equipment completes initialization, the target controller is the second controller or the third controller, the target controller transmits the initialization completion flag to the first controller through the first communication interface, and the first controller stores the initialization completion flag of each target controller in the state storage device. The target controller generates the initialization completion flag for the first controller and stores the initialization completion flag in the state storage device. When the first controller receives the initial state query request sent by the upper computer, the first controller obtains the initialization completion flag of each target controller from the state storage device and stores the initialization flag in the upper computer.

[0052] In the embodiments of the present disclosure, the running functions of each controller in the test board card are detected in real time during the running process in the initialization stage and the test stage to determine whether the controller running is abnormal, without additional operations on the test board card, the efficiency of obtaining the state of the functional chip is improved, and the reliability of the test result of the chip test equipment is ensured. In addition, the exception flag is transmitted through the first communication interface, which not only ensures the transmission efficiency of the exception flag, but also does not occupy the transmission interface of the test data between the first controller, the second controller and the third controller, ensures the transmission efficiency of the test data, and each exception function corresponds to an exception flag, each exception flag corresponding to each target controller is stored in the exception storage unit in a partitioned manner, which facilitates fast searching of the exception flag and fast positioning of the abnormal function. The first controller queries the exception storage unit, updates the storage state of the exception storage control unit when it is determined that the exception flag is stored in the exception storage unit, and then quickly responds and reports when the upper computer performs the exception state polling request, thereby realizing efficient positioning of the test board card exception.

[0053] Figure 2 is a flowchart of a test board card self-checking method provided by another exemplary embodiment of the present application. As shown in Figure 2 Figure 1 ​The chip test method can further include the following steps:

[0054] At step S140, in response to the first controller receiving the abnormal state polling request sent by the host computer, the storage state of the abnormal storage control unit is obtained.

[0055] The abnormal storage unit includes a plurality of memories, each memory is used to store a type of abnormal flag, and the abnormal storage flag includes at least one of a communication abnormal flag, a clock abnormal flag, a power supply abnormal flag, a temperature control abnormal flag, and a decoding abnormal flag. When the host computer needs to read the abnormal flag, the host computer sends an abnormal state polling request to the first controller. When the first controller receives the abnormal state polling request, the first controller obtains the storage state of the abnormal storage control unit.

[0056] At step S150, in response to the storage state indicating that there is an abnormal flag, the first controller polls each memory to obtain the abnormal flag, and sends the abnormal flag to the host computer.

[0057] When the storage state indicates that there is no abnormal flag, the first controller feeds back information indicating that there is no abnormality to the host computer.

[0058] For example, the first controller queries the state flag bit of the abnormal storage control unit. When the state flag bit is 0x1, it indicates that the storage state indicates that there is an abnormal flag. The first controller polls each memory to obtain the abnormal flag, and sends the abnormal flag to the host computer through the first communication interface. When the state flag bit is 0x0, it indicates that the storage state indicates that there is no abnormal flag. The first controller feeds back information indicating that there is no abnormality to the host computer.

[0059] In some optional embodiments, the running functions include a communication function, a clock loss or active function, a power supply function, a temperature control function, and a data decoding function. The first controller, the second controller, and the third controller each include an abnormal storage unit. The target controller detects in parallel and generates an abnormal flag corresponding to an abnormal function when detecting that there is an abnormal function in the running function, and stores the abnormal flag in the abnormal storage unit of the target controller. The abnormal storage unit of the second controller or the third controller transmits the abnormal flag to the abnormal storage unit of the first controller.

[0060] In the embodiment, the exception storage units in the second controller and the third controller are configured to store the exception flags corresponding to the controllers and transmit the exception flags to the exception storage unit of the first controller. The exception storage units in the second controller and the third controller are in communication connection with the exception storage unit of the first controller. The exception storage unit of the first controller is configured to integrate the exception flags transmitted by the target controllers and store the exception flags corresponding to the target controllers in different partitions. The partition storage in the exception storage unit of the first controller can be divided according to the running functions. The exception storage unit of the first controller includes a plurality of memories, and the plurality of memories respectively store the communication function exception, the clock loss function exception, the active function exception, the power supply function exception, the temperature control function exception and the data decoding function exception.

[0061] The target controllers detect the running functions in parallel, and when an abnormal function is detected in the running functions, the target controllers generate an exception flag corresponding to the abnormal function and transmit the exception flag to the exception storage unit of the first controller for partition storage. The detection speed of the abnormal function is fast, the identification of the exception flag is unified and identified by the first controller, the communication link is simple, and the identification speed is fast.

[0062] In some optional embodiments, in the embodiment, the running functions include at least one of a communication function, a clock loss or active function, a power supply function, a temperature control function and a data decoding function. The first controller, the N second controllers and the M third controllers each include an exception storage unit. The target controllers detect the running functions in parallel, and when an abnormal function is detected in the running functions, the target controllers generate an exception flag corresponding to the abnormal function and store the exception flag in the exception storage unit of the target controller. The exception storage units of the N second controllers or the M third controllers transmit the exception flag to the exception storage unit of the first controller.

[0063] Correspondingly, in the step S100 of detecting the running functions of the target controllers in the embodiment, the running functions are communication functions. The method can include: in response to that the target controller receives a test data frame through a second preset communication interface, detecting a frame sequence number, frame data and a data receiving duration of receiving the test data frame of the test data frame; and in response to that the frame sequence number is abnormal, the frame data is abnormal or the data receiving duration is abnormal, determining that there is an abnormal function in the target controller.

[0064] The second preset communication interface is configured to transmit the test data frame. The test data frame can include other data in the test equipment except the exception flag. The test data frame can include, for example, a test vector, test result data and the like.

[0065] In one embodiment, the first controller, the N second controllers and the M third controllers are each provided with a second communication protocol and a second communication interface. The transmission of the test data frame can be based on the second communication protocol and the second communication interface. For example, the second communication protocol can be a Gigabit Transceiver (GXT) protocol, and the second communication interface can be a high-speed GXT (10G BASE-R) high-speed communication interface.

[0066] In one embodiment, the test data frame can include a frame header, a frame sequence number, a frame length, frame data and check data.

[0067] When the frame sequence number of the test data frame is not continuous with the frame sequence number of the previous test data frame of the test data frame, it is determined that the frame sequence number is abnormal, otherwise, it is determined that the frame sequence number is normal; when the target controller does not receive the data of the frame length of the test data frame within a preset time length, it is determined that the data receiving time length is abnormal, otherwise, it is determined that the data receiving time length is normal; based on a preset check algorithm and the frame data of the test data frame, the check data corresponding to the frame data is generated, and when the check data corresponding to the frame data is inconsistent with the check data in the test data frame, it is determined that the frame data is abnormal, otherwise, it is determined that the frame data is normal. For example, the preset check algorithm can be a Cyclic Redundancy Check (CRC) algorithm. The check data in the test data frame is generated based on the preset check algorithm and the frame data of the test data frame.

[0068] When the frame sequence number is abnormal, it is determined that the frame sequence number is an abnormal function, when the frame data is abnormal, it is determined that the frame data is an abnormal function, and when the data receiving time length is abnormal, it is determined that the data receiving time length is an abnormal function.

[0069] The communication abnormality flag is generated, the test data frame is deleted, and the operation of receiving the next test data frame is performed.

[0070] Correspondingly, the generation of the communication abnormality flag corresponding to the abnormal function can include: when the frame sequence number is abnormal, the target controller generates an abnormal flag corresponding to the frame sequence number abnormality; when the frame data is abnormal, the target controller generates an abnormal flag corresponding to the frame data abnormality; when the data receiving time length is abnormal, the target controller generates an abnormal flag corresponding to the data receiving time length abnormality.

[0071] When the frame sequence number abnormality, the frame data abnormality or the data receiving time length abnormality is detected, it can be determined that the received test data frame has an error, at this time, the target controller deletes the test data frame, and starts to receive the next test data frame. Therefore, not only the problem of repeated abnormal alarm caused by the transmission of the erroneous test data frame to other controllers is avoided, the accuracy of the alarm is improved, but also the problem of communication lag caused by the erroneous test data frame is avoided, and the communication efficiency is improved.

[0072] In the embodiment of the present application, the frame sequence number, frame data and data receiving duration of the test data frame are detected to detect the communication function state of the target controller, and the host computer is reported in real time when the communication function is abnormal.

[0073] In some optional embodiments, the running function of the target controller is detected in step S100 of the embodiment of the present application, the running function is a communication function, and the method can further include:

[0074] In response to detecting that the first communication interface does not receive abnormal data within a preset duration, it is determined that the first communication interface is abnormal, the abnormal data includes an abnormal flag or empty data, and a first communication interface abnormal flag is generated.

[0075] In one embodiment, the abnormal data is transmitted at a rate of 1Mhz according to the UART protocol (the first communication protocol), and the HUART interface (the first communication interface) is started once every 1ms to send abnormal data. When it is detected that the first communication interface does not receive abnormal data within 1s (the preset duration), it is determined that the first communication interface is abnormal. When the first communication interface is detected to be abnormal, an abnormal flag corresponding to the first communication interface is generated.

[0076] In the embodiment of the present application, the detection of abnormal data communication is realized by detecting the case that the first communication interface receives abnormal data.

[0077] In response to detecting that the second communication interface is not connected within a preset duration, it is determined that the second communication interface is abnormal, and a second communication interface abnormal flag is generated.

[0078] In the embodiment, it is detected whether the second preset communication interface is successfully connected (LINK), if the connection is successful, it is determined that the connection state of the second preset communication interface is normal, and the operation of receiving the test data frame is performed, if the connection fails, the connection of the second preset communication interface is re-established, if the connection (LINK) is not successful within a preset duration (1s), a reset instruction is sent, and it is repeatedly detected whether the second preset communication interface is successfully connected (LINK), the process is repeated for a preset number of times (5 times), if the LINK is not successful, the connection state of the second preset communication interface is abnormal, and a LINK abnormal flag (an abnormal flag corresponding to the abnormal state of the second preset communication interface) is generated.

[0079] In some optional embodiments, the running function of the target controller is detected in step S100 of the embodiment of the present application, the running function is a data decoding function, and the method includes:

[0080] In response to the target controller not receiving data of the frame length of the to-be-sent data frame within a preset time length after detecting the frame header of the to-be-sent data frame, it is determined that data decoding is abnormal; a communication abnormality flag is generated, the to-be-sent data frame is deleted, and a decoding module of the target controller is initialized.

[0081] The to-be-sent data frame is data output by the target controller. In an embodiment, when data decoding is detected to be abnormal, the target controller generates an abnormality flag corresponding to the data decoding, and deletes the to-be-sent data frame and initializes the decoding module of the target controller to perform an operation of a new to-be-sent data frame.

[0082] An exemplary, Figure 3 is a flowchart of data decoding provided by an exemplary embodiment of the present application. As Figure 3 indicated, the to-be-sent data frame can include a frame header, a frame length, and valid data (frame data). The frame length is greater than 1. A data generation module in the target controller generates the to-be-sent data frame and sends the to-be-sent data frame to a decoding queue (Rx_fifo), the decoding queue sends the to-be-sent data frame to a feedback control module (Return_ctrl), the feedback control module receives the frame header of the to-be-sent data frame and writes the frame header into a data queue (tx_fifo), and receives and reads the frame length of the to-be-sent data frame, then continues to receive the to-be-sent data frame and determines whether the frame length of valid data is written into the data queue within 10 ms (a preset time length), when it is determined that the frame length of valid data is not written into the data queue within 10 ms, a timeout flag (an abnormality flag corresponding to data decoding) is generated, the data queue is reset to clear the contents therein, and an operation of receiving the frame header of a next to-be-sent data frame is performed, when it is determined that the frame length of data is written into the data queue within 10 ms, the frame length is written into a length information queue (len_fifo), a judging module (Tx_ctrl) sends according to the frame length in the length information queue to determine the sending order of the to-be-sent data frame, waits for a response of the uplink arbitration, and sends the to-be-sent data frame according to the response.

[0083] In the embodiment of the present application, whether the frame length of data is received within a preset time length is detected to determine whether the decoding function of the target controller is normal, thereby realizing detection of the decoding function, and deleting the to-be-sent data frame in real time when the decoding function is abnormal, avoiding data transmission jam and improving data transmission efficiency.

[0084] In some optional embodiments, the step S100 in the embodiment of the present application detects the running function of the target controller, the running function is a clock lockout function, and the method can include:

[0085] A reference lock signal of a system clock or a sampling clock is acquired.

[0086] reading a lock signal output by a system clock or a sampling clock, comparing the lock signal with a reference lock signal, and counting a number of times of losing lock;

[0087] generating a clock losing lock abnormality flag if the number of times of losing lock is not a preset value.

[0088] In the embodiment, the target controller is provided with a system clock and an external clock for generating a sampling clock, and a lock signal of the system clock can be used as a reference lock signal of the system clock, and a lock signal of the sampling clock of the external clock can be used as a reference lock signal of the sampling clock. In the embodiment, the external clock is a clock chip.

[0089] detecting a lock signal of the system clock, determining that the system clock is abnormal when a falling edge of the lock signal of the system clock is detected and the lock signal output by the system clock is inconsistent with the reference lock signal, and recording a time of losing lock. In the embodiment, the losing lock counter is incremented by 1, and a value of the losing lock counter is detected in real time. When the number of times of losing lock is not a preset value, which is 0 in the embodiment, it is indicated that the system clock has a losing lock situation, and a clock losing lock abnormality flag is generated. Similarly, the detection principle of the lock signal of the sampling clock is the same, and is not described herein.

[0090] In the embodiment, the system clock and the sampling clock are detected to realize real-time detection of abnormality of the system clock and the sampling clock.

[0091] In some optional embodiments, the running function of the target controller detected in step S100 is a clock active function, and the method can include:

[0092] acquiring the sampling clock and frequency dividing the sampling clock to obtain a frequency-divided sampling clock;

[0093] sampling the frequency-divided sampling clock based on the system clock, and recording a rising edge or a falling edge time of the frequency-divided sampling clock;

[0094] generating a clock active abnormality flag if the rising edge or the falling edge of the frequency-divided sampling clock is not acquired within a preset time.

[0095] In the embodiment of the present application, when the target controller is the third controller, the target controller is further connected with a clock chip for controlling the sampling frequency of the third controller. After the target controller detects the indication of the clock chip being locked, the active state of the clock chip is detected. Specifically, the register of the target controller controlled by the clock chip is flipped, the sampling clock signal input by the clock chip is divided, for example, 10 division can be used, and then the generated divided waveform is sampled based on the system clock. After sampling, the time of the rising edge and the falling edge of the divided waveform is counted. If the rising edge or the falling edge of the divided sampling clock is not obtained within a preset time, the clock active abnormal flag is generated. For example, if no rising edge or falling edge is generated within 1ms, it indicates that the clock chip stops or is abnormal. At this time, it is determined that the active state of the clock chip is abnormal, and the abnormal flag corresponding to the active state of the clock chip, i.e., the clock active abnormal flag, is generated.

[0096] In some optional embodiments, the running function of the target controller is detected in step S100 in the embodiment of the present application, and the running function is the power supply function or the temperature control function. The method can include:

[0097] A preset temperature threshold of the target controller is obtained.

[0098] The temperature of the target controller is obtained in real time.

[0099] The temperature of the target controller is compared with the preset temperature threshold.

[0100] If the absolute value of the temperature of the target controller exceeds the preset temperature threshold, the temperature control abnormal flag is generated.

[0101] The host computer pre-downloads the preset temperature threshold into the memory of the test board card, and the preset temperature threshold after being downloaded is effective in real time. The memory can be, for example, an electrically erasable programmable read-only memory (EEPROM). The temperature of the target controller can be detected by a plurality of temperature sensors. Specifically, the target controller can read the temperature of the target controller from the plurality of temperature sensors in real time, and read the preset temperature threshold from the memory. When the temperature exceeds the preset temperature threshold, it is determined that the temperature of the target controller is abnormal, and the abnormal flag corresponding to the temperature abnormality, i.e., the temperature control abnormal flag, is generated.

[0102] In some optional embodiments, in the embodiment of the present application, when the running function is the power supply function, the detection of the running function of the target controller to generate the abnormal flag corresponding to the abnormal function can include:

[0103] The power supply information of the target controller is acquired in real time, the power supply information of the target controller is compared with the preset power state information, and a power abnormality flag is generated in response to the power supply information of the target controller being inconsistent with the preset power state information.

[0104] The power supply information may include a power supply flag, which is used to indicate the power supply status, and the preset power status information may include a preset power status flag. Specifically, the test equipment further includes a power supply chip, which is used to supply power to the first controller, N second controllers, and M third controllers, and detect the power supply status of the first controller, N second controllers, and M third controllers in real time. The power supply flag of the target controller can be read from the power supply chip, and the power supply flag is compared with the preset power status flag (POWER GOOD). If the power supply flag is different from the preset power status flag, that is, the power flag is not POWER GOOD, it is determined that the power supply is abnormal, and a power abnormality flag is generated.

[0105] For example, Figure 4 FIG. 1 is a flow chart of communication detection provided by an exemplary embodiment of the present application. Figure 4 As shown, the test data frame may include: a frame header, a frame length, valid data (frame data) and check data, and the frame length is greater than 1.

[0106] During the initialization (INIT) process, a detection is generated to detect whether the second preset communication interface is connected (LINK) successfully. If the connection is successful, it is determined that the connection state of the second preset communication interface is normal, and an operation of receiving a test data frame is performed. If the connection fails, the connection of the second preset communication interface is re-established. If the communication connection (LINK) is not successful within a preset time (1s), a reset instruction is sent to repeatedly detect whether the second preset communication interface is connected (LINK) successfully. This process is repeated a preset number of times (5 times). If the communication connection is successful within 5 times, the communication link is reset. If the LINK is not successful, the connection state of the second preset communication interface is abnormal, and a LINK abnormal flag is generated;

[0107] When it is determined that the second preset communication interface is successfully connected, i.e., LINK is successful, the test data frame is received, first, the frame header is received, when the frame header is received, the next received data is the frame sequence number, and it is determined whether the frame sequence number is continuous, if not, a continuity flag (an exception flag corresponding to the frame sequence number exception) is generated, then the frame length is received, and then the valid data (frame data) of the number of subsequent frame lengths is received, when the data of the frame length is not received within 10 ms (a preset time length), a timeout flag (an exception flag corresponding to a data receiving time length exception) is generated, the test data frame is deleted, and the operation of receiving the frame header of the next test data frame is performed, when the valid data of the frame length is received within 10 ms, the data of the CRC check bit (check data) is received, the check data corresponding to the frame data is generated based on the CRC algorithm and the valid data of the frame length, and when the check data corresponding to the frame data is inconsistent with the check data in the test data frame, a CRC check flag (an exception flag corresponding to a frame data exception) is generated, when the check data corresponding to the frame data is consistent with the check data in the test data frame, the test data frame is received, and the operation of receiving the frame header of the next test data frame is performed.

[0108] Specifically, the target controller is provided with a received data control module (rd_data_ctrl), which receives the test data frame in the order of the frame header, the frame sequence number, the frame length, the frame valid data (frame data) and the data of the CRC check bit. In the receiving process, the frame sequence number, the frame length and the frame valid data are written into the rx_fifo buffer, the frame sequence number, the frame length, the frame valid data and the data of the CRC check bit are written into the CRC_CHECK, when the frame valid data of the frame length is all written into the rx_fifo buffer, the frame length is written into the len_fifo buffer, and after the CRC result flag (check data) is calculated by the CRC_CHECK, the CRC result flag is written into the CRC_FIFO buffer; the rd_data_ctrl reads the data of the frame length from the rx_fifo according to the frame length in the len_fifo and the CRC_fifo to perform CRC check, if the CRC check is normal, the data of the frame length is output to the next stage, otherwise, the data of the frame length is discarded and not sent to the next stage.

[0109] In some optional embodiments, in the embodiment of the present application, the target controller is connected with a peripheral chip. The test board card self-checking method further includes: in the initialization stage, detecting the read-write state of the peripheral chip and the read-write state of the storage device in the peripheral chip; and in response to the read-write state of the peripheral chip being abnormal or the read-write state of the storage device being abnormal, generating a corresponding exception flag. That is, the target controller detects the function of the peripheral chip, and generates an exception flag corresponding to the abnormal function when there is an abnormal function in the peripheral chip.

[0110] The peripheral chip can be an FPGA, and the peripheral chip is provided with a clock. In an embodiment, the target controller can detect the functions of the peripheral chip.

[0111] For example, the target controller can collect the lock signal of the clock, and when the lock signal of the clock is low, the level of the abnormal flag corresponding to the clock of the peripheral chip is pulled high to generate the abnormal flag corresponding to the clock abnormality of the peripheral chip. Alternatively,

[0112] The peripheral chip can perform self-detection, and when an abnormality is detected, corresponding alarm information is generated. The target controller can collect the alarm information on the peripheral chip and generate the abnormal flag corresponding to the alarm information. Alternatively,

[0113] The target controller can receive the READY signal of the peripheral chip. If the READY signal is continuously low within 1 ms, it indicates that the peripheral chip is abnormal, and the abnormal flag corresponding to the peripheral chip is pulled high to generate the abnormal flag corresponding to the abnormality of the peripheral chip.

[0114] In some optional embodiments, in the embodiment of the present application, when the target controller is an Mth third controller, the target controller is further connected with a clock chip, and the clock chip is used to control the sampling frequency of the third controller. The test board card self-detection method further includes: the target controller detects the active state of the clock chip, and in response to detecting that the active state of the clock chip is abnormal, the target controller generates the abnormal flag corresponding to the active state abnormality.

[0115] In the embodiment of the present application, when the target controller detects the indication of the lock of the clock chip, the active state of the clock chip is detected. Specifically, the register of the target controller controlled by the clock chip is flipped, the clock signal input by the clock chip is divided by 10, for example, and then the generated frequency division waveform is sampled. The time of the rising edge and the falling edge of the frequency division waveform is counted after sampling. If no rising edge or falling edge is generated within 1 ms, it indicates that the clock chip stops or is abnormal. At this time, it is determined that the active state of the clock chip is abnormal, and the abnormal flag corresponding to the active state abnormality of the clock chip is generated.

[0116] In some optional embodiments, in the embodiment of the present application, the test board card self-detection method further includes: in the initialization stage, the read-write state of the peripheral chip and the read-write state of the storage device in the peripheral chip are detected, and in response to the read-write state of the peripheral chip being abnormal or the read-write state of the storage device being abnormal, the corresponding abnormal flag is generated.

[0117] The memory device may be, for example, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0118] In one embodiment, the target controller sends a read request to the external chip, the external chip returns a chip ID of the external chip, when the chip ID is not the same as the chip ID of the external chip stored in the target controller, at this time the chip ID returns incorrectly, the target controller determines that the read state of the external chip is abnormal, generates an abnormal flag corresponding to the read state abnormality of the external chip, when the chip ID is the same as the chip ID of the external chip stored in the target controller, at this time the chip ID returns correctly, the target controller determines that the read state of the external chip is normal; for all readable and writable addresses in the peripheral chip, the target controller writes preset fixed data in the readable and writable address, and then the target controller reads the data in the readable and writable address, when the read data is the same as the preset fixed data, it is determined that the return is correct, when the read data is not the same as the preset fixed data, it is determined that the return is incorrect; when all readable and writable addresses correspond to correct returns, the target controller determines that the write state of the external chip is normal, when at least one readable and writable address corresponds to an incorrect return, the target controller determines that the write state of the external chip is abnormal, and generates an abnormal flag corresponding to the write state abnormality of the external chip.

[0119] The target controller can detect whether the memory device completes initialization, when it is detected that the memory device does not complete initialization, the target controller generates an abnormal flag corresponding to the memory device not completing initialization.

[0120] When the peripheral chip receives the self-checking instruction, the memory device of the peripheral chip performs self-checking, specifically including:

[0121] (1) taking the incremental data as the first input data, writing the first input data into each address of the memory device, then traversing each address, reading the data of each address, determining whether the read data is the same as the written first input data, and determining the first self-checking to be successful when they are the same, otherwise determining the first self-checking to fail;

[0122] (2) taking the decremental data as the second input data, writing the second input data into each address of the memory device, then traversing each address, reading the data of each address, determining whether the read data is the same as the written second input data, and determining the second self-checking to be successful when they are the same, otherwise determining the second self-checking to fail;

[0123] (3) writing third input data, which can be AAAAAAAAAAAAAAAAA for example, into each address of the storage device, then traversing each address, reading data of each address, determining whether the read data is the same as the written third input data, and determining that the third self-check is successful when they are the same, otherwise determining that the third self-check fails;

[0124] (4) writing fourth input data, which can be 5555555555555555 for example, into each address of the storage device, then traversing each address, reading data of each address, determining whether the read data is the same as the written fourth input data, and determining that the fourth self-check is successful when they are the same, otherwise determining that the fourth self-check fails;

[0125] If the above four self-checks are all self-check successes, a self-check completion flag is output to the target controller, and when the target controller receives the self-check completion flag, it is determined that the read-write state of the storage device is normal; if there is a self-check failure in the above four self-checks, a self-check completion status data and an error data count are output to the target controller, and when the target controller receives the self-check completion status data and the error data count, it is determined that the read-write state of the storage device is abnormal, and the target controller generates an abnormality flag corresponding to the abnormal read-write state of the storage device.

[0126] In the embodiment of the application, the efficient detection of the peripheral chip of the target controller is realized by detecting the function of the peripheral chip of the target controller.

[0127] For example, the test board card is provided with a BE FPGA (first controller), an INTEL FPGA (second controller) and an FE FPGA (third controller). The BE FPGA is connected with the backboard to communicate with the upper computer, the INTEL FPGA is connected with the BE FPGA and the FE FPGA, the FE FPGA chip is used to connect the function module, in the embodiment, the function module is an arbitrary waveform generator AWG and a waveform collector DIG, which are used to control the DAC / ADC of the function module, the BE FPGA, the INTEL FPGA and the FE FPGA are connected with a peripheral chip respectively, the FE FPGA is connected with a clock chip, the BE FPGA includes an abnormality storage control unit and an abnormality storage unit. The BE FPGA, the INTEL FPGA and the FE FPGA are provided with a plurality of HUART interfaces (first communication interfaces), the INTEL FPGA and the FE FPGA transmit the abnormality flag to the BE FPGA through the HUART interface, and the BE FPGA stores the abnormality flag in the memory (abnormality register) corresponding to the abnormality storage unit respectively.

[0128] Figure 5is a structural block diagram of a test board card self-checking system provided by an exemplary embodiment of the present application. The test board card self-checking system is applied to a test device, such as Figure 5 As shown in the figure, the test device comprises a host computer and a slave computer, the slave computer comprises a test board card, the test board card comprises a first controller, N second controllers and M third controllers connected in sequence, and the test board card self-checking system comprises:

[0129] A first detection module 200 is configured to detect a running function of a target controller in an initialization stage and a test stage of the test device, and generate an abnormal flag corresponding to an abnormal function when detecting that the target controller has the abnormal function, the target controller being one of the first controller, the N second controllers or the M third controllers.

[0130] An abnormal data transmission module 210 is configured to transmit the abnormal flag to the first controller through a first communication interface in response to the target controller being the second controller or the third controller.

[0131] An abnormal storage module 220 is configured to store the abnormal flag corresponding to each target controller in an abnormal storage unit by the first controller, the abnormal storage unit being configured to store each abnormal flag corresponding to each target controller in a partition.

[0132] An abnormal storage control module 230 is configured to query the abnormal storage unit by the first controller, and update a storage state of the abnormal storage control unit when determining that the abnormal storage unit stores the abnormal flag.

[0133] In some optional embodiments, the abnormal storage unit comprises a plurality of memories, each memory being configured to store one type of abnormal flag, the abnormal storage flag comprising at least one of a communication abnormal flag, a clock abnormal flag, a power supply abnormal flag, a temperature control abnormal flag and a decoding abnormal flag, and the test board card self-checking system further comprises:

[0134] A data receiving module is configured to obtain the storage state of the abnormal storage control unit in response to the first controller receiving an abnormal state polling request sent by the host computer.

[0135] A data sending module is configured to poll each abnormal storage unit to obtain the abnormal flag by the first controller in response to the storage state indicating that there is the abnormal flag, and send the abnormal flag to the host computer.

[0136] In some optional embodiments, the running functions include at least one of a communication function, a clock loss function, an active function, a power supply function, a temperature control function, and a data decoding function, the first controller, the second controller, and the third controller each include an exception storage unit, the target controller detects in parallel and generates an exception flag corresponding to an abnormal function when detecting that the abnormal function exists in the running functions, and stores the exception flag into the exception storage unit of the target controller, and the exception storage unit of the second controller or the third controller transmits the exception flag into the exception storage unit of the first controller.

[0137] In some optional embodiments, the first detection module 200 is specifically configured to, in response to the target controller receiving a test data frame through the second preset communication interface, detect a frame sequence number, frame data, and a data receiving duration of the test data frame; in response to the frame sequence number being abnormal, the frame data being abnormal, or the data receiving duration being abnormal, determine that an abnormal function exists in the target controller; generate a communication exception flag, delete the test data frame, and perform an operation of receiving a next test data frame.

[0138] In some optional embodiments, the first detection module 200 is specifically configured to, in response to detecting that the first communication interface does not receive abnormal data within a preset duration, determine that the first communication interface is abnormal, the abnormal data including an exception flag or empty data, and generate a first communication interface exception flag; in response to detecting that the second communication interface is not connected within a preset duration, determine that the second communication interface is abnormal, and generate a second communication interface exception flag.

[0139] In some optional embodiments, the first detection module 200 is specifically configured to, in response to the target controller not receiving data of a frame length of a to-be-sent data frame within a preset duration after detecting a frame header of the to-be-sent data frame, determine that a data decoding exception exists; generate a communication exception flag, delete the to-be-sent data frame, and initialize a decoding module of the target controller.

[0140] In some optional embodiments, the first detection module 200 is specifically configured to acquire a reference lock signal of a system clock or a sampling clock; read a lock signal output by the system clock or the sampling clock, compare the lock signal with the reference lock signal, and count a number of lock losses; and generate a clock loss exception flag if the number of lock losses is not a preset value.

[0141] In some optional embodiments, the first detection module 200 is specifically configured to acquire a sampling clock and divide the sampling clock to obtain a divided sampling clock; sample the divided sampling clock based on the system clock, and record a rising edge or a falling edge time of the divided sampling clock; and if the rising edge or the falling edge of the divided sampling clock is not acquired within a preset time, generate a clock active abnormality flag.

[0142] In some optional embodiments, the first detection module 200 is specifically configured to acquire a preset temperature threshold of the target controller; acquire a temperature of the target controller in real time; compare the temperature with the preset temperature threshold; and if an absolute value of the temperature exceeds the preset temperature threshold, generate a temperature control abnormality flag.

[0143] In some optional embodiments, the first detection module 200 is specifically configured to acquire power supply information of the target controller in real time; compare the power supply information of the target controller with preset power supply state information; and in response to the power supply information of the target controller being inconsistent with the preset power supply state information, generate a power supply abnormality flag.

[0144] In some optional embodiments, the target controller is connected with a peripheral chip; and the first detection module 200 is specifically configured to, in the initialization stage, detect a read-write state of the peripheral chip and a read-write state of a storage device in the peripheral chip; and in response to the read-write state of the peripheral chip being abnormal or the read-write state of the storage device being abnormal, generate a corresponding abnormality flag.

[0145] The test board card self-checking device of the embodiments of the present application and the embodiments of the test board card self-checking method of the present application correspond to each other, and related contents can be mutually referred, which will not be repeated here.

[0146] The beneficial technical effects of the exemplary embodiments of the test board card self-checking device of the present application can be referred to the corresponding beneficial technical effects of the corresponding exemplary method part, which will not be repeated here.

[0147] Figure 6 is a structural block diagram of a test equipment provided by an exemplary embodiment of the present application. Figure 7 is a structural block diagram of a test board card. As shown in Figure 6 and 7 In the embodiments of the present application, the test equipment includes an upper computer and a lower computer. The lower computer includes a test board card, and the test board card includes a first controller, N second controllers and M third controllers. The first controller, the N second controllers and the M third controllers are respectively connected with at least one peripheral chip. The third controller is further connected with a clock chip. The test equipment further includes the test board card self-checking system.

[0148] In one embodiment, the first controller, the second controller and the third controller are provided with a first communication interface and a second communication interface, and the first controller is connected with the exception storage control unit and the exception storage unit.

[0149] Exemplarily, Figure 8 is a schematic diagram of a target controller provided by an exemplary embodiment of the present application. As shown in Figure 8 The target controller can include an uplink arbitration module, a first communication module, a second communication module and a decoding module. The target controller can be one of the first controller, the second controller and the third controller.

[0150] The first communication module includes a first communication interface. The first communication module is configured to detect whether the first communication interface is abnormal, generate a corresponding exception flag when an exception is determined, send information to the uplink arbitration module, and transmit the exception flag according to the transmission order fed back by the uplink arbitration module. The second communication module includes a second communication interface. The second communication module is configured to detect whether the second communication interface is abnormal, whether the communication function thereof is abnormal, and transmit and send test data frames, generate a corresponding exception flag when an exception is determined, and then transmit the exception flag to the exception storage unit thereof. When the target controller is the second controller or the third controller, the first communication interface in the first communication module is controlled to send the exception flag to the exception storage unit in the first controller. The second communication module also receives and transmits the test data frames based on the transmission order given by the uplink arbitration module. The decoding module is configured to detect a data decoding function, decode the data frame to be transmitted, generate a corresponding exception flag when an exception is determined, and then transmit the exception flag to the exception storage unit thereof. When the target controller is the second controller or the third controller, the first communication interface in the first communication module is controlled to send the exception flag to the exception storage unit in the first controller. The decoding module also receives and transmits the data frame to be sent based on the transmission order given by the uplink arbitration module.

[0151] The test device of the embodiments of the present application corresponds to the embodiments of the test board card self-checking method described above, and the related contents can be mutually referred to, which will not be repeated here.

[0152] The beneficial technical effects of the exemplary embodiments of the test device of the embodiments of the present application can be referred to the corresponding beneficial technical effects of the exemplary method part described above, which will not be repeated here.

[0153] In addition, the present disclosure also provides an electronic device, comprising:

[0154] a memory for storing a computer program;

[0155] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the test board self-test method described in any of the above embodiments of the present disclosure is implemented.

[0156] Figure 9 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Figure 9 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be either or both of the first device and the second device, or a standalone device independent of them, and the standalone device may communicate with the first device and the second device to receive collected input signals from them.

[0157] like Figure 9 As shown, the electronic device includes one or more processors and memory.

[0158] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0159] The memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the test board self-test method of each embodiment of the present disclosure described above and / or other desired functions.

[0160] In one example, the electronic device may further include an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0161] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0162] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0163] Of course, to simplify, Figure 9Only some of the components of the electronic device related to the present disclosure are shown in the figure, and components such as a bus, an input / output interface, and the like are omitted. In addition, the electronic device can further include any other appropriate components according to a specific application.

[0164] In addition to the above-mentioned method and device, an embodiment of the present disclosure can also be a computer program product, which includes computer program instructions, which, when executed by a processor, cause the processor to perform the steps of the test board card self-test method according to various embodiments of the present disclosure described in the above parts of the specification.

[0165] The computer program product can be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C++, and the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a standalone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0166] In addition, an embodiment of the present disclosure can also be a computer readable storage medium, which stores computer program instructions, which, when executed by a processor, cause the processor to perform the steps of the test board card self-test method according to various embodiments of the present disclosure described in the above parts of the specification.

[0167] The computer readable storage medium can employ any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium, for example, can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0168] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the aforementioned program can be stored in a computer readable storage medium, and the program is executed to perform the steps of the above-mentioned method embodiments; and the aforementioned storage medium includes ROM, RAM, magnetic disc or optical disc and various storage medium that can store program code.

[0169] The above describes the basic principles of the present disclosure in conjunction with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present disclosure are only examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present disclosure. In addition, the above specific details of the disclosure are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present disclosure to be necessarily implemented with the above specific details.

[0170] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between each embodiment can be mutually referred to. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0171] The block diagrams of the devices, apparatuses, equipment, systems involved in the present disclosure are only exemplary examples and are not intended to require or imply the connection, arrangement, configuration shown in the block diagram. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner. Words such as "include", "contain", "have" and the like are open-ended words, which mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0172] The methods and devices of the present disclosure can be implemented in many ways. For example, the methods and devices of the present disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above order of steps for the method is only for illustration, and the steps of the method of the present disclosure are not limited to the above specific description, unless otherwise specifically described. In addition, in some embodiments, the present disclosure can also be implemented as programs recorded in recording media, which include machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers the recording media storing the programs for executing the method according to the present disclosure.

[0173] It should also be noted that in the devices, equipment and methods of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the present disclosure.

[0174] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0175] The above description has been presented to enable any person skilled in the art to make or use the disclosure. Furthermore, the purpose of the above description is not intended to limit the embodiments of the present disclosure to the form disclosed herein. Although various example aspects and embodiments have been discussed above, those of ordinary skill in the art will appreciate a variety of modifications, alternatives, permutations, additions, and sub-combinations of the described aspects and embodiments.

Claims

1. A test board self-test method, characterized in that: Applied to a test device, the test device includes a host computer and a slave computer, the slave computer includes a test board, the test board includes a first controller, N second controllers, and M third controllers connected in sequence, the method includes: During an initialization phase and a test phase of the test device, the operating functions of a target controller are detected in real time, and when an abnormal function is detected in the target controller, an abnormal flag corresponding to the abnormal function is generated, wherein the target controller is at least one of the first controller, the N second controllers, or the M third controllers; In response to the target controller being the second controller or the third controller, the target controller transmitting the abnormal flag to the first controller through the first communication interface; The first controller stores the abnormal flags corresponding to the target controllers in an abnormal storage unit, and the abnormal storage unit is used to store the abnormal flags corresponding to the target controllers in partitions; The first controller queries the abnormality storage unit and updates a storage state of the abnormality storage control unit when determining that an abnormality flag is stored in the abnormality storage unit.

2. The method according to claim 1, characterized in that The abnormality storage unit includes a plurality of memories, each memory is used to store a type of abnormality flag, the abnormality storage flag includes at least one of a communication abnormality flag, a clock abnormality flag, a power abnormality flag, a temperature control abnormality flag, and a decoding abnormality, and the method further includes: In response to the first controller receiving the abnormal state polling request sent by the host computer, obtaining the storage state of the abnormal storage control unit; In response to the storage status indicating the presence of an abnormal flag, the first controller polls each of the memories to obtain the abnormal flag, and sends the abnormal flag to the host computer.

3. The method according to claim 1 or 2, characterized in that The operating function includes at least one of a communication function, a clock lock or active function, a power supply function, a temperature control function, and a data decoding function. The first controller, the N second controllers, and the M third controllers all include an abnormality storage unit. The target controller performs parallel detection and, when detecting that an abnormal function exists in the operating function, generates an abnormality flag corresponding to the abnormal function and stores it in the abnormality storage unit of the target controller. The abnormality storage unit of the N second controllers or the M third controllers transmits the abnormality flag to the abnormality storage unit of the first controller.

4. The method according to claim 3, characterized in that When the operating function is a communication function, the real-time detection of the operating function of the target controller and the generation of an abnormal flag corresponding to the abnormal function include: In response to the target controller receiving a test data frame through the second preset communication interface, detecting a frame sequence number, frame data, and a data receiving time length of the test data frame; In response to the frame sequence number being abnormal, the frame data being abnormal, or the data reception duration being abnormal, determining that an abnormal function exists in the target controller; A communication abnormality flag is generated, the test data frame is deleted, and an operation of receiving the next test data frame is performed.

5. The method according to claim 3, characterized in that When the operating function is a communication function, the real-time detection of the operating function of the target controller and the generation of an abnormal flag corresponding to the abnormal function include: In response to detecting that the first communication interface does not receive abnormal data within a preset time period, determining that the first communication interface is abnormal, the abnormal data includes an abnormal flag or empty data, and generating a first communication interface abnormal flag; In response to detecting that the second communication interface is not connected within a preset time period, it is determined that the second communication interface is abnormal, and a second communication interface abnormality flag is generated.

6. The method according to claim 3, characterized in that When the operating function is a data decoding function, the real-time detection of the operating function of the target controller and the generation of an abnormal flag corresponding to the abnormal function include: In response to the target controller not receiving data of the frame length of the data frame to be sent within a preset time period after detecting the frame header of the data frame to be sent, determining that data decoding is abnormal; generating a communication abnormality flag, deleting the data frame to be sent, and initializing the decoding module of the target controller.

7. The method according to claim 3, characterized in that When the operating function is a clock lock loss function, detecting the operating function of the target controller and generating an abnormal flag corresponding to the abnormal function includes: Obtain a reference lock signal for the system clock or sampling clock; reading a lock signal output by the system clock or the sampling clock, comparing the lock signal with the reference lock signal, and counting the number of times the lock is lost; If the number of times the clock is unlocked is not the preset value, a clock unlock exception flag is generated.

8. The method according to claim 7, characterized in that When the operating function is a clock active function, detecting the operating function of the target controller and generating an abnormal flag corresponding to the abnormal function include: Obtaining a sampling clock and dividing the frequency to obtain a divided sampling clock; Sampling the divided sampling clock based on the system clock, and recording the rising edge or falling edge time of the divided sampling clock; If the rising edge or falling edge of the divided sampling clock is not obtained within a preset time, a clock active abnormality flag is generated.

9. The method according to claim 1, characterized in that When the operating function is a temperature control function, detecting the operating function of the target controller and generating an abnormal flag corresponding to the abnormal function includes: Obtaining a preset temperature threshold of the target controller; Acquiring the temperature of the target controller in real time; comparing the temperature with the preset temperature threshold; If the absolute value of the temperature exceeds the preset temperature threshold, a temperature control abnormality flag is generated.

10. The method according to claim 9, characterized in that When the operating function is a power supply function, detecting the operating function of the target controller and generating an abnormal flag corresponding to the abnormal function includes: Acquiring power supply information of the target controller in real time; Comparing the power supply information of the target controller with preset power status information; In response to the power supply information of the target controller being inconsistent with the preset power state information, a power abnormality flag is generated.

11. The method according to claim 1, wherein The target controller is connected to a peripheral chip, and the method further includes: During the initialization phase, detecting the read and write status of the peripheral chip and the read and write status of the storage device in the peripheral chip; In response to an abnormality in the read / write state of the peripheral chip or an abnormality in the read / write state of the memory device, a corresponding abnormality flag is generated.

12. A test board self-test system, characterized in that: Applied to a test device, the test device includes a host computer and a slave computer, the slave computer includes a test board, the test board includes a first controller, N second controllers and M third controllers connected in sequence, and the test board self-test system includes: a first detection module, configured to detect an operating function of a target controller during an initialization phase and a test phase of the test device, and, upon detecting an abnormal function in the target controller, generate an abnormal flag corresponding to the abnormal function, wherein the target controller is one of the first controller, the N second controllers, or the M third controllers; an abnormal data transmission module, configured to, in response to the target controller being the second controller or the third controller, transmit the abnormal flag to the first controller via the first communication interface; An abnormality storage module, configured for the first controller to store the abnormality flags corresponding to the target controllers in an abnormality storage unit, wherein the abnormality storage unit is configured to store the abnormality flags corresponding to the target controllers in partitions; The abnormal storage control module is used for the first controller to query the abnormal storage unit and update the storage state of the abnormal storage control unit when it is determined that the abnormal storage unit stores an abnormal flag.

13. A testing device, characterized in that: include: An upper computer and a lower computer, the lower computer includes at least one test board, the test board includes a first controller, N second controllers and M third controllers connected in sequence, the first controller includes an abnormal storage control unit and an abnormal storage unit, the first controller, the N second controllers and the M third controllers are respectively connected to at least one peripheral chip, the third controller is also connected to a clock chip, and the test equipment also includes the test board self-test system according to claim 11.

14. An electronic device, characterized in that: include: memory for storing computer programs; The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the test board self-test method described in any one of claims 1 to 10 is implemented.

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