Cache and its operation method in artificial intelligence chips

Abstract

This disclosure provides a cache for an artificial intelligence chip and a method for operating the cache to efficiently execute management operation commands. The cache includes a command table and a hit-miss checking unit. The hit-miss checking unit is coupled to the command table. In response to one of the multiple computing cores sending a management operation command to the cache, the hit-miss checking unit registers the management operation command in the command table to replace its execution. In response to one of the multiple computing cores sending an access request to the cache, the hit-miss checking unit also executes the management operation command registered in the command table during the execution of the access request.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence (AI) chip technology, and particularly to a cache for an AI chip and its operation method. Background Technology

[0002] Computing devices such as AI chips, Graphics Processing Units (GPUs), and General-Purpose GPUs (GPGPUs) can manage caches by sending management operation commands, such as invalidating caches or modifying their priorities. Because these management operations affect the entire cache, in multi-core parallel systems, a management operation command issued by one core can affect the cache lines used by other cores. Furthermore, when executing management operation commands for the entire cache, if the command information is actually written to tag RAM, each set needs to be updated. If the number of sets is large, the latency of the management operation commands will be significant. How to implement caching is one of the many technical issues in this field. Summary of the Invention

[0003] This disclosure provides a cache for an artificial intelligence chip and a method for operating the cache thereon, so as to efficiently execute management operation commands for the cache.

[0004] In embodiments according to this disclosure, the cache includes a command table and a hit-miss check unit. The hit-miss check unit is coupled to the command table. In response to one of the plurality of compute cores sending a management operation command to the cache, the hit-miss check unit registers the management operation command in the command table but temporarily refrains from executing the management operation command. In response to one of the plurality of compute cores sending an access request to the cache, the hit-miss check unit also executes the management operation command registered in the command table while executing the access request.

[0005] In an embodiment according to this disclosure, the operation method includes: in response to one of the plurality of computing cores sending a management operation command to a cache, the cache's hit-miss check unit registers the management operation command in the cache's command table and temporarily suspends the execution of the management operation command; and in response to one of the plurality of computing cores sending an access request to the cache, the hit-miss check unit also executes the management operation command registered in the command table during the execution of the access request.

[0006] Based on the above, in some embodiments, the cache is configured with a command table. A computation core sends a management operation command to the cache, which registers the management operation command in the command table but does not execute it temporarily. Therefore, for the computation core that sent the command, the management operation command is executed efficiently. In response to a computation core sending an access request to the cache, the cache executes the management operation command registered in the command table while executing the access request. For the cache, the execution of the access request and the execution of the management operation command registered in the command table can occur simultaneously. Therefore, the execution of the management operation command does not affect the cache's efficiency in handling access requests. Based on this, the cache can efficiently execute management operation commands.

[0007] In embodiments according to this disclosure, the cache includes a tag array and a hit-miss checking unit. The tag array includes multiple tag sets. Each of the multiple tag sets includes multiple tags. Each of the multiple tags stores corresponding cache line information. Each of the multiple tags also includes a kernel identifier field. The kernel identifier field is used to distinguish which compute core is currently using the cache line (i.e., the kernel identifier field is used to distinguish the compute core using the current cache line). The hit-miss checking unit is coupled to the tag array. In response to commands from the multiple compute cores, the compute core sends management operation commands to the cache, and the hit-miss checking unit iterates through each of the multiple tag sets to execute the management operation commands. The iterative operation includes: the hit-miss check unit reads the current tag group from multiple tag groups in the tag array; the hit-miss check unit checks the core identifier field of each of the multiple tags in the current tag group to select the target tag corresponding to the command sending computation core from the multiple tags in the current tag group; in response to the existence of a target tag corresponding to the command sending computation core in the current tag group, the hit-miss check unit executes a management operation command on the target tag corresponding to the command sending computation core, and the hit-miss check unit does not execute management operation commands on the remaining tags in the current tag group; in response to the absence of a target tag corresponding to the command sending computation core in the current tag group, the hit-miss check unit does not execute a management operation command on the current tag group; and the hit-miss check unit writes the current tag group back to the tag array.

[0008] In an embodiment according to this disclosure, the method includes: in response to a command sending computational core among a plurality of computational cores, the computational core sends a management operation command to a cache; a cache hit-miss checking unit iterates over each of a plurality of tag groups in the cache's tag array to execute the management operation command. Each of the plurality of tag groups includes a plurality of tags. Each of the plurality of tags is used to store corresponding cache line information. Each of the plurality of tags also includes a core identifier field. The core identifier field is used to distinguish which computational core is currently using the cache line. The iterative operation includes: reading the current tag group from the plurality of tag groups from the tag array; checking the core identifier field of each of the plurality of tags in the current tag group to select a target tag from the plurality of tags in the current tag group that corresponds to the computational core that sent the command; in response to the existence of a target tag in the current tag group that corresponds to the computational core that sent the command, executing the management operation command on the target tag that corresponds to the computational core that sent the command, and not executing management operation commands on the remaining tags in the current tag group; in response to the absence of a target tag in the current tag group that corresponds to the computational core that sent the command, not executing the management operation command on the current tag group; and writing the current tag group back to the tag array.

[0009] Based on the above, in some embodiments, each tag in the cached tag array is configured with a core identifier field to refine the granularity of management operations. When a computation core sends a management operation command to the cache, the cache only executes the management operation command on the target tag corresponding to the computation core that sent the command, and does not execute management operation commands on the remaining tags in the tag array. Therefore, in a multi-core parallel system, a management operation command issued by one computation core will not affect the cache lines being used by other computation cores, and the cache can efficiently execute management operation commands for itself. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a circuit block of an artificial intelligence chip according to an embodiment of the present disclosure;

[0011] Figure 2 This is a schematic diagram of a tag array according to one embodiment;

[0012] Figure 3 This is a schematic diagram of a tag array illustrated according to an embodiment of the present disclosure;

[0013] Figure 4 This is a schematic flowchart illustrating a caching operation method according to an embodiment of the present disclosure;

[0014] Figure 5 This is a circuit block diagram of an artificial intelligence chip according to another embodiment of the present disclosure;

[0015] Figure 6 This is a schematic flowchart of a caching operation method according to another embodiment of the present disclosure;

[0016] Figure 7 This is a schematic diagram of a command table drawn according to an embodiment of the present disclosure;

[0017] Figure 8 This is a schematic diagram of a command table illustrated according to another embodiment of the present disclosure.

[0018] Explanation of icon numbers:

[0019] 100. The first artificial intelligence chip,

[0020] 500. The second artificial intelligence chip.

[0021] 110. First calculation core,

[0022] 510. Second calculation core,

[0023] 120. First cache

[0024] 520, Second Cache

[0025] 121. First Hit-Miss Check Unit

[0026] 521. Second hit-miss check unit.

[0027] 122. First tag array,

[0028] 200, the second tag array,

[0029] 300, the third tag array,

[0030] 522, 4th tag array,

[0031] 123. First Operation Engine

[0032] 523, Second Operation Engine

[0033] 124. First cache line array,

[0034] 524, Second Cache Linear Array

[0035] 130. First main memory,

[0036] 530. Secondary main memory.

[0037] 210_1, Tag Group 1_1

[0038] 210_2, Tag Group 1_2

[0039] 210_c, tag group 1_c

[0040] 310_1, Tag Group 2_1

[0041] 310_2, Tag Group 2_2

[0042] 310_c, tag group 2_c

[0043] 525. First command list,

[0044] 700, Command Table 2

[0045] 800, Command Table 3

[0046] 710_1, Group 1_1 Command Chart

[0047] 710_2, Command Chart Group 1_2

[0048] Command diagrams for group 710_c and 1_c.

[0049] Command diagrams in group 810_1 and 2_1.

[0050] 810_2, Group 2_2 of the command diagram,

[0051] Command diagrams for group 810_c and 2_c.

[0052] 811_1, Command diagram of core 1,

[0053] 811_2, Second Core Command Diagram

[0054] 811_n, the command graph of the nth core,

[0055] cmd_1, the first command enable bit.

[0056] cmd_2, the second command enable bit.

[0057] cmd_m, the enable bit for the m-th command.

[0058] tag2_1, tag 1_1

[0059] tag2_2, tag 1_2,

[0060] tag2_d, the first_d tag,

[0061] tag3_1, tag 2_1

[0062] tag3_2, tag 2_2

[0063] tag3_d, the second tag. Detailed Implementation

[0064] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0065] The term "coupled (or connected)" as used throughout this disclosure (including the claims) can refer to any direct or indirect connection means. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some connection means. The terms "first," "second," etc., used throughout this disclosure (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components, parts, and steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components, parts, and steps using the same reference numerals or the same terms in different embodiments can be referred to mutually in the relevant descriptions. It should be understood that the features of the following embodiments can be combined with each other. For example, the features of the second embodiment can be combined with the features of the first embodiment. Those skilled in the art can select appropriate combinations of features according to actual design requirements.

[0066] Computing devices such as artificial intelligence (AI) chips can provide enormous computing power. This immense computing power stems from the large number of internal hardware cores. An AI chip typically contains multiple programmable processors, such as a stream processor cluster (SPC). Each programmable processor typically contains multiple compute units (CUs), and each compute unit typically contains multiple execution units (EUs). Execution units may include at least one of the following: tensor cores (Tcores), integer cores (INTs), floating-point cores (FPs), and vector cores (Vcores). By organizing these compute cores through programming, AI chips can support general-purpose computing, scientific computing, and neural network computing. The compute cores of an AI chip typically access data in main memory through caches, such as last-level caches (LLCs). The following examples illustrate various implementation paradigms of caching.

[0067] Figure 1 This is a circuit block diagram of an artificial intelligence chip according to an embodiment of the present disclosure. Figure 1 The first artificial intelligence chip 100 shown includes multiple first computing cores 110, a first cache 120, and a first main memory 130. The number of first computing cores 110 can be determined according to the actual design and application. The first computing core 110 is also called a first computing unit. (Although not shown in the diagram...) Figure 1 Each first computing core 110 typically contains multiple execution units and shared memory. Different execution cores within the same computing core can exchange data with each other through shared memory. A first cache 120 is coupled between the first computing core 110 and the first main memory 130. The first cache 120 can be the last-level cache of the first artificial intelligence chip 100 or other caches. The first computing core 110 accesses data in the first main memory 130 through the first cache 120.

[0068] exist Figure 1 In the illustrated embodiment, the first cache 120 includes a first hit-miss check unit 121, a first tag array 122, a first operation engine 123, and a first cache line array 124. Depending on the design, in some embodiments, at least one of the first hit-miss check unit 121 and the first operation engine 123 may be implemented as hardware circuitry. In other embodiments, at least one of the first hit-miss check unit 121 and the first operation engine 123 may be implemented as a combination of hardware, firmware, and software (i.e., programs).

[0069] In terms of hardware, at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented as logic circuits on an integrated circuit. For example, the relevant functions of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented in various logic blocks, modules and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs) or other processing units. The relevant functions of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented as hardware circuits, such as various logic blocks, modules and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0070] In software or firmware form, the functions of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented as programming codes. For example, the functions of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded or stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium to implement the functions of at least one of the first hit-miss check unit 121 and the first operation engine 123.

[0071] The first hit-miss check unit 121 is coupled to the first tag array 122 and the first compute core 110. The first tag array 122 includes multiple tag groups, and each tag group includes multiple tags. The first operation engine 123 is coupled to the first hit-miss check unit 121, the first cache line array 124, and the first main memory 130. The first cache line array 124 includes multiple cache lines. The multiple cache lines of the first cache line array 124 correspond one-to-one with the multiple tags of the first tag array 122. Each tag is used to store the corresponding cache line information.

[0072] For example, Figure 2 This is a schematic diagram of a tag array according to one embodiment. Figure 2 The second tag array 200 shown can be used as Figure 1 This is one of many implementation examples of the first tag array 122 shown. Figure 2 In the illustrated embodiment, the second tag array 200 includes multiple tag groups (tag group 1_1 210_1, tag group 1_2 210_2, ..., tag group 1_c 210_c). The number c of tag groups 1_1 to 1_c can be determined according to the actual design and application. Each tag group in tag groups 1_1 to 1_c includes multiple tags. For example, tag group 1_1 includes multiple tags (tag2_1, tag2_2, ..., tag2_d). The number d of tag2_1 to tag2_d can be determined according to the actual design and application. Other tag groups besides tag group 1_1 210_1 (tag group 1_2 210_2 to tag group 1_c 210_c) can be referred to the relevant description of tag group 1_1 210_1 and deduced by analogy, so they will not be elaborated here.

[0073] exist Figure 2 In the illustrated embodiment, each tag from tag1_1 to tag2_1 to tag1_d includes a tag address field, a valid bit field, and a dirty bit field. Generally, the access request sent by the computation core includes the set address and tag address. Please refer to... Figure 1 and Figure 2The first hit-miss check unit 121 retrieves the corresponding tag group from the first tag array 122 (e.g., the second tag array 200) based on the group address, and then compares the tag address carried in the access request with the tag address field of each tag in the corresponding tag group. If the tag address field content of a certain tag matches the tag address carried in the access request, the first hit-miss check unit 121 determines it as a "hit". In response to the first hit-miss check unit 121 determining the access request of the first computing core 110 as a hit, the first operation engine 123 accesses the target cache line corresponding to the access request in multiple cache lines of the first cache line array 124. If the tag address field content of each tag does not match the tag address carried in the access request, the first hit-miss check unit 121 determines it as a "miss". In response to the first hit-miss check unit 121 determining that the access request to the first computing core 110 is a miss, the first operation engine 123 accesses the first main memory 130.

[0074] By sending management operation commands to the first cache 120, the first AI chip 100 can perform management operations on the first cache 120, such as clearing operations or modifying priorities. In response to a first computing core 110 sending a management operation command to the first cache 120, the first hit-miss checking unit 121 performs an iterative operation on each of the multiple tag groups in the first tag array 122 (e.g., each of tag groups 210_1 to 210_c of the second tag array 200) to execute the management operation command. The iterative operation includes: reading one tag group from the multiple tag groups in the first tag array 122 as the current tag group; executing a management operation command (e.g., a clearing command) on each tag of the target tag group; and writing the current tag group back to the first tag array 122. Generally, the first tag array 122 is stored in the random access memory (RAM) of the first cache 120, which is coupled to the first hit-miss check unit 121. When executing management operation commands for the entire first cache 120, if the command information is actually written to the tag memory, each tag group needs to be updated once. If there are many groups, the latency of the management operation commands will be relatively large. Furthermore, since these management operations operate on the entire first cache 120, in a multi-core parallel system, a management operation command issued by a first compute core 110 will affect the cache lines used by other cores.

[0075] Figure 3 This is a schematic diagram of a tag array illustrated according to an embodiment of the present disclosure. Figure 3 The third tag array 300 shown can be used as Figure 1 This is one of many implementation examples of the first tag array 122 shown. Figure 3 In the illustrated embodiment, the third tag array 300 includes multiple tag groups (tag group 310_1, tag group 310_2, ..., tag group 310_c). The number c of tag groups 310_1 to 310_c can be determined according to the actual design and application. Each of tag groups 310_1 to 310_c includes multiple tags. For example, tag group 310_1 includes multiple tags (tag3_1, tag3_2, ..., tag3_d). The number d of tag3_1 to tag3_d can be determined according to the actual design and application. The other tag groups (tag groups 310_2 to 310_c) other than tag 3_1 can be referred to the relevant description of tag 3_1 and deduced by analogy, so they will not be elaborated on. Figure 3 The third tag array 300, the second tag group 310_1 to the second tag group 310_c, and the second tag 3_1 to the second tag 3_d shown can be referenced. Figure 2 The relevant descriptions of the second tag array 200, the first tag group 210_1 to the first tag group 210_c, and the first tag tag2_1 to the first tag tag2_d shown are not repeated here.

[0076] Unlike Figure 2 The embodiment shown, Figure 3 Each tag also includes a kernel identifier field. In response to a request from one of the multiple first compute cores 110 to use a corresponding cache line of the first cache line array 124 of the first cache 120, the first hit-miss checking unit 121 places the kernel identifier (kernel ID) from the request into the kernel identifier field of the target tag corresponding to the cache line among the multiple tags in the first tag array 122. Therefore, the kernel identifier field can be used to distinguish which compute core is currently using the cache line.

[0077] Figure 4 This is a flowchart illustrating a caching operation method according to an embodiment of the present disclosure. Please refer to... Figure 1 , Figure 3 and Figure 4In step S410, one of the plurality of first computing cores 110 sends a management operation command to the first cache 120. In response to the command-sending computing core 110 sending the management operation command to the first cache 120, the first hit-miss checking unit 121 performs an iterative operation (step S420) on each of the plurality of tag groups (e.g., each of tag groups 2_1 310_1 to 2_c 310_c) to execute the management operation command. Figure 4 In the illustrated embodiment, the iterative operation includes steps S421 to S429.

[0078] In step S421, the first hit-miss checking unit 121 reads one of the multiple tag groups from the first tag array 122 as the current tag group (e.g., reading one of the second_1 tag group 310_1 to the second_c tag group 310_c from the third tag array 300). In step S422, the first hit-miss checking unit 121 checks the core identifier field of each of the multiple tags in the current tag group to select the target tag corresponding to the command sending calculation core from the multiple tags in the current tag group.

[0079] In step S423, it is determined whether the current tag group contains a target tag corresponding to the command sending calculation core. If the current tag group contains a target tag corresponding to the command sending calculation core (the determination result of step S423 is "yes"), the first hit-miss check unit 121 executes a management operation command on the target tag corresponding to the command sending calculation core, and the first hit-miss check unit 121 does not execute management operation commands on the remaining tags in the current tag group (step S424). If the current tag group does not contain a target tag corresponding to the command sending calculation core (the determination result of step S423 is "no"), the first hit-miss check unit 121 does not execute management operation commands on any tag in the current tag group (step S425).

[0080] After completing step S424 or step S425, in step S426, the first hit-miss check unit 121 writes the current tag group back to the first tag array 122 (e.g., the third tag array 300). The first hit-miss check unit 121 determines whether the first tag array 122 has an unprocessed next tag group. In step S427, it determines whether the first tag array 122 has an unprocessed next tag group. In response to the first tag array 122 having an unprocessed next tag group (the determination result of step S427 is "yes"), the first hit-miss check unit 121 selects the next tag group as the current tag group (step S428), and then returns to step S421. In response to the first tag array 122 having no unprocessed next tag group (the determination result of step S427 is "no"), the first hit-miss check unit 121 ends the iteration operation of this management operation command (step S429).

[0081] In summary, each tag in the first tag array 122 (e.g., the third tag array 300) of the first cache 120 is configured with a core identifier field to refine the granularity of management operations. When a first compute core 110 sends a management operation command to the first cache 120, the first cache 120 only executes the management operation command on the target tag corresponding to the compute core that sent the command, and does not execute management operation commands on the other tags in the first tag array 122. Therefore, in a multi-compute-core parallel system, a management operation command issued by one compute core will not affect the cache lines currently being used by other compute cores, and the first cache 120 can efficiently execute management operation commands for itself.

[0082] Figure 5 This is a circuit block diagram of an artificial intelligence chip according to another embodiment of the present disclosure. Figure 5 The second artificial intelligence chip 500 shown includes multiple second computing cores 510, a second cache 520, and a second main memory 530. Figure 5 The second cache 520 shown includes a second hit-miss check unit 521, a fourth tag array 522, a second operation engine 523, and a second cache line array 524. Figure 5 The second AI chip 500, second computing core 510, second cache 520, second hit-miss check unit 521, fourth tag array 522, second operation engine 523, second cache line array 524, and second main memory 530 shown can be referenced. Figure 1 The descriptions of the first artificial intelligence chip 100, the first computing core 110, the first cache 120, the first hit-miss check unit 121, the first tag array 122, the first operation engine 123, the first cache line array 124, and the first main memory 130 shown are similar and will not be repeated here.

[0083] Unlike Figure 1 The embodiment shown, Figure 5 The second AI chip 500 also includes a first command table 525. A second hit-miss check unit 521 is coupled to the first command table 525. Generally, the fourth tag array 522 is stored in the random access memory (RAM) of the second cache 520, which is coupled to the second hit-miss check unit 521. Figure 5 In the illustrated embodiment, the first command table 525 may be stored in a flip-flop (FF) array or other storage component array, which is coupled to the second hit-miss check unit 521.

[0084] Figure 6 This is a flowchart illustrating a caching operation method according to another embodiment of the present disclosure. Please refer to... Figure 5 and Figure 6 In step S610, one of the multiple second computing cores 510 sends a management operation command to the second cache 520. In response to the command sending computing core in the multiple second computing cores 510 sending the management operation command to the second cache 520, the second hit-miss check unit 521 registers the management operation command in the first command table 525, but temporarily does not execute the management operation command (step S620).

[0085] Figure 7 This is a schematic diagram of a command table illustrated according to an embodiment of the present disclosure. Figure 7 The second command table 700 shown can be used as Figure 5 This is one of the many implementation examples shown in Table 525 of Command 1. Figure 7 In the illustrated embodiment, the second command table 700 includes multiple set command maps, such as set command map 710_1 (set 1), set command map 710_2 (set 1), ..., set command map 710_c (set 1). Set command maps 710_1 to 710_c of the second command table 700 correspond one-to-one with multiple tag groups in the fourth tag array 522. Based on practical design and application, in some embodiments... Figure 2 The second tag array 200 shown can be used as Figure 5 This is one of many implementation examples of the fourth tag array 522 shown. In other embodiments, Figure 3 The third tag array 300 shown can be used as Figure 5 This is one of many implementation examples of the fourth tag array 522 shown.

[0086] Please refer to Figure 5 and Figure 7 Each of the command diagrams 710_1 to 710_c in group 1_1 includes multiple command enable bits (command enable bit cmd_1, command enable bit cmd_2, ..., command enable bit cmd_m) to represent different management commands. For example (but not limited to), command enable bit cmd_1 can correspond to a clear operation command, while the other command enable bits (command enable bits cmd_2 to cmd_m) can correspond to other different operation commands. The number m of command enable bits cmd_1 to cmd_m can be determined based on the number of management command types in the actual application scenario.

[0087] Assume that the management operation command sent by the second computing core 510 to the second cache 520 is a clear operation command. The effect of this clear operation command includes that the second hit-miss check unit 521 will... Figure 2 The valid bit field of all tags in the second tag array 200 is reset to logical "false", such as logical value "0". In response to the second computation core 510 sending a clear operation command to the second cache 520, the second hit-miss check unit 521 registers the clear operation command in the first command table 525, but temporarily does not execute the clear operation command (that is, temporarily stops the clear operation command on the valid bits of the fourth tag array 522).

[0088] In detail, "the second hit-miss check unit 521 registers the clear operation command in the first command table 525" means that the first command enable bit cmd_1 of each of the first group command diagrams 710_1 to the first group command diagrams 710_c is set to logical "truth", for example, logical value "1". The first command enable bit cmd_1 of a certain group command diagram being set to logical "truth" indicates that the valid bit clearing operation for a certain corresponding tag group in the fourth tag array 522 has not yet been performed. In response to the second computing core 510 sending the management operation command to the second cache 520, the second hit-miss check unit 521 sets the target command enable bit corresponding to the management operation command in the first command enable bit cmd_1 to the m-th command enable bit cmd_m of each of the first group command diagrams 710_1 to the first group command diagrams 710_c. Assume that the management operation command sent by the second computing core 510 to the second cache 520 is a clear operation command, and assume that the first command enable bit cmd_1 of each of the first group of command diagrams 710_1 to 710_c corresponds to the clear operation command. In response to the second computing core 510 sending the clear operation command to the second cache 520, the second hit-miss check unit 521 sets the target command enable bit (first command enable bit cmd_1) of each of the first group of command diagrams 710_1 to 710_c to logical "true".

[0089] Please refer to Figure 5 , Figure 6 and Figure 7 In step S630, one of the multiple second computing cores 510 sends an access request to the second cache 520. In response to any second computing core 510 sending an access request to the second cache 520, the second hit-miss checking unit 521 also executes management operation commands registered in the first command table 525 during the execution of the access request (step S640). When the second hit-miss checking unit 521 receives an access request from any second computing core 510, it queries the target group command diagrams corresponding to the target tag group in command diagrams 710_1 to 710_c of group 1_1 in the first command table 525 based on the target tag group of this access request.

[0090] Furthermore, the second hit-miss check unit 521 reads the target tag group corresponding to the access request from multiple tag groups (tag group 210_1 to tag group 210_c) from the fourth tag array 522 based on the access request from the second computing core 510. The second hit-miss check unit 521 executes the management operation command registered in the first command table 525 on the target tag group. The second hit-miss check unit 521 executes the access request. After the second hit-miss check unit 521 completes the execution of the access request, the second hit-miss check unit 521 writes the target tag group back to the fourth tag array 522.

[0091] For example, suppose that the first command enable bit cmd_1 of each of the command diagrams 710_1 to 710_c of the first group of command diagrams corresponds to a clear operation command, and suppose that the first command enable bit cmd_1 of each of the command diagrams 710_1 to 710_c of the first group of command diagrams has been set to logical "true", and suppose that the target group command diagram corresponding to the target tag group (tag group 210_1 of the first group of access requests) is the command diagram 710_1 of the first group of command diagrams. When the second hit-miss check unit 521 receives any access request issued by the second computing core 510, the second hit-miss check unit 521 queries the target group command diagram (command diagram 710_1 of the first group of command diagrams) based on the target tag group (tag group 210_1 of the first group of access requests). Because the target command enable bit (first command enable bit cmd_1) of the target group command diagram (command diagram 710_1 of group 1) is logically "true", the second hit-miss check unit 521 can know that the valid bit field of the target tag group (tag group 210_1 of group 1) should be logically "false" (although the valid bit field of tag group 210_1 of group 1 is actually logically "true" at this time). At this time, in addition to executing the access request with the condition that "the valid bit field of the target tag group (tag group 210_1 of group 1) should be logically false", the second hit-miss check unit 521 also executes the clear operation command registered in the first command table 525 on the target tag group (tag group 210_1 of group 1) during the execution of the access request. This means that the second hit-miss check unit 521 resets the valid bit fields of all tags in the target tag group (tag group 210_1, 1_1) to logical "false". After the second hit-miss check unit 521 completes the execution of the access request, it writes the target tag group (tag group 210_1, 1_1) back to the fourth tag array 522. In response to the second hit-miss check unit 521 executing the clear operation command registered in the first command table 525 on the target tag group (tag group 210_1, 1_1) in the fourth tag array 522, the second hit-miss check unit 521 resets the target command enable bit (first command enable bit cmd_1) corresponding to the clear operation command in the target group command diagram (command diagram 710_1, 1_1 group) to logical "false".

[0092] In summary, the second cache 520 is configured with a first command table 525. When a second compute core 510 sends a management operation command to the second cache 520, the second cache 520 registers the management operation command in the first command table 525 but does not execute it temporarily. Therefore, for the command-sending compute core (second compute core 510), the management operation command is executed efficiently. In response to a second compute core 510 sending an access request to the second cache 520, the second cache 520 executes the management operation command registered in the first command table 525 while executing the access request. For the second cache 520, the execution of the access request and the execution of the management operation command registered in the first command table 525 can occur simultaneously. Therefore, the execution of the management operation command does not affect the efficiency of the second cache 520 in executing access requests. Based on this, the second cache 520 can efficiently execute management operation commands for the cache.

[0093] Figure 8 This is a schematic diagram of a command table illustrated according to another embodiment of the present disclosure. Figure 8 The third command table 800 shown can be used as Figure 5 This is one of the many implementation examples shown in Table 525 of Command 1. Figure 7 In the illustrated embodiment, the third command table 800 includes multiple group command diagrams, such as group 2_1 command diagram 810_1, group 2_2 command diagram 810_2, ..., group 2_c command diagram 810_c. Group 2_1 command diagrams 810_1 to group 2_c command diagrams 810_c of the third command table 800 correspond one-to-one with multiple tag groups of the fourth tag array 522. Based on practical design and application, in some embodiments, Figure 3 The third tag array 300 shown can be used as Figure 5 This is one of many implementation examples of the fourth tag array 522. In response to a request from one of the multiple second computing cores 510 to use the corresponding cache line of the second cache 520, the second hit-miss checking unit 521 places the kernel identifier (ID) included in the request into the kernel identifier field of the target tag corresponding to the cache line in one of the multiple tag groups of the fourth tag array 522 (e.g., tag groups 310_1 to 310_c of the second_1 tag group of the third tag array 300). The kernel identifier field can be used to distinguish which computing core is currently using the cache line.

[0094] Please refer to Figure 3 , Figure 5 and Figure 8Each of the command diagrams in group 2_1 (810_1) to group 2_c (810_c) includes multiple core command diagrams. Taking group 2_1 command diagram 810_1 as an example, the other command diagrams (group 2_2 command diagrams 810_2 to group 2_c command diagrams 810_c) can be deduced by referring to the relevant description of group 2_1 command diagram 810_1, and therefore will not be repeated here. Group 2_1 command diagram 810_1 includes multiple core command diagrams (core command diagram 811_1, core command diagram 811_2, ..., core command diagram 811_n). Within the same group of command diagrams (such as command diagram 810_1 of group 2_1), core command diagrams (such as core command diagrams 811_1 to nth core command diagrams 811_n) correspond one-to-one with multiple second computing cores 510 (assuming the number of second computing cores 510 is n). Each of core command diagrams 811_1 to nth core command diagrams 811_n includes multiple command enable bits (command enable bit cmd_1, command enable bit cmd_2, ..., command enable bit cmd_m) representing different management commands. For example (but not limited to), command enable bit cmd_1 may correspond to a clear operation command, while other command enable bits (command enable bits cmd_2 to mth command enable bits cmd_m) may correspond to other different operation commands. The number m of command enable bits cmd_1 to mth command enable bits cmd_m can be determined based on the number of types of management commands in the actual application scenario.

[0095] In response to a second computing core 510 sending a management operation command to a second cache 520, the second hit-miss check unit 521 selects the target core command map corresponding to the computing core (second computing core 510) from the core command maps of each of the second_1 group command maps 810_1 to the second_c group command maps 810_c (e.g., the first core command map 811_1 to the nth core command map 811_n). The second hit-miss check unit 521 sets the target command enable bit corresponding to the management operation command in the multiple command enable bits (first command enable bit cmd_1 to mth command enable bit cmd_m) of the target core command map of each of the second_1 group command maps 810_1 to the second_c group command maps 810_c. For example, suppose that the management operation command sent by a second computing core 510 to the second cache 520 is a clear operation command, suppose that the target core command diagram corresponding to the command sent computing core (second computing core 510) is the first core command diagram 811_1 in each of the command diagrams 810_1 in the second group of command diagrams 810_1 to the second group of command diagrams 810_c, and suppose that the command enable bit corresponding to the clear operation command is the first command enable bit cmd_1. In response to a second computing core 510 sending a clear operation command to the second cache 520, the second hit-miss check unit 521 selects the first core command diagram 811_1 of each of the second group of command diagrams 810_1 to the second group of command diagrams 810_c as the target core command diagram corresponding to the computing core (second computing core 510). The second hit-miss check unit 521 sets the target command enable bit (first command enable bit cmd_1) in the target core command diagram (first core command diagram 811_1) of each of the second group of command diagrams 810_1 to the logical "true" bit (e.g., logical value "1"). The first command enable bit cmd_1 of a certain core command graph in a certain group command graph is set to logical "true", indicating that the valid bit clearing operation for the tag corresponding to a certain computing core in a certain corresponding tag group of the fourth tag array 522 has not yet been performed.

[0096] Based on the group address included in the access request of a certain second computing core 510, the second hit-miss check unit 521 reads the target tag group (e.g., tag group 310_1) corresponding to the access request from multiple tag groups (tag group 310_1 to tag group 310_c) in the third tag array 300. In addition, the second hit-miss check unit 521 obtains from the third command table 800 multiple command enable bits (command enable bit cmd_1 to command enable bit cmd_m) of each target core command graph (e.g., core command graph 811_1 to core command graph 811_n) in the group command graph corresponding to the target tag group (e.g., group command graph 810_1). The second hit-miss check unit 521 identifies which command-sending computing core sent the management operation command from among multiple second computing cores 510 based on the first command enable bit cmd_1 to the m command enable bit cmd_m (i.e., the management operation command registered in the third command table 800) of different core command diagrams in the first core command diagram 811_1 to the nth core command diagram 811_n.

[0097] The second hit-miss check unit 521 checks the core identifier field of each tag in the target tag group to select the target tag corresponding to the command sending calculation core from the multiple tags in the target tag group. In response to the existence of a target tag corresponding to the command sending calculation core in the target tag group, the second hit-miss check unit 521 executes the management operation command registered in the third command table 800 for the target tag corresponding to the command sending calculation core, and does not execute the management operation commands registered in the third command table 800 for the remaining tags in the target tag group other than the target tag. In response to the absence of a target tag corresponding to the command sending calculation core in the target tag group, the second hit-miss check unit 521 does not execute the management operation commands registered in the third command table 800 for the target tag group.

[0098] For example, suppose the target tag group (tag group 310_1, group 2_1) corresponds to command diagram 810_1 in command table 800, and only the first command enable bit cmd_1 of the first core command diagram 811_1 in the target group command diagram (tag group 310_1) is logically "true", while the other command enable bits in the target group command diagram (tag group 310_1) are logically "false". The second hit-miss check unit 521 can know from the target group command diagram (tag group 310_1) that, for the target tag group (tag group 310_1), the clear operation command previously sent by a certain computing core corresponding to the first core command diagram 811_1 has not yet been executed. The second hit-miss checking unit 521 checks the core identifier field of each of the second-first tag tag3_1 to the second-second tag tag3_d in the target tag group (second-first tag group 310_1) to select the target tag corresponding to the command sending calculation core from the multiple tags (second-first tag tag3_1 to the second-second tag tag3_d) in the target tag group (second-first tag group 310_1). Assuming that tag 2_1 is the target tag corresponding to the command sending calculation core, the second hit-miss check unit 521 performs a clearing operation command on the target tag (tag 2_1, tag 3_1) (resetting the valid bit field of tag 2_1, tag 3_1 to logical "false"), and the second hit-miss check unit 521 does not perform clearing operation commands on the other tags (tag 2_2, tag 3_2 to tag 2_d, tag 3_d) in the target tag group (tag group 2_1, tag group 310_1) except for the target tag (tag 2_1, tag 3_1). Assuming that the kernel identifier field of all tags (tag3_1 to tag3_d) in the target tag group (tag3_1) does not match the command sending calculation kernel (i.e., in response to the fact that there is no target tag in the target tag group (tag3_1) that corresponds to the command sending calculation kernel), the second hit-miss check unit 521 does not execute the clear operation command for the target tag group (tag3_1).

[0099] While performing the preceding operations on the target tag group (tag group 310_1, 2_1), the second hit-miss check unit 521 can also execute an access request. After the second hit-miss check unit 521 completes the execution of the access request, it writes the target tag group (tag group 310_1, 2_1) back to the third tag array 300. In response to the second hit-miss check unit 521 executing a management operation command (e.g., a clear operation command) registered in the third command table 800 on the target tag group (the second_1 tag group 310_1), the second hit-miss check unit 521 selects the target core command diagram (e.g., the first core command diagram 811_1) corresponding to the command sending calculation core from multiple core command diagrams (the first core command diagram 811_1 to the nth core command diagram 811_n) of the target group command diagram (the second_1 group command diagram 810_1), and the second hit-miss check unit 521 resets the target command enable bit (e.g., the first command enable bit cmd_1) corresponding to the management operation command in the target core command diagram (e.g., the first core command diagram 811_1) of the target group command diagram (the second_1 group command diagram 810_1).

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and not to limit them; although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A cache for an artificial intelligence chip, characterized in that, The cache includes: Command table; and A hit-miss check unit, coupled to the command table, wherein... In response to one of the multiple computing cores sending a management operation command to the cache, the hit-miss check unit registers the management operation command in the command table and temporarily suspends execution of the management operation command; and In response to one of the plurality of computing cores sending an access request to the cache, the hit-miss checking unit also executes the management operation command registered in the command table during the execution of the access request.

2. The cache according to claim 1, characterized in that, The cache also includes: A tag array, coupled to the hit-miss checking unit, wherein the tag array includes multiple tag groups, each of the multiple tag groups includes multiple tags, and each of the multiple tags is used to store corresponding cache line information. The hit-miss check unit reads the target tag group corresponding to the access request from the tag array of the plurality of tag groups based on the access request; The hit-miss check unit executes the management operation command registered in the command table on the target tag group; The hit-miss check unit executes the access request; and After the hit-miss check unit completes the execution of the access request, the hit-miss check unit writes the target tag group back to the tag array.

3. The cache according to claim 2, characterized in that, The cache also includes: A trigger array, coupled to the hit-miss check unit, wherein the command table is stored in the trigger array; and Random access memory, coupled to the hit-miss check unit, wherein the tag array is stored in the random access memory.

4. The cache according to claim 2, characterized in that, The command table includes multiple group command diagrams, each corresponding one-to-one with one of the multiple tag groups in the tag array. Each of the multiple group command diagrams includes multiple command enable bits representing different management commands. In response to one of the multiple computing cores sending the management operation command to the cache, the hit-miss check unit sets the target command enable bit corresponding to the management operation command in the multiple command enable bits of each of the multiple group command graphs.

5. The cache according to claim 4, characterized in that, The target label group corresponds to the target group command graph in the plurality of group command graphs, and In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target group command diagram.

6. The cache according to claim 2, characterized in that, The cache also includes: A cache line array, comprising a plurality of cache lines, wherein the plurality of cache lines of the cache line array correspond one-to-one with the plurality of tags of the tag array; and The operation engine is coupled to the hit-miss check unit and the cache line array, wherein, In response to the hit-miss check unit determining that the access request is a hit, the operation engine accesses the target cache line corresponding to the access request among the plurality of cache lines in the cache line array; and In response to the hit-miss check unit determining that the access request is a miss, the operation engine accesses the main memory.

7. The cache according to claim 1, characterized in that, The cache also includes: A tag array, coupled to the hit-miss check unit, wherein the tag array includes multiple tag groups, each of the multiple tag groups includes multiple tags, each of the multiple tags is used to store corresponding cache line information, and each of the multiple tags also includes a core identifier field, the core identifier field being used to distinguish which computing core is currently using the cache line; The hit-miss check unit reads the target tag group corresponding to the access request from the tag array of the plurality of tag groups based on the access request; The hit-miss check unit distinguishes the command sending core from the plurality of computing cores based on the management operation commands registered in the command table; The hit-miss checking unit checks the core identifier field of each of the plurality of tags in the target tag group to select the target tag corresponding to the command sending calculation core from the plurality of tags in the target tag group; In response to the existence of a target tag in the target tag group that corresponds to the command sending calculation core, the hit-miss check unit executes the management operation command registered in the command table for the target tag corresponding to the command sending calculation core, and the hit-miss check unit does not execute the management operation command registered in the command table for the remaining tags in the target tag group; In response to the absence of a target tag corresponding to the command sending calculation core in the target tag group, the hit-miss check unit does not execute the management operation command registered in the command table for the target tag group; The hit-miss check unit executes the access request; and After the hit-miss check unit completes the execution of the access request, the hit-miss check unit writes the target tag group back to the tag array.

8. The cache according to claim 7, characterized in that, In response to a request from one of the plurality of computing cores to use the corresponding cache line of the cache, the hit-miss check unit places the core identifier carried by the request into the core identifier field of the target tag corresponding to the corresponding cache line among the plurality of tags.

9. The cache according to claim 7, characterized in that, The command table includes multiple group command graphs, each corresponding one-to-one with a group of tags in the tag array. Each group command graph includes multiple core command graphs, each corresponding one-to-one with a group of computing cores. Each core command graph includes multiple command enable bits representing different management commands. In response to the command sending computation core sending the management operation command to the cache, the hit-miss check unit selects the target core command graph corresponding to the command sending computation core from the multiple core command graphs of each of the multiple group command graphs, and the hit-miss check unit sets the target command enable bit corresponding to the management operation command in the multiple command enable bits of the target core command graph of each of the multiple group command graphs.

10. The cache according to claim 9, characterized in that, The target label group corresponds to the target group command graph in the plurality of group command graphs, and In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit selects the target core command graph corresponding to the command sending calculation core from the plurality of core command graphs in the target group command graph, and the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target core command graph of the target group command graph.

11. A method for operating a cache in an artificial intelligence chip, characterized in that, The operation method includes: In response to one of the multiple computing cores sending a management operation command to the cache, the cache's hit-miss checking unit registers the management operation command in the cache's command table and temporarily suspends its execution, wherein the hit-miss checking unit is coupled to the command table; and In response to one of the plurality of computing cores sending an access request to the cache, the hit-miss checking unit also executes the management operation command registered in the command table during the execution of the access request.

12. The operating method according to claim 11, characterized in that, The operation method further includes: The hit-miss checking unit reads the target tag group corresponding to the access request from the tag array of the cached tag array based on the access request, wherein the tag array is coupled to the hit-miss checking unit, each of the multiple tag groups includes multiple tags, and each of the multiple tags is used to store corresponding cache line information; The hit-miss check unit executes the management operation command registered in the command table on the target tag group; The access request is executed by the hit-miss check unit; and After the hit-miss check unit completes the execution of the access request, the hit-miss check unit writes the target tag group back to the tag array.

13. The operating method according to claim 12, characterized in that, The operation method further includes: The command table is stored in the trigger array of the cache, wherein the trigger array is coupled to the hit-miss check unit; and The tag array is stored in the random access memory of the cache, wherein the random access memory is coupled to the hit-miss check unit.

14. The operating method according to claim 12, characterized in that, The command table includes multiple group command diagrams, each group command diagram in the command table corresponding one-to-one with the multiple tag groups of the tag array. Each of the multiple group command diagrams includes multiple command enable bits for representing different management commands. The operation method further includes: In response to one of the multiple computing cores sending the management operation command to the cache, the hit-miss check unit sets the target command enable bit corresponding to the management operation command in the multiple command enable bits of each of the multiple group command graphs.

15. The operating method according to claim 14, characterized in that, The target label group corresponds to the target group command graph in the plurality of group command graphs, and the operation method further includes: In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target group command diagram.

16. The operating method according to claim 12, characterized in that, The operation method further includes: In response to the hit-miss check unit determining that the access request is a hit, the cache operation engine accesses the target cache line corresponding to the access request among multiple cache lines in the cache line array, wherein the multiple cache lines in the cache line array correspond one-to-one with the multiple tags in the tag array, and the operation engine is coupled to the hit-miss check unit and the cache line array; and In response to the hit-miss check unit determining that the access request is a miss, the operation engine accesses the main memory.

17. The operating method according to claim 11, characterized in that, The operation method further includes: The hit-miss checking unit reads the target tag group corresponding to the access request from the tag array of the cache based on the access request. The tag array is coupled to the hit-miss checking unit. Each of the multiple tag groups includes multiple tags. Each of the multiple tags is used to store corresponding cache line information. Each of the multiple tags also includes a core identifier field. The core identifier field is used to distinguish which computing core is currently using the cache line. The hit-miss checking unit distinguishes the command sending computing core from the plurality of computing cores based on the management operation commands registered in the command table; The hit-miss checking unit checks the core identifier field of each of the plurality of tags in the target tag group to select the target tag corresponding to the command sending calculation core from the plurality of tags in the target tag group; In response to the existence of a target tag in the target tag group that corresponds to the command sending calculation core, the hit-miss check unit executes the management operation command registered in the command table on the target tag corresponding to the command sending calculation core, and the hit-miss check unit does not execute the management operation command registered in the command table on the remaining tags in the target tag group; If the target tag group does not contain a target tag corresponding to the command sending calculation core, the hit-miss check unit will not execute the management operation command registered in the command table for the target tag group; The access request is executed by the hit-miss check unit; and After the hit-miss check unit completes the execution of the access request, the hit-miss check unit writes the target tag group back to the tag array.

18. The operating method according to claim 17, characterized in that, The operation method further includes: In response to a request from one of the plurality of computing cores to use the corresponding cache line of the cache, the hit-miss check unit places the core identifier carried in the request into the core identifier field of the target tag corresponding to the corresponding cache line among the plurality of tags.

19. The operating method according to claim 17, characterized in that, The command table includes multiple group command graphs, each group command graph in the command table corresponding one-to-one with the multiple tag groups of the tag array. Each of the multiple group command graphs includes multiple core command graphs, each core command graph in the same group command graph corresponding one-to-one with the multiple computing cores. Each of the multiple core command graphs includes multiple command enable bits for representing different management commands. The operation method further includes: In response to the command sending computation core sending the management operation command to the cache, the hit-miss checking unit selects the target core command graph corresponding to the command sending computation core from the multiple core command graphs of each of the multiple group command graphs, and the hit-miss checking unit sets the target command enable bit corresponding to the management operation command in the multiple command enable bits of the target core command graph of each of the multiple group command graphs.

20. The operating method according to claim 19, characterized in that, The target label group corresponds to the target group command graph in the plurality of group command graphs, and the operation method further includes: In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit selects the target core command graph corresponding to the command sending calculation core from the plurality of core command graphs in the target group command graph, and the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target core command graph of the target group command graph.

21. A cache for an artificial intelligence chip, characterized in that, The cache includes: A tag array, wherein the tag array includes multiple tag groups, each of the multiple tag groups includes multiple tags, each of the multiple tags is used to store corresponding cache line information, and each of the multiple tags also includes a core identifier field, and the core identifier field is used to distinguish which computing core is currently using the cache line; and A hit-miss check unit is coupled to the tag array, wherein In response to a command sent by one of the multiple computing cores, the computing core sends a management operation command to the cache. The hit-miss checking unit iterates over each of the multiple tag groups to execute the management operation command, and the iterative operation includes: The hit-miss check unit reads the current tag group from the plurality of tag groups from the tag array; The hit-miss checking unit checks the core identifier field of each of the plurality of tags in the current tag group to select the target tag corresponding to the command sending calculation core from the plurality of tags in the current tag group; In response to the existence of a target tag corresponding to the command sending calculation core in the current tag group, the hit-miss check unit executes the management operation command on the target tag corresponding to the command sending calculation core, and the hit-miss check unit does not execute the management operation command on the remaining tags in the current tag group; In response to the fact that the current tag group does not contain the target tag corresponding to the command sending calculation core, the hit-miss check unit does not execute the management operation command for the current tag group; and The hit-miss check unit writes the current tag group back to the tag array.

22. The cache according to claim 21, characterized in that, In response to a request from one of the plurality of computing cores to use the corresponding cache line of the cache, the hit-miss check unit places the core identifier carried by the request into the core identifier field of the target tag corresponding to the corresponding cache line among the plurality of tags.

23. A method for operating the cache of an artificial intelligence chip, characterized in that, The operation method includes: In response to commands from multiple compute cores, the compute core sends management operation commands to the cache. The cache's hit-miss checking unit iterates through each of the multiple tag groups in the cache's tag array to execute the management operation command. Each of the multiple tag groups includes multiple tags, each tag stores corresponding cache line information, and each tag also includes a core identifier field. The core identifier field is used to distinguish which compute core is currently using the cache line. The iterative operation includes: Read the current tag group from the plurality of tag groups from the tag array; The core identifier field of each of the plurality of tags in the current tag group is checked to select the target tag corresponding to the command sending calculation core from the plurality of tags in the current tag group; In response to the existence of a target tag corresponding to the command sending calculation core in the current tag group, the management operation command is executed on the target tag corresponding to the command sending calculation core, and the management operation command is not executed on the remaining tags in the current tag group; In response to the fact that the current tag group does not contain the target tag corresponding to the command sending computation core, the management operation command is not executed on the current tag group; and Write the current tag group back to the tag array.

24. The operating method according to claim 23, characterized in that, The operation method further includes: In response to a request from one of the plurality of computing cores to use the corresponding cache line of the cache, the core identifier carried by the request is placed in the core identifier field of the target tag corresponding to the corresponding cache line among the plurality of tags.

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