Network-on-chip fault-tolerant system based on fault-processable routers and double fault-tolerant distributed routing

Abstract

The invention discloses a network-on-chip fault-tolerant system based on a fault processing router and a dual fault-tolerant distributed route, and relates to the technical field of network-on-chip. The system comprises a fault processing router and a dual fault-tolerant distributed routing mechanism. The fault processing router comprises a port distribution module, a redirection FIFO module, an error correction module, a crossbar switch module, a crossbar switch bypass module and a detection master control module. The modules cooperate to realize fault isolation and path reconstruction. According to the dual fault-tolerant distributed routing mechanism, fault tolerance is realized through single fault isolation, composite fault collaboration and dynamic routing adjustment, and deadlock is avoided and network connectivity under fault topology is maximized by dynamically relaxing and forbidding a steering rule. The problems of single-point failure and composite fault accumulation caused by permanent faults of transistors of the network-on-chip are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of network-on-chip, in particular to a network-on-chip fault-tolerant system based on a fault-tolerant router and a double fault-tolerant distributed route. BACKGROUND

[0002] With the continuous shrinking of transistor size, the integration density of modern microchips is constantly improving, and multi-core processors (CMP) can integrate tens or even hundreds of cores on a single chip. As the core architecture of inter-core communication, network-on-chip (NoC) realizes efficient and scalable communication through distributed packet switching routers, and becomes the mainstream solution to replace buses and crossbars. However, the global communication of network-on-chip (NoC) relies on a single physical medium, making it a "single point of failure" risk point for the system - its permanent failure can cause the entire chip communication to be paralyzed. For example, the failure of a single router crossbar will block all communications of the node, and traditional manufacturing tests cannot detect the progressive failure accumulated over time, making network-on-chip (NoC) a bottleneck for the reliability of multi-core systems.

[0003] To address the reliability challenges of network-on-chip (NoC), existing solutions mainly fall into two categories: one is routing algorithm optimization, which avoids failures by dynamically adjusting paths (such as supporting up to 5 failed nodes with virtual channels); the other is hardware architecture enhancement, which shields failures through replicated components voting mechanism, or relies on redundant switching structures to improve fault tolerance.

[0004] However, existing methods have significant limitations in balancing reliability, performance, and cost: dynamic routing algorithms have strict constraints on the number or location of failures, with limited adaptation scenarios; hardware redundancy solutions will increase chip area, conflicting with the area and power consumption limitations of the system-on-chip; centralized reconstruction algorithms rely on central node coordination, requiring dedicated hardware to transmit global topology information, making it difficult to adapt to distributed architecture; traditional solutions focus on single-level failure handling, which is prone to global paralysis due to local failure in complex failure scenarios, and lack effective response measures for the failure of reliability hardware itself. SUMMARY

[0005] The present application provides a network-on-chip fault-tolerant system based on a fault-tolerant router and a double fault-tolerant distributed route to address the single point failure and composite failure accumulation problems of network-on-chip (NoC) caused by transistor permanent failure.

[0006] The network-on-chip fault-tolerant system based on a fault-tolerant router and a double fault-tolerant distributed route of the present application adopts the following technical solutions to solve the above technical problems:

[0007] An on-chip network fault-tolerant system based on a fault-tolerant router and a double fault-tolerant distributed routing mechanism, comprising a fault-tolerant router and a double fault-tolerant distributed routing mechanism;

[0008] The fault-tolerant router comprises a port allocation module, a redirection FIFO module, an error correction module, a crossbar module, a crossbar bypass module and a detection and control module, which cooperatively realize fault isolation and path reconstruction;

[0009] The double fault-tolerant distributed routing mechanism realizes fault tolerance through single fault isolation, composite fault cooperation and dynamic routing adjustment, and maximizes network connectivity under a fault topology while avoiding deadlock through dynamically relaxed disabled steering rules.

[0010] Optionally, the port allocation module receives input data in the local, east, west, south and north directions; the port allocation module is internally provided with a dynamic allocation strategy engine, which intelligently routes the input data to internal processing channels through hardware logic based on preset rules or real-time fault detection states sent by the detection and control module;

[0011] When at least one direction link fault is detected, the port allocation module preferentially allocates healthy port resources to critical service data through a priority arbitration mechanism, and redirects data of the fault link to the internal processing channel corresponding to the remaining healthy link.

[0012] Further optionally, the redirection FIFO module is based on an asynchronous FIFO architecture and has data buffering and fault skipping functions:

[0013] The redirection FIFO module temporarily stores the data output by the port allocation module through a depth-configurable storage queue to buffer burst traffic and match upstream and downstream clock domain differences;

[0014] In a fault scenario, the read pointer and the write pointer are indexed through a redirection table, which maps the sequential FIFO positions to reconfigurable FIFO positions, and adjusts the read-write counter through hardware before accessing the next register unit, thereby skipping the fault register unit;

[0015] The redirection table configuration pointer reset signal ensures that the system correctly uses the remaining healthy registers to maintain the FIFO function when the number of faults increases.

[0016] Further optionally, the error correction module is disposed between the output end of the redirection FIFO module and the input end of the crossbar module, adopts an end-to-end forward error correction mechanism, and realizes error detection and repair at the data link layer;

[0017] The error correction module supports configurable check algorithm to check input data in real time: for single-bit error, the hardware error correction logic directly corrects; for uncorrectable multi-bit error or continuous error event, the state register marks the faulty link and triggers the downstream redirection mechanism.

[0018] Further, the crossbar module is a 5*5 bidirectional transmission channel matrix, supporting dynamic path establishment and multicast communication based on routing table.

[0019] The crossbar module adopts wormhole routing mechanism to realize non-blocking data transmission through input port arbitration and output port distribution logic.

[0020] The crossbar module has a built-in fault sensing unit to monitor the channel health state in real time, and when it detects that the continuous error code of a channel exceeds the threshold, it automatically triggers the bypass switching logic to route data to the crossbar bypass module.

[0021] Further, the crossbar bypass module is a direct bus independent of the main switching matrix of the crossbar module, which contains special control logic.

[0022] When the main channel of the crossbar module is interrupted due to hardware failure or software error, the crossbar bypass module directly guides the data to the target output port through the hardware priority switching mechanism.

[0023] Further, the detection control module is a central management module of the fault-tolerant router, integrating distributed fault detection unit, state fusion unit and fault-tolerant coordination unit.

[0024] The detection control module collects the running parameters of each module in real time through the sensor network of the network on chip interconnection, and identifies the fault mode through the finite state machine; after detecting the fault, the detection control module sends the arbitration rule adjustment signal to the port distribution module, sends the fault label and priority signal to the redirection table of the redirection FIFO module, and starts the built-in fault detection unit to perform deep diagnosis on the suspicious components, realizing fault isolation and fault-tolerant linkage.

[0025] Further, in the dual fault-tolerant distributed routing mechanism, the single fault isolation mechanism realizes fault isolation through the local functions of each module: the redirection FIFO module skips the fault register unit through the redirection table to maintain the storage function; the error correction module detects and corrects single-bit error and marks uncorrectable error; the crossbar module triggers bypass switching through the fault sensing unit, and the crossbar bypass module takes over the transmission; the port distribution module avoids the faulty link through link remapping to ensure the communication continuity in single fault scenario.

[0026] In the dual-fault-tolerant distributed routing mechanism, a composite fault coordination mechanism is used to handle multiple faults accumulated in the same data path: the crossbar bypass module responds to the crossbar module main channel fault first, directly connecting the input and output ports; at the same time, the port allocation module detects the link state in real time, and redirects the data to the input port corresponding to the other healthy link, and realizes the hierarchical isolation and path reconstruction of the composite fault through cross-module linkage;

[0027] In the dual-fault-tolerant distributed routing mechanism, a dynamic routing adjustment mechanism is used to update the routing table based on the real-time fault state shared by the detection master module of each fault-tolerant router through a "rule checking" mechanism: selectively relax the disabled steering rules in traditional routing to maximize network connectivity while avoiding deadlock; based on local neighbor node information, it makes independent decisions without the need for central controller coordination, ensuring system performance in large-scale fault scenarios.

[0028] Preferably, in the dual-fault-tolerant distributed routing mechanism, the data transmission path is: data passes through the redirection FIFO module of the source fault-tolerant router, error correction module encoding, crossbar module or crossbar bypass module, transmission link, port allocation module of the target fault-tolerant router, and finally reaches the redirection FIFO module of the target fault-tolerant router.

[0029] The on-chip network fault-tolerant system based on fault-tolerant routers and dual-fault-tolerant distributed routing of the application has the following advantages compared with the prior art:

[0030] 1、The application realizes fine fault isolation through hardware module coordination: the crossbar bypass module takes over data transmission when the main channel fails, with a delay consistent with the main channel and low area overhead, balancing the redundancy cost and performance; the redirection FIFO module skips the fault register unit through the redirection table, maintaining functionality even if there is a storage unit failure, alleviating the high fault sensitivity caused by the high area ratio of traditional FIFO; the end-to-end error correction module corrects single-bit errors in real time and marks non-repairable faults, triggering the downstream redirection mechanism and improving data link reliability; the port allocation module dynamically remaps the ports based on real-time fault state, and through priority arbitration, it preferentially allocates healthy resources to critical business data, ensuring basic communication capabilities under single-component / link fault;

[0031] 2. The present invention uses a dual-fault-tolerant distributed routing mechanism in collaboration with hardware modules to give the system the ability to adapt to complex faults: in a single-fault scenario, each fault-handling router independently detects and triggers component-level repairs (such as FIFO pointer redirection and cross-switch bypass module switching) through the detection control module; in the event of a complex fault or a cross-router fault, the dynamic routing adjustment mechanism selectively relaxes traditional steering rules (such as relaxing steering restrictions in a mesh topology) based on distributed fault state synchronization, autonomously generating new routing paths while avoiding deadlock; this collaborative architecture of fault-handling routers and a dual-fault-tolerant distributed routing mechanism requires no central node coordination, supports performance degradation under large-scale faults, breaks through the limitations of traditional solutions on the number and location of faults, and can significantly improve the reliability and scalability of on-chip networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Attachment Figure 1 This is a diagram of the architecture of a fault-handling router of the present invention;

[0033] Attachment Figure 2 is a schematic diagram of a port allocation module of the present invention;

[0034] Attachment Figure 3 It is a schematic diagram of the redirection FIFO module of the present invention;

[0035] Attachment Figure 4 It is a schematic diagram of a specific embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the technical solution, the technical problems solved and the technical effects of the present invention more clear, the technical solution of the present invention is clearly and completely described below in conjunction with specific embodiments.

[0037] Example 1:

[0038] This embodiment proposes an on-chip network fault-tolerant system based on a fault-handling router and dual-fault-tolerant distributed routing, which is characterized by including a fault-handling router and a dual-fault-tolerant distributed routing mechanism.

[0039] (1) Reference Appendix Figure 1 ,The fault handling router includes a port allocation module, a redirection FIFO module, an error correction module, a crossbar switch module, a crossbar switch bypass module and a ,detection control module. Each module works together to achieve fault isolation and path ,reconstruction.

[0040] Specifically, refer to the attached Figure 2The port allocation module receives input data in the local, east, west, south, and north directions. The port allocation module is internally provided with a dynamic allocation strategy engine. Based on preset rules or real-time fault detection states (including link error rate and component health) sent by the total control module, the dynamic allocation strategy engine intelligently routes the input data to internal processing channels through hardware logic. When at least one direction link fault is detected, the port allocation module preferentially allocates healthy port resources to critical service data through a priority arbitration mechanism, and redirects the data of the fault link to the internal processing channel corresponding to the remaining healthy link.

[0041] Reference is made to the accompanying drawings Figure 3 The redirection FIFO module is based on an asynchronous FIFO architecture and has data caching and fault skipping functions. The redirection FIFO module temporarily stores the data output by the port allocation module through a storage queue with a depth that can be configured, so as to buffer burst traffic and match the clock domain difference between the upstream and downstream. In a fault scenario, the read pointer and the write pointer are indexed through a redirection table, the redirection table maps the sequential FIFO positions to the reconfigurable FIFO positions, the read-write counter is adjusted through hardware before the next register unit is accessed, and the skipping of the fault register unit is realized. The redirection table configuration pointer reset signal ensures that the system correctly uses the remaining healthy register to maintain the FIFO function when the number of faults increases.

[0042] The error correction module is disposed between the output end of the redirection FIFO module and the input end of the crossbar module, adopts an end-to-end forward error correction (FEC) mechanism, and realizes error detection and repair at the data link layer. The error correction module supports a configurable check algorithm (including Hamming code and cyclic redundancy check CRC-32), performs real-time checking on the input data, directly corrects single-bit errors through hardware error correction logic, and marks the fault link through a state register and triggers the downstream redirection mechanism for non-correctable multi-bit errors or continuous error events.

[0043] The crossbar module is a 5x5 bidirectional transmission channel switch matrix that supports dynamic path establishment and multicast communication based on a routing table. The crossbar module adopts a wormhole routing mechanism and realizes non-blocking data transmission through input port arbitration and output port allocation logic. The crossbar module is internally provided with a fault sensing unit (including channel parity bits) that monitors the channel health state in real time. When it is detected that the continuous error code of a channel exceeds a threshold, the bypass switching logic is automatically triggered to route the data to the crossbar bypass module.

[0044] The crossbar bypass module is a direct connection bus independent of the main switching matrix of the crossbar module, and includes special control logic. When the main channel of the crossbar module is interrupted due to hardware failure (such as transistor breakdown, interconnection open circuit) or software error (such as abnormal routing table), the crossbar bypass module directly guides the data to the target output port through a hardware priority switching mechanism, with a transmission delay consistent with the main channel and a small area overhead.

[0045] The detection supervisor module is a central management module of the fault-tolerant router, and integrates a distributed fault detection unit, a state fusion unit and a fault-tolerant coordination unit. The detection supervisor module collects the running parameters (such as bit error rate) of each module in real time through the sensor network interconnected by the network on chip, and identifies the fault mode through a finite state machine (FSM). After detecting the fault, the detection supervisor module sends an arbitration rule adjustment signal to the port allocation module, sends a fault tag and a priority signal to the redirection table of the redirection FIFO module, and starts the built-in fault detection unit to perform deep diagnosis on the suspicious components, thereby realizing fault isolation and fault-tolerant linkage.

[0046] The dual fault-tolerant distributed routing mechanism realizes fault tolerance through single fault isolation, composite fault coordination and dynamic routing adjustment, dynamically relaxes the disabled steering rules to maximize the network connectivity under the fault topology while avoiding deadlock, and solves the problems of single point failure and composite fault accumulation caused by transistor permanent failure in the network on chip.

[0047] Specifically, in the dual fault-tolerant distributed routing mechanism, the single fault isolation mechanism realizes fault isolation through the local functions of each module: the redirection FIFO module skips the fault register unit through the redirection table to maintain the storage function; the error correction module detects and corrects single-bit errors and marks uncorrectable errors; the crossbar module triggers bypass switching through the fault sensing unit, and the crossbar bypass module takes over the transmission; and the port allocation module avoids fault links by link remapping to ensure communication continuity in a single fault scenario.

[0048] In the dual fault-tolerant distributed routing mechanism, the composite fault coordination mechanism is used to handle multiple faults (such as crossbar channel failure and link failure coexisting) accumulated in the same data path: the crossbar bypass module responds to the main channel failure of the crossbar module first, and directly connects the input and output ports; at the same time, the port allocation module detects the link state in real time, redirects the data to the input port corresponding to the other healthy link, and realizes hierarchical isolation and path reconstruction of composite faults through cross-module linkage.

[0049] In the dual-fault-tolerant distributed routing mechanism, the dynamic routing adjustment mechanism is based on the real-time fault state detected by each fault-tolerant processing router of the total control module shared, and the routing table is dynamically updated through the "rule checking" mechanism: selectively relaxing the disabled steering rules in the traditional routing (such as the steering limit in the mesh topology), maximizing network connectivity while avoiding deadlock; based on local neighbor node information, it makes independent decisions without the need for central controller coordination, ensuring system performance in large-scale fault scenarios.

[0050] In the dual-fault-tolerant distributed routing mechanism, the data transmission path is: data passes through the redirection FIFO module of the source fault-tolerant processing router, error correction module encoding, crossbar module or crossbar bypass module, transmission link, port allocation module of the target fault-tolerant processing router, and finally reaches the redirection FIFO module of the target fault-tolerant processing router.

[0051] In combination with the accompanying Figure 4 Based on the fault-tolerant system on a chip network of the embodiment, instantiation is performed under specific fault scenarios, and the process is as follows:

[0052] 1. Fault scenario initialization.

[0053] In the data transmission path between the source fault-tolerant processing router and the target fault-tolerant processing router, a certain output link (marked "X") on the source fault-tolerant processing router side fails due to physical layer damage (such as metal wire breakage), and a certain intermediate component (such as a crossbar channel) in the transmission path cannot be turned on due to transistor permanent fault. Data flits need to be sent from the local port of the source fault-tolerant processing router, and after network-level rerouting and router-level component fault tolerance, they finally reach the target fault-tolerant processing router.

[0054] 2. Source fault-tolerant processing router fault perception and initial allocation.

[0055] The built-in detection and control module of the source fault-tolerant processing router detects that the north output link error rate is continuously higher than the threshold through the distributed fault detection unit, and determines that the link is faulty; the detection and control module generates a fault state vector, marks the fault position and type, and synchronizes to the port allocation module and the downstream routing module.

[0056] After the transmission data flits are input from the local port of the source fault-tolerant processing router, the port allocation module redirects the data flits to the internal processing channel corresponding to the healthy east direction link according to the fault state vector and the "critical data first" rule, bypassing the north direction fault link, and realizes the first layer of fault avoidance.

[0057] 3. Router-level component fault tolerance.

[0058] After the data piece enters the redirection FIFO module, the read-write pointer indexes the logical address through the redirection table, and if a storage unit inside the FIFO fails, the pointer automatically skips the storage unit, ensures the data to be cached in sequence, maintains the continuity of the queue, and the FIFO can still work normally even if there are a small number of faulty units.

[0059] After the data piece is output through the redirection FIFO module, it enters the error correction module, uses the CRC-32 algorithm to check the data integrity, corrects single-bit errors in real time, triggers the downstream redirection mark for uncorrectable errors, and notifies the network-level routing module to bypass the path.

[0060] Meanwhile, the detection general control module of the source fault-tolerant processing router monitors the continuous error of the parity bit of the internal cross switch channel through the distributed fault detection unit, and determines that the component is faulty. The fault sensing unit built in the cross switch module triggers the cross switch bypass module, the data piece bypasses the faulty channel, and is directly guided to the target output port through the special direct connection bus, realizes the component-level redundancy, and ensures uninterrupted data transmission.

[0061] 4. Network-level distributed routing.

[0062] After the data piece in the source fault-tolerant processing router is transmitted to the processing channel through the east direction healthy link, the input port of the next router detects potential faults of the associated link, and remaps the data piece to the input port of the west direction healthy link of the router through the greedy algorithm, so as to avoid the influence of double faults on the same path.

[0063] The detection general control modules of the source fault-tolerant processing router and the target fault-tolerant processing router dynamically adjust the routing table through a distributed communication protocol, relax the turning restriction of the traditional network topology, realize north-west turning, expand the available path set, and ensure that the data piece normally flows to the next hop in the target fault-tolerant processing router.

[0064] The whole process forms a fault-tolerant closed loop in a double-fault scenario through component-level fault tolerance and distributed routing, without the intervention of a central controller, efficiently balances fault tolerance capability and cost, and verifies the communication continuity of the system in a complex fault scenario.

[0065] As can be seen, the on-chip network fault-tolerant system based on the fault-tolerant processing router and the double fault-tolerant distributed routing can solve the single-point failure and the cumulative problem of composite faults of the on-chip network (NoC) caused by transistor permanent faults through the fault-tolerant processing router and the double fault-tolerant distributed routing mechanism.

[0066] The principles and implementation manners of the present application are described in detail by using the above specific examples, and the examples are only used to help understand the core technical content of the present application. Based on the above specific examples of the present application, any improvement and modification of the present application made by the person skilled in the art without departing from the principles of the present application shall fall within the patent protection scope of the present application.

Claims

1. A fault-tolerant network-on-chip system based on a fault-handling router and dual-fault-tolerant distributed routing, characterized in that: Includes fault-handling routers and dual-fault-tolerant distributed routing mechanisms; The fault-handling router includes a port allocation module, a redirection FIFO module, an error correction module, a crossbar switch module, a crossbar switch bypass module, and a detection control module, and each module works together to achieve fault isolation and path reconstruction; The dual-fault-tolerant distributed routing mechanism achieves fault tolerance through single fault isolation, compound fault coordination and dynamic routing adjustment, and maximizes network connectivity under fault topology while avoiding deadlock by dynamically relaxing disabled steering rules.

2. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 1, characterized in that: The port allocation module receives input data in local, east, west, south, and north directions; the port allocation module has a built-in dynamic allocation strategy engine, which intelligently routes the input data to the internal processing channel through hardware logic based on preset rules or real-time fault detection status sent by the detection master control module; When a link failure in at least one direction is detected, the port allocation module preferentially allocates healthy port resources to critical business data through a priority arbitration mechanism, and redirects data on the failed link to the internal processing channels corresponding to the remaining healthy links.

3. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 2, characterized in that: The redirection FIFO module is based on an asynchronous FIFO architecture and has data caching and fault skipping functions: The redirection FIFO module temporarily stores the data output by the port allocation module through a storage queue with configurable depth to buffer burst traffic and match the upstream and downstream clock domain differences; In a fault scenario, the read and write pointers are indexed by a redirection table that maps sequential FIFO locations to reconfigurable FIFO locations. The read and write counters are adjusted in hardware before accessing the next register cell, allowing the faulty register cell to be skipped. The redirection table configures the pointer reset signal to ensure that the system correctly uses the remaining healthy registers to maintain FIFO functionality when the number of faults increases.

4. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 3, characterized in that: The error correction module is deployed between the output of the redirection FIFO module and the input of the crossbar switch module, and adopts an end-to-end forward error correction mechanism to realize error detection and repair at the data link layer; The error correction module supports a configurable verification algorithm to perform real-time verification of input data: for single-bit errors, they are directly corrected through hardware error correction logic; for uncorrectable multi-bit errors or continuous error events, the faulty link is marked through the status register and the downstream redirection mechanism is triggered.

5. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 4, characterized in that: The crossbar switch module is a switching matrix composed of 5×5 bidirectional transmission channels, supporting dynamic path establishment and multicast communication based on routing tables; The crossbar switch module adopts a wormhole routing mechanism to achieve non-blocking data transmission through input port arbitration and output port allocation logic; The crossbar switch module has a built-in fault sensing unit that monitors the health status of the channel in real time. When it detects that the continuous bit errors in a channel exceed the threshold, it automatically triggers the bypass switching logic and routes the data to the crossbar switch bypass module.

6. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 5, characterized in that: The crossbar switch bypass module is a direct-connect bus independent of the main switch matrix of the crossbar switch module and contains dedicated control logic; When the communication of the main channel of the crossbar switch module is interrupted due to hardware failure or software error, the crossbar switch bypass module directly guides the data to the target output port through the hardware priority switching mechanism.

7. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 6, characterized in that: The detection master control module serves as the central management module of the fault-handling router, integrating a distributed fault detection unit, a state fusion unit and a fault-tolerant coordination unit; The detection master control module collects the operating parameters of each module in real time through a sensor network interconnected by an on-chip network, and performs fault mode identification through a finite state machine. After detecting a fault, the detection master control module sends an arbitration rule adjustment signal to the port allocation module, sends a fault label and priority signal to the redirection table of the redirection FIFO module, and activates the built-in fault detection unit to perform in-depth diagnosis of suspicious components, thereby realizing fault isolation and fault tolerance linkage.

8. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 7, characterized in that: In the dual-fault-tolerant distributed routing mechanism, the single fault isolation mechanism implements fault isolation through the local functions of each module: the redirection FIFO module skips the fault register unit through the redirection table to maintain the storage function; The error correction module detects and corrects single-bit errors and flags uncorrectable errors; The crossbar switch module triggers bypass switching through the fault sensing unit, and the crossbar switch bypass module takes over the transmission; the port allocation module avoids faulty links through link remapping, ensuring communication continuity in single-fault scenarios; In the dual-fault-tolerant distributed routing mechanism, a compound fault coordination mechanism is used to handle multiple faults accumulated in the same data path: the crossbar bypass module prioritizes responding to faults in the crossbar module's main channel, directly connecting the input and output ports. Simultaneously, the port allocation module monitors link status in real time and redirects data to the input ports corresponding to other healthy links. This cross-module coordination achieves hierarchical isolation and path reconstruction for compound faults. In the dual-fault-tolerant distributed routing mechanism, the dynamic routing adjustment mechanism is based on the real-time fault status shared by the master control module of each fault-handling router. The routing table is dynamically updated through a "rule-checking" mechanism. The mechanism selectively relaxes the disabled redirection rules in the routing to maximize network connectivity while avoiding deadlock. It makes independent decisions based on local neighbor node information, without the need for coordination from a central controller, ensuring system performance in large-scale failure scenarios.

9. The on-chip network fault-tolerant system based on a fault-handling router and dual fault-tolerant distributed routing according to claim 8, characterized in that: In the dual-fault-tolerant distributed routing mechanism, the data transmission path is as follows: data passes through the redirection FIFO module of the source fault-handling router, the error correction module encoding, the crossbar switch module or the crossbar switch bypass module, the transmission link, the port allocation module of the target fault-handling router, and finally reaches the redirection FIFO module of the target fault-handling router.

Images