Analog circuit hybrid fault diagnosis method and system based on MST-Transform-MMOE

Abstract

The invention provides an analog circuit hybrid fault diagnosis method based on an MST-Transform-MMOE, and the method comprises the steps: carrying out the fault feature extraction of an analog circuit through a Transform network architecture, and obtaining the features of a multi-channel time sequence response signal; performing feature enhancement and aggregation processing on the time sequence response signal features through a bidirectional long and short time memory network architecture to obtain aggregation features; and performing fault diagnosis on the aggregation features through an MMOE model constructed according to a multi-task learning mechanism and a multi-gating mechanism to obtain a diagnosis result. According to the method, the accuracy and efficiency of circuit system fault diagnosis are improved through a three-level architecture of Transform feature extraction, feature aggregation and multi-gate control expert tower cooperation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit fault diagnosis, in particular to a mixed fault diagnosis method and system for analog circuits based on MST-Transformer-MMOE. BACKGROUND

[0002] With the wide application of various electronic components in modern life, the stability and reliability of electronic components during their life cycle have become a key issue to ensure the safety of complex circuits. In complex circuits, 80% of the faults are caused by analog circuits, which account for 20%. Therefore, reducing the failure rate of analog circuits is the key to ensuring the normal operation of the circuit. According to the different fault degrees of components, the analog circuit faults are divided into soft faults and hard faults. Soft fault means that the parameter value of the component in the analog circuit deviates from the allowed tolerance range due to environmental factors (temperature, humidity and pressure), where tolerance represents the inherent error of the parameter value of the component during the processing process. Hard fault means that the analog circuit short circuit or open circuit fault caused by the deformation of the component structure or the extreme overrun of the parameter value. Hard fault can cause serious failure or complete damage of electronic equipment, resulting in catastrophic failure.

[0003] However, the traditional diagnosis method is limited by the high nonlinearity of analog circuits, component tolerance and the inseparability of mixed fault characteristics, and cannot accurately distinguish single fault from multiple fault modes, resulting in low diagnosis accuracy and poor generalization ability. Although deep learning has been applied in fault diagnosis, the existing method still has two defects: one is that the time series modeling and dynamic feature selection mechanism are not effectively fused, which is difficult to handle the local-global correlation of fault signals; the second is the lack of multi-stage decoupling design for mixed faults, which cannot overcome the classification ambiguity problem caused by feature aliasing. Therefore, it is necessary to design a mixed fault diagnosis method and system for analog circuits based on MST-Transformer-MMOE. SUMMARY

[0004] The purpose of the present application is to provide a mixed fault diagnosis method and system for analog circuits based on MST-Transformer-MMOE, which improves the accuracy and efficiency of circuit system fault diagnosis through a three-level architecture of Transformer feature extraction, feature aggregation and multi-gate expert tower cooperation.

[0005] To achieve the above purpose, the present application provides the following scheme:

[0006] A mixed fault diagnosis method for analog circuits based on MST-Transformer-MMOE, characterized in that it comprises the following steps:

[0007] The fault feature extraction is performed on the analog circuit through a Transformer network architecture to obtain multi-channel time sequence response signal features.

[0008] The feature enhancement and aggregation processing are performed on the time sequence response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features.

[0009] The fault diagnosis is performed on the aggregated features through an MMOE model constructed according to a multi-task learning mechanism and a multi-gate mechanism to obtain a diagnosis result.

[0010] Optionally, the fault feature extraction is performed on the analog circuit through a Transformer network architecture to obtain multi-channel time sequence response signal features, including:

[0011] The analog circuit is constructed and the output response of a test node is obtained.

[0012] The weight score and the embedding feature of the output response are obtained through a multi-head dynamic sparse attention mechanism.

[0013] The weight score and the embedding feature are fused through a residual connection to obtain hidden layer features.

[0014] The hidden layer features are activated through a ReLU function to obtain activated features.

[0015] The activated features are subjected to layer normalization processing to obtain time sequence response signal features.

[0016] Optionally, the feature enhancement and aggregation processing are performed on the time sequence response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features, including:

[0017] The importance of the time sequence response signal features is evaluated through a dynamic feature selection mechanism to generate a feature weight vector.

[0018] The feature weight vector is subjected to bidirectional processing through a cross-step gate mechanism, and the fused forward hidden state and backward hidden state obtained are fused to obtain bidirectional features.

[0019] The bidirectional features are pyramidally fused through a multi-level feature aggregation strategy to obtain aggregated features.

[0020] Optionally, the fault diagnosis is performed on the aggregated features through an MMOE model constructed according to a multi-task learning mechanism and a multi-gate mechanism to obtain a diagnosis result, including:

[0021] A bottom network comprising multiple spatio-temporal convolution networks is constructed.

[0022] The linear transformation is performed on the aggregated features through the bottom network to obtain mixed features.

[0023] According to the mixed features, the analog circuit is diagnosed to obtain a diagnosis result.

[0024] Optionally, the MMOE model constructed according to the multi-task learning mechanism and the multi-gate mechanism is used to diagnose the aggregated features to obtain a diagnosis result, and the method further includes: calculating a classification loss of the aggregated features and the mixed features, and constructing a multi-fault classification loss function according to the classification loss; and an expression of the multi-fault classification loss is as follows: ;

[0025] wherein, 、 and are proportional weights, 、 and respectively represent different feature quantities, is a predicted label, is a correct probability of single-fault prediction, is a correct probability of multi-fault prediction, and are hyperparameters.

[0026] An analog circuit hybrid fault diagnosis system based on MST-Transformer-MMOE includes:

[0027] A feature extraction module is configured to extract fault features of the analog circuit through a Transformer network architecture to obtain multi-channel time sequence response signal features.

[0028] A feature enhancement module is configured to enhance and aggregate the time sequence response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features.

[0029] A classification diagnosis module is configured to diagnose the aggregated features through an MMOE model constructed according to a multi-task learning mechanism and a multi-gate mechanism to obtain a diagnosis result.

[0030] According to the embodiments provided in the present application, the following technical effects are disclosed: the analog circuit hybrid fault diagnosis method based on MST-Transformer-MMOE provided in the present application includes: extracting fault features of the analog circuit through a Transformer network architecture to obtain multi-channel time sequence response signal features; enhancing and aggregating the time sequence response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features; and diagnosing the aggregated features through an MMOE model constructed according to a multi-task learning mechanism and a multi-gate mechanism to obtain a diagnosis result. The method uses a three-level architecture of Transformer feature extraction, feature aggregation, and multi-gate expert tower cooperation to improve the accuracy and efficiency of circuit system fault diagnosis. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 This is a flow chart of the analog circuit hybrid fault diagnosis method of the present invention;

[0033] Figure 2 This is a diagram showing the structure of a bidirectional long short-term memory network according to an embodiment of the present invention;

[0034] Figure 3 This is a structural diagram of an MMOE model according to an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of a four-op-amp biquadratic high-pass filter circuit according to an embodiment of the present invention;

[0036] Figure 5 It is an iteration curve diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figure 1 As shown, the present invention provides an analog circuit hybrid fault diagnosis method based on MST-Transformer-MMOE, which is characterized by comprising the following steps:

[0040] Step 100: Extract fault features from the analog circuit using the Transformer network architecture to obtain multi-channel timing response signal features;

[0041] Step 200: Perform feature enhancement and aggregation processing on the temporal response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features;

[0042] Step 300: performing fault diagnosis on the aggregated features by an MMOE model constructed according to a multi-task learning mechanism and a multi-gating mechanism to obtain a diagnosis result.

[0043] Specifically, the step of extracting fault features of the analog circuit by the Transformer network architecture includes:

[0044] After establishing a circuit simulation model by using Pspice software, 300 Monte Carlo simulation experiments are carried out for each type of fault, and the output responses of each test node are obtained. The circuit simulation model includes k excitation sources and n measurement nodes. The data set is composed of test response signals and corresponding labels, wherein the label adopts an independent vector coding mode, and each code corresponds to a specific fault type, characteristic parameter and response mode.

[0045] Then, a Transformer architecture composed of a dynamic sparse attention mechanism (DSA), a residual connection and a regularization layer, and a feedforward layer composed of a multilayer perception mechanism is constructed. Based on the multi-head dynamic sparse attention mechanism in the Transformer architecture, after the data set is input into the architecture, the query Q, key K and value V of each input signal sequence X are calculated, and the calculation formula is: wherein X is the input feature, W Q , W K and W V are weight matrices corresponding to Q, K and V respectively; for each query Q, the attention score of all keys is calculated, and only the top k keys are retained, and the calculation formula is: wherein a is a sparse rate in (0, 1), N represents the number of features, Top-k represents the top k values, and A sparse represents a sparse A matrix, and the value of DSA is calculated and taken as a weight score, which represents the correlation degree of the value of the current signal point and other parts of the input signal, and the calculation formula is: wherein represents the i-th data. The multi-head dynamic sparse attention mechanism obtains multi-head attention value MultiHead by initializing Q, K and V matrices in multiple groups, and the expression is:

[0046] ;

[0047] wherein represents a splicing vector, represents different feature heads, ​​​denotes the attention mechanism. After obtaining the sparse attention weight score through the multi-head dynamic sparse attention mechanism, the weight score and the embedding feature obtained through the multi-head dynamic sparse attention mechanism are connected in residual, to obtain the hidden layer feature, the expression is: ; wherein is the embedding feature. In addition to the DSA requiring residual connection, the feedforward layer also requires residual connection, the expression is: , wherein denotes the hidden layer feature, is the feedforward layer feature. The feedforward layer feature is projected into a larger feature space, and the rich feature information thereof is extracted by using the ReLU function, and then projected back to the original feature space, the expression is: , wherein and denote the hidden layer weight, and denote the hidden layer bias, denotes the activation function.

[0048] This embodiment also introduces multi-scale convolution in the input layer and the intermediate layer in the Transformer architecture to capture local and global features. The short-range convolution in it adopts 3x1 convolution to extract local patterns, and the long-range convolution adopts 7x1 dilated convolution with an expansion rate of 2 to expand the receptive field, the expressions are respectively: , X short is the feature extracted by the short-range convolution, and X long is the feature extracted by the long-range convolution.

[0049] Finally, the local and global features are normalized by layer to normalize them to the standard normal distribution. First, calculate the mean of the data samples on different channels , then calculate the variance of the matrix , m represents the number of samples, and then use the formula to perform layer normalization processing on a single sample, wherein and denote the small bias term, and denote the learnable weight. Finally, all normalized features are fused across scales, the expression is: .

[0050] Specifically, the embodiment performs feature enhancement and aggregation processing on the time-series response signal features through a bidirectional long short-term memory network architecture. The bidirectional long short-term memory network is composed of two independent LSTMs, a forward LSTM that processes the input sequence in time order, and a backward LSTM that processes the input sequence in reverse time order. The outputs of the two LSTM layers are merged at each time step by splicing or weighted averaging, etc., to form the final output, and the overall architecture is as shown in Figure 2 For time step , the forward LSTM hidden state and memory unit . The backward LSTM processes in reverse order from to , the hidden state and memory unit , and the forward and backward hidden states of the bidirectional LSTM output are spliced to obtain the bidirectional features, expressed as: After obtaining the spliced output, a linear layer and Softmax are used for output, and the BCE Loss is selected as the loss function.

[0051] It should be noted that the embodiment enhances the expression ability of the model by introducing dynamic feature selection and cross-step gating mechanism in the bidirectional long short-term memory network architecture. In terms of dynamic feature selection, the network automatically evaluates the importance of the input features at each time step and adjusts the weights of the features accordingly, so that the model can focus more on the features that contribute most to the current prediction task. This mechanism not only improves the model's ability to capture key information, but also reduces the interference of irrelevant features. The addition of the cross-step gating mechanism further optimizes the information flow between time steps, dynamically controls the information interaction intensity between different time steps through a learnable gating unit, so that the network can adaptively decide which time step information needs to be strengthened and which needs to be weakened, thereby more flexibly fusing the hidden state. In addition, a skip connection and a feature pyramid structure are introduced in the deep part of the network to fuse features of different time scales, thereby preserving fine-grained local information and integrating global context representation, making the model more robust when processing complex sequence patterns.

[0052] Specifically, the embodiment performs fault diagnosis on the aggregated features through the MMOE model constructed according to the multi-task learning mechanism and the multi-gating mechanism. As shown in Figure 3 , the main structure of the MMOE model includes a shared bottom expert network, a gating network, and a multi-layer perceptron (MLP). The bottom expert network is used for multiple task contributions to control the gating units of different task combinations and the task towers that output different task results, achieving fine classification or prediction tasks for different tasks. When given M tasks, the MMOE model outputs a separate output for each task All follow the corresponding specific task tower, for task , the expression of the overall model is: , wherein is expressed as a mapping function of the tower network, is a mapping expert tower network. For the expert tower network of task mixing, the expression is: , wherein is a gating network supporting task , which is composed of a linear transformation layer with a softmax layer, which takes the hidden layer features as input, and the expression is: , wherein is a learnable matrix, is the number of expert towers, is the dimension of the hidden layer feature. When the gating mechanism only selects the expert network with the highest score, the model divides the input space into multiple linear decision regions, each of which is exclusively assigned to a specific expert. Finally, the output of the MMOE model is the final fault diagnosis result.

[0053] It should be noted that the MMOE model realizes intelligent modeling of task correlation by dynamically adjusting the overlap degree of the gating network. When dealing with multiple tasks with low correlation, the model will spontaneously form a differentiated expert selection strategy: on the one hand, shared experts will gradually be weakened due to poor performance; on the other hand, the gating network of each task will optimize itself and tend to select different exclusive experts. This adaptive mechanism enables the model to flexibly adjust the parameter sharing strategy according to the actual correlation between tasks, thereby effectively decoupling when there is task conflict and maintaining necessary information sharing when there is task correlation.

[0054] Specifically, the embodiment also uses Focal Loss as the loss function in the task tower. There is a loss when obtaining the aggregated features and mixed features, and the expression of the overall multi-fault classification loss function is:

[0055] ;

[0056] , wherein , and are proportional weights, whose values are [0, 1], , and represent different feature quantities, is the predicted label, is the correct probability of single fault prediction, is the correct probability of multi-fault prediction, and These are all hyperparameters. By properly controlling the weight ratio of each task, the model can focus on different tasks and achieve an effective balance.

[0057] This embodiment also uses a four-op-amp biquadratic high-pass filter circuit as an experimental object to verify the method of the present invention. Figure 4 As shown, in this embodiment, the tolerances of the resistor and capacitor are set to 10% and 5% respectively, and the fault degree Set to 20%, the device nominal value is set to , during which the fault value is set to , then the upward deviation and downward deviation can be expressed as: and According to the sensitivity analysis, the easy-to-fail components of the four-op-amp biquadratic high-pass filter circuit are , the fault mode is set to 9 categories of single fault, 11 categories of multiple faults and normal state. The single fault category is set to the uplink deviation and downlink deviation of all components. The multiple fault category selects the difficult-to-classify multiple fault types as follows: , , , , , , , , , , The fault parameter values ​​are shown in Table 1, where SF represents a single fault and DF represents multiple faults.

[0058] Table 1 Fault parameter table

[0059] Fault code Fault class Nominal value Fault value F0 NF - - SF1 [C1↓] 5nF 4nF SF2 [C1↑] 5nF 6nF SF3 [C2↓] 5nF 4nF SF4 [C2↑] 5nF 6nF SF5 [R2↓] 3kΩ 2.4kΩ SF6 [R2↑] 3kΩ 3.6kΩ SF7 [R3↓] 2kΩ 2.4kΩ SF8 [R3↑] 2kΩ 1.6kΩ SF9 [R4↓] 4kΩ 3.2kΩ SF10 [R4↑] 4kΩ 4.8kΩ SF11 [R5↓] 4kΩ 3.2kΩ SF12 [R5↑] 4kΩ 4.8kΩ DF1 [C1↑ & R2↓] 5nF & 6.2kΩ 6nF & 4.96kΩ DF2 [C1↑ & R1↓] 5nF & 6.2kΩ 6nF & 4.96kΩ DF3 [C1↑ & R3↓] 5nF & 6.2kΩ 6nF & 4.96kΩ DF4 [C1↓ & R1↓ ] 5nF & 6.2kΩ 4nF & 4.96kΩ DF5 [C2↓ & R3↑] 5nF & 6.2kΩ 4nF & 7.44kΩ DF6 [R1↑ & R2↑] 6.2kΩ & 6.2kΩ 7.44kΩ & 7.44kΩ DF7 [R1↑ & R3↑] 6.2kΩ & 6.2kΩ 7.44kΩ & 3.2kΩ DF8 [C2↓ & R2↓ ] 5nF & 6.2kΩ 4nF & 4.96kΩ DF9 [R2↑ & R3↑] 6.2kΩ & 6.2kΩ 7.44kΩ & 7.44kΩ DF10 [R1↑ & R3↓ & C2↑] 6.2kΩ & 6.2kΩ & 5nF 7.44kΩ & 4.96kΩ & 4nF DF11 [R1↑ & R3↑ & R2↑] 6.2kΩ & 6.2kΩ & 6.2kΩ 7.44kΩ & 7.44kΩ & 7.44kΩ DF12 [R2↑ & R3↑ & C2↓] 6.2kΩ & 6.2kΩ & 5nF 7.44kΩ & 7.44Ω & 5nF

[0060] A multi-source sine wave is used as the excitation source of the circuit, with a voltage amplitude of 5V and a sampling period of 1us. A total of 1000 data points are obtained, with a total of 23 faults. Each fault is simulated 300 times in total, resulting in a total of 6900 experimental data. The training set and test set are divided into a ratio of 7:3. The number of layers of the Transformer is set to 3, the number of heads is set to 8, the hidden layer feature dimension is 128, AdamW is used as the optimizer, 50 iterations are performed, the batch size is set to 32, the dropout ratio is set to 0.1, the activation function is GeLU, and the iteration curve is as follows: Figure 5 As shown in the figure, the final diagnosis accuracy of 23 mixed faults of the four-op-amp biquadratic high-pass filter circuit is 95.65%.

[0061] The present invention also provides an analog circuit hybrid fault diagnosis system based on MST-Transformer-MMOE, comprising:

[0062] a feature extraction module configured to extract fault features of the analog circuit through a Transformer network architecture to obtain multi-channel time sequence response signal features;

[0063] a feature enhancement module configured to perform feature enhancement and dimension reduction processing on the time sequence response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features;

[0064] a classification and diagnosis module configured to perform fault diagnosis on the aggregated features through an MMOE model constructed according to a multi-task learning mechanism and a multi-gate mechanism to obtain a diagnosis result.

[0065] The beneficial effects of the present application are as follows:

[0066] 1) Through the three-stage multi-task collaborative architecture, the feature processing paths of single faults and multiple faults are separated, effectively suppressing signal superposition interference and solving the problem of mixed fault feature aliasing;

[0067] 2) A dynamic sparse attention mechanism is adopted in combination with multi-scale convolution to realize synchronous capture of local mutation and global correlation features of fault responses, thereby improving the time sequence feature extraction capability;

[0068] 3) Through a multi-gate expert tower and a Focal Loss loss function, fine differentiation of different single / multiple type faults is realized, and the diagnosis accuracy of multiple fault decoupling is greatly enhanced.

[0069] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be mutually referred to.

[0070] The principles and implementation modes of the present application are described by applying specific examples in the present application, and the above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A hybrid fault diagnosis method for analog circuits based on MST-Transformer-MMOE, characterized in that: The steps include: The fault characteristics of the analog circuit are extracted through the Transformer network architecture to obtain the timing response signal characteristics of multiple channels; Performing feature enhancement and aggregation processing on the temporal response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features; Fault diagnosis is performed on the aggregated features using an MMOE model constructed according to a multi-task learning mechanism and a multi-gating mechanism to obtain a diagnosis result.

2. The analog circuit hybrid fault diagnosis method based on MST-Transformer-MMOE according to claim 1 is characterized in that: The Transformer network architecture is used to extract fault features from analog circuits, obtaining multi-channel timing response signal features, including: constructing the simulation circuit and obtaining the output response of the test node; Obtaining weight scores and embedding features of the output responses through a multi-head dynamic sparse attention mechanism; The weight score and the embedded feature are fused through residual connection to obtain a hidden layer feature; Activating the hidden layer features through the ReLU function to obtain activation features; Perform layer normalization processing on the activation features to obtain the temporal response signal features.

3. The analog circuit hybrid fault diagnosis method based on MST-Transformer-MMOE according to claim 1 is characterized in that: The temporal response signal features are enhanced and aggregated using a bidirectional long short-term memory network architecture to obtain aggregated features, including: Performing importance evaluation on the features of the time series response signal through a dynamic feature selection mechanism to generate a feature weight vector; Bidirectionally processing the feature weight vector through a stride gating mechanism, and fusing the obtained fused forward hidden state and backward hidden state to obtain a bidirectional feature; The bidirectional features are fused in a pyramidal manner through a multi-level feature aggregation strategy to obtain aggregated features.

4. The hybrid fault diagnosis method for analog circuits based on MST-Transformer-MMOE according to claim 1, characterized in that: The MMOE model constructed based on the multi-task learning mechanism and the multi-gating mechanism is used to perform fault diagnosis on the aggregated features to obtain the following diagnostic results: Build an underlying network consisting of multiple spatiotemporal convolutional networks; Performing a linear transformation on the aggregated features through the underlying network to obtain mixed features; Fault diagnosis is performed on the analog circuit according to the mixed characteristics to obtain the diagnosis result.

5. The hybrid fault diagnosis method for analog circuits based on MST-Transformer-MMOE according to claim 4, characterized in that: The method further includes performing fault diagnosis on the aggregated features by using an MMOE model constructed according to a multi-task learning mechanism and a multi-gating mechanism to obtain a diagnosis result, and further includes: calculating the classification loss of the aggregated features and the hybrid features, and constructing a multi-fault classification loss function according to the classification loss; the expression of the multi-fault classification loss is: ; in, 、 and are proportional weights, 、 and Represents different numbers of features, is the predicted label, is the correct probability of single fault prediction, is the correct probability of multiple fault predictions, and are all hyperparameters.

6. A hybrid fault diagnosis system for analog circuits based on MST-Transformer-MMOE, characterized in that: include: The feature extraction module is used to extract fault features from analog circuits using the Transformer network architecture to obtain multi-channel timing response signal features; A feature enhancement module is used to perform feature enhancement and aggregation processing on the temporal response signal features through a bidirectional long short-term memory network architecture to obtain aggregated features; The classification diagnosis module is used to perform fault diagnosis on the aggregated features through an MMOE model constructed according to a multi-task learning mechanism and a multi-gating mechanism to obtain a diagnosis result.

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