Large signal modeling method and device of semiconductor device, storage medium and model

Abstract

The invention discloses a large signal modeling method and device of a semiconductor device, a storage medium and a model. The large signal modeling method of the semiconductor device comprises the steps that first voltage and first current of the semiconductor device are acquired, the semiconductor device comprises a first electrode and a second electrode, the first voltage is voltage between the first electrode and the second electrode, and the first current is current flowing between the first electrode and the second electrode; establishing a first simulation model corresponding to the semiconductor device; a temperature change coefficient corresponding to the semiconductor device is obtained, a compensation current value corresponding to the semiconductor device is obtained, and the temperature change coefficient and the compensation current value are parameters influencing each other; based on the first simulation model, the temperature change coefficient, the compensation current value, the first voltage and the first current, a second simulation model of the semiconductor device is established, and the second simulation model is used for simulating the voltage and current relation of the semiconductor device. The accuracy of the simulation model corresponding to the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic device model design, and particularly relates to a large-signal modeling method and device for a semiconductor device, a storage medium and a model. BACKGROUND

[0002] The GaN HEMT (GaN High Electron Mobility Transition) transistor of the semiconductor device has the advantages of wide band gap, high temperature resistance, high breakdown electric field, large two-dimensional electron gas density, large transconductance, high cutoff frequency, low noise and fast switching speed, and is widely used in the fields of integrated circuits and microwave radio frequencies. The device model of the semiconductor device is a bridge connecting the physics and the computer simulation design of the circuit, and is crucial to the integrated circuit design. The device model is converted into a model recognizable by a computer simulator through the description of the electrical characteristics of the actual physical device, can shorten the cycle of circuit design, and therefore the accuracy of the device performance predicted by the device model directly affects the accuracy of the integrated circuit design. However, the existing modeling method has the technical problem of low model accuracy. SUMMARY

[0003] The embodiments of the present application provide a large-signal modeling method, device, storage medium and model for a semiconductor device, to solve the technical problem of low model accuracy in the prior art.

[0004] In a first aspect, the embodiments of the present application provide a large-signal modeling method for a semiconductor device, comprising:

[0005] obtaining a first voltage and a first current of the semiconductor device, wherein the semiconductor device comprises a first electrode and a second electrode, the first voltage is a voltage between the first electrode and the second electrode, and the first current is a current flowing between the first electrode and the second electrode;

[0006] establishing a first simulation model corresponding to the semiconductor device;

[0007] obtaining a temperature variation coefficient corresponding to the semiconductor device, and obtaining a compensation current value corresponding to the semiconductor device, wherein the temperature variation coefficient and the compensation current value are mutually influencing parameters;

[0008] establishing a second simulation model of the semiconductor device based on the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage and the first current, wherein the second simulation model is used to simulate the voltage-current relationship of the semiconductor device.

[0009] The large-signal modeling method of the semiconductor device in the embodiment, on the basis of the first simulation model, combines the temperature variation coefficient and the compensation current value to establish a second simulation model of the semiconductor device, improves the accuracy of the second simulation model, significantly improves the prediction accuracy of the model on the semiconductor device, and through the accurate second simulation model, improves the design accuracy of the semiconductor device.

[0010] In some embodiments, the first simulation model corresponding to the semiconductor device is established, including:

[0011] An intrinsic parameter corresponding to the semiconductor device is obtained;

[0012] The first simulation model is established based on the intrinsic parameter.

[0013] In some embodiments, the second simulation model of the semiconductor device is established based on the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage and the first current, including:

[0014] A preset parameter fitting model is obtained;

[0015] The test data of the semiconductor device and the to-be-fitted parameters corresponding to the second simulation model are obtained;

[0016] The test data is input into the parameter fitting model, so that the to-be-fitted parameters are updated to the model parameters;

[0017] The second simulation model is established based on the model parameters, the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage and the first current.

[0018] In some embodiments, the temperature variation coefficient corresponding to the semiconductor device is obtained, including:

[0019] A parasitic parameter corresponding to the semiconductor device is obtained, the parasitic parameter including a first group of parameters, and the first group of parameters including a device temperature, an ambient temperature and a power dissipation value;

[0020] The device temperature, the ambient temperature and the power dissipation value are processed to obtain a thermal resistance value;

[0021] The thermal resistance value, the ambient temperature and the power dissipation value are processed to obtain the temperature variation coefficient.

[0022] In some embodiments, the parasitic parameter further includes a second group of parameters, the second group of parameters including a charge variation rate, the model parameter includes an amplitude factor, and the compensation current value corresponding to the semiconductor device is obtained, including:

[0023] The charge variation rate is processed to obtain an updated charge variation rate;

[0024] According to the amplitude factor and the updated charge variation rate, a compensation current value is determined.

[0025] In some embodiments, the model parameters further include a temperature correction factor, and the data updating process on the charge variation rate to obtain the updated charge variation rate comprises:

[0026] According to the temperature correction factor, the device temperature and the ambient temperature, the data updating process on the charge variation rate to obtain the updated charge variation rate.

[0027] In some embodiments, the large-signal modeling method of the semiconductor device further comprises:

[0028] obtaining preset voltage data;

[0029] inputting the preset voltage data into the second simulation model to obtain current data output by the second simulation model;

[0030] obtaining a data correspondence relationship between the current data and the voltage data;

[0031] determining a performance index of the semiconductor device based on the data correspondence relationship.

[0032] In some embodiments, the expression of the second simulation model is:

[0033]

[0034] wherein, I ds (t, T) is the second simulation model, I ds0 is the first simulation model, T(t) is a temperature variation coefficient, is the compensation current value, A is an amplitude factor, τ trap is the updated charge variation rate, a T is the temperature correction factor, T ref is an ambient reference temperature, and t is a time parameter.

[0035] The second aspect of the embodiments of the present application provides another large-signal modeling device of a semiconductor device, which comprises a processor and a memory, and the memory stores a computer program which, when executed by the processor, implements the steps of the large-signal modeling method of the semiconductor device in any of the above embodiments. Therefore, the large-signal modeling device of the semiconductor device has all the beneficial effects of the large-signal modeling method of the semiconductor device in any of the above embodiments, which will not be repeated here.

[0036] In a third aspect, the application provides a readable storage medium having a program or instructions stored thereon, which, when executed by a processor, implement the steps of the large-signal modeling method of the semiconductor device according to any one of the above embodiments. Therefore, the readable storage medium has all the beneficial effects of the large-signal modeling method of the semiconductor device according to any one of the above embodiments, which will not be repeated here.

[0037] In a fourth aspect, the application provides a large-signal model of a semiconductor device, which is a second simulation model determined by the large-signal modeling method of the semiconductor device according to any one of the above embodiments. Therefore, the large-signal model of the semiconductor device has all the beneficial effects of the large-signal modeling method of the semiconductor device according to any one of the above embodiments, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0039] Figure 1 A flow chart of the large-signal modeling method of the semiconductor device according to the embodiments of the application;

[0040] Figure 2 One of the schematic diagrams of the semiconductor device according to the embodiments of the application;

[0041] Figure 3 The second schematic diagram of the semiconductor device according to the embodiments of the application;

[0042] Figure 4 The third schematic diagram of the semiconductor device according to the embodiments of the application;

[0043] Figure 5 A structural block diagram of the large-signal modeling device of the semiconductor device according to the embodiments of the application;

[0044] Figure 6 A circuit diagram of the semiconductor device according to the embodiments of the application;

[0045] In the above description, the following applies: Figure 6 The correspondence between the reference signs and the component names in the above description is as follows:

[0046] 900 semiconductor device, 901 drain-source current source, 902 drain-source intrinsic capacitance, 903 gate-source intrinsic resistance, 904 gate-source charge source, 905 gate-source current source, 906 gate-drain resistance, 907 gate-drain current source, 908 gate-drain charge source, 909 gate parasitic resistance, 910 gate parasitic inductance, 911 source parasitic resistance, 912 source parasitic inductance, 913 drain parasitic resistance, 914 drain parasitic inductance, 915 gate-source parasitic capacitance, 916 gate-source parasitic resistance, 917 drain-source parasitic capacitance, 918 drain-source parasitic resistance, 919 gate trap capacitance, 920 gate trap resistance, 921 drain trap capacitance, 922 drain trap resistance, 923 ambient temperature, 924 power dissipation, 925 self-heating effect resistance, 926 self-heating effect capacitance. DETAILED DESCRIPTION

[0047] In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification will be described in detail below through the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present specification and the embodiments are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations of the technical solutions of the present specification. In the case of no conflict, the technical features in the embodiments of the present specification and the embodiments can be combined with each other.

[0048] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... " does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element. The term "two or more" includes two or more than two.

[0049] In some embodiments, as shown in FIG. 1, a large-signal modeling method of a semiconductor device is provided in the embodiments of the present application, which comprises: Figure 1

[0050] Step S101, obtaining a first voltage and a first current of a semiconductor device.

[0051] ​In this embodiment, a large-signal modeling method of a semiconductor device is provided, and a first voltage and a first current of the semiconductor device are obtained, wherein the semiconductor device comprises a first electrode and a second electrode, the first voltage is a voltage between the first electrode and the second electrode, and the first current is a current flowing between the first electrode and the second electrode.

[0052] It should be noted that the large-signal modeling method is a modeling method of a high-frequency high-power large-signal model, the high frequency can refer to a working frequency of, for example, 1 GHz or more, and the high power can refer to, for example, one hundred watts or more. Under the working condition of high frequency and high power, a large enough alternating current signal is superimposed on a fixed bias point of the semiconductor device, so that the device enters a nonlinear region and exhibits phenomena such as gain compression or signal distortion. At this time, the alternating current signal can be referred to as a large signal.

[0053] Exemplarily, the semiconductor device can be a GaN HEMT transistor.

[0054] Exemplarily, the first electrode can be a drain electrode, the second electrode can be a source electrode, the first voltage can be a drain-source voltage, and the first current can be a drain-source current.

[0055] Step S102, a first simulation model corresponding to the semiconductor device is established.

[0056] The first simulation model corresponding to the semiconductor device is established, wherein the first simulation model is a preset large-signal current model.

[0057] Exemplarily, the first simulation model can be a preset mathematical model.

[0058] Exemplarily, the first simulation model can be a static drain-source current model.

[0059] Step S103, a temperature variation coefficient corresponding to the semiconductor device is obtained, and a compensation current value corresponding to the semiconductor device is obtained.

[0060] The temperature variation coefficient and the compensation current value corresponding to the semiconductor device are obtained respectively, wherein the temperature variation coefficient is used to represent the relationship between the power and the temperature of the semiconductor device, and the compensation current value is used to compensate the current of the semiconductor device.

[0061] Exemplarily, the compensation current value is used to compensate the phenomenon of output current decrease caused by trap effect.

[0062] The temperature variation coefficient and the compensation current value are mutually influenced parameters, the temperature variation coefficient can affect the numerical value of the compensation current value, and the compensation current value can also affect the temperature variation coefficient.

[0063] Exemplarily, the temperature variation coefficient can be a self-heating effect influence coefficient.

[0064] Exemplarily, the compensation current value can be a value of the influence of the trap effect.

[0065] In step S104, a second simulation model of the semiconductor device is established based on the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage and the first current.

[0066] In step S104, a second simulation model of the semiconductor device is established based on the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage and the first current.

[0067] It should be noted that, by considering the interaction between the temperature variation coefficient and the compensation current value, the second simulation model can offset the influence of the interaction of the self-heating effect and the trap effect on the device, and thus can more accurately predict the dynamic behavior of the semiconductor device under high frequency and high power conditions. Therefore, the second simulation model has the advantages of high accuracy, etc.

[0068] The large signal modeling method of the semiconductor device in this embodiment, on the basis of the first simulation model, combines the temperature variation coefficient and the compensation current value and considers the interaction therebetween, establishes a second simulation model of the semiconductor device, improves the accuracy of the second simulation model, significantly improves the prediction accuracy of the model for the semiconductor device, and improves the design accuracy for the semiconductor device through the accurate second simulation model.

[0069] In some embodiments, a large signal modeling method of a semiconductor device is provided in the embodiments of the present application, and a first simulation model corresponding to the semiconductor device is established, including:

[0070] In step S201, intrinsic parameters corresponding to the semiconductor device are obtained.

[0071] In step S202, the first simulation model is established based on the intrinsic parameters.

[0072] In this embodiment, the semiconductor device is detected for parameters during the operation of the semiconductor device to obtain intrinsic parameters of the semiconductor device, and the first simulation model is established based on the intrinsic parameters, wherein the intrinsic parameters are parameters representing inherent properties of the semiconductor device.

[0073] Exemplarily, the extraction step of the intrinsic parameters includes: extracting device small signal S parameters using TRL de-embedding technology, such as the small signal parameters S 11 , S 12 , S 21 , S 22The test can be carried out at as large a static current as possible, for example at 200 mA and above. First, the small signal S parameters of the device are measured, and the S parameters need to be converted into Y parameters, which can be converted by using a known parameter conversion formula, and therefore will not be described in detail. The parameter conversion formula can be:

[0074]

[0075] wherein Z0 is a characteristic impedance, usually 50 Ω, Y 11 , Y 21 , Y 12 , Y 22 is a parameter to be obtained, S 11 , S 12 , S 21 , S 22 is a small signal parameter.

[0076] The Y parameters obtained here are total Y parameters, and therefore a known de-embedding method is used to remove the parasitic parameters of the semiconductor device (such as the parameters of the circuit board, device package, attenuator, etc.) to obtain the intrinsic y parameters of the device, denoted by a lowercase y. Based on the obtained intrinsic y parameters, the intrinsic parameters are extracted: gate-drain resistance R gd , drain-source intrinsic capacitance C ds , gate-source parasitic resistance R gs , gate-source charge Q gs , gate-drain charge Q gd , gate parasitic resistance R g , gate parasitic inductance L g , source parasitic resistance R s , source parasitic inductance L s , drain parasitic resistance R d , drain parasitic inductance L d , gate-source parasitic capacitance C gs , drain-source parasitic capacitance C ds , drain-source parasitic resistance R ds The intrinsic parameters can be calculated by using the following formula, and the specific calculation formula is as follows:

[0077] R gd = (1 / ω 2 C gd 2 ) x Re (y 12 ) ;

[0078] C ds = (1 / ω) x Im (y 22 +y 12 ) ;

[0079] R gs = (1 / ω 2C gs 2 )×Re(y 11 +y 12 );

[0080] Q gs =(1 / ω)×lm(y 11 );

[0081] Q gd =(1 / ω)×lm(y 12 );

[0082] L g =(1 / ω)×lm(y 11 );

[0083] L d =(1 / ω)×lm(y 12 +y 22 );

[0084] L s =(1 / ω)×lm(y 22 );

[0085] R s =Re(y 11 );

[0086] R g =Re(y 11 +y 12 );

[0087] R d =Re(y 22 );

[0088] R ds =Re(y 22 +y 12 );

[0089] C gs =(1 / ω)×lm(y 11 +y 12 );

[0090] wherein the y-parameters and the Y-parameters are complex numbers, ω is a parameter selected according to the debugging results of the semiconductor device, Re denotes the real part of a complex number, Im denotes the imaginary part of a complex number, C gd denotes the gate-drain capacitance.

[0091] Exemplarily, the first analog model can be:

[0092] I ds0 =I pk (1+tanh(Φ))(1+λV ds )tanh(αVds );

[0093] wherein, I ds0 represents a first simulation model, I pk is a peak value of the first current, V ds is a first voltage, Φ is a nonlinear factor corresponding to the first voltage, λ is a current compression parameter, used to describe a nonlinear change of the first current with the first voltage, especially a current compression effect in a saturation region, α is a modulation coefficient of the first voltage, i.e., a modulation coefficient of a drain-source voltage, reflecting a degree of current hysteresis, and tanh is a trigonometric function.

[0094] In some embodiments, a large-signal modeling method of a semiconductor device is provided in the embodiments of the present application, and a second simulation model of the semiconductor device is established based on a first simulation model, a temperature variation coefficient, a compensation current value, a first voltage, and a first current, including:

[0095] In step S301, a preset parameter fitting model is obtained.

[0096] In this embodiment, the preset parameter fitting model is obtained, wherein the parameter fitting model is used to calculate an algorithm model including a fitting parameter.

[0097] For example, the parameter fitting model can include a particle swarm algorithm, a genetic algorithm, a simulated annealing algorithm, a Newton-Raphson method, or a Bayesian optimization algorithm.

[0098] In step S302, a fitting parameter corresponding to the second simulation model and test data of the semiconductor device are obtained.

[0099] The fitting parameter corresponding to the second simulation model and the test data of the semiconductor device are obtained, wherein the fitting parameter is a parameter that needs to be fitted in the second simulation model, and the test data is data obtained by testing the semiconductor device.

[0100] For example, the test data can include voltage data and current data obtained by performance testing of the semiconductor device.

[0101] For example, the fitting parameter specifically includes: a current compression parameter (λ) that needs to be fitted, used to describe a nonlinear change of a drain-source current with a drain-source voltage, especially a current compression effect in a saturation region; a trap effect amplitude factor (A) that needs to be fitted, used to represent an influence degree of a trap effect on current hysteresis; a drain-source voltage modulation coefficient (α) that needs to be fitted, reflecting a degree of current hysteresis; a drain-source voltage nonlinear factor (Φ) that needs to be fitted, describing nonlinearity under a large signal; and a temperature correction factor (α T ) that needs to be fitted, used to represent an influence degree of a self-heating effect model on current hysteresis.

[0102] Step S303: input the test data into the parameter fitting model so that the parameters to be fitted are updated to the model parameters.

[0103] The test data is input into the parameter fitting model to update the data of the parameters to be fitted, thereby obtaining the model parameters, wherein the model parameters are the parameters constituting the fitted model.

[0104] For example, the model parameters include: the current compression parameter (λ) after fitting, the trap effect amplitude factor (A) after fitting, the drain-source voltage modulation coefficient (α) after fitting, the drain-source voltage nonlinear factor (Φ) after fitting, the temperature correction factor (α) after fitting T ).

[0105] Step S304 : establishing a second simulation model based on the model parameters, the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage, and the first current.

[0106] A second simulation model is established according to the model parameters, the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage, and the first current.

[0107] Exemplarily, the parameter fitting model includes a particle swarm algorithm. First, the initial parameters of the algorithm are set (such as speed, position, learning factor, inertia weight, etc.), the first generation of particle swarms are randomly initialized, and a fitness function is constructed. During iteration, particles can update themselves by tracking the optimal solution they are currently looking for (individual optimal) and the optimal solution currently found by the population (global optimal). In each iteration, the particle must first update its own speed according to its own speed before the iteration, the distance to the individual optimal solution, and the distance to the global optimal solution. Then, according to the current speed and the position before the iteration, the position after the iteration is repositioned to complete the continuous iteration of the particle position. All required parameter fitting work is performed by this method. The fitness function is constructed based on the variance of the measured value and the predicted value, where the measured value is the measured value of the parameter and the predicted value is the predicted value of the parameter. Speed ​​update and position update adopt v i t+1 =ω×ν i t +c1(Pb i -x i t )+c2(Gb-x i t ) and x i t+1 =x i t +ν i t+1. Here, ω is an inertial weight used to control the inertia of the particle's velocity at the previous time, and is usually set to a value between 0.5 and 1; c1 and c2 are learning factors that control the velocity of the particle towards the local optimum and the global optimum. The variance of the simulation results and the measured results is taken as the evaluation standard to construct the fitness function, and the fitness function is:

[0108]

[0109] where θ represents the set of all parameters to be optimized in the model; N is the total number of data points; I ds,meas and I ds,pred respectively represent the actual measured current and the model predicted current of the i-th data point; P ds,meas and P ds,pred respectively represent the actual measured output power and the model predicted output power of the i-th data point; ω1 and ω2 are weight parameters.

[0110] In some embodiments, a large-signal modeling method of a semiconductor device is provided in the embodiments of the present application, and a temperature variation coefficient corresponding to the semiconductor device is obtained, including:

[0111] In step S401, a parasitic parameter corresponding to the semiconductor device is obtained, and the parasitic parameter includes a first group of parameters, and the first group of parameters includes a device temperature, an ambient temperature, and a power dissipation value.

[0112] In step S402, data processing is performed on the device temperature, the ambient temperature, and the power dissipation value to obtain a thermal resistance value.

[0113] In step S403, data processing is performed on the thermal resistance value, the ambient temperature, and the power dissipation value to obtain a temperature variation coefficient.

[0114] In this embodiment, the parasitic parameter corresponding to the semiconductor device is obtained, wherein the parasitic parameter refers to a parameter generated in a circuit due to the non-ideal characteristics of the device.

[0115] The parasitic parameter includes a first group of parameters, and the first group of parameters is a parameter corresponding to self-heating effect, and the first group of parameters includes a device temperature, an ambient temperature, and a power dissipation value, wherein the device temperature represents the self-temperature of the semiconductor device, the ambient temperature is a reference temperature of the environment in which the semiconductor device is located, and the power dissipation value is a power value consumed by the semiconductor device.

[0116] Exemplarily, during the operation of the semiconductor device, temperature detection is performed on the semiconductor device to obtain the device temperature and the ambient temperature corresponding to the semiconductor device.

[0117] Exemplarily, the semiconductor device includes a self-heating effect sub-circuit and a trap effect sub-circuit, and the extraction of the parasitic parameter can be divided into two parts of the self-heating effect sub-circuit and the trap effect sub-circuit.

[0118] For the self-heating effect sub-circuit, a measuring device is used to measure the device temperature T, the ambient temperature T amb and the dissipated power P diss , the self-heating effect resistance R th (referred to as thermal resistance) is calculated using the formula R amb = (T-T diss ) / P th , and the self-heating effect capacitance C th (referred to as thermal capacitance) is calculated using the formula C heat = ΔQ th / ΔT.

[0119] It should be noted that the thermal capacitance C th and the thermal resistance R th in the parasitic parameters are related to the temperature variation coefficient, and the thermal capacitance C th and the thermal resistance R th in the parasitic parameters describe the thermal characteristics of the device. These two parameters are directly related to the dynamic changes of the dissipated power P diss and the junction temperature. By measuring the parasitic parameters, the influence of the self-heating effect of the device on the temperature variation of the device can be expressed.

[0120] The device temperature, the ambient temperature, and the power dissipation value are subjected to data processing to obtain the thermal resistance value, wherein the power dissipation value is the power value consumed by the semiconductor device, and the thermal resistance value is the thermal resistance of the semiconductor device.

[0121] Exemplarily, the calculation formula of the thermal resistance value R th is as follows:

[0122] R th = (T-T amb ) / P diss ;

[0123] wherein T is the device temperature, T amb is the ambient temperature, and P diss is the power dissipation value.

[0124] The thermal resistance value, the ambient temperature, and the power dissipation value are subjected to data processing to obtain the temperature variation coefficient.

[0125] Exemplarily, the calculation formula of the temperature variation coefficient T(t) is as follows:

[0126]

[0127] wherein T ref is the ambient temperature, R th is the thermal resistance value, P diss is the power dissipation value, and τ th is the thermal time constant, τth = R th x C th , C th and R th are the heat capacity and thermal resistance in the parasitic parameters.

[0128] In some embodiments, a large-signal modeling method of a semiconductor device is provided in the embodiments of the present application, and a compensation current value corresponding to the semiconductor device is obtained, including:

[0129] In step S501, a charge change rate corresponding to the semiconductor device is obtained.

[0130] In step S502, data updating processing is performed on the charge change rate to obtain an updated charge change rate.

[0131] In step S503, a compensation current value is determined according to an amplitude factor and the updated charge change rate.

[0132] In this embodiment, parasitic parameters corresponding to the semiconductor device are obtained, wherein the parasitic parameters further include a second group of parameters, the second group of parameters being parameters corresponding to trap effect, and the second group of parameters including the charge change rate. In addition, the model parameters include an amplitude factor, wherein the amplitude factor is a trap effect amplitude factor, used to represent the influence degree of the trap effect on current hysteresis, and the charge change rate represents the capture and release rate of the charge.

[0133] Exemplarily, the amplitude factor is a key parameter in the trap effect model, used to describe the amplitude of the influence of the trap effect on the current hysteresis.

[0134] Exemplarily, the semiconductor device includes two parts of self-heating effect sub-circuit and trap effect sub-circuit, and the extraction of the parasitic parameters can be divided into two parts of the self-heating effect sub-circuit and the trap effect sub-circuit.

[0135] For the trap effect sub-circuit, the capacitance change of the device under different bias states is obtained through a capacitance voltage measurement device, for example, an LCR meter can be selected to measure the capacitance value under different gate voltages and drain voltages, to obtain the curve of the capacitance change with the voltage under different gate voltages and drain voltages, combined with the intrinsic parameters C gs , C ds , C gd , R g , R s , R d , a suitable model is selected to fit the capacitance voltage curve to finally obtain the trap capacitance C trap , which will not be described here.

[0136] The pulse IV test is used to obtain the trap resistance R trap, the self-heating effect can be removed by using the pulse IV test. A short pulse voltage is applied to the device, and the time constant of the current recovery is recorded. The dynamic effect of the trap effect on the corresponding device is analyzed. By applying a pulse gate-source voltage, the current of the gate and the drain is recorded as a function of time. After the pulse is turned off, the recovery curve of the current is observed. These recovery characteristics directly reflect the capture and release process of the trap charge, thereby providing dynamic information related to the trap effect. By the recovery curve of the current after the pulse is turned off, the time constant τ of the trap effect is extracted, and C trap trap trap and C trap extracted from the above are used to extract the trap resistance.

[0137] It should be noted that the trap resistance R trap and the trap capacitance C trap in the parasitic parameters are related to the compensation current value. Similarly, in the trap effect model, the trap resistance R trap and the trap capacitance C trap describe the dynamic characteristics of charge capture and release. These two parameters are directly related to current hysteresis and collapse. By measuring the parasitic parameters, the dynamic effect of the trap effect on the current can be expressed.

[0138] The charge change rate is updated to obtain an updated charge change rate.

[0139] Exemplarily, the updated charge change rate can be the charge change rate corresponding to the trap effect model.

[0140] The amplitude factor and the updated charge change rate are processed to determine the compensation current value.

[0141] Exemplarily, the calculation formula of the compensation current value is:

[0142]

[0143] where A is the amplitude factor, τ trap is the updated charge change rate, and ΔI trap (t) is the compensation current value.

[0144] In some embodiments, a large-signal modeling method of a semiconductor device is provided in the embodiments of the present application. The charge change rate corresponding to the semiconductor device is obtained, including:

[0145] Step S601, according to the temperature correction factor, the device temperature and the environmental temperature, the charge change rate is updated to obtain an updated charge change rate.

[0146] ​​In this embodiment, the parasitic parameters further include a device temperature and an ambient temperature, and the model parameters further include a temperature correction factor, wherein the temperature correction factor is used to represent a degree of influence of a self-heating effect model on current hysteresis.

[0147] Exemplarily, during the operation of the semiconductor device, the temperature of the semiconductor device is detected to obtain the device temperature and the ambient temperature of the semiconductor device.

[0148] According to the temperature correction factor, the device temperature and the ambient temperature, the data updating processing is performed on the charge change rate to obtain an updated charge change rate.

[0149] Exemplarily, the updated compensation current value τ trap is calculated according to the following formula:

[0150] τ trap = τ0× (1+ α T (T-T ref ));

[0151] wherein τ0 is an initial compensation current value, α T is the temperature correction factor, T is the device temperature, T amb is the ambient reference temperature. It should be noted that semiconductor devices of different materials have different initial charge change rates, and the initial charge change rates of semiconductor devices of different materials can also be determined through short pulse testing.

[0152] In some embodiments, the embodiments of the present application provide a large signal modeling method of a semiconductor device, and the large signal modeling method of the semiconductor device further includes:

[0153] In step S701, preset voltage data is obtained.

[0154] In step S702, the preset voltage data is input into a second simulation model to obtain current data output by the second simulation model.

[0155] In step S703, a data correspondence relationship between the current data and the voltage data is obtained.

[0156] In step S704, a performance index of the semiconductor device is determined based on the data correspondence relationship.

[0157] In this embodiment, the preset voltage data is obtained, and the preset voltage data is input into the second simulation model to obtain the current data output by the second simulation model, wherein the voltage data is the input voltage of the second simulation model, and the current data is the output current of the second simulation model.

[0158] Obtaining a data correspondence between the current data and the voltage data, wherein the data correspondence is a correspondence between the current data and the voltage data.

[0159] Based on the data correspondence, determining a performance index of the semiconductor device, wherein the performance index represents a performance level of the semiconductor device.

[0160] In some embodiments, a large-signal modeling method of a semiconductor device is provided in the embodiments of the present application, and an expression of a second simulation model is:

[0161]

[0162] wherein I ds (t,T) is a second simulation model, I ds0 is a first simulation model, is a compensation current value, A is an amplitude factor, τ trap is an updated charge change rate, α T is a temperature correction factor, T(t) is a temperature change coefficient, T ref is an environmental reference temperature, and t is a time parameter.

[0163] It should be noted that the self-heating effect causes the device temperature to rise, and the temperature affects the release speed of the charge in the trap. The temperature rise reduces the time constant τ trap of the charge release related to the trap effect, the release speed of the charge becomes faster, the influence of the trap effect on the device is weakened, and considering that the self-heating effect directly affects the size of the current, a temperature correction term needs to be added to the above self-heating effect model, and α T (T-T ref ) is obtained, α T (T-T ref ) is a temperature correction term, and the temperature correction term with the temperature change coefficient as a variable can correct the temperature change coefficient. In addition, considering the actual physical behavior of the device: as the temperature rises, the current gradually decreases rather than increases, and when the temperature rises, the influence of the trap effect is weakened, the current hysteresis is reduced, but at the same time the overall drain-source current will decrease, in order to more effectively describe, the self-heating effect model is further modified, and a linear term can be used to represent: (1-α T (T-T ref )).

[0164] Because of the significant interaction between self-heating effect and trapping effect. For example, when the temperature rises, the time constant of the trapping effect decreases, causing the trapped charges to be released faster, thus reducing the current hysteresis phenomenon. On the other hand, the hysteresis effect of the trapping effect itself also causes the thermal effect of the device to be amplified. Because when the trapping effect is significant, the current collapse causes the change of power dissipation, which indirectly intensifies the influence of self-heating effect, thereby further increasing the temperature. Therefore, in order to reflect the mutual interaction of self-heating effect and trapping effect, the above two models are multiplied in the manner, indicating that the two effects exist synergistically when determining the final result. Because the two main nonlinear factors of self-heating effect and trapping effect are interdependent, rather than simply independent effects, the effects of these factors on the system cannot be simply linearly superimposed. Therefore, in order to reflect the mutual coupling between them, since multiplication can capture the complex effects of the simultaneous occurrence of the two and the nonlinear behavior between the two, multiplying the two effects can more accurately represent the proportional or dependent relationship between them. In summary, combined with the static drain-source current model, the following formula is obtained:

[0165]

[0166] wherein I ds (t,T) is a second simulation model, I ds0 is a first simulation model, T(t) is a temperature change coefficient, is a compensation current value, A is an amplitude factor, τ trap is an updated charge change rate, a T is a temperature correction factor, T ref is an environmental reference temperature, and t is a time parameter.

[0167] Because the model takes into account the effects of the interaction between self-heating effect and trapping effect on the device, it can more accurately predict the dynamic behavior of GaN HEMT devices under high-frequency, high-power conditions. The feedback mechanism accurately describes the coupling relationship between self-heating effect and trapping effect under large signal conditions. Figure 2 Fig. 4 shows the measured (circles) and simulated (solid line) current-voltage relationship of the first simulation model, with the horizontal axis representing voltage data in volts and the vertical axis representing current data in amperes, Figure 3 Fig. 5 shows the measured (circles) and simulated (solid line) current-voltage relationship of the second simulation model, with the horizontal axis representing voltage data in volts and the vertical axis representing current data in amperes. The embodiment can better represent the current hysteresis and current collapse phenomenon, significantly improving the prediction accuracy of the model. Not only does it improve the performance prediction and design guidance capability of the device, but it also provides a more accurate reference for the design of radio frequency power amplifiers.

[0168] Exemplarily,Figure 2 、 Figure 3 and Figure 4 The simulation results of three different large signal models are shown, by comparing the differences between the simulation values and the actual measured values, the influence of self-heating effect and trap effect on the relationship between drain-source current (I ds ) and drain-source voltage (V ds ) of GaN HEMT device is comprehensively analyzed, and then the innovation and superiority of the second simulation model established in the embodiment are revealed.

[0169] Exemplarily, Figure 2 corresponding to the model without considering any effect, Figure 2 the solid line in the figure represents the simulation result of the traditional large signal model, which does not consider self-heating effect and trap effect. The following characteristics and deficiencies can be observed from the figure:

[0170] First, the deviation between simulation and measurement: in the low voltage range (V ds <5V), Figure 2 the solid line simulation result in the figure is basically consistent with the actual measured value. As V ds increases (especially when V ds >10V), Figure 2 the solid line prediction value in the figure is significantly higher than the measured value, indicating that the model fails to accurately capture the drain-source current decay phenomenon under high power conditions.

[0171] Second, the dynamic behavior description is insufficient: in the high voltage range (V ds >20V), the downward trend of the drain-source current is ignored in the simulation result. This is mainly due to the fact that the model does not consider the self-heating effect and trap effect caused by power dissipation.

[0172] Exemplarily, Figure 3 corresponding to the model considering self-heating effect, Figure 3 the solid line in the figure represents the simulation result of the improved model considering only self-heating effect. Compared with Figure 2 , the accuracy of the model under high power conditions is significantly improved, which is specifically manifested as follows:

[0173] Improved fitting between simulation and measurement: in the range of V ds >10V, Figure 3 the prediction result of the solid line in the figure is closer to the actual measured value than the solid line in Figure 2 . In the high voltage (V ds >30V) range, the decay trend of the drain-source current is well captured, but the dynamic change of the measured value is still not fully reproduced.

[0174] Exemplarily, Figure 4 corresponding to the model considering both self-heating effect and trap effect, Figure 4The solid line in represents the second simulation model created in this embodiment. By introducing the coupling mechanism of self-heating effect and trap effect, the simulation accuracy and dynamic behavior description capability are significantly improved. Specifically,

[0175] High consistency between simulation and measurement: ds Within the range, Figure 4 The simulation results of the solid line are significantly better than the measured values ​​of the first two models. Especially in the high power range (V ds >20V), Figure 4 The solid line in the middle can accurately describe the rapid decay and dynamic hysteresis of the drain-source current.

[0176] In summary, through Figure 2 、 Figure 3 and Figure 4 The comparative analysis shows clearly that Figure 2 The solid line model cannot accurately capture the dynamic behavior under high power conditions; Figure 3 The solid line model is improved after considering the self-heating effect, but it is still not enough to fully characterize the device performance. Figure 4 By introducing the coupling mechanism of self-heating effect and trap effect, the solid line model not only improves the simulation accuracy, but also significantly enhances the ability to describe dynamic behavior, providing a more accurate theoretical basis for RF power amplifier design.

[0177] In some embodiments, as Figure 5 As shown, a large-signal modeling apparatus 800 for a semiconductor device is provided. The large-signal modeling apparatus 800 includes a processor 802 and a memory 804. Memory 804 stores a computer program that, when executed by processor 802, implements the steps of the large-signal modeling method for a semiconductor device described in any of the aforementioned embodiments. Therefore, the large-signal modeling apparatus 800 for a semiconductor device has all the advantages of the large-signal modeling method for a semiconductor device described in any of the aforementioned embodiments, and no further details are given here.

[0178] In some embodiments, a readable storage medium is provided on which a program is stored. When the program is executed by a processor, the steps of the large-signal modeling method for semiconductor devices in any of the above embodiments are implemented, thereby having all the beneficial technical effects of the large-signal modeling method for semiconductor devices in any of the above embodiments.

[0179] In some embodiments, a semiconductor device is provided, comprising: a large-signal modeling device of a semiconductor device as in any of the above embodiments, and / or a readable storage medium as in any of the above embodiments, and thus having all the beneficial technical effects of the large-signal modeling device of a semiconductor device in any of the above embodiments, and / or the readable storage medium in any of the above embodiments, which will not be elaborated upon here.

[0180] Exemplarily, as shown in the small signal equivalent circuit, the large signal equivalent circuit adds the equivalent circuit representation of the trap effect and the self-heating effect. Figure 6

[0181] Among them, the semiconductor device 900 can be a GaN HEMT device, the trap effect refers to the existence of buffer layer and surface state trap in the GaN HEMT device, these traps will capture and release free carriers, resulting in current hysteresis and collapse phenomenon, especially under large signal conditions; the self-heating effect refers to the junction temperature rise due to power dissipation when the device is running at high power, the temperature rise further affects the carrier mobility, device current and output power. In order to accurately describe the performance of the device under large signal test conditions, therefore, the establishment of the model needs to consider the self-heating effect and the trap effect. Therefore, this model is based on the small signal equivalent circuit of GaN HEMT device, considering the parasitic effect and the electrical characteristics of the device itself, the model contains the modeling part of parasitic inductance, resistance, parasitic capacitance, self-heating effect and trap effect, the structure is very complex and comprehensive.

[0182] ​The large-signal equivalent circuit is mainly divided into two parts: intrinsic unit and parasitic unit. The intrinsic unit includes drain-source current source 901, drain-source intrinsic capacitor 902, gate-source intrinsic resistor 903, gate-source charge source 904, gate-source current source 905, gate-drain resistor 906, gate-drain current source 907, and gate-drain charge source 908. The drain-source current source 901 is connected in parallel with the drain-source intrinsic capacitor 902; the gate-source intrinsic resistor 903 and the gate-source charge source 904 are connected in series and then connected in parallel with the gate-source current source 905; the gate-drain resistor 906 and the gate-drain charge source 908 are connected in series and then connected in parallel with the gate-drain current source 907, and then the three are connected in parallel. The parasitic unit includes gate parasitic resistor 909, gate parasitic inductor 910, source parasitic resistor 911, source parasitic inductor 912, drain parasitic resistor 913, drain parasitic inductor 914, gate-source parasitic capacitor 915, gate-source parasitic resistor 916, drain-source parasitic capacitor 917, and drain-source parasitic resistor 918. In the above structure, the gate parasitic resistor 909 and the gate parasitic inductor 910 are connected in series to connect the gate; the source parasitic resistor 911 and the source parasitic inductor 912 are connected in series to connect the source; the drain parasitic resistor 913 and the drain parasitic inductor 914 are connected in series to connect the drain; the gate-source parasitic capacitor 915, the gate-source parasitic resistor 916, the drain-source parasitic capacitor 917, and the drain-source parasitic resistor 918 are connected in series to connect the gate-source and the drain-source, respectively. It can be seen that the model uses a charge source for description instead of a parasitic capacitor, because the charge representation can more accurately capture the nonlinear dynamic characteristics of the device under large signal and high frequency conditions. Under large signal and high frequency conditions, the parasitic effects and intrinsic characteristics of semiconductor devices exhibit strong nonlinearity. This nonlinear characteristic not only affects the current and voltage characteristics of the device, but also affects the performance of the parasitic parameters such as capacitance and inductance. Using charge representation, these nonlinear changes can be better captured, especially under large signal conditions, the change of charge more directly reflects the dynamic behavior of the device because the charge is directly related to the current change and voltage change. In the traditional parasitic capacitor representation, the capacitance value is obtained by measuring under static or low frequency conditions. When using the charge representation, the parameters are more dependent on dynamic testing, especially techniques such as pulse IV testing, which can more accurately reflect the nonlinear behavior under large signal and high frequency conditions. In addition, the charge representation model often needs to combine more dynamic characteristic parameters, such as current hysteresis, charge capture and release time constant, etc., which are difficult to accurately capture in the parasitic capacitor representation.

[0183] In addition to the parasitic sub-circuit, there are also trap effect sub-circuit and self-heating effect sub-circuit. The gate trap effect sub-circuit (left side) includes a gate trap capacitor 919 and a gate trap resistor 920 connected in series, and the gate trap capacitor 919 and the gate trap resistor 920 are connected in parallel with the three branches in parallel in the intrinsic sub-circuit, and are connected in series with the gate side part of the parasitic sub-circuit. The drain trap effect sub-circuit (right side) includes a drain trap capacitor 921 and a drain trap resistor 922 connected in series, and the drain trap capacitor 921 and the drain trap resistor 922 are connected in parallel with the three branches in parallel in the intrinsic sub-circuit, and are connected in series with the drain side part of the parasitic sub-circuit.

[0184] The self-heating effect sub-circuit includes an ambient temperature 923 and a power dissipation 924 connected in series, and a self-heating effect resistor 925 and a self-heating effect capacitor 926 connected in parallel. The ambient temperature 923 and the power dissipation 924 connected in series are connected in parallel with the self-heating effect resistor 925 and the self-heating effect capacitor 926, respectively. The physical location of the self-heating effect sub-circuit is arbitrary in theory, as long as the location of the self-heating effect sub-circuit does not affect the layout of the circuit diagram. The trap effect sub-circuit represents the trap effect of the gate and the drain through the trap capacitor and the trap resistor in series, respectively, simulating the hysteresis effect of the capture and release of gate charge on gate current and the effect of the capture and release of drain charge on drain-source current. The self-heating effect sub-circuit describes the self-heating effect caused by the power dissipation 924, simulates how the junction temperature rise is fed back to the current source, affecting the size of the drain-source current Ids. The circuit includes a thermal resistance and a thermal capacitance connected in parallel, the ambient temperature 923 refers to the temperature of the external environment, which is usually used as a reference temperature for calculating the rise of junction temperature. The self-heating effect sub-circuit reflects the self-heating behavior of the device by monitoring the temperature rise of the device during operation. The power dissipation 924 refers to the power consumed by the device during operation, which will be converted into heat, thereby causing the junction temperature to rise. The existence of the power dissipation 924 is crucial in the modeling of self-heating effect, so it needs to be included in the model. Since the self-heating effect is a temperature T dependent function, it is represented separately in the thermal effect circuit.

[0185] In some embodiments, a large signal model of a semiconductor device is provided, which is a second simulation model determined by the large signal modeling method of the semiconductor device in any of the above embodiments. Therefore, the large signal model of the semiconductor device has all the beneficial effects of the large signal modeling method of the semiconductor device in any of the above embodiments, which will not be repeated here.

[0186] In this embodiment, the expression of the large signal model is:

[0187]

[0188] where I ds (t,T) is a large signal model, I ds0T(t) is a temperature change coefficient for a first simulation model, Icomp is a compensation current value, A is an amplitude factor, τ trap Q is an updated charge change rate, a T T is a temperature correction factor, T ref T is an ambient reference temperature, t is a time parameter.

[0189] It should be noted that the descriptions of the various embodiments are each given with emphasis on different aspects. Those skilled in the art will readily understand that the descriptions of the various embodiments given in the context of one embodiment can be applied to the other embodiments.

[0190] Those skilled in the art will understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-readable storage media (including, but not limited to, disk memory, CD-ROMs, optical storage media, etc.) embodying computer readable program code.

[0191] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowcharts and / or block diagrams block or blocks. Figure 1 one or more flows and / or blocks Figure 1 means for carrying out the function specified by the block or blocks.

[0192] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions means which implement the function specified in the flowcharts and / or block diagrams block or blocks. Figure 1 one or more flows and / or blocks Figure 1 means for carrying out the function specified by the block or blocks.

[0193] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowcharts and / or block diagrams block or blocks. Figure 1 one or more flows and / or blocksFigure 1 Figure 1 the steps of the functions described in the one or more blocks.

[0194] The embodiments of the present application further provide a computer program product, which comprises computer software instructions, and when the computer software instructions are run on a processing device, the processing device executes the flow of the method for large signal modeling of a semiconductor device.

[0195] The computer program product comprises one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the flow or function according to the embodiments of the present application is wholly or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through a wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be stored by the computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

[0196] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0197] In several embodiments provided in the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic, for example, the division of units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0198] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e. may be located in one place, or may also be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0199] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0200] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the method of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0201] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

[0202] Although the preferred embodiments of the present specification have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present specification.

[0203] Obviously, those skilled in the art can make various modifications and variations to the present specification without departing from the spirit and scope of the present specification. Thus, if these modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalents, the present specification also intends to include these modifications and variations.

Claims

1. A large signal modeling method for a semiconductor device, characterized in that: The method comprises: Obtaining a first voltage and a first current of the semiconductor device, wherein the semiconductor device includes a first electrode and a second electrode, the first voltage is a voltage between the first electrode and the second electrode, and the first current is a current flowing between the first electrode and the second electrode; Establishing a first simulation model corresponding to the semiconductor device; Obtaining a temperature variation coefficient corresponding to the semiconductor device, and obtaining a compensation current value corresponding to the semiconductor device, wherein the temperature variation coefficient and the compensation current value are parameters that influence each other; A second simulation model of the semiconductor device is established based on the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage, and the first current, wherein the second simulation model is used to simulate the voltage-current relationship of the semiconductor device.

2. The large signal modeling method for semiconductor devices according to claim 1, wherein: The establishing of a first simulation model corresponding to the semiconductor device includes: Obtaining intrinsic parameters corresponding to the semiconductor device; Based on the intrinsic parameters, the first simulation model is established.

3. The large signal modeling method for semiconductor devices according to claim 1, wherein: The step of establishing a second simulation model of the semiconductor device based on the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage, and the first current includes: Get the preset parameter fitting model; Acquiring parameters to be fitted corresponding to the second simulation model and test data of the semiconductor device; Inputting the test data into the parameter fitting model so that the parameters to be fitted are updated to model parameters; The second simulation model is established based on the model parameters, the first simulation model, the temperature variation coefficient, the compensation current value, the first voltage, and the first current.

4. The large signal modeling method for a semiconductor device according to claim 3, wherein: The obtaining of the temperature variation coefficient corresponding to the semiconductor device includes: Obtaining parasitic parameters corresponding to the semiconductor device, the parasitic parameters including a first group of parameters, the first group of parameters including device temperature, ambient temperature, and power dissipation value; performing data processing on the device temperature, the ambient temperature, and the power dissipation value to obtain a thermal resistance value; Data processing is performed on the thermal resistance value, the ambient temperature, and the power dissipation value to obtain the temperature variation coefficient.

5. The large signal modeling method for semiconductor devices according to claim 4, characterized in that: The parasitic parameters further include a second group of parameters, the second group of parameters including a charge change rate, the model parameters including an amplitude factor, and obtaining a compensation current value corresponding to the semiconductor device includes: performing data updating processing on the charge change rate to obtain an updated charge change rate; The compensation current value is determined according to the amplitude factor and the updated charge change rate.

6. The large signal modeling method for a semiconductor device according to claim 5, wherein: The model parameters also include a temperature correction factor. The data updating process of the charge change rate to obtain the updated charge change rate includes: The charge change rate is updated according to the temperature correction factor, the device temperature, and the ambient temperature to obtain an updated charge change rate.

7. The large signal modeling method for a semiconductor device according to any one of claims 1 to 6, characterized in that: The large signal modeling method of the semiconductor device further includes: Get preset voltage data; Inputting the preset voltage data into the second simulation model to obtain current data output by the second simulation model; Acquiring a data correspondence relationship between the current data and the voltage data; Based on the data correspondence, a performance indicator of the semiconductor device is determined.

8. The large signal modeling method for a semiconductor device according to any one of claims 1 to 6, characterized in that: The expression of the second simulation model is: Among them, I ds (t, T) is the second simulation model, I ds0 is the first simulation model, T(t) is the temperature variation coefficient, is the compensation current value, A is the amplitude factor, τ trap is the updated charge change rate, α T is the temperature correction factor, T ref is the ambient reference temperature, and t is the time parameter.

9. A large signal modeling device for a semiconductor device, characterized in that: include: processor; A memory, wherein a program or instruction is stored in the memory, and when the processor executes the program or instruction in the memory, the processor implements the steps of the large signal modeling method for a semiconductor device according to any one of claims 1 to 8.

10. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the large signal modeling method for a semiconductor device according to any one of claims 1 to 8 are implemented.

11. A large signal model of a semiconductor device, characterized in that: The expression of the large signal model is: Among them, I ds (t, T) is the large signal model, I ds0 is the first simulation model, T(t) is the temperature variation coefficient, is the compensation current value, A is the amplitude factor, τ trap is the updated charge change rate, α T is the temperature correction factor, T ref is the ambient reference temperature, and t is the time parameter.

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