Method and device for determining line parameters in power supply scheme, equipment and storage medium

Abstract

The application discloses a line parameter determination method, device and equipment in a power supply scheme and a storage medium, the method comprising: acquiring module parameters of a target chip module; determining the correlation between line spacing parameters and line width parameters of a ground wire or a power supply wire and line voltage drop and track utilization under the constraint of the module parameters; and machine learning the change of the line voltage drop and the track utilization with the line spacing parameters and the line width parameters to obtain a change rule model; and performing optimization iteration operation on the line spacing parameters and the line width parameters according to the change rule model to obtain optimal line spacing parameters and optimal line width corresponding to line voltage drop less than a voltage drop threshold and track utilization less than a utilization threshold, and taking the optimal line spacing parameters and the optimal line width as the line parameters of the power supply scheme of the target chip module. In the application, the time and manpower consumed in power supply scheme design are greatly reduced, and the power supply scheme design cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip circuit design technology, and in particular to a method, apparatus, device, and computer-readable storage medium for determining circuit parameters in a power supply scheme. Background Technology

[0002] In the field of semiconductor manufacturing technology, the design of the power plan for chip modules is crucial. The trade-off between the resources occupied by power lines and ground lines and signal lines directly affects the working performance of the chip module.

[0003] Currently, power supply design in chip modules typically involves engineers determining various circuit parameters based on their experience, referencing reference power supply schemes provided by the process manufacturer for the corresponding process node. They then use Power Integrity (PI) simulation tools to verify whether the power supply scheme meets requirements in terms of voltage drop, electromigration, etc. If the requirements are met, the power supply design is considered complete. This approach is highly dependent on the designer's experience, which can vary significantly between designers. Furthermore, power supply design is a complex process involving numerous parameters and design rules. Manually adjusting circuit parameters and design rules is extremely difficult and prone to omissions and errors. Therefore, conventional power supply design methods often fail to efficiently and accurately complete designs for large-scale and complex chip designs. Additionally, PI simulation cycles are lengthy. If PI simulation tools are needed to verify different power supply schemes for the same chip module multiple times, it will undoubtedly extend the power supply design cycle and require significantly more manpower. Summary of the Invention

[0004] The purpose of this invention is to provide a method, apparatus, device, and computer-readable storage medium for determining line parameters in a power supply scheme, which can simplify the design difficulty of power supply schemes in chip modules to a certain extent and reduce the design cycle and manpower input of power supply schemes.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for determining line parameters in a power supply scheme, comprising:

[0006] Obtain the module parameters of the target chip module;

[0007] Determine the relationship between the spacing and width parameters of the ground or power lines and the line voltage drop and the utilization rate of the wiring track, under the constraints of the module parameters.

[0008] Based on the aforementioned correlation, machine learning is used to analyze the variation patterns of the line voltage drop and the track utilization rate with the line spacing parameters and line width parameters to obtain a variation pattern model.

[0009] Based on the change law model, the line spacing parameter and the line width parameter are optimized and iterated to obtain the optimal line spacing parameter and the optimal line width corresponding to the line voltage drop being less than the voltage drop threshold and the routing track utilization being less than the utilization threshold. The optimal line spacing parameter and the optimal line width are then used as the line parameters of the power supply scheme for the target chip module.

[0010] In one optional embodiment of this application, determining the correlation between the line spacing parameters and line width parameters and the line voltage drop and the utilization rate of the wiring track, under the constraints of the module parameters, includes:

[0011] Based on the module parameters, construct the initial power network and the current density of the target chip module;

[0012] Based on the current density, the current values ​​from the (k-1)th layer line to the standard device in the target chip module are normalized to obtain the average current value of the power supply connection point between the (k-1)th layer line and the kth layer line in the initial power network after normalization; where k is 2 or 3.

[0013] Based on the average current value, determine the voltage drop formula for the shortest current path from the outermost line to the innermost line in the initial power network. ;in, For voltage drop; The average current value; The electrical parameters of the cube; For the first Line width parameters of the layer circuit; The outermost layer number of the circuit; when hour, According to the first Layer to the first The line spacing parameters of the first layer of the line are determined. The first layer of the line The layer lines are respectively connected to the first Layer circuit and the first Line length parameters of the two nearest power supply connection points between the layer lines; It is a positive integer greater than k-1; when hour, For the first The first layer of the line Layer circuit and the first The length parameter of the line between the nearest power supply connection point and the power terminal between the layers;

[0014] Based on the number of traces in each layer and the spacing between traces in each layer in the initial power network, determine the utilization relationship between trace utilization and spacing parameters.

[0015] The voltage drop formula and the utilization rate relationship are used as the correlation relationship.

[0016] In an optional embodiment of this application, constructing an initial power network and determining the current density of the initial power network based on the module parameters includes:

[0017] Based on the module parameters, determine the module operating frequency, number of standard devices, ratio of registers to logic devices, average toggle rate of all standard devices, module static power consumption coefficient, module dynamic power consumption coefficient, module area, module operating voltage, number of traces on each layer, trace spacing on each layer, and sheet resistance parameters.

[0018] Based on the number of standard components, the number of traces, and the spacing between the traces, an initial power network is constructed.

[0019] According to the current density formula Determine the current density of the target chip module; wherein, Where F is the current density, T is the module operating frequency, V is the average toggle ratio, and C is the module operating voltage. The dynamic power consumption coefficient of the module. Let A be the static power consumption coefficient of the module, and let A be the area of ​​the module.

[0020] In an optional embodiment of this application, the current value from the (k-1)th layer line to the standard device in the target chip module is normalized according to the current density to obtain the average current value of the power supply connection point between the (k-1)th layer line and the kth layer line in the initial power network after normalization, including:

[0021] A rectangular normalized window is defined in the initial power network; wherein, at least a set number of standard devices and a set number of lines are defined in the rectangular normalized window from the 0th layer to the (k-1)th layer respectively;

[0022] The total current value of the rectangular normalized window is determined by multiplying the current density and the window area of ​​the rectangular normalized window.

[0023] The average current value is the ratio of the total current value to the number of lines in the (k-1)th layer contained in the rectangular normalized window.

[0024] In one optional embodiment of this application, it further includes:

[0025] The correspondence between the pin density of standard devices and the interface density of chip modules and the utilization threshold is determined in advance based on the principles of big data statistics.

[0026] After obtaining the module parameters of the target chip module, the method further includes:

[0027] Based on the number of pins and the number of interfaces of the standard device in the module parameters, determine the current pin density and the current interface density;

[0028] The utilization threshold is determined based on the current pin density, the current interface density, and the corresponding relationship.

[0029] In an optional embodiment of this application, based on the correlation, machine learning is performed on the variation patterns of the line voltage drop and the track utilization rate with the changes in the line spacing parameter and the line width parameter to obtain the variation pattern model, including:

[0030] Based on the aforementioned correlation, determine the line voltage drop samples and track utilization rate samples corresponding to multiple sets of line spacing samples and line width samples;

[0031] Neural network learning is performed on each group of line spacing samples, line width samples, line voltage drop samples, and track utilization rate samples to obtain a neural network model characterizing the change pattern, and the neural network model is used as the change pattern model.

[0032] Accordingly, the line spacing parameter and the line width parameter are optimized and iteratively calculated according to the change pattern, including:

[0033] Based on the change pattern model and the correlation, a greedy algorithm is used to iteratively calculate the line spacing parameter and the line width parameter to obtain the optimal line spacing parameter and the optimal line width.

[0034] A line parameter determination device for a power supply scheme, comprising:

[0035] The parameter acquisition module is used to acquire the module parameters of the target chip module;

[0036] The data relationship module is used to determine the correlation between the spacing and width parameters of the ground or power lines and the line voltage drop and the utilization rate of the wiring track, under the constraints of the module parameters.

[0037] The model training module is used to perform machine learning on the variation law of the line voltage drop and the utilization rate of the track as a function of the line spacing parameter and the line width parameter, based on the correlation relationship, to obtain a variation law model;

[0038] The optimization calculation module is used to perform optimization iterative calculations on the line spacing parameter and the line width parameter according to the change law model, to obtain the optimal line spacing parameter and the optimal line width when the line voltage drop is less than the voltage drop threshold and the line track utilization rate is less than the utilization rate threshold, and to use the optimal line spacing parameter and the optimal line width as the line parameters of the power supply scheme of the target chip module.

[0039] In one optional embodiment of this application, the data relationship module specifically includes:

[0040] The first computing unit is used to construct an initial power network and the current density of the target chip module based on the module parameters.

[0041] The second arithmetic unit is used to normalize the current value from the (k-1)th layer line to the standard device in the target chip module according to the current density, so as to obtain the average current value of the power supply connection point between the (k-1)th layer line and the kth layer line in the initial power network after normalization; where k is 2 or 3.

[0042] The third calculation unit is used to determine the voltage drop formula for the shortest current path between the outermost and innermost lines of the initial power network based on the average current value. ;in, For voltage drop; The average current value; The electrical parameters of the cube; For the first Line width parameters of the layer circuit; The outermost layer number of the circuit; when hour, According to the first Layer to the first The line spacing parameters of the first layer of the line are determined. The first layer of the line The layer lines are respectively connected to the first Layer circuit and the first Line length parameters of the two nearest power supply connection points between the layer lines; It is a positive integer greater than k-1; when hour, For the first The first layer of the line Layer circuit and the first The length parameter of the line between the nearest power supply connection point and the power terminal between the layers;

[0043] The fourth calculation unit is used to determine the utilization relationship between the trace utilization rate and the trace spacing parameter based on the number of traces in each layer and the trace spacing in each layer in the initial power network.

[0044] The fifth calculation unit is used to use the voltage drop formula and the utilization rate correlation as the correlation relationship.

[0045] A line parameter determination device in a power supply scheme includes:

[0046] Memory, used to store computer programs;

[0047] A processor for executing the computer program to implement the steps of the method for determining line parameters in the power supply scheme as described in any of the preceding claims.

[0048] A computer-readable storage medium storing a computer program that is executed to implement the steps of the method for determining line parameters in a power supply scheme as described in any of the preceding claims.

[0049] The present invention provides a method, apparatus, design, and computer-readable storage medium for determining line parameters of a power supply scheme. The method may include: acquiring module parameters of a target chip module; determining the correlation between the spacing and width parameters of ground or power lines and the line voltage drop and trace utilization rate under the constraints of the module parameters; performing machine learning on the variation law of line voltage drop and trace utilization rate with the spacing and width parameters based on the correlation law to obtain a variation law model; performing optimization iterative calculations on the spacing and width parameters based on the variation law model to obtain the optimal spacing and width parameters where the line voltage drop is less than a voltage drop threshold and the trace utilization rate is less than a utilization rate threshold, and using the optimal spacing and width parameters as the line parameters of the power supply scheme for the target chip module.

[0050] This application determines the relationship between the line spacing and line width parameters of any one of the ground or power lines in the power supply scheme, based on the parameters of the target chip module's heating module, and the voltage drop and trace utilization rate. Using this as a basis, machine learning is performed to determine the variation law model of line voltage drop and trace utilization rate with the changes in line spacing and line width parameters. Then, based on this variation law model, the line spacing and line width parameters are optimized iteratively to finally determine the optimal line spacing and line width parameters that simultaneously meet the voltage drop threshold and utilization rate threshold requirements. Compared to the power supply scheme design method that manually adjusts a large number of line parameters, the line parameters of the ground or power lines in this application can be determined by automated iterative calculations by a computer, greatly reducing the time and manpower required for power supply scheme design and lowering the design cost. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the structure of a portion of the power network in the chip module provided in an embodiment of this application;

[0053] Figure 2 A flowchart illustrating the method for determining line parameters in a power supply scheme provided in this application embodiment;

[0054] Figure 3 This is a schematic diagram of the structure of another part of the power network in the chip module provided in the embodiments of this application;

[0055] Figure 4 This is a structural block diagram of the line parameter determination device in the power supply scheme provided in an embodiment of the present invention. Detailed Implementation

[0056] The core of this invention is to provide a method for determining line parameters in a power supply scheme, which can greatly reduce the power supply scheme design cycle and reduce the input of human resources.

[0057] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a portion of the power network in a chip module provided in an embodiment of this application.

[0059] It should be noted that the power supply design for a chip module mainly includes power lines, ground lines, and signal lines. In addition to these lines, the chip module also contains standard devices connected to them, such as registers and logic gates. These standard devices are located at the bottom layer of the chip module, with multiple layers of circuitry arranged sequentially upwards from the standard devices. Each layer of circuitry includes power lines, ground lines, and signal lines. Figure 1In the four-layer circuit shown in M0 to M3, the power lines and ground lines in each layer are evenly spaced and uniformly arranged. The routing directions of adjacent layers are perpendicular to each other, and the same type of lines in adjacent layers are electrically connected through through holes at the intersections.

[0060] Based on this, this application mainly concerns how to determine the line parameters of power lines and ground lines in a power supply scheme. These line parameters primarily involve the spacing and width parameters of power lines in each layer of the circuit, or the spacing and width parameters of ground lines in each layer of the circuit. In practical applications, the method for determining the line parameters in a power supply scheme in this application can determine the line parameters of either ground lines or power lines. In short, after determining a set of optimal line parameters, both power lines and ground lines can be laid out according to the same line parameters.

[0061] like Figure 2 As shown, Figure 2 This is a flowchart illustrating the method for determining line parameters in a power supply scheme provided in an embodiment of this application.

[0062] S1: Obtain the module parameters of the target chip module.

[0063] The target chip module in this embodiment can be a CPU chip module or any other chip module that requires power supply design. This embodiment does not impose any specific restrictions on this.

[0064] After selecting the target chip module, its back-end input components can be determined, such as the netlist, timing constraints (SDC), and operating scenario requirements (Spec). Module parameters can then be further extracted from these netlist, timing constraints, and operating scenario requirements. For example, the netlist can provide information on the standard devices included in the target chip module, their quantities, pin counts, and the number of interfaces. The timing constraints can be used to extract the frequency parameters of the target chip module, and the operating scenario requirements can be used to extract information on the module's operating scenario, shape, and size.

[0065] S2: Determine the relationship between the spacing and width parameters of the ground or power lines, the line voltage drop, and the utilization rate of the wiring track, under the constraints of the module parameters.

[0066] As described above, multiple layers of circuits are arranged sequentially from bottom to top in the target chip module; the line spacing parameter in this embodiment refers to the spacing between the same type of circuits in each layer, while the line width parameter refers to the line width of each type of circuit in each layer.

[0067] Based on this, the target chip module has multiple layers of routing tracks, which are used to accommodate power lines, ground lines, and information lines. The routing tracks in each layer are evenly distributed. After selecting the target chip module, the number of routing tracks for each layer and the spacing between them are known. Therefore, when setting the actual spacing parameters, the spacing of each layer should be an integer multiple of the spacing between adjacent routing tracks in that layer.

[0068] It is understood that the line voltage drop in this embodiment refers to the voltage drop caused by the resistance of each layer of lines during the process of power supply from the outermost line of the target chip module to the innermost standard device of the target chip module. This is obviously related to the circuit relationship formed by the layout of each layer of lines based on the line spacing parameters, as well as the resistance of each layer of lines. The resistance of each layer of lines is determined by the line width parameters and the line spacing parameters. Based on this relationship, the correlation between the line spacing parameters, the line width parameters and the line voltage drop can obviously be derived.

[0069] The utilization rate of the cabling tracks, based on the spacing parameters, represents the utilization of the cabling tracks required for each layer. This is directly determined by the spacing parameters and the number of cabling tracks in each layer. Of course, the line width parameters of each layer also affect the utilization rate to some extent. For example, there is a minimum line width limit for each line. If the line width of a line within a certain cabling track is too large, even the minimum line width lines in the two adjacent cabling tracks cannot be laid out. This is equivalent to one line occupying the layout space of three cabling tracks, which also affects the utilization rate of the cabling tracks.

[0070] Based on this, the correlation between line spacing parameters, line width parameters, line voltage drop, and track utilization rate can be determined.

[0071] As mentioned above, the line parameters determined in this application can be either power line line parameters or ground line line parameters. In this embodiment and subsequent embodiments, each layer of lines can be regarded as all power line lines or all ground line lines. It does not include the case where some layer lines are power line lines and other lines are ground line lines, nor does it include the case where some lines in the same layer are power line lines and some are ground line lines. This will not be repeated later.

[0072] S3: Based on the correlation, machine learning is used to study the variation patterns of line voltage drop and track utilization with line spacing and line width parameters to obtain a variation pattern model.

[0073] It is understood that the above-mentioned correlation and change law model in this embodiment are essentially characterizing the correlation between the line spacing parameter and the line width parameter and the line voltage drop and the utilization rate of the track.

[0074] Furthermore, the reason for needing to further train a machine learning model to determine the changing patterns based on the known relationships mentioned above is that in the target chip module, the number of lines required for a single layer can be in the hundreds or thousands, and the total number of lines required for a multi-layer circuit is even larger. In such a complex circuit layout, each adjustment to the line spacing and line width parameters requires a massive amount of data computation to determine the corresponding line voltage drop and routing track utilization. Therefore, in this embodiment, machine learning is further used to obtain a model that can predict the corresponding line voltage drop and routing track utilization more quickly and accurately when the line spacing and line width parameters are determined.

[0075] Optionally, the learning and creation process of the change pattern model in this embodiment may include:

[0076] Based on the correlation, determine the line voltage drop samples and track utilization rate samples corresponding to multiple sets of line spacing samples and line width samples;

[0077] Neural network learning was performed on each group of line spacing samples, line width samples, line voltage drop samples, and track utilization rate samples to obtain a neural network model representing the change law, and the neural network model was used as the change law model.

[0078] This embodiment utilizes the aforementioned correlation to determine multiple sets of line spacing samples, line width samples, and corresponding line voltage drop samples and track utilization rate samples. Based on these sample data, a neural network model can be trained. The specific training process is similar to that of a conventional neural network model training process, and this application does not provide specific limitations or explanations.

[0079] S4: Based on the change law model, perform optimization and iterative calculations on the line spacing parameters and line width parameters to obtain the optimal line spacing parameters and optimal line width corresponding to the line voltage drop being less than the voltage drop threshold and the track utilization rate being less than the utilization rate threshold. Then, use the optimal line spacing parameters and optimal line width as the power supply scheme parameters of the target chip module.

[0080] In this embodiment, the line spacing parameters and line width parameters can be repeatedly adjusted and optimized. The updated neural network model is used to predict the line voltage drop and track utilization rate corresponding to the updated line spacing parameters and line width parameters. Based on this, it is determined whether the updated line spacing parameters and line width parameters meet the requirements. This process continues until the line voltage drop corresponding to the finally determined line spacing parameters and line width parameters is less than the voltage drop threshold and the track utilization rate is less than the utilization rate threshold. At this point, the line spacing parameters and line width parameters are the optimal line spacing parameters and optimal line width parameters.

[0081] Further, optionally, the process of iteratively optimizing the line spacing and line width parameters may include:

[0082] Based on the change pattern model and the aforementioned correlation, a greedy algorithm is used to iteratively calculate the line spacing parameter and the line width parameter to obtain the optimal line spacing parameter and the optimal line width.

[0083] It should be noted that in the actual process of optimizing and iterating the line spacing and line width parameters, there may be multiple sets of line spacing and line width parameters whose corresponding line voltage drop is less than the voltage drop threshold and whose track utilization rate is less than the utilization rate threshold. In practical applications, the set of line spacing and line width parameters with the lowest track utilization rate based on the corresponding line voltage drop being less than the voltage drop threshold should be selected as the optimal line spacing and optimal line width.

[0084] As mentioned above, the lines in this application mainly refer to the line parameters of ground wires and power lines. Signal lines also need to be laid out in the power supply scheme. In order to ensure the balance between the routing track resources occupied by power lines, ground wires and signal lines, it is necessary to limit the utilization rate of the routing tracks corresponding to power lines and ground wires. Therefore, the utilization rate threshold in this embodiment is also the maximum utilization rate of the routing tracks occupied by power lines and ground wires.

[0085] In an optional embodiment of this application, the process of determining the utilization threshold may include:

[0086] The correspondence between the pin density of standard devices and the interface density of chip modules and the utilization threshold is determined in advance based on the principles of big data statistics.

[0087] After obtaining the module parameters of the target chip module, the following is also included:

[0088] Determine the current pin density and current interface density based on the number of pins and interfaces of the standard devices in the module parameters;

[0089] Determine the utilization threshold based on the current pin density, current interface density, and their corresponding relationship.

[0090] Based on the principles of big data statistics, this embodiment combines the pin density of standard devices and the interface density of chip modules in various chip modules with the utilization rate of their ground or power lines to the trace tracks. It then fits and determines the correspondence between the pin density of standard devices, the interface density of chip modules, and the utilization rate threshold. Based on this correspondence and the pin density and interface density in the current target chip module, a reasonable utilization rate threshold can be determined.

[0091] It is understood that the pin density in this embodiment is calculated by the ratio between the number of pins on the standard device and the circumference length of the pins that can be placed on the standard device, while the interface density is calculated by the ratio between the number of interfaces in the target chip module and the axial length of the interfaces that can be placed on the target chip module.

[0092] In summary, this application, based on the module parameters of the target chip module, determines the correlation between the spacing and width parameters of the ground or power lines in the power supply scheme and the voltage drop and trace utilization. Using this as a basis, it performs learning to determine the variation law of line voltage drop and trace utilization with the spacing and width parameters, and then optimizes and iterates the spacing and width parameters to ultimately determine the optimal spacing and width parameters that simultaneously meet the voltage drop threshold and utilization threshold requirements. Compared to manually adjusting a large number of line parameters, the method of determining the ground or power line parameters in this application can be automated by computer calculation, greatly reducing the time and manpower required for power supply scheme design, and lowering the design cost.

[0093] Based on the above embodiments, in an optional embodiment of this application, the process of determining the correlation between line spacing parameters and line width parameters and line voltage drop and track utilization rate based on module parameters may specifically include:

[0094] S21: Based on the module parameters, construct the initial power network and the current density of the target chip module.

[0095] Based on the module parameter density, at least the following parameters can be determined: module operating frequency, number of standard devices, ratio of registers to logic devices, average toggle rate of all standard devices, module static power consumption coefficient, module dynamic power consumption coefficient, module area, module operating voltage, number of traces on each layer, trace spacing on each layer, and sheet resistance parameters.

[0096] Understandably, once the module parameters of the target chip module are obtained, the basic framework of the power network of the target chip module can be determined, which is similar to... Figure 1 The power network structure shown is shown.

[0097] Based on this, the initial line spacing and initial line width of each layer of the power network can be set first. Based on the basic architecture of the power network structure and the initial line spacing and initial line width, the initial power network of the target chip module can be constructed.

[0098] In addition, in this embodiment, the target chip module refers to the current surface density of the entire target chip module.

[0099] Based on this, we can use the current density formula Determine the current density of the target chip module; among which, Where F is the current density, T is the module operating frequency, V is the average toggle ratio, and C is the proportional gain. The module's dynamic power consumption coefficient. Let A be the static power consumption coefficient of the module, and let A be the area of ​​the module.

[0100] S22: Based on the current density, normalize the current value from the (k-1)th layer line to the standard device in the target chip module to obtain the average current value of the power supply connection point between the (k-1)th layer line and the kth layer line in the power network after normalization; where k is 2 or 3.

[0101] As mentioned earlier, the current density in this embodiment refers to the current density across the entire surface of the target chip module. The reason for determining the current density of the entire target chip module in this embodiment is to determine the voltage drop that the power supply travels through each layer of the initial power network, from the outermost layer to the innermost layer, and finally to the standard device.

[0102] It is understandable that the supply voltage of different standard devices in the target chip module is not the same. As a result, the voltage drop from the outermost line to the voltage input terminal of different standard devices is also different. Therefore, the voltage drop between the voltage input terminal of any standard device and the outermost line cannot accurately represent the voltage drop between the lines of the entire target chip module.

[0103] Based on this, in this embodiment, the circuits below the (k-1)th layer are subjected to current normalization processing. That is, the average current of each power supply connection point between the (k-1)th layer line and the kth layer line (that is, the point where the two layers of lines intersect and are electrically connected through vias) is used to represent the current from the standard device to the (k-1)th layer line. Based on this average current value, the voltage drop from the (k-1)th layer line to the outermost layer line is further determined, which is equivalent to using the average voltage drop between the outermost layer line and the standard device to characterize the voltage drop of each layer of the target chip module.

[0104] Further optional, refer to Figure 1 The process of normalizing the current values ​​from the k-1 layer circuitry to the standard device in the target chip module to obtain the aforementioned average current value may include:

[0105] Define a rectangular normalized window in the initial power network; wherein, at least a set number of standard devices and a set number of lines in the lines from layer 0 to layer (k-1) are enclosed in the rectangular normalized window;

[0106] The total current value of the rectangular normalized window is determined by multiplying the current density by the window area of ​​the rectangular normalized window.

[0107] The average current value is the ratio of the total current value to the number of lines in the (k-1)th layer contained in the rectangular normalized window.

[0108] like Figure 1 In the illustrated embodiment, a rectangular normalized window is defined with k=3 as an example, and M0, M1, M2, and M3 represent the lines from layer 0 to layer 3, respectively. It should be noted that, in this embodiment where the spacing and width parameters of the ground wires are determined, all three layers of lines M1 to M3 are ground wires; while the lines in layer M0 should simultaneously include power and ground wires. Conversely, in this embodiment where the spacing and width parameters of the power wires are determined, all three layers of lines M1 to M3 are power wires; while the lines in layer M0 should also simultaneously include power and ground wires.

[0109] It should be noted that the long and wide sides of this rectangular normalized window are parallel to the two axial tracks of the target chip module in two different directions. This normalized window encloses a set number of standard devices; generally, at least three different types of standard devices are enclosed within this rectangular normalized window. Furthermore, the number of lines in the layer 0 circuits (i.e., the M0 layer circuits) enclosed within this rectangular normalized window is no less than three. Figure 1 In the embodiment shown, the number of lines in the 0th layer circled in the rectangular normalized window is 5, the number of lines in the 1st layer circled is 3, and the number of lines in the 2nd and 3rd layers circled is 1 each.

[0110] Based on this, the standard device, layer 0 line, layer 1 line and layer 2 line enclosed in the rectangular normalization window are regarded as a whole module. That is, the current in the standard device and layer 0 to layer 2 lines is normalized, and the product of the area of ​​the rectangular normalization window and the current density of the target chip module is used as the average value of the current flowing into and out of the rectangular normalization window.

[0111] like Figure 1 As shown, to simplify the calculation process, in Figure 1In the embodiment shown, one line from the (k-1)th layer and one line from the kth layer should be located on the center line of the rectangular normalized window. That is to say, the rectangular normalized window in this embodiment is a window centered on a power supply connection point between the (k-1)th layer and the kth layer.

[0112] Therefore, the average flow from the third-layer line to the second-layer line is equal to the product of the area of ​​the rectangular normalized window and the current density. It can be understood that if the second-layer line included in the rectangular normalized window contains two lines, then the average flow from the third-layer line to the second-layer line should be equal to half the product of the area of ​​the rectangular normalized window and the current density. If the second-layer line included in the rectangular normalized window contains three lines, then the average flow from the third-layer line to the second-layer line should be equal to one-third the product of the area of ​​the rectangular normalized window and the current density.

[0113] The above explanation uses k=3 as an example. In practical applications, the current from the M1 layer line to the standard device can also be normalized, i.e., k=2. In this case, the rectangular normalization window can be smaller than the rectangular normalization window when k=3, ensuring that at least one line in the M1 layer line passes through the rectangular normalization window. The calculation method for the average current value and voltage drop when k=2 is exactly the same as when k=3, and will not be elaborated here.

[0114] S23: Determine the voltage drop formula for the shortest current path from the outermost layer to the innermost layer of the initial power network based on the average current value. ;in, For voltage drop; This is the average current value; The electrical parameters of the cube; For the first Line width parameters of the layer circuit; The number of layers in the outermost circuit; when hour, According to the first Layer to the first The line spacing parameters of the first layer of the line are determined. The first layer of the line The layer lines are respectively connected to the first Layer circuit and the first Line length parameters of the two nearest power supply connection points between the layer lines; It is a positive integer greater than k-1; when hour, For the first The first layer of the line Layer circuit and the first The length parameter of the line between the nearest power supply connection point and the power supply terminal between the layers.

[0115] As described above, after considering the standard devices enclosed in the rectangular normalized window and the lines from layer 0 to layer 2 as a whole module, based on the principle that the current path in the circuit should be the path with the minimum resistance, the shortest current path from the outermost line to the innermost line is determined; this shortest current path is also the shortest current path from the outermost line to the rectangular normalized window, specifically, the shortest current path from the outermost line to the power supply connection point between the second and third layer lines in the rectangular normalized window.

[0116] Reference Figure 3 , Figure 3 The diagram shows the shortest circuit path from the M7 layer circuit to the rectangular normalized window, i.e. Figure 3 The arrows indicate the current paths. In determining the shortest current path, the power connection point between one line in the second layer and one line in the third layer within the rectangular normalized window can be taken as the first node of the starting node. The shortest current path is determined along the reverse direction of the current flow; that is, the power connection point between the second and third layer lines within the rectangular normalized window is taken as the first node, and the power connection point between the third and fourth layer lines in the initial power network determined based on the initial line spacing, which is closest to the first node, is taken as the second node. These first and second nodes represent the connections between the third layer line and the second and fourth layer lines, respectively. The two nearest power supply connection points; in the same way, the power supply connection point closest to the second node among the power supply connection points between the fourth and fifth layer lines can be determined as the third node. The second and third nodes are also the two nearest power supply connection points between the fourth layer line and the third and fifth layer lines, respectively. By analogy, the power supply connection point between the outermost and second outermost layer lines can be determined as the Nth node. The shortest current path is that the current flows from the Nth node as the starting point through the (N-1)th node to the 1st node. The voltage drop between the Nth node and the 1st node is the voltage drop in the target chip module.

[0117] Based on the aforementioned shortest current path and the initial line spacing and line width parameters in each layer of the circuit, the current magnitude and voltage drop between two adjacent nodes under these set initial line spacing and line width conditions can be determined. The cumulative value of the voltage drop between each pair of adjacent nodes is the voltage drop between the Nth node and the 1st node, which can also be used as the voltage drop in the target chip module. Based on this, the voltage drop formula can be determined as follows: Although the voltage drop formula does not involve the line spacing parameter, Yes, the first On the layer line, the first Layer circuit and the first Between the layers of lines, and the first Layer circuit and the first The line length parameter between the two nearest power supply connection points between the layers; obviously, this line length parameter is determined by the first... Layer line to the first The spacing parameters of the lines in the layer are determined; and when hour, For the first The first layer of the line Layer circuit and the first The line length parameter between the nearest power supply connection point between the layers (i.e., the Nth node determined when determining the shortest current path) and the power supply terminal (the power supply terminal if the line is a power line, and the power grounding terminal if the line is a ground line); obviously, it also varies with the line length from the kth layer to the kth layer. The voltage drop is determined by the line spacing parameter of the layer line; therefore, the above voltage drop formula is also the formula that characterizes the relationship between the line spacing parameter, the line width parameter and the line voltage drop.

[0118] S24: Based on the number of traces in each layer and the spacing between traces in each layer in the initial power network, determine the utilization relationship between the trace utilization rate and the trace spacing parameter.

[0119] As mentioned above, the spacing parameters of each layer of the line are all integer multiples of the spacing of the wiring track in that layer. Based on this principle, the relationship between the utilization rate of the wiring track and the spacing parameters can be determined.

[0120] S25: The relationship between voltage drop formula and utilization rate is used as the correlation.

[0121] The following describes the line parameter determination device in the power supply scheme provided by the embodiments of the present invention. The line parameter determination device in the power supply scheme described below and the line parameter determination method in the power supply scheme described above can be referred to in correspondence with each other.

[0122] Figure 4 This is a structural block diagram of the line parameter determination device in the power supply scheme provided in the embodiment of the present invention, with reference to... Figure 4 The line parameter determination device in the power supply scheme may include:

[0123] The parameter acquisition module 100 is used to acquire the module parameters of the target chip module;

[0124] Data relationship module 200 is used to determine the relationship between the spacing parameters and width parameters of the ground wire or power wire and the line voltage drop and the utilization rate of the wiring track under the constraints of the module parameters.

[0125] The model training module 300 is used to perform machine learning on the variation law of the line voltage drop and the utilization rate of the track as a function of the line spacing parameter and the line width parameter, based on the correlation relationship, to obtain the variation law model;

[0126] The optimization calculation module 400 is used to perform optimization iterative calculations on the line spacing parameter and the line width parameter according to the change law model, to obtain the optimal line spacing parameter and the optimal line width when the line voltage drop is less than the voltage drop threshold and the routing track utilization rate is less than the utilization rate threshold, and to use the optimal line spacing parameter and the optimal line width as the line parameters of the power supply scheme of the target chip module.

[0127] In one optional embodiment of this application, the data relationship module specifically includes:

[0128] The first computing unit is used to construct an initial power network and the current density of the target chip module based on the module parameters.

[0129] The second arithmetic unit is used to normalize the current value from the k-1 layer line to the standard device in the target chip module according to the current density, so as to obtain the average current value of the power supply connection point between the k-1 layer line and the k layer line in the initial power network after normalization; where k is 2 or 3.

[0130] The third calculation unit is used to determine the voltage drop formula for the shortest current path between the outermost and innermost lines of the initial power network based on the average current value. ;in, For voltage drop; The average current value; The electrical parameters of the cube; For the first Line width parameters of the layer circuit; The outermost layer number of the circuit; when hour, According to the first Layer to the first The line spacing parameters of the first layer of the line are determined. The first layer of the line The layer lines are respectively connected to the first Layer circuit and the first Line length parameters of the two nearest power supply connection points between the layer lines; It is a positive integer greater than k-1; when hour, For the first The first layer of the line Layer circuit and the first The length parameter of the line between the nearest power supply connection point and the power terminal between the layers;

[0131] The fourth calculation unit is used to determine the utilization relationship between the trace utilization rate and the trace spacing parameter based on the number of traces in each layer and the trace spacing in each layer in the initial power network.

[0132] The fifth calculation unit is used to use the voltage drop formula and the utilization rate correlation as the correlation relationship.

[0133] In an optional embodiment of this application, the first arithmetic unit is specifically used to determine, based on the module parameters, the module operating frequency, the number of standard devices, the ratio of registers to logic devices, the average toggle ratio of all standard devices, the module static power consumption coefficient, the module dynamic power consumption coefficient, the module area, the module operating voltage, the number of traces on each layer, the trace spacing on each layer, and the sheet resistance parameters; construct an initial power network based on the number of standard devices, the number of traces, and the trace spacing; and apply the current density formula... Determine the current density of the target chip module; wherein, Where F is the current density, T is the module operating frequency, V is the average toggle ratio, and C is the module operating voltage. The dynamic power consumption coefficient of the module. Let A be the dynamic power consumption coefficient of the module, and let A be the area of ​​the module.

[0134] In an optional embodiment of this application, the second computing unit is specifically used to delineate a rectangular normalized window in the initial power network; wherein, the rectangular normalized window includes at least a set number of standard devices, and a set number of lines from layer 0 to layer (k-1) are respectively included; the total current value of the rectangular normalized window is determined based on the product of the current density and the window area of ​​the rectangular normalized window; and the average current value is the ratio of the total current value to the number of lines in the (k-1)th layer included in the rectangular normalized window.

[0135] In an optional embodiment of this application, a data statistics module is further included, which is used to pre-determine the correspondence between the pin density of the standard device and the interface density of the chip module and the utilization threshold based on the big data statistics principle.

[0136] It also includes a utilization module specifically used to determine the current pin density and the current interface density based on the number of pins and the number of interfaces of the standard device in the module parameters; and to determine the utilization threshold based on the current pin density, the current interface density and the corresponding relationship.

[0137] In an optional embodiment of this application, the model training module 300 is specifically used to determine the line voltage drop samples and track utilization rate samples corresponding to multiple sets of line spacing samples and line width samples according to the correlation relationship; to perform neural network learning on each set of line spacing samples, line width samples, line voltage drop samples and track utilization rate samples to obtain a neural network model characterizing the change law, and to use the neural network model as the change law model;

[0138] Accordingly, the optimization calculation module 400 is specifically used to perform iterative calculations on the line spacing parameter and the line width parameter using a greedy algorithm based on the neural network model and the correlation relationship, to obtain the optimal line spacing parameter and the optimal line width.

[0139] In this embodiment, the line parameter determination device in the power supply scheme is used to implement the aforementioned line parameter determination method in the power supply scheme. Therefore, the specific implementation of the line parameter determination device in the power supply scheme can be found in the embodiment section of the power supply scheme line parameter determination method above. The specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.

[0140] This application also provides an embodiment of a power supply scheme line parameter determination device, which may include:

[0141] Memory, used to store computer programs;

[0142] A processor for executing the computer program to implement the steps of the method for determining line parameters in the power supply scheme as described in any of the preceding claims.

[0143] This application also provides an embodiment of a computer-readable storage medium storing a computer program that is executed to implement the steps of the method for determining line parameters in the power supply scheme as described in any of the preceding claims.

[0144] The computer-readable storage medium may be random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0145] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0146] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for line parameter determination in a power supply scheme, characterized by, The method comprises: acquiring module parameters of a target chip module; determining a correlation between line spacing parameters and line width parameters of a ground wire or a power supply wire and line voltage drop and track utilization rate under constraints of the module parameters; according to the correlation, machine learning variation laws of the line voltage drop and the track utilization rate with the line spacing parameters and the line width parameters, and obtaining a variation law model; according to the variation law model, performing iterative operation on the line spacing parameters and the line width parameters, and obtaining optimal line spacing parameters and optimal line width corresponding to the line voltage drop less than a voltage drop threshold and the track utilization rate less than a utilization rate threshold, and taking the optimal line spacing parameters and the optimal line width as line parameters of a power supply scheme of the target chip module; determining the correlation between the line spacing parameters and the line width parameters and the line voltage drop and the track utilization rate under the constraints of the module parameters comprises: according to the module parameters, constructing an initial power supply network and a current density of the target chip module; according to the current density, performing normalization processing on current values from a k-1 layer line to a standard device in the target chip module, and obtaining average current values of power supply connection points between the k-1 layer line and a k layer line in the initial power supply network after normalization processing; wherein k is 2 or 3; Based on the average current value, determine the voltage drop formula for the shortest current path from the outermost line to the innermost line in the initial power network. ;in, For voltage drop; The average current value; These are the parameters for sheet resistance; For the first Line width parameters of the layer circuit; The outermost layer number of the circuit; when hour, According to the first Layer to the first The line spacing parameters of the first layer of the line are determined. The first layer of the line The layer lines are respectively connected to the first Layer circuit and the first Line length parameters of the two nearest power supply connection points between the layer lines; It is a positive integer greater than k-1; when hour, For the first The first layer of the line Layer circuit and the first The length parameter of the line between the nearest power supply connection point and the power terminal between the layers; according to the number of track layers and the track spacing of each layer in the initial power supply network, determining a utilization correlation between the track utilization rate and the line spacing parameters; taking the voltage drop formula and the utilization correlation as the correlation; according to the module parameters, constructing an initial power supply network and determining a current density of the initial power supply network, comprises: according to the module parameters, determining module operating frequency, standard device quantity, proportion of registers and logic devices, average flip rate of all standard devices, module static power consumption coefficient, module dynamic power consumption coefficient, module area, module operating voltage, number of track layers, track spacing of each layer and sheet resistance parameters; according to the standard device quantity, the number of track layers and the track spacing, constructing the initial power supply network; According to the current density formula , the current density of the target chip module is determined; wherein, is the current density, F is the module operating frequency, T is the average flip rate, V is the module operating voltage, and C is the proportion, is the module dynamic power consumption coefficient, is the module static power consumption coefficient, and A is the module area.

2. The method of claim 1, wherein the line parameters are determined by: according to the current density, performing normalization processing on current values from the k-1 layer line to the standard device in the target chip module, and obtaining average current values of power supply connection points between the k-1 layer line and the k layer line in the initial power supply network after normalization processing, comprises: delimiting a rectangular normalization window in the initial power supply network; wherein the rectangular normalization window at least encloses a set number of standard devices, and a set number of lines in the 0th layer to the k-1 layer lines are respectively enclosed; determining a total current value of the rectangular normalization window according to the product of the current density and the window area of the rectangular normalization window; taking the ratio of the total current value to the number of lines in the k-1 layer line included in the rectangular normalization window as the average current value.

3. The method of claim 1, wherein the line parameters are determined by: Further comprising: The corresponding relationship between the pin density of the standard device and the interface density and utilization threshold of the chip module is determined in advance according to a big data statistical principle; After the module parameters of the target chip module are acquired, the method further includes: According to the number of pins and the number of interfaces of the standard device in the module parameters, current pin density and current interface density are determined; According to the current pin density and the current interface density and the corresponding relationship, the utilization threshold is determined.

4. The method of line parameter determination for a power supply scheme of any one of claims 1 to 3, wherein, According to the association relationship, machine learning is performed on the change rule of the line voltage drop and the track utilization rate with the line spacing parameter and the line width parameter, and a change rule model is obtained, including: According to the association relationship, a plurality of line spacing samples and line width samples are determined, and line voltage drop samples and track utilization rate samples corresponding to the line spacing samples and the line width samples are determined; The neural network model representing the change rule is obtained by performing neural network learning on each set of line spacing samples, line width samples, line voltage drop samples and track utilization rate samples, and the neural network model is used as the change rule model; According to the change rule, the line spacing parameter and the line width parameter are iteratively calculated, including: According to the change rule model and the association relationship, the line spacing parameter and the line width parameter are iteratively calculated by using a greedy algorithm, and the optimal line spacing parameter and the optimal line width are obtained.

5. A device for determining line parameters in a power supply scheme, characterized in that, including: A parameter acquisition module is configured to acquire module parameters of a target chip module; A data relationship module is configured to determine an association relationship between line spacing parameters and line width parameters of a ground wire or a power supply wire and line voltage drops and track utilization rates under constraints of the module parameters; A model training module is configured to perform machine learning on a change rule of the line voltage drop and the track utilization rate with the line spacing parameter and the line width parameter according to the association relationship, and obtain a change rule model; An optimization calculation module is configured to perform optimization iterative calculation on the line spacing parameter and the line width parameter according to the change rule model, and obtain optimal line spacing parameters and optimal line widths corresponding to the line voltage drop being less than a voltage drop threshold and the track utilization rate being less than a utilization threshold, and use the optimal line spacing parameters and the optimal line widths as line parameters of a power supply scheme of the target chip module; The data relationship module specifically includes: A first calculation unit is configured to construct an initial power supply network and a current density of the target chip module according to the module parameters; A second calculation unit is configured to normalize current values from a k-1 layer line to a standard device in the target chip module according to the current density, and obtain average current values of power supply connection points between the k-1 layer line and a k layer line in the initial power supply network after normalization; wherein k is 2 or 3; The third calculation unit is used to determine the voltage drop formula for the shortest current path between the outermost and innermost lines of the initial power network based on the average current value. ;in, For voltage drop; The average current value; These are the parameters for sheet resistance; For the first Line width parameters of the layer circuit; The outermost layer number of the circuit; when hour, According to the first Layer to the first The line spacing parameters of the first layer of the line are determined. The first layer of the line The layer lines are respectively connected to the first The line length parameters of the two nearest power supply connection points between the first-layer line and the second-layer line; It is a positive integer greater than k-1; when hour, For the first The first layer of the line Layer circuit and the first The length parameter of the line between the nearest power supply connection point and the power terminal between the layers; A fourth calculation unit is configured to determine a utilization association relationship between the track utilization rate and the line spacing parameter according to the number of track layers and the track spacing between the layers in the initial power supply network. A fifth operation unit configured to use the voltage drop formula and the utilization correlation as the correlation; The first operation unit is specifically configured to determine, according to the module parameters, a module working frequency, a standard device quantity, a proportion of a register and a logic device, an average flip rate of all standard devices, a module static power consumption coefficient, a module dynamic power consumption coefficient, a module area, a module working voltage, a track quantity of each layer, a track spacing of each layer, and a square resistance parameter; construct an initial power supply network according to the standard device quantity, the track quantity, and the track spacing; and determine a current density of the target chip module according to a current density formula , wherein, is the current density, F is the module working frequency, T is the average flip rate, V is the module working voltage, C is the proportion, is the module dynamic power consumption coefficient, is the module dynamic power consumption coefficient, and A is the module area.

6. A line parameter determination device in a power supply scheme, characterized by The method comprises the following steps: A memory configured to store a computer program; A processor configured to execute the computer program to implement the steps of the line parameter determination method in the power supply scheme according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer program stored in the computer readable storage medium is executed to implement the steps of the line parameter determination method in the power supply scheme according to any one of claims 1 to 4.

Images