Verification method and device and related equipment

Abstract

The invention provides a verification method and device and related equipment. The method comprises the steps that conversion relation mapping information, module design information of a functional module and system-on-chip design information of a system-on-chip are acquired; the conversion relation mapping information is used for indicating a mapping relation of each module in the functional module converted to a hierarchical instance name of the system on chip; generating an actual connection relation table and a target connection relation table based on the conversion relation mapping information, the module design information of the functional module and the on-chip system design information of the on-chip system; the actual connection relation table is used for indicating the actual connection relation between the modules of the corresponding function modules in the system on chip, and the target connection relation table is used for indicating the target connection relation between the modules of the corresponding function modules in the system on chip; and comparing the actual connection relation table with the target connection relation table, and determining the connection correctness between the modules of the corresponding functional modules in the system on chip. According to the method, the connection correctness between the modules of the corresponding functional modules in the system on chip can be confirmed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip technical field, and in particular, to a verification method and device and related equipment. BACKGROUND

[0002] With the increase of the scale and complexity of a system on chip (SOC), more and more functional modules, which can also be referred to as intellectual property cores (IP cores), are integrated into the SOC. In order to optimize power consumption, area and back-end layout, the modules inside the functional modules can be "scattered" and re-divided into different hierarchical structures of the SOC, but the connection relationship between the modules after re-division still needs to be ensured unchanged. In the SOC, if the hierarchical division or the connection relationship of the modules of the functional modules is wrong, the correctness of the functions of the functional modules will be directly affected.

[0003] Under this background, how to provide a verification method to confirm the connection correctness between the modules of the corresponding functional modules in the SOC has become a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0004] Therefore, embodiments of the present application provide a verification method, device and related equipment to confirm the connection correctness between the modules of the corresponding functional modules in the SOC.

[0005] To achieve the above object, embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, embodiments of the present application provide a verification method applied to an SOC, the SOC integrating a functional module, the functional module including a plurality of modules, and the method including:

[0007] obtaining transformation relationship mapping information, module design information of the functional module and SOC design information of the SOC; the transformation relationship mapping information being used to indicate a mapping relationship of conversion of each module in the functional module to a hierarchical instance name of the SOC;

[0008] generating an actual connection relationship table and a target connection relationship table based on the transformation relationship mapping information, the module design information of the functional module and the SOC design information of the SOC; the actual connection relationship table being used to indicate an actual connection relationship between the modules of the corresponding functional module in the SOC, and the target connection relationship table being used to indicate a target connection relationship between the modules of the corresponding functional module in the SOC;

[0009] comparing the actual connection relationship table with the target connection relationship table to confirm the connection correctness between the modules of the corresponding functional module in the SOC.

[0010] Optionally, the generating the actual connection relationship table and the target connection relationship table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip comprises:

[0011] The generating the initial target connection relationship table and the actual connection relationship table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip.

[0012] The generating the target connection relationship table based on the conversion relationship mapping information, the initial target connection relationship table and the actual connection relationship table.

[0013] Optionally, the generating the initial target connection relationship table and the actual connection relationship table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip comprises:

[0014] The generating the first mapping table and the second mapping table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip; the first mapping table is used for indicating the mapping relationship between the hierarchical instance name of the functional module level and the module name, and the second mapping table is used for indicating the mapping relationship between the hierarchical instance name of the system-on-chip level and the module name.

[0015] The generating the first input signal table and the second input signal table based on the conversion relationship mapping information, the module design information of the functional module, the system-on-chip design information of the system-on-chip, the first mapping table and the second mapping table.

[0016] The generating the first shell file and the second shell file based on the module design information of the functional module and the system-on-chip design information of the system-on-chip.

[0017] The generating the initial target connection relationship table and the actual connection relationship table based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file and the second shell file.

[0018] Optionally, the comparing the actual connection relationship table with the target connection relationship table to confirm the connection correctness between the modules corresponding to the functional module in the system-on-chip comprises:

[0019] If the actual connection relationship table is consistent with the target connection relationship table, it indicates that the connection between the modules corresponding to the functional module in the system-on-chip is correct.

[0020] If the actual connection relationship table is not consistent with the target connection relationship table, it indicates that the connection between the modules corresponding to the functional module in the system-on-chip is incorrect.

[0021] Optionally, the generating the first mapping table and the second mapping table based on the conversion relationship mapping information, the module design information of the functional module, and the system-on-chip design information of the system-on-chip comprises:

[0022] The first mapping table is generated based on the conversion relationship mapping information and the module design information of the functional module corresponding to the hierarchical instance name of the functional module level.

[0023] The second mapping table is generated based on the conversion relationship mapping information and the system-on-chip design information of the system-on-chip corresponding to the hierarchical instance name of the system-on-chip level.

[0024] Optionally, the generating the first input signal table and the second input signal table based on the conversion relationship mapping information, the module design information of the functional module, the system-on-chip design information of the system-on-chip, the first mapping table, and the second mapping table comprises:

[0025] The first target hierarchical instance name and the second target hierarchical instance name are determined based on the conversion relationship mapping information, wherein the first target hierarchical instance name is used to indicate the hierarchical instance name of the functional module level, and the second target hierarchical instance name is used to indicate the hierarchical instance name of the system-on-chip level.

[0026] The first target module name corresponding to the first target hierarchical instance name and the second target module name corresponding to the second target hierarchical instance name are determined based on the first mapping table and the second mapping table.

[0027] The first input signal table and the second input signal table are generated based on the module design information of the functional module, the system-on-chip design information of the system-on-chip, the first target module name, and the second target module name.

[0028] Optionally, the determining the first target module name corresponding to the first target hierarchical instance name and the second target module name corresponding to the second target hierarchical instance name based on the first mapping table and the second mapping table comprises:

[0029] The first target module name corresponding to the first target hierarchical instance name is determined based on the first mapping table.

[0030] The second target module name corresponding to the second target hierarchical instance name is determined based on the second mapping table.

[0031] Optionally, the first input signal table and the second input signal table are generated based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, and the first target module name and the second target module name, and the first input signal table and the second input signal table are generated based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, and the first target module name and the second target module name.

[0032] The first input signal table is generated by extracting the input signal corresponding to the first target module name from the module design information of the functional module.

[0033] The second input signal table is generated by extracting the input signal corresponding to the second target module name from the system-on-chip design information of the system-on-chip.

[0034] Optionally, the initial target connection relationship table and the actual connection relationship table are generated based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file and the second shell file.

[0035] The initial target connection relationship table is generated by determining the output signal corresponding to the input signal of the first input signal table from the first shell file based on the first mapping table and the first input signal table.

[0036] The actual connection relationship table is generated by determining the output signal corresponding to the input signal of the second input signal table from the second shell file based on the second mapping table and the second input signal table.

[0037] Optionally, the first shell file and the second shell file are generated based on the module design information of the functional module and the system-on-chip design information of the system-on-chip.

[0038] The original internal logic corresponding to the module name in the first mapping table in the module design information of the functional module is removed, and the output signal is set to 0, and the remaining module design information of the functional module is taken as the first shell file.

[0039] The original internal logic corresponding to the module name in the second mapping table in the system-on-chip design information of the system-on-chip is removed, and the output signal is set to 0, and the remaining system-on-chip design information of the system-on-chip is taken as the second shell file.

[0040] In a second aspect, an embodiment of the present application provides a verification device applied to a system-on-chip, the system-on-chip integrated with a functional module, the functional module including a plurality of modules, and the device including:

[0041] The obtaining module is configured to obtain conversion relationship mapping information, module design information of the functional module and system-on-chip design information of the system-on-chip; the conversion relationship mapping information is used to indicate the mapping relationship of the conversion of each module in the functional module to the hierarchical instance name of the system-on-chip.

[0042] The generating module is configured to generate an actual connection relationship table and a target connection relationship table based on the conversion relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip; the actual connection relationship table is used to indicate actual connection relationships between modules of the corresponding functional module in the system on chip; and the target connection relationship table is used to indicate target connection relationships between modules of the corresponding functional module in the system on chip.

[0043] The comparing module is configured to compare the actual connection relationship table with the target connection relationship table to confirm the connection correctness between the modules of the corresponding functional module in the system on chip.

[0044] In a third aspect, an electronic device is provided, including at least one memory and at least one processor, the memory storing one or more computer-executable instructions, and the processor invoking the one or more computer-executable instructions to perform the verification method in the first aspect.

[0045] In a fourth aspect, a storage medium is provided, the storage medium storing one or more computer-executable instructions, and the one or more computer-executable instructions being executed to implement the verification method in the first aspect.

[0046] In a fifth aspect, a computer program product is provided, including one or more computer-executable instructions, and the one or more computer-executable instructions being executed to implement the verification method in the first aspect.

[0047] The embodiments of the present application provide a verification method, device and related equipment, and the method includes: obtaining conversion relationship mapping information, module design information of a functional module, and system on chip design information of a system on chip; the conversion relationship mapping information is used to indicate mapping relationships of each module in the functional module converted to a hierarchical instance name of the system on chip; generating an actual connection relationship table and a target connection relationship table based on the conversion relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip; the actual connection relationship table is used to indicate actual connection relationships between modules of the corresponding functional module in the system on chip; and the target connection relationship table is used to indicate target connection relationships between modules of the corresponding functional module in the system on chip; and comparing the actual connection relationship table with the target connection relationship table to confirm the connection correctness between the modules of the corresponding functional module in the system on chip.

[0048] It can be seen that the verification method provided by the embodiment of the present application uses the conversion relationship mapping information, the module design information of the functional module and the system on chip design information of the system on chip as the basis to generate the actual connection relationship table and the target connection relationship table, so that the connection correctness between the modules corresponding to the functional module in the system on chip can be confirmed by comparing the actual connection relationship table with the target connection relationship table.

[0049] Further, the verification method provided by the embodiment of the present application can carry out the inspection work after the functional module is integrated into the system on chip, effectively avoids the problem that the rework occurs in the subsequent research and development process due to the error of the connection relationship between the modules after integration, significantly accelerates the research and development iteration cycle and the overall project progress of the system on chip project, and provides a strong guarantee for the efficient research and development of the system on chip. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiment or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0051] Figure 1 is a conversion structure diagram of the conversion from the intellectual property core level to the system on chip level provided by the embodiment of the present application;

[0052] Figure 2 is an optional flow diagram of the verification method provided by the embodiment of the present application;

[0053] Figure 3 is an optional flow diagram of step S200 provided by the embodiment of the present application;

[0054] Figure 4 is an optional flow diagram of step S210 provided by the embodiment of the present application;

[0055] Figure 5 is an optional structure diagram of the connection relationship between the modules provided by the embodiment of the present application;

[0056] Figure 6 is an optional flow diagram of step S212 provided by the embodiment of the present application;

[0057] Figure 7 is an optional structure diagram of the verification device provided by the embodiment of the present application;

[0058] Figure 8 is an optional block diagram of the electronic device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0060] As described in the background, with the increase of the scale and complexity of a system on chip (SOC), more and more functional modules, which can also be referred to as intellectual property cores (IP cores), are integrated into the system on chip. In order to optimize power consumption, area and back-end layout, the modules inside the functional module can be "scattered" and re-divided into different hierarchical structures of the system on chip, but the connection relationship between the modules still needs to be ensured unchanged after re-division. In the system on chip, if the hierarchical division or the connection relationship of the modules of the functional module is wrong, the correctness of the function of the functional module will be directly affected.

[0061] For ease of understanding, reference is made to Figure 1 An example of the conversion structure diagram of the conversion of the functional module hierarchical structure to the system on chip hierarchical structure is shown in FIG. 1. Figure 1 As shown in FIG. 1, the functional module A includes three modules B, C and D. After the functional module A is integrated into the system on chip M, the module B is divided into the module O in the module N, the module C is divided into the module P, and the module D is divided into the module Q. The signal connection relationship of the three modules B, C and D after the conversion of the functional module hierarchical structure to the system on chip hierarchical structure needs to be kept unchanged.

[0062] In an optional implementation, whether the connection relationship between the modules after the integration of the functional module into the system on chip is wrong can be verified by manual work, or after the integration of the system on chip is completed, whether the connection relationship between the modules is wrong can be confirmed by the way of the simulation of the whole system on chip, that is, if the simulation has functional error, it can be deduced that the connection relationship between the modules is wrong after the integration of the IP core into the system on chip.

[0063] The inventors believe that, as the complexity of the functional module increases, the number of connection signals between the internal modules will be extremely large. If a manual verification method is used to check whether the connection relationship between the modules is incorrect, a large amount of time and labor cost will be consumed. Moreover, for the relatively complex functional module at present, it is extremely difficult to rely on the manual verification method to check the correctness of all signal connection relationships, and usually only part of the key signals can be checked. This checking method cannot comprehensively cover all signals, and there is a potential risk for the unexamined signals. At the same time, even if the signals are manually verified, there may be omissions due to human negligence.

[0064] If the overall simulation of the system on a chip is used to confirm whether the connection relationship between the modules is incorrect, many problems will also be encountered. On the one hand, the overall simulation of the system on a chip needs the basic functions of the entire system on a chip to be complete, which means that it has to wait until the project is in a relatively late stage. In this way, once a problem is found, the time is already late, which will cause the overall iteration cycle of the project to be lengthened. On the other hand, due to the large size of the system on a chip, it will take a considerable amount of time to locate the root cause of the problem after the problem is found in the simulation process, which will also adversely affect the project schedule. In addition, the overall simulation of the system on a chip mainly focuses on the overall functional behavior of the system on a chip, and it is difficult to ensure that it can comprehensively cover and check the connection relationship between all the internal modules of the functional module, and there is also a risk of omission.

[0065] Therefore, the embodiments of the present application provide a verification method, device and related equipment, wherein the method comprises: obtaining conversion relationship mapping information, module design information of a functional module and system on a chip design information of a system on a chip; the conversion relationship mapping information is used to indicate the mapping relationship of the conversion of each module in the functional module to the hierarchical instance name of the system on a chip; based on the conversion relationship mapping information, the module design information of the functional module and the system on a chip design information of the system on a chip, an actual connection relationship table and a target connection relationship table are generated; the actual connection relationship table is used to indicate the actual connection relationship between the modules of the corresponding functional module in the system on a chip, and the target connection relationship table is used to indicate the target connection relationship between the modules of the corresponding functional module in the system on a chip; the actual connection relationship table and the target connection relationship table are compared to confirm the connection correctness between the modules of the corresponding functional module in the system on a chip.

[0066] It can be seen that the verification method provided by the embodiments of the present application uses the conversion relationship mapping information, the module design information of the functional module and the system on a chip design information of the system on a chip as the basis to generate the actual connection relationship table and the target connection relationship table, so that the connection correctness between the modules of the corresponding functional module in the system on a chip can be confirmed by comparing the actual connection relationship table and the target connection relationship table.

[0067] Further, the verification method provided by the embodiments of the present application can carry out inspection work after the functional module is integrated into the system on chip, effectively avoiding the problem of rework in the subsequent research and development process due to the connection relationship between modules after integration, significantly speeding up the research and development iteration cycle and overall project progress of the system on chip, and providing a strong guarantee for efficient research and development of the system on chip.

[0068] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments of the present application.

[0069] Reference Figure 2 , Figure 2 is an optional flowchart of the verification method provided by the embodiments of the present application. The verification method can be applied to a system on chip, the system on chip integrates a functional module, the functional module includes a plurality of modules, such as Figure 2 As shown in the figure, the method can include the following steps:

[0070] Step S100, obtaining transformation relationship mapping information, module design information of the functional module and system on chip design information of the system on chip.

[0071] The transformation relationship mapping information is used to indicate the mapping relationship of the conversion of each module in the functional module to the hierarchical instance name of the system on chip. For example, the functional module includes a plurality of modules, such as Figure 1 For example, the conversion structure diagram of the functional module hierarchy to the system on chip hierarchy is exemplarily shown, and the corresponding transformation relationship mapping information can be shown as follows in Table 1.

[0072] Table 1: Transformation relationship mapping information table

[0073] Hierarchical instance name of the functional module hierarchy module Hierarchical instance name of the system-on-chip hierarchy module A.B M.N.O.B A.C M.P.C A.D M.Q.D

[0074] The module design information of the functional module can be, for example, a register transfer level file of the functional module, and the system on chip design information of the system on chip can be, for example, a register transfer level file of the system on chip. The register transfer level file of the functional module describes the hardware behavior of a specific functional module (such as a processor, an interface controller, etc.), emphasizes functional independence and interface standardization, and is usually used as a reusable design unit. The register transfer level file of the system on chip is the top-level design of the entire chip, integrates multiple functional modules, and realizes system-level functions through bus architecture, clock domain management, etc., and focuses on the cooperation between modules. The module design information of the functional module and the system on chip design information of the system on chip together constitute the core of the integrated circuit design. The module design information of the functional module provides basic functional modules, and the system on chip design information of the system on chip realizes a complex system through hierarchical integration.

[0075] With reference to Figure 1 , the step S200 is continued, and based on the transformation relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip, an actual connection relationship table and a target connection relationship table are generated.

[0076] The actual connection relationship table is used to indicate the actual connection relationship between the modules of the corresponding functional module in the system on chip, and the target connection relationship table is used to indicate the target connection relationship between the modules of the corresponding functional module in the system on chip.

[0077] The present application uses the transformation relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip as the basis to generate the actual connection relationship table and the target connection relationship table, so that the connection correctness between the modules of the corresponding functional module in the system on chip can be confirmed by comparing the actual connection relationship table with the target connection relationship table.

[0078] In an optional implementation, with reference to Figure 3 An optional flowchart of the step S200 is exemplarily shown, as shown in Figure 3 The step S200, based on the transformation relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip, to generate an actual connection relationship table and a target connection relationship table, can include the following steps:

[0079] The step S210, based on the transformation relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip, to generate an initial target connection relationship table and an actual connection relationship table.

[0080] The initial target connection relationship table indicates the actual connection relationship between the modules of the functional module. The actual connection relationship table indicates the actual connection relationship between the modules of the corresponding functional module in the system on chip.

[0081] Specifically, referring to Figure 4 An optional flowchart of step S210 is exemplarily shown as Figure 4 As shown, step S210, based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip, generating an initial target connection relationship table and an actual connection relationship table, can include the following steps:

[0082] Step S211, based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip, generating a first mapping table and a second mapping table.

[0083] The first mapping table is used to indicate the mapping relationship between the hierarchical instance name of the functional module level and the module name, and the second mapping table is used to indicate the mapping relationship between the hierarchical instance name of the system-on-chip level and the module name.

[0084] In a specific implementation, based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip, generating a first mapping table and a second mapping table can include: based on the conversion relationship mapping information, extracting the module name corresponding to the hierarchical instance name of the functional module level from the module design information of the functional module, to generate the first mapping table; based on the conversion relationship mapping information, extracting the module name corresponding to the hierarchical instance name of the system-on-chip level from the system-on-chip design information of the system-on-chip, to generate the second mapping table.

[0085] In this application, the first mapping table and the second mapping table are generated in the same way. Taking the generation of the second mapping table as an example, the mapping relationship between the hierarchical instance name and the module name can be established by parsing the hierarchical structure of the hierarchical instance name (such as M.N.O.B) and tracing back the module name corresponding to each instance name layer by layer. For example, taking the hierarchical instance name M.N.O.B as an example, M.N.O.B indicates that module B is located in the sub-level of module O, module O is located in the sub-level of module N, and so on. The hierarchical instance name M.N.O.B can be split according to the hierarchical structure (for example, split into M.N.O.B, M.N.O, and M.N), and then for each level, the module name corresponding to the instance name of the level is found from the code of the system-on-chip design information of the system-on-chip corresponding to the module of the previous level, thereby generating the second mapping table.

[0086] Taking the hierarchical instance name of the system-on-chip level module in Table 1 as an example, the generated second mapping table can be shown in Table 2 as follows.

[0087] Table 2: Second mapping table

[0088] Hierarchical instance name of the system-on-chip hierarchy module Module name M.N.O.B Module_B M.N.O Module_O M.N Module_N M.P.C Module_C M.P Module_P M.Q.D Module_D M.Q Module_Q

[0089] Referring to Figure 4 , step S212 is continued to generate the first input signal table and the second input signal table based on the conversion relationship mapping information, the module design information of the functional module, the system on chip design information of the system on chip, the first mapping table, and the second mapping table.

[0090] Since the input and the output between the modules are in a one-to-one correspondence, as shown in Figure 5 , the output 0, the output 1, and the output 2 of the module B correspond to the input 0, the input 1, and the input 2 of the module C respectively, and the output 3, the output 4, and the output 5 of the module C correspond to the input 3, the input 4, and the input 5 of the module B respectively, so that the connection relationship between the modules can be uniquely determined by extracting only the input signal. At the same time, it can also avoid the same connection relationship being repeatedly recorded due to the extraction of the input signal and the output signal at the same time.

[0091] Specifically, referring to Figure 6 , an optional flowchart of step S212 is exemplarily shown, as shown in Figure 6 , step S212, based on the conversion relationship mapping information, the module design information of the functional module, the system on chip design information of the system on chip, the first mapping table, and the second mapping table, to generate the first input signal table and the second input signal table, can include the following steps:

[0092] Step S2121, based on the conversion relationship mapping information, determines the first target hierarchical instance name and the second target hierarchical instance name that need to be converted.

[0093] The first target hierarchical instance name is used to indicate the hierarchical instance name of the functional module level, and the second target hierarchical instance name is used to indicate the hierarchical instance name of the system on chip level.

[0094] Step S2122, based on the first mapping table and the second mapping table, determines the first target module name corresponding to the first target hierarchical instance name and the second target module name corresponding to the second target hierarchical instance name.

[0095] In a specific implementation, the determination of the first target module name corresponding to the first target hierarchical instance name and the second target module name corresponding to the second target hierarchical instance name based on the first mapping table and the second mapping table can include: determining the first target module name corresponding to the first target hierarchical instance name based on the first mapping table; and determining the second target module name corresponding to the second target hierarchical instance name based on the second mapping table.

[0096] In step S2123, the first input signal table and the second input signal table are generated based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, and the first target module name and the second target module name.

[0097] In a specific implementation, the first input signal table and the second input signal table are generated based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, and the first target module name and the second target module name, which can include: extracting the input signal corresponding to the first target module name from the module design information of the functional module to generate the first input signal table; and extracting the input signal corresponding to the second target module name from the system-on-chip design information of the system-on-chip to generate the second input signal table.

[0098] Taking the system-on-chip level as an example, the generated second input signal table can be shown in Table 3 as follows.

[0099] Table 3: Second input signal table

[0100] Input signal of the system-on-chip hierarchy module M.N.O.B.signal0 … M.N.O.B.signalN M.P.C.signal0 … M.P.C.signalN M.Q.D.signal0 … M.Q.D.signalN

[0101] Reference Figure 4 , and step S213 is continued to be executed to generate the first shell file and the second shell file based on the module design information of the functional module and the system-on-chip design information of the system-on-chip.

[0102] The embodiments of the present application can significantly simplify the internal complexity of the module by generating the first shell file and the second shell file based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, and only the topological structure of the interface signal is retained, thereby facilitating the subsequent efficient extraction of the connection relationship between the modules and the rapid verification of the correctness and integrity of the connection relationship.

[0103] In an optional implementation, the first shell file and the second shell file are generated based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, which can include: removing the original internal logic of the functional module design information corresponding to the module name in the first mapping table and setting the output signal to 0, and taking the remaining functional module design information as the first shell file; and removing the original internal logic of the system-on-chip design information corresponding to the module name in the second mapping table and setting the output signal to 0, and taking the remaining system-on-chip design information as the second shell file.

[0104] The hardware behavior of the functional module described in the module design information of the functional module can include complex timing logic, combinational logic or state machine, and direct analysis of the signal connection relationship thereof needs to deal with various dynamic scenarios (such as conditional branching, signal competition and the like). By converting it into the first shell file, the original internal logic of the module is removed, and the output signal is set to 0, which can improve the subsequent verification efficiency. For example, in the first shell file, all output signals of the module are fixed to 0, so it is only necessary to match the signal connection to 0 to quickly judge whether the signal is an input signal of the module. At the same time, it is not necessary to track the dynamic propagation path of the signal in the module, and it is only necessary to focus on the topological connection of the interface signal.

[0105] Similarly, the system-on-chip design information of the system-on-chip is the top-level design of the entire chip, integrates a plurality of functional modules and realizes system-level functions through bus architecture, clock domain management and the like, and the internal logic of the module is relatively complex. If no conversion is performed, subsequent extraction of the signal connection relationship needs to deal with many different complex situations, which will result in a very complicated processing process. Therefore, the original internal logic corresponding to the module name in the first mapping table in the system-on-chip design information of the system-on-chip needs to be removed, and the output signal is set to 0. In this way, when the signal connection relationship is extracted, it is only necessary to match the 0 value connection to judge that the signal is the corresponding input signal in the connection relationship, thereby speeding up the extraction speed of the signal connection relationship.

[0106] Reference Figure 4 , continue to perform step S214, and generate an initial target connection relationship table and an actual connection relationship table based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file and the second shell file.

[0107] In a specific implementation, the generating of the initial target connection relationship table and the actual connection relationship table based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file and the second shell file can include: determining the output signal corresponding to the input signal of the first input signal table from the first shell file based on the first mapping table and the first input signal table, and generating the initial target connection relationship table; and determining the output signal corresponding to the input signal of the second input signal table from the second shell file based on the second mapping table and the second input signal table, and generating the actual connection relationship table.

[0108] In the present application, the initial target connection relationship table and the actual connection relationship table are generated in the same way. Taking the generation of the actual connection relationship table as an example, the input signal of the hierarchical module can be traversed recursively, and the corresponding output signal can be tracked to establish the connection relationship table. Taking the input signal M.N.O.B.signal0 as an example, the hierarchical structure is analyzed, the upper hierarchical instance name (for example, M.N.O), the current instance name (for example, B), and the current input signal (for example, signal0) are extracted, then the corresponding module name is found according to the upper hierarchical instance name information, then the connection relationship of the current input signal corresponding to the current instance name is found in the second shell file corresponding to the module name, and the connection of the signal in the module is determined according to the connection relationship.

[0109] The connection relationship can include the following three states:

[0110] (1) If the input signal is connected to the upper module input, the recursion continues to the upper module, and the connection relationship of the upper module is searched. For example, signal0 is connected to the upper module input M.N.O.signal1, and the upper hierarchical instance name is M.N, the current instance name is O, and the current input signal is signal1.

[0111] (2) If the input signal is connected to the input signal of other instances in the module, the recursion continues to the inside of the connection module, and the connection relationship of the inside of the connection module is searched. For example, signal0 is connected to M.N.O.C.signal1 in the module O, and the hierarchical instance name of the recursive layer is M.N.O.C, and the current input signal is signal1. The current instance name is not required when searching downward.

[0112] (3) If the input signal is driven by a preset statement (such as an assign statement), the final corresponding output signal is determined, and the output signal is output to the actual connection relationship table.

[0113] Taking the system-on-chip level as an example, the actual connection relationship table generated thereby can be shown in Table 4 as follows.

[0114] Table 4: Actual connection relationship table

[0115] Output signal Input signal M.N.O.B.signal0 M.P.C.signal0 M.P.C.signal1 M.N.O.B.signal1 M.N.O.B.signal2 M.Q.D.signal2 M.Q.D.signal3 M.N.O.B.signal3 M.P.C.signal4 M.Q.D.signal4 M.Q.D.signal5 M.P.C.signal5

[0116] It should be noted that, based on the first mapping table and the first input signal table, the output signal corresponding to the input signal of the first input signal table is determined from the first shell file, and the process of generating the initial target connection relationship table, since the module at the function module level is not located inside other modules, when the connection of the signal in the module is determined according to the connection relationship at the function module level, the connection can only include the above (2) and (3) two states.

[0117] Reference Figure 3 , continue to execute step S220, based on the conversion relationship mapping information, replace the hierarchical instance name in the initial target connection relationship table with the corresponding system-on-a-chip level hierarchical instance name, and generate a target connection relationship table.

[0118] After generating the initial target connection relationship table, the hierarchical instance name in the initial target connection relationship table can be replaced with the corresponding system-on-a-chip level hierarchical instance name based on the conversion relationship mapping information, thereby generating a target connection relationship table.

[0119] Reference Figure 2 , continue to execute step S300, compare the actual connection relationship table with the target connection relationship table, and confirm the connection correctness between the modules corresponding to the function modules in the system-on-a-chip.

[0120] By comparing the actual connection relationship table indicating the actual connection relationship between the modules corresponding to the function modules in the system-on-a-chip with the target connection relationship table indicating the target connection relationship between the modules corresponding to the function modules in the system-on-a-chip, the connection correctness between the modules corresponding to the function modules in the system-on-a-chip can be confirmed.

[0121] If the actual connection relationship table is consistent with the target connection relationship table, it indicates that the connection between the modules corresponding to the function modules in the system-on-a-chip is correct; if the actual connection relationship table is inconsistent with the target connection relationship table, it indicates that the connection between the modules corresponding to the function modules in the system-on-a-chip is incorrect.

[0122] It can be seen that the verification method provided by the embodiment of the application generates the actual connection relationship table and the target connection relationship table by using the conversion relationship mapping information, the module design information of the function module and the system-on-a-chip design information of the system-on-a-chip as the basis, so that the connection correctness between the modules corresponding to the function modules in the system-on-a-chip can be confirmed by comparing the actual connection relationship table with the target connection relationship table.

[0123] Further, the verification method provided by the embodiments of the present application can carry out checking work after the functional module is integrated into the system on chip, effectively avoids the problem that rework occurs in the subsequent research and development process due to the connection error between modules after integration, significantly speeds up the research and development iteration cycle and the overall project progress of the system on chip, and provides a strong guarantee for efficient research and development of the system on chip.

[0124] Next, the verification device provided by the embodiments of the present application is introduced. The verification device described below can be considered as a software function module or a hardware function module required to be set to implement the verification method provided by the embodiments of the present application. The content of the verification device described below can be mutually corresponding and referred to the method content described above.

[0125] In an optional implementation, Figure 7 An optional structural schematic diagram of the verification device provided by the embodiments of the present application is exemplarily shown as Figure 7 As shown in the figure, the verification device can include:

[0126] The acquisition module 11 is configured to acquire the conversion relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip; the conversion relationship mapping information is used to indicate the mapping relationship of the conversion of each module in the functional module to the hierarchical instance name of the system on chip;

[0127] The generation module 12 is configured to generate an actual connection relationship table and a target connection relationship table based on the conversion relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip; the actual connection relationship table is used to indicate the actual connection relationship between the modules of the corresponding functional module in the system on chip, and the target connection relationship table is used to indicate the target connection relationship between the modules of the corresponding functional module in the system on chip;

[0128] The comparison module 13 is configured to compare the actual connection relationship table and the target connection relationship table to confirm the connection correctness between the modules of the corresponding functional module in the system on chip.

[0129] Optionally, the actual connection relationship table and the target connection relationship table are generated based on the conversion relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip, and the generation includes:

[0130] Generating an initial target connection relationship table and an actual connection relationship table based on the conversion relationship mapping information, the module design information of the functional module, and the system on chip design information of the system on chip;

[0131] Replacing the hierarchical instance name in the initial target connection relationship table with the corresponding hierarchical instance name of the system on chip level based on the conversion relationship mapping information to generate the target connection relationship table.

[0132] Optionally, the generating the initial target connection relationship table and the actual connection relationship table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip comprises:

[0133] generating a first mapping table and a second mapping table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip; the first mapping table is used to indicate a mapping relationship between a hierarchical instance name of a functional module level and a module name; and the second mapping table is used to indicate a mapping relationship between a hierarchical instance name of a system-on-chip level and a module name;

[0134] generating a first input signal table and a second input signal table based on the conversion relationship mapping information, the module design information of the functional module, the system-on-chip design information of the system-on-chip, the first mapping table and the second mapping table;

[0135] generating a first shell file and a second shell file based on the module design information of the functional module and the system-on-chip design information of the system-on-chip;

[0136] generating the initial target connection relationship table and the actual connection relationship table based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file and the second shell file.

[0137] Optionally, the comparing the actual connection relationship table with the target connection relationship table to confirm the connection correctness between the modules corresponding to the functional module in the system-on-chip comprises:

[0138] if the actual connection relationship table is consistent with the target connection relationship table, it indicates that the connection between the modules corresponding to the functional module in the system-on-chip is correct;

[0139] if the actual connection relationship table is not consistent with the target connection relationship table, it indicates that the connection between the modules corresponding to the functional module in the system-on-chip is incorrect.

[0140] Optionally, the generating the first mapping table and the second mapping table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip comprises:

[0141] extracting a module name corresponding to a hierarchical instance name of a functional module level from the module design information of the functional module based on the conversion relationship mapping information to generate the first mapping table;

[0142] extracting a module name corresponding to a hierarchical instance name of a system-on-chip level from the system-on-chip design information of the system-on-chip based on the conversion relationship mapping information to generate the second mapping table.

[0143] Optionally, the generating the first input signal table and the second input signal table based on the conversion relationship mapping information, the module design information of the functional module, the system on chip design information of the system on chip, the first mapping table, and the second mapping table comprises:

[0144] determining the first target hierarchical instance name and the second target hierarchical instance name that need to be converted based on the conversion relationship mapping information, wherein the first target hierarchical instance name is used to indicate a hierarchical instance name at a functional module level, and the second target hierarchical instance name is used to indicate a hierarchical instance name at a system on chip level;

[0145] determining the first target module name corresponding to the first target hierarchical instance name and the second target module name corresponding to the second target hierarchical instance name based on the first mapping table and the second mapping table;

[0146] generating the first input signal table and the second input signal table based on the module design information of the functional module, the system on chip design information of the system on chip, and the first target module name and the second target module name.

[0147] Optionally, the determining the first target module name corresponding to the first target hierarchical instance name and the second target module name corresponding to the second target hierarchical instance name based on the first mapping table and the second mapping table comprises:

[0148] determining the first target module name corresponding to the first target hierarchical instance name based on the first mapping table;

[0149] determining the second target module name corresponding to the second target hierarchical instance name based on the second mapping table.

[0150] Optionally, the generating the first input signal table and the second input signal table based on the module design information of the functional module, the system on chip design information of the system on chip, and the first target module name and the second target module name comprises:

[0151] extracting an input signal corresponding to the first target module name from the module design information of the functional module to generate the first input signal table;

[0152] extracting an input signal corresponding to the second target module name from the system on chip design information of the system on chip to generate the second input signal table.

[0153] Optionally, the generating the initial target connection relationship table and the actual connection relationship table based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file, and the second shell file comprises:

[0154] determine, based on the first mapping table and the first input signal table, an output signal corresponding to an input signal of the first input signal table from the first shell file, to generate an initial target connection relationship table;

[0155] determine, based on the second mapping table and the second input signal table, an output signal corresponding to an input signal of the second input signal table from the second shell file, to generate an actual connection relationship table.

[0156] Optionally, the generating the first shell file and the second shell file based on the module design information of the functional module and the system-on-chip design information of the system-on-chip comprises:

[0157] removing original internal logic corresponding to a module name in the first mapping table in the module design information of the functional module, and setting an output signal as 0, to take the remaining module design information of the functional module as the first shell file;

[0158] removing original internal logic corresponding to a module name in the second mapping table in the system-on-chip design information of the system-on-chip, and setting an output signal as 0, to take the remaining system-on-chip design information of the system-on-chip as the second shell file.

[0159] It can be seen that the verification device provided in the embodiments of the present application takes the transformation relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip as the basis to generate the actual connection relationship table and the target connection relationship table, so that the connection correctness between the modules corresponding to the functional module in the system-on-chip can be confirmed by comparing the actual connection relationship table with the target connection relationship table.

[0160] The embodiments of the present application also provide an electronic device, which can include at least one memory and at least one processor, the memory stores one or more computer executable instructions, and the processor invokes the one or more computer executable instructions to execute the verification method as described above.

[0161] As an optional implementation, reference is made to Figure 8 , Figure 8 is an optional block diagram of the electronic device provided in the embodiments of the present application. As shown in Figure 8 , the electronic device can include at least one processor 10, at least one communication interface 20, at least one instruction memory 30 and at least one communication bus 40.

[0162] In the embodiments of the present application, the number of the processor 10, the communication interface 20, the instruction memory 30 and the communication bus 40 is at least one, and the processor 10, the communication interface 20 and the instruction memory 30 complete the communication with each other through the communication bus 40.

[0163] Optionally, the processor 10 can be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a NPU (Neural-network Processing Unit), a FPGA (Field Programmable Gate Array), a TPU (Tensor Processing Unit), an AI chip, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application, etc.

[0164] Optionally, the communication interface 20 can be an interface of a communication module for network communication.

[0165] The instruction memory 30 can include a high-speed RAM memory, and can also include a non-volatile memory such as at least one disk memory. The instruction memory 30 stores one or more computer executable instructions, and the processor 10 invokes the one or more computer executable instructions to execute the verification method as described above.

[0166] The embodiments of the present application also provide a storage medium storing one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the verification method as described above.

[0167] The embodiments of the present application also provide a computer program product, which can include one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the verification method as described above.

[0168] The above describes the multiple embodiment schemes provided by the embodiments of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending multiple possible embodiment schemes, which can be considered as the embodiments disclosed and disclosed by the embodiments of the present application.

[0169] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A verification method, characterized in that: Applied to a system on chip, the system on chip integrates a functional module, the functional module includes multiple modules, and the method includes: Acquire conversion relationship mapping information, module design information of the functional module, and system-on-chip design information of the system-on-chip; the conversion relationship mapping information is used to indicate the mapping relationship between each module in the functional module and the hierarchical instance name of the system-on-chip; Based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip, an actual connection relationship table and a target connection relationship table are generated; the actual connection relationship table is used to indicate the actual connection relationship between modules of the corresponding functional modules in the system-on-chip, and the target connection relationship table is used to indicate the target connection relationship between modules of the corresponding functional modules in the system-on-chip; The actual connection relationship table is compared with the target connection relationship table to confirm the correctness of the connection between modules of corresponding functional modules in the system on chip.

2. The verification method according to claim 1, wherein: The generating of the actual connection relationship table and the target connection relationship table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip includes: Generate an initial target connection relationship table and an actual connection relationship table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip; Based on the conversion relationship mapping information, the hierarchical instance names in the initial target connection relationship table are replaced with the hierarchical instance names of the corresponding system-on-chip layers to generate a target connection relationship table.

3. The verification method according to claim 2, wherein: The generating of the initial target connection relationship table and the actual connection relationship table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip includes: Based on the conversion relationship mapping information, the module design information of the functional module, and the system-on-chip design information of the system-on-chip, a first mapping table and a second mapping table are generated; the first mapping table is used to indicate the mapping relationship between the hierarchical instance name and the module name at the functional module level, and the second mapping table is used to indicate the mapping relationship between the hierarchical instance name and the module name at the system-on-chip level; Generate a first input signal table and a second input signal table based on the conversion relationship mapping information, the module design information of the functional module, the system-on-chip design information of the system-on-chip, the first mapping table, and the second mapping table; generating a first shell file and a second shell file based on the module design information of the functional module and the system-on-chip design information of the system-on-chip; An initial target connection relationship table and an actual connection relationship table are generated based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file, and the second shell file.

4. The verification method according to claim 1, wherein: The comparing the actual connection relationship table with the target connection relationship table to confirm the correctness of the connection between modules of corresponding functional modules in the system on chip includes: If the actual connection relationship table is consistent with the target connection relationship table, it indicates that the connections between modules of the corresponding functional modules in the system on chip are correct; If the actual connection relationship table is inconsistent with the target connection relationship table, it indicates that the connection between modules of the corresponding functional modules in the system on chip is wrong.

5. The verification method according to claim 3, wherein: The generating of the first mapping table and the second mapping table based on the conversion relationship mapping information, the module design information of the functional module and the system-on-chip design information of the system-on-chip includes: Based on the conversion relationship mapping information, extracting module names corresponding to hierarchical instance names of the functional module hierarchy from the module design information of the functional module to generate a first mapping table; Based on the conversion relationship mapping information, module names corresponding to hierarchical instance names of the system-on-chip hierarchy are extracted from the system-on-chip design information of the system-on-chip to generate a second mapping table.

6. The verification method according to claim 3, characterized in that: The generating of the first input signal table and the second input signal table based on the conversion relationship mapping information, the module design information of the functional module, the system-on-chip design information of the system-on-chip, the first mapping table, and the second mapping table includes: Based on the conversion relationship mapping information, determining a first target hierarchical instance name and a second target hierarchical instance name that need to be converted; wherein the first target hierarchical instance name is used to indicate a hierarchical instance name at a functional module level, and the second target hierarchical instance name is used to indicate a hierarchical instance name at a system-on-chip level; Determining, based on the first mapping table and the second mapping table, a first target module name corresponding to the first target hierarchical instance name and a second target module name corresponding to the second target hierarchical instance name; A first input signal table and a second input signal table are generated based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, as well as the first target module name and the second target module name.

7. The verification method according to claim 6, characterized in that: The determining, based on the first mapping table and the second mapping table, a first target module name corresponding to the first target hierarchical instance name and a second target module name corresponding to the second target hierarchical instance name includes: Determining, based on the first mapping table, a first target module name corresponding to the first target hierarchical instance name; Based on the second mapping table, a second target module name corresponding to the second target hierarchical instance name is determined.

8. The verification method according to claim 6, wherein: The generating of the first input signal table and the second input signal table based on the module design information of the functional module and the system-on-chip design information of the system-on-chip, as well as the first target module name and the second target module name, comprises: extracting input signals corresponding to the first target module name from the module design information of the functional module, and generating a first input signal table; Input signals corresponding to the second target module name are extracted from the system-on-chip design information of the system-on-chip to generate a second input signal table.

9. The verification method according to claim 3, wherein: The generating of the initial target connection relationship table and the actual connection relationship table based on the first mapping table, the second mapping table, the first input signal table, the second input signal table, the first shell file and the second shell file includes: Based on the first mapping table and the first input signal table, determining the output signal corresponding to the input signal of the first input signal table from the first shell file, and generating an initial target connection relationship table; Based on the second mapping table and the second input signal table, output signals corresponding to input signals in the second input signal table are determined from the second shell file, and an actual connection relationship table is generated.

10. The verification method according to claim 3, characterized in that: The generating of the first shell file and the second shell file based on the module design information of the functional module and the system-on-chip design information of the system-on-chip includes: Removing the original internal logic corresponding to the module name in the first mapping table from the module design information of the functional module, setting the output signal to 0, and using the remaining module design information of the functional module as the first shell file; The original internal logic corresponding to the module name in the second mapping table in the SoC design information of the SoC is removed, and the output signal is set to 0, and the remaining SoC design information of the SoC is used as the second shell file.

11. A verification device, characterized in that: Applied to a system on chip, the system on chip is integrated with a functional module, the functional module includes multiple modules, and the device includes: An acquisition module is used to acquire conversion relationship mapping information, module design information of the functional module, and system-on-chip design information of the system-on-chip; the conversion relationship mapping information is used to indicate the mapping relationship between each module in the functional module and the hierarchical instance name of the system-on-chip; a generation module for generating an actual connection relationship table and a target connection relationship table based on the conversion relationship mapping information, the module design information of the functional module, and the system-on-chip design information of the system-on-chip; the actual connection relationship table is used to indicate the actual connection relationship between modules of corresponding functional modules in the system-on-chip, and the target connection relationship table is used to indicate the target connection relationship between modules of corresponding functional modules in the system-on-chip; The comparison module is used to compare the actual connection relationship table with the target connection relationship table to confirm the correctness of the connection between modules of corresponding functional modules in the system on chip.

12. An electronic device, characterized in that: The system comprises at least one memory and at least one processor, wherein the memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the verification method according to any one of claims 1 to 10.

13. A storage medium, characterized in that The storage medium stores one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, the verification method according to any one of claims 1 to 10 is implemented.

14. A computer program product, characterized in that The method comprises one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, the verification method according to any one of claims 1 to 10 is implemented.

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