Network loop detection method based on deep traversal, electronic equipment and storage medium

By constructing an adjacency list and using a depth-first search algorithm, the problem of rapid detection of network loops in printed circuit boards was solved, achieving efficient loop localization and problem localization.

CN120805830AActive Publication Date: 2025-10-17SHANGHAI UNIVISTA IND SOFTWARE GRP CO LTD +1

Patent Information

Application Number
CN202511317050.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-09-16
Publication Date
2025-10-17
Estimated Expiration
2045-09-16

AI Technical Summary

Technical Problem

Existing electronic design automation tools have difficulty in quickly and accurately identifying and locating network loops in printed circuit boards, which limits design iteration efficiency and reliability verification.

Method used

A network loop detection method based on depth-first traversal is adopted. By constructing an adjacency list and combining it with a depth-first search algorithm, a loop queue is obtained, and the loop queue is standardized to remove duplicates, thereby achieving fast and accurate location of network loops.

Benefits of technology

It enables rapid and accurate detection of network loops, improving design iteration efficiency and reliability verification effectiveness.

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Abstract

The invention relates to the technical field of electronic design automation, in particular to a network loop detection method based on deep traversal, electronic equipment and a storage medium, and the method comprises the steps: obtaining a node set and an edge set under a target network, constructing an adjacency list for each node, carrying out the traversal, obtaining a loop queue, carrying out the standardization processing, and removing repeated loops. All non-repeated standard loop queues are obtained; the standardization processing comprises the following steps: acquiring a unique identity identifier of each edge in a current loop queue; circularly shifting the edge corresponding to the unique identity label with the minimum value to the first position of the current loop queue to obtain a candidate loop queue; if the second element in the candidate loop queue is smaller than the last element, determining that the candidate loop queue is a standard loop queue after standardization processing; otherwise, all elements in the candidate loop queue are stored again according to a reverse sequence, then cyclic shift is executed, a standard loop queue is obtained, and all network loops can be rapidly detected.
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Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, in particular to a network loop detection method based on deep traversal, an electronic device and a storage medium. BACKGROUND

[0002] In printed circuit board (PCB) design, a network (Net) is used to represent a group of device pins, vias and interconnection traces with the same electrical potential, and its topology directly determines signal integrity and electrical performance. With the improvement of circuit integration and the popularity of high-speed signal design, the complexity of PCB wiring increases significantly, and cross-layer wiring and redundant connections frequently occur in multi-layer boards, which may form unintended closed conductive paths within the same network, i.e. network loops. Such loops are formed by repeated connections or redundant traces in the same network, although they do not break the electrical connectivity of the network, they essentially introduce an additional ring conductor structure. This structure is prone to form parasitic inductance effects under high-frequency signal transmission or transient current changes, which may induce electromagnetic interference enhancement, signal crosstalk aggravation and other problems, seriously affecting system stability and anti-interference ability.

[0003] Existing electronic design automation (EDA) tools mainly rely on network tables (Netlist) for electrical rule checking (ERC) and wiring connectivity verification, and their core logic focuses on the completeness of pin connections, but they lack effective criteria for determining whether there are redundant closed paths within the same network. Since network loops do not violate basic connection rules, conventional DRC (Design Rule Check) processes cannot identify such structural defects. Current detection methods mainly rely on manual visual inspection or preliminary screening based on simple geometric overlap, which is inefficient and prone to missed detection. Especially in high-density interconnection (HDI) or multi-layer board design, cross-layer wiring is complex and loop patterns are diverse, and there is a lack of automated and systematic detection mechanisms, which makes it difficult to quickly and accurately identify and locate the specific position and constituent path of network loops, seriously affecting design iteration efficiency and reliability verification process. Therefore, there is an urgent need for a network loop detection method that is fast and can accurately locate. SUMMARY

[0004] To solve the above technical problems, the technical solution adopted by the present application is: a network loop detection method based on deep traversal, comprising the following steps: S100, obtaining a node set and an edge set under a target network, wherein the nodes in the node set are pins, vias or intersection points, and the edges in the edge set are traces between two nodes.

[0005] S300, constructing an adjacency list for each node according to the node set and the edge set; wherein each entry in the adjacency list records all adjacent nodes of the current node and edges connecting the node and each adjacent node.

[0006] S500, obtaining loop queues in the network by traversing the adjacency list, and performing standardization processing on each loop queue to obtain a standard loop queue, removing duplicate standard loop queues to obtain all non-duplicate standard loop queues; wherein the standardization processing comprises: S510, obtaining a unique identity of each edge in the current loop queue.

[0007] S530, cyclically shifting the edge corresponding to the unique identity with the minimum value to the first position of the current loop queue to obtain a candidate loop queue.

[0008] S550, if the second element in the candidate loop queue is smaller than the last element, the candidate loop queue is the standard loop queue after standardization processing; otherwise, all elements in the candidate loop queue are stored in reverse order and then S530 is executed to obtain the standard loop queue.

[0009] In addition, the application further provides a non-transitory computer readable storage medium, wherein the storage medium stores at least one instruction or at least one program, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0010] In addition, the application further provides an electronic device comprising a processor and the above non-transitory computer readable storage medium.

[0011] The application has at least the following beneficial effects: The embodiment of the application provides a network loop detection method based on deep traversal, which can quickly detect all network loops in the network by establishing an adjacency list, obtaining loop queues by traversal, performing standardization processing on each loop queue to obtain a standard loop queue, removing duplicate standard loop queues, and obtaining all non-duplicate standard loop queues, thereby facilitating user positioning. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1A deep traversal-based network loop detection method flowchart is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0015] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meanings as commonly understood by a person of ordinary skill in the art.

[0016] Please refer to Figure 1 The embodiments of the present application provide a deep traversal-based network loop detection method flowchart, and the method comprises the following steps: S100, a node set and an edge set under a target network are acquired, a node in the node set is a pin, a via or a junction, and an edge in the edge set is a trace between two nodes.

[0017] Among them, the network (net) refers to a set of circuit nodes that are electrically connected to each other in network design, used to realize signal or power connection between specific device pins.

[0018] Among them, the pin (Pin) refers to the electrical access end point of an integrated circuit device, a discrete element or a connector on the package, which is the starting point or the end point of the network. Each pin has a unique identifier in the schematic diagram and corresponds to a metal pad or bump in the physical layout.

[0019] Among them, the via (Via) refers to a conductive structure for realizing vertical electrical connection between different conductive layers in a multi-layer printed circuit board (PCB) or integrated circuit interconnection layer. The via is usually formed by plating copper or filling conductive material on the inner wall of the hole, which can connect the traces of the same network in different layers.

[0020] Among them, the junction refers to a geometric connection point where three or more traces intersect in the same conductive layer or multi-layer wiring, used to realize electrical merging of multiple branch paths. The junction is not an independent physical structure, but a logical node in the trace topology.

[0021] Among them, the trace (Trace) refers to a continuous conductive path for connecting two or more electrical nodes in a PCB or chip interconnection layer, usually composed of a metal wire formed by photolithography. The electrical nodes can be pins, vias or junctions.

[0022] The network loop refers to a closed current path formed by wiring or element connection in the same network.

[0023] In S300, an adjacency list is constructed for each node according to the node set and the edge set; each entry in the adjacency list records all adjacent nodes of the current node and the edges connecting the node and each adjacent node.

[0024] It should be noted that there can be multiple edges between two nodes, so both edges and nodes are considered when designing the adjacency list. As an example, when there are two wires eid1 and eid2 between node NodeA and node NodeB, the entry of node NodeA in the adjacency list is {NodeA,{{NodeB,eid1},{NodeB,eid2}}}, and the entry of node NodeB in the adjacency list is {NodeB,{{NodeA,eid1},{NodeA,eid2}}}.

[0025] In an embodiment, the adjacency list is constructed based on an undirected graph model to record the bidirectional connection relationship between nodes. The electrical connection relationship in the target network is abstracted into an undirected graph model, in which pins, vias, and intersections are nodes of the graph, and wires are edges connecting the nodes. The graph model is represented by constructing an adjacency list data structure, which provides a basis for subsequent depth-first traversal and loop detection.

[0026] In S500, the adjacency list is traversed to obtain loop queues in the network, and each loop queue is standardized to obtain a standard loop queue. The repeated standard loop queues are removed to obtain all non-repeated standard loop queues.

[0027] In an embodiment, the algorithm for traversing the adjacency list is depth-first search (DFS), breadth-first search (BFS), or Tarjan algorithm. Other types of algorithms for traversing the adjacency list to obtain loops are within the protection scope of the present application.

[0028] The loop queue refers to the wires in the detected loop being arranged in sequence according to their adjacent relationship in the closed current path in the traversal direction, forming a wire sequence representing the topology of the loop.

[0029] The purpose of the standard loop queue is to remove duplicates. Since the same network loop can generate different wire sequences at different traversal starting points or directions, to avoid repeated identification, the detected loop path is standardized, so that different loop queues of the same loop are aligned to the same loop queue under the action of standardization, which is used for loop deduplication and storage.

[0030] Further, the step of the standardization processing comprises: S510, obtaining a unique identity of each edge in the current loop queue.

[0031] In an embodiment, the unique identity of each edge is pre-allocated when the network topology model is constructed, for uniquely identifying the trace between any two nodes; the identity remains unchanged in the entire loop detection process, to support subsequent path recording, standardization processing, etc.

[0032] S530, circularly shifting the edge corresponding to the unique identity with the minimum value to the first position of the current loop queue, to obtain a candidate loop queue.

[0033] Wherein, the circular shift can ensure that the relative position relationship between each edge in the loop queue remains unchanged.

[0034] As an example, when the original loop queue is {66, 55, 77, 88}, the candidate loop queue obtained after the minimum number 55 is circularly shifted to the left is {55, 77, 88, 66}, and the relative position relationship of each element in the loop queue remains unchanged.

[0035] S550, if the second element in the candidate loop queue is less than the last element, the candidate loop queue is the standard loop queue after the standardization processing; otherwise, all elements in the candidate loop queue are stored in reverse order, and then S530 is executed to obtain the standard loop queue.

[0036] It should be noted that the standardization processing is required after each loop is detected, and when the same standard loop queue is found, it is no longer stored repeatedly. Wherein, S530 can solve the repetition problem caused by different starting points, and S550 can eliminate the two representations of the same loop caused by different traversal directions, such as clockwise or counterclockwise, thereby realizing complete deduplication in a true sense and ensuring that the same loop is recorded only once.

[0037] As an example, when the candidate loop queue is {55, 77, 88, 66}, since the second element in the candidate loop queue is greater than the last element, it is stored in reverse order to obtain {66, 88, 77, 55}, and then S530 is executed according to {66, 88, 77, 55} to obtain {55, 66, 88, 77}, which is the final standard loop queue.

[0038] In one embodiment, the step of traversing in S500 comprises: employing a depth-first search algorithm to traverse the adjacency list, starting from any unvisited node, recursively visiting its adjacent nodes, and recording the sequence of nodes and edges in the traversal path; when the adjacent node of a certain node has been visited, it is determined that there is a loop in the network.

[0039] In one embodiment, in order to further improve the efficiency and accuracy of loop detection, a fast criterion based on local topology is introduced in the traversal process. Before the traversal in S500, the following steps are further included: S51, the network is divided into multiple connected components, each connected component representing a set of nodes that are electrically connected to each other; independent loop detection is performed based on the topology of each connected component. It should be noted that a connected component is a set of nodes that are connected to each other in a graph, and nodes within the same connected component can reach each other through an edge sequence, while nodes between different components are not connected.

[0040] S52, the number of nodes N and the number of edges M contained in each connected component are counted respectively.

[0041] S53, loop detection is performed for each connected component, and if N>M, it is determined that there is no loop in the current connected component, and the next connected component is directly traversed.

[0042] It should be noted that the above method can reduce the number of invalid traversals, improve the detection accuracy and efficiency.

[0043] As an example, taking a ring composed of a node NodeA, a node NodeB, a node NodeC, and the node NodeA as an example, wherein an edge between the node NodeA and the node NodeB is eid1, an edge between the node NodeB and the node NodeC is eid2, and an edge between the node NodeC and the node NodeA is eid3. Wherein, an adjacency list of the node NodeA is {NodeA, {NodeB, eid1}, {NodeC, eid3}}, an adjacency list of the node NodeB is {NodeB, {NodeA, eid1}, {NodeC, eid2}}, and an adjacency list of the node NodeC is {NodeC, {NodeB, eid2}, {NodeA, eid3}}. It is assumed that the ring is exactly one connected component, and before the traversal starts, a node queue and an edge queue are initialized as empty. DFS traversal is performed on the current connected component to detect the ring. Since the number of nodes is 3 and the number of edges is 3, both are equal, and thus the traversal is performed. First, the node NodeA is visited, and the node NodeA is put into the node queue {NodeA}, the adjacency list of the node NodeA is traversed, and {NodeB, eid1} is processed first. The node NodeB is visited, and since the node NodeB has not been visited, the node NodeB is put into the node queue to obtain a new node queue {NodeA, NodeB}, and eid1 is put into the path queue to obtain a new path queue {eid1}; the adjacency list of the node NodeB is traversed: {NodeA, eid1} and {NodeC, eid2}, since the node NodeA is a parent node, it is skipped; since the node NodeC has not been visited, the next step is processed. The node NodeC is visited, the node NodeC is put into the node queue to obtain a new node queue {NodeA, NodeB, NodeC}, and eid2 is put into the edge queue to obtain a new edge queue {eid1, eid2}; the adjacency list of the node NodeC is traversed: {NodeB, eid2} and {NodeA, eid3}, since the node NodeB is a parent node, it is skipped; since the node NodeA is already in the node queue and is not a parent node, a ring is found at this time. If the current ring constitutes a closed path, eid3 is put into the edge queue to obtain a new edge queue {eid1, eid2, eid3}, and the edge queue is the ring path.

[0044] In an embodiment, before the traversal, the node with a degree of 1 is excluded as the initial traversal starting point in S500, and the traversal is only started for the node with a degree greater than 1. It should be noted that since each node in the loop must be connected to at least two different wires, i.e., the degree is greater than or equal to 2, the node with a degree of 1 cannot participate in forming a closed path. Therefore, before the traversal, the degree of all nodes is counted, and only the node with a degree greater than 1 is used as the traversal starting point of the potential loop area. In this way, meaningless search can be avoided, and the detection efficiency can be significantly improved. It should be noted that although the node with a degree of 1 is not used as the starting point, if the path passes through such a node during the traversal of other nodes, the connection relationship of the node will still be normally accessed and recorded to ensure the integrity of the network topology.

[0045] In an embodiment, the method further comprises: S400, applying Tarjan algorithm to identify the cut point and the bridge in the network, and decomposing the network into a plurality of biconnected components; for each biconnected component, S500 is performed respectively to detect the loop. As an example, in order to better understand the cut point, two loops are taken as an example: the node connection order of the first loop is node NodeA, node NodeB, node NodeC and node NodeA in turn; the node connection order of the second loop is node NodeA, node NodeD, node NodeE and node NodeA in turn; wherein, the first loop and the second loop share the node NodeA, and the node NodeA is a cut point. As another example, in order to better understand the bridge, two loops are taken as an example: the node connection order of the first loop is node NodeA, node NodeB, node NodeC and node NodeA in turn; node NodeA is connected to node NodeF, and the node connection order of the second loop is node NodeF, node NodeD, node NodeE and node NodeF in turn; wherein, the first loop and the second loop share the bridge composed of node NodeA and node NodeF.

[0046] In summary, the embodiment of the present application provides a network loop detection method based on deep traversal, which establishes an adjacency list and combines traversal to obtain a loop queue, and standardizes each loop queue to obtain a standard loop queue, removes duplicate standard loop queues, and obtains all non-duplicate standard loop queues. Through this method, all network loops in the network can be quickly detected, and the user can easily locate the problem.

[0047] The embodiment of the present application further provides a non-transitory computer readable storage medium, which can be arranged in an electronic device to store at least one instruction or at least one program for implementing a method related to the method in the method embodiment, and the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided by the above embodiment.

[0048] The embodiment of the present application further provides an electronic device, comprising a processor and the aforementioned non-transitory computer readable storage medium.

[0049] The embodiment of the present application further provides a computer program product, which comprises program codes, and when the program product is run on an electronic device, the program codes are used to make the electronic device execute the steps in the method according to various exemplary embodiments of the present application described in the specification.

[0050] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the above-described functions.

[0051] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, but not for limiting the scope of the present application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A network loop detection method based on deep traversal, characterized in that: The method comprises the following steps: S100, obtaining a node set and an edge set in a target network, wherein a node in the node set is a pin, a via, or an intersection, and an edge in the edge set is a line between two nodes; S300, constructing an adjacency list for each node based on the node set and the edge set; wherein each entry in the adjacency list records all adjacent nodes of the current node and the edges connecting the node and each adjacent node; S500: traverse the adjacency table to obtain loop queues in the network, perform standardization processing on each loop queue to obtain a standard loop queue, remove duplicate standard loop queues, and obtain all non-duplicate standard loop queues; wherein the standardization processing step includes: S510, obtaining a unique identifier for each edge in the current loop queue; S530, cyclically shifting the edge corresponding to the unique identifier with the smallest value to the first position in the current loop queue to obtain a candidate loop queue; S550, if the second element in the candidate loop queue is smaller than the last element, the candidate loop queue is a standard loop queue after normalization; otherwise, all elements in the candidate loop queue are stored again in reverse order and then S530 is executed to obtain a standard loop queue.

2. The method according to claim 1, characterized in that In S500, the traversal step includes: using a depth-first search algorithm to traverse the adjacency list, starting from any unvisited node, recursively visiting its adjacent nodes, and recording the node sequence and edge sequence in the traversal path; when the adjacent node of a certain node has been visited, it is determined that there is a loop in the network.

3. The method according to claim 1, characterized in that In S500, before traversal, the following steps are also included: S51, dividing the network into a plurality of connected components, each connected component representing a set of nodes electrically connected to each other; performing independent loop detection based on the topological structure of each connected component; S52, counting the number of nodes N and the number of edges M contained in each connected component respectively; S53, traverse and detect loops for each connected component. If N>M is satisfied, it is determined that there is no loop in the current connected component, and the current connected component is skipped directly and the next connected component is traversed.

4. The method according to claim 1, wherein In S500 , before traversal, nodes with a degree of 1 are excluded as initial traversal starting points, and traversal is only started for nodes with a degree greater than 1.

5. The method according to claim 1, wherein The method further includes: S400, applying the Tarjan algorithm to identify cut points and bridges in the network, and decomposing the network into a plurality of biconnected components; and executing S500 for loop detection for each biconnected component.

6. The method according to claim 1, characterized in that In S500, the algorithm for traversing the adjacency list is depth-first search, breadth-first search or Tarjan algorithm.

7. The method according to claim 1, characterized in that The unique identity of each edge is pre-assigned when the network topology model is constructed. It is used to uniquely identify the route between any two nodes. This identity remains unchanged throughout the loop detection process.

8. The method according to claim 1, characterized in that The adjacency table in S300 is constructed based on an undirected graph model and is used to record bidirectional connection relationships between nodes.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

Citation Information

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