Synaptic plastic mechanism bionic circuit based on memristor

Abstract

The invention discloses a synaptic plastic mechanism bionic circuit based on a memristor, and relates to the technical field of bionic circuits, the bionic circuit comprises a synaptic enhancement module, a synaptic suppression module, a steady-state window control module, a synaptic conductance updating module and a synaptic unit; the design method of the circuit comprises the following steps: firstly, determining the amplitude of a positive voltage pulse applied to the memristor, designing a synaptic conductance updating module and a synaptic enhancement and suppression module according to the amplitude, generating a pulse signal capable of controlling the memristor conductance, connecting the signal with the memristor synaptic through the synaptic conductance updating module, and generating a memristor synaptic signal; and if the curve can be fitted with a biological synaptic plastic mechanism, the process is ended, and otherwise, the circuit is redesigned. The bionic circuit provided by the invention has low requirements on neuron signals before and after memristive synapse, the fitting precision of the simulated synapse plastic mechanism is higher, the dynamic range of the learning rate is wider, and the pulse width and the steady-state window can be more accurately controlled by introducing the steady-state window control module.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of bionic circuit, in particular to a synapse plasticity mechanism bionic circuit based on memristor. BACKGROUND

[0002] In today's era of rapid development of science and technology, the cross field of neuroscience and electronic engineering is giving birth to many breakthrough innovations. As the most sophisticated and complex information processing system in nature, the brain transmits and stores information between neurons through synapses. Synaptic plasticity, which refers to the dynamic adjustment of synaptic connection strength based on neuronal activity, is considered as the core mechanism of high-level cognitive functions such as learning and memory.

[0003] With the deepening of the mystery of the brain, researchers are committed to simulating this magical biological process at the hardware level, which has given rise to the study of bionic circuits based on memristors. As a new type of electronic component with resistance memory characteristics, in 2008, Hewlett-Packard Laboratory developed the first titanium oxide-based thin film memristor physical model, confirming Professor Chua's conjecture in 1971 that there is a fourth basic circuit element - memristor in addition to resistance, capacitance, and inductance. Memristor has unique properties such as nonlinearity, passivity, and non-volatility when power is off. When the two ends of the memristor are subjected to the same pulse stimulation as the neural synapse, the conductance change is very similar to the change in synaptic weight. Therefore, the memristor is considered an ideal device for simulating artificial neural synapses.

[0004] In recent years, in order to better explain the learning and memory functions of the biological brain, the spike-timing-dependent plasticity (STDP) learning rule has been proposed, which is a mechanism for regulating synaptic strength in the brain through the relative time of presynaptic and postsynaptic pulses. It is the theoretical basis for biological neural networks to learn and adapt to external disturbances. Researchers exploring brain-like bionic chips began to build synapse circuits based on memristors and implement the STDP learning function. However, artificial synapse circuits based on memristors, like traditional COMS synapse circuits, have the problem of single simulation type and unsatisfactory fitting effect.

[0005] Chinese patent CN110428050A discloses a synapse bionic circuit based on memristor to implement diversified STDP learning rules, including an enhancement module, an inhibition module, and a memristor synapse module. The enhancement module and the inhibition module output different signals to the memristor synapse module through the time sequence and time interval of the input signals, respectively. The memristor synapse module changes the conductance of the memristor accordingly by receiving the signals, thereby simulating the synaptic plasticity mechanism. SUMMARY

[0006] The technical problem solved by the present application is to provide a synaptic plasticity mechanism bionic circuit with higher precision and smaller fitting error.

[0007] To solve the above technical problems, the technical solution adopted by the present application is:

[0008] The synaptic plasticity mechanism bionic circuit based on the memristor is characterized in that the bionic circuit is divided into an excitatory synaptic plasticity mechanism bionic circuit and an inhibitory synaptic plasticity mechanism bionic circuit; the excitatory synaptic plasticity mechanism bionic circuit comprises a synaptic potentiation module, a synaptic depression module, a synaptic conductance update module and a memristive synapse unit; the inhibitory synaptic plasticity mechanism bionic circuit comprises a synaptic potentiation module, a synaptic depression module, a steady-state window control module, a synaptic conductance update module and a memristive synapse unit.

[0009] The steady-state window module generates voltage pulse enable signals for controlling the synaptic potentiation module and the synaptic depression module through the arrival order and time interval of presynaptic and postsynaptic neuron signals, the synaptic potentiation module and the synaptic depression module generate positive pulse voltage signals for enhancing and inhibiting the memristive synaptic conductance respectively, and the synaptic conductance update module outputs voltage pulses for changing the memristive synaptic conductance by receiving the positive pulse voltage signals output by the synaptic potentiation module and the synaptic depression module.

[0010] Preferably, the synaptic potentiation module of the inhibitory synaptic plasticity mechanism bionic circuit comprises two enhancement signal Enhance1 and Enhance2 generation circuits corresponding to the cases of -20us≤△t<0 and 0<△t≤20us respectively.

[0011] The pre-synaptic neuron signal Pre is connected to the 2-input end of the first NAND gate after being connected to the parallel resistance R8 and the capacitor C5, the enable signal Pre_enable is connected to the parallel resistance R10 after being connected to the first inverter, the output end of the first inverter is connected to the 1-input end of the first NAND gate, the output end of the first NAND gate is connected to the gate of the P-channel transistor M1, the source of the M1 is connected to the 5V power supply, and the drain of the M1 is connected to the resistance R1, the capacitor C1 and the 3-pin of the four-way analog switch U2 respectively; the 2-pin of the U2 is connected to the 3-pin of the four-way analog switch U1, the 1-pin of the U2 is connected to the steady-state window control module and receives the signal Enable_Enhance1; the 1-pin of the U1 receives the post-synaptic neuron signal Post, the 2-pin of the U1 is connected to the resistance R2, the capacitor C2 and the same direction input end of the first comparator respectively, and the other ends of the R2 and C2 are grounded; the reverse input end of the first comparator receives the reference voltage Vthr, the positive power supply pin of the first comparator is connected to the 5V power supply, and the resistance R5 is connected between the output end and the positive power supply pin, the negative power supply pin of the first comparator is grounded, the output end of the first comparator is connected to the parallel capacitor C9 and serves as one output end of the synaptic enhancement module, and the output signal is Enhance1.

[0012] The post-synaptic neuron signal Post is connected to the 5-input end of the second NAND gate after being connected to the parallel resistance R7 and the capacitor C6, the enable signal Post_enable is connected to the parallel resistance R6 after being connected to the second inverter, the output end of the second inverter is connected to the 4-input end of the second NAND gate, the output end of the second NAND gate is connected to the gate of the P-channel transistor M2, the source of the M2 is connected to the 5V power supply, and the drain of the M2 is connected to the resistance R3, the capacitor C3 and the 6-pin of the four-way analog switch U2 respectively; the 7-pin of the U2 is connected to the 6-pin of the four-way analog switch U1, the 8-pin of the U2 is connected to the steady-state window control module and receives the signal Enable_Enhance1; the 8-pin of the U1 receives the pre-synaptic neuron signal Pre, the 7-pin of the U1 is connected to the resistance R4, the capacitor C4 and the same direction input end of the second comparator respectively, and the other ends of the R4 and C4 are grounded; the reverse input end of the second comparator receives the reference voltage Vthr, the positive power supply pin of the second comparator is connected to the 5V power supply, and the resistance R98 is connected between the output end and the positive power supply pin, the negative power supply pin of the second comparator is grounded, the output end of the second comparator is connected to the parallel capacitor C10 and serves as the other output end of the synaptic enhancement module, and the output signal is Enhance2.

[0013] Preferably, the steady-state window control module of the inhibitory synaptic plasticity mechanism simulation circuit is responsible for generating a voltage pulse enable signal by receiving pre-synaptic and post-synaptic neuron signals, so as to control the working state of the synaptic enhancement module and the synaptic inhibition module; the specific circuit is as follows:

[0014] The pre-synaptic neuron signal Pre is connected to the 3-port of the third inverter and the 3-port of the fourth inverter respectively, the output of the third inverter is connected to the gate of the P-channel transistor M3, the source of the M3 is connected to the 5V power supply, the drain of the M3 is connected to the capacitor C31, the resistor R31 and the non-inverted input of the third comparator respectively, the other end of the C31 and R31 is grounded; the inverted input of the third comparator is connected to the reference voltage Vthr40μs, the positive power supply pin is connected to the 5V power supply and is connected to the output of the third comparator through the resistor R32, the negative power supply pin is grounded, the output of the third comparator is connected to the 1-port of the first XOR gate after being connected to the capacitor C32 in parallel, the 2-port of the first XOR gate receives the signal Enable_Enhance1, the output of the first XOR gate outputs the signal Enable_Inhibite1; the output of the fourth NAND gate is connected to the gate of the P-channel transistor M4, the source of the M4 is connected to the 5V power supply, the drain of the M4 is connected to the capacitor C41, the resistor R41 and the non-inverted input of the fourth comparator respectively, the other end of the C41 and R41 is grounded; the inverted input of the fourth comparator is connected to the reference voltage Vthr20μs, the positive power supply pin is connected to the 5V power supply and is connected to the output of the fourth comparator through the resistor R42, the negative power supply pin is grounded, the output of the fourth comparator outputs the signal Enable_Enhance1 after being connected to the capacitor C42 in parallel;

[0015] The post-synaptic neuron signal Post is connected to the 3-port of the fifth inverter and the 3-port of the sixth inverter respectively, the output of the fifth inverter is connected to the gate of P-channel transistor M5, the source of M5 is connected to 5V power supply, the drain of M5 is connected to capacitor C51, resistor R51 and the same-phase input of the fifth comparator respectively, the other end of C51 and R51 is grounded; the reverse input of the fifth comparator is connected to reference voltage Vthr40μs, the positive power pin is connected to 5V power supply and is connected to the output of the fifth comparator through resistor R52, the negative power pin is grounded, the output of the fifth comparator is connected to the 1-port of the second XOR gate through capacitor C52 in parallel, the 2-port of the second XOR gate receives signal Enable_Enhance2, the output of the second XOR gate is connected to capacitor C95 in parallel and outputs signal Enable_Inhibite2; the output of the sixth NAND gate is connected to the gate of P-channel transistor M6, the source of M6 is connected to 5V power supply, the drain of M6 is connected to capacitor C61, resistor R61 and the same-phase input of the sixth comparator respectively, the other end of C61 and R61 is grounded; the reverse input of the sixth comparator is connected to reference voltage Vthr20μs, the positive power pin is connected to 5V power supply and is connected to the output of the sixth comparator through resistor R62, the negative power pin is grounded, the output of the sixth comparator outputs signal Enable_Enhance2 through capacitor C62 in parallel.

[0016] Preferably, the synaptic inhibition module of the inhibitory synaptic plasticity mechanism simulation circuit comprises two inhibitory signal Inhibite1 and Inhibite2 generation circuits.

[0017] The input end of the presynaptic neuron signal Pre is connected with the 1 port of the seventh inverter and the 3 port of the eighth inverter respectively, the output end of the seventh inverter is connected with the gate of the P-channel transistor M7, the source of the M7 is connected with the 5V power supply, the drain of the M7 is connected with the resistor R71, the capacitor C71 and the inverting input end of the seventh comparator respectively, the other end of the C71 and R71 is grounded; the non-inverting input end of the seventh comparator receives the reference voltage VthrContrl, the positive power supply pin is connected with the 5V voltage and connected with the output end of the seventh comparator through the resistor R72, the negative power supply pin is grounded, the output end of the seventh comparator is connected with the 2 port of the third XOR gate; the 1 port of the third XOR gate receives the signal Enable_Enhance2, the output end of the third XOR gate is connected with the 2 port of the first AND gate; the 1 port of the first AND gate receives the signal Enable_Inhibite2, the output end of the first AND gate outputs the signal Inhibite_PW2; the output end of the eighth inverter is connected with the gate of the P-channel transistor M8, the source of the M8 is connected with the 5V power supply, the drain of the M8 is connected with the resistor R81, the capacitor C81 and the 3 pin of the four-way analog switch U3 respectively, the other end of the R81 and C81 is grounded; the 2 pin of the U3 is connected with the resistor R82, the capacitor C82 and the non-inverting input end of the eighth comparator respectively, the inverting input end of the eighth comparator receives the reference voltage Vthr_Inhibite, the positive power supply pin of the eighth comparator is connected with the 5V voltage and connected with the output end of the eighth comparator through the resistor R83, the output end of the eighth comparator is connected with the capacitor C83 in parallel and outputs the signal Inhibite1, the other end of the C83 is grounded;

[0018] The post-synaptic neuron signal Post is connected to the 3rd port of the ninth inverter and the 3rd port of the tenth inverter respectively; the output of the ninth inverter is connected to the gate of P-channel transistor M9, the source of M9 is connected to 5V voltage, the drain of M9 is connected to resistor R91, capacitor C91 and the 6th pin of four-way analog switch U3 respectively, the other ends of R91 and C91 are grounded; the 7th pin of U3 is connected to resistor R92, capacitor C92 and the non-inverting input of the ninth comparator respectively, the other ends of R92 and C92 are grounded; the inverting input of the ninth comparator receives reference voltage Vthr_Inhibite, the positive power pin of the ninth comparator is connected to 5V power supply and connected to the output of the ninth comparator through resistor R93, the negative power pin is grounded, the output of the ninth comparator is connected to capacitor C93 in parallel to output signal Inhibite2, the other end of C93 is grounded; the output of the tenth inverter is connected to the gate of P-channel transistor M10, the source of M10 is connected to 5V voltage, the drain of M10 is connected to capacitor C101, resistor R101 and the inverting input of the tenth comparator respectively, the other ends of C101 and R101 are grounded; the non-inverting input of the tenth comparator receives reference voltage VthrContrl, the positive power pin of the tenth comparator is connected to 5V voltage and connected to the output of the tenth comparator through resistor R102, the negative power pin is grounded, the output of the tenth comparator is connected to capacitor C102 in parallel and then connected to the 2nd port of the fourth XOR gate, the 1st port of the fourth XOR gate receives signal Enable_Enhance1, the output of the fourth XOR gate is connected to the 5th port of the second AND gate, the 4th port of the second AND gate receives signal Enable_Inhibite1, the output of the second AND gate outputs signal Inhibite_PW1.

[0019] The 1st pin of U3 receives signal Inhibite_PW1, the 16th pin receives post-synaptic neuron signal Post, the 9th pin receives presynaptic neuron signal Pre, the 8th pin receives signal Inhibite_PW2, the 14th pin is connected to the drain of M7, the 11th pin is connected to the drain of M10, the 10th and 15th pins are grounded.

[0020] Preferably, the synaptic conductance updating module of the inhibitory synaptic plasticity mechanism simulation circuit is specifically as follows:

[0021] The 1 and 16 pins of the four-way analog switch U4 receive the Enhance1 signal, the 8 and 9 pins of the U4 receive the Enhance2 signal, the 3 and 11 pins of the U4 are connected to a 2V power supply, the 14 and 6 pins are grounded, the 15 and 7 pins output a signal Mem- as an output terminal, the 2 and 10 pins of the U4 are connected in parallel with a resistor R13 and a capacitor C8, and output a signal Mem+ as an output terminal;

[0022] The 1 and 16 pins of the four-way analog switch U5 receive the Inhibite1 signal, the 8 and 9 pins of the U4 receive the Inhibite2 signal, the 3 and 11 pins of the U4 are connected to a 0.13V power supply, the 14 and 6 pins are grounded, the 15 and 7 pins output a signal Mem+ as an output terminal, the 2 and 10 pins of the U4 are connected in parallel with a resistor R16 and a capacitor C12, and output a signal Mem- as an output terminal.

[0023] Preferably, all the four-way analog switches used in the bionic circuit use four-way analog switches of the ADG442 type, and the VDD pin is externally connected to a 15V voltage, the VSS pin is externally connected to a -15V voltage, and the ground pin is grounded.

[0024] Preferably, the design method of the circuit comprises the following steps:

[0025] 1) determining the amplitude of a positive voltage pulse applied to the memristive synapse, and the amplitude must exceed the working threshold of the memristor, and designing a memristive synapse conductance update module according to the amplitude to control the output of positive and negative voltage pulses;

[0026] 2) designing a voltage pulse generation circuit triggered by the pre-synaptic and post-synaptic neuron pulse time interval△t, including a synaptic enhancement circuit and a synaptic inhibition circuit, to generate a positive pulse voltage signal for enhancing or inhibiting the conductance of the memristive synapse, and the pulse width PW of the positive pulse voltage signal is modulated by△t;

[0027] 3) connecting the outputs of the synaptic enhancement circuit module and the synaptic inhibition circuit module to the memristive synapse conductance update module, when the synaptic enhancement circuit module has a voltage pulse signal output, the conductance update module will output a positive pulse with the same pulse width as the voltage pulse signal; conversely, when the synaptic inhibition circuit module has a voltage pulse signal output, the conductance update module will output a negative pulse with the same pulse width as the voltage pulse signal; the positive and negative pulses are signals measured with Mem- as the negative electrode and Mem+ as the positive electrode, and the absolute value of the amplitude is equal to the amplitude of the positive voltage pulse set in step 1);

[0028] 4) connecting the memristive synapse conductance update module to the memristive synapse, setting the memristive synapse to the same initial state, and changing△t to obtain the memristive conductance variable△G(△t) curve;

[0029] 5) using the model of the excitatory synaptic plasticity mechanism and the model of the inhibitory synaptic plasticity mechanism of the living being to fit the curve of △G(△t), if the fitting is successful, it indicates that the pulse waveforms of the pre-synaptic and post-synaptic neurons meet the requirements of the bionic circuit design, and the design is completed; otherwise, the parameters of the enhancement circuit module, the inhibition circuit module or the synaptic conductance update module are adjusted again, and the second step is continuously executed.

[0030] Preferably, when designing the bionic circuit of the excitatory synaptic plasticity mechanism, the relationship between △t and the pulse width PW of the positive pulse voltage signal needs to meet the following conditions: when △t<0, the synaptic enhancement circuit module is triggered to start working, and as |△t| decreases, the pulse width of the output voltage pulse becomes wider; when △t>0, the synaptic inhibition circuit module is triggered to start working, and as |△t| decreases, the pulse width of the output voltage pulse becomes wider.

[0031] When designing the bionic circuit of the inhibitory synaptic plasticity mechanism, the relationship between △t and the pulse width PW of the positive pulse voltage signal needs to meet the following conditions: when |△t| is smaller than the steady-state window t wisp , the synaptic enhancement circuit module is triggered to start working, and as |△t| decreases, the pulse width of the output voltage pulse becomes wider; when |△t| is larger than the steady-state window t wisp , the synaptic inhibition circuit module is triggered to start working, and as |△t| increases, the pulse width of the output voltage pulse increases and finally fixes to a certain value.

[0032] The technical scheme has the following beneficial effects:

[0033] The synaptic enhancement module and the synaptic inhibition module in the application can be realized by circuit design without complex waveforms, and the pre-synaptic and post-synaptic neuron waveforms can be directly simulated by square wave pulses.

[0034] The application uses a steady-state window control module to realize the synaptic enhancement module and the synaptic inhibition module in the bionic circuit of the inhibitory synaptic plasticity mechanism, which can accurately control the pulse width and the steady-state window, thereby obtaining a circuit with higher fitting degree and a wider learning rate dynamic range.

[0035] The synaptic conductance update module in the application is not limited to threshold symmetry or threshold asymmetry memristors through adjustable voltage parameters, and has better universality. BRIEF DESCRIPTION OF DRAWINGS

[0036] The application will be further described in detail below with reference to the drawings and specific embodiments.

[0037] Figure 1 (a) is a schematic diagram of the pulse time interval of the pre-synaptic and post-synaptic neurons according to the model of the excitatory synaptic plasticity mechanism of the living being;

[0038] Figure 1(b) is a schematic diagram of the change of the synaptic weight change amount of the biological excitatory synaptic plasticity mechanism model according to the present application with the time interval;

[0039] Figure 2 (a) is a schematic diagram of the pre-and post-synaptic neuron pulse time interval of the biological inhibitory synaptic plasticity mechanism model according to the present application;

[0040] Figure 2 (b) is a schematic diagram of the change of the synaptic weight change amount of the biological inhibitory synaptic plasticity mechanism model according to the present application with the time interval;

[0041] Figure 3 It is a design method schematic diagram of a synaptic plasticity mechanism biomimetic circuit based on a memristor according to the present application;

[0042] Figure 4 It is a biomimetic circuit block diagram of an inhibitory synaptic plasticity mechanism based on a memristor according to the present application;

[0043] Figure 5 It is a circuit principle diagram of a synaptic enhancement module and a synaptic conductance update module in the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0044] Figure 6 It is a circuit principle diagram of a steady state window control module in the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0045] Figure 7 It is a waveform of an enable signal output by the steady state window control module after the Pre signal input in the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0046] Figure 8 It is a circuit principle diagram of a synaptic inhibition module in the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0047] Figure 9 It is a waveform of a key signal in the synaptic inhibition module in the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0048] Figure 10 It is a change curve of the output signal pulse width under different reference voltages Vthr_Inhibite in the synaptic inhibition module in the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0049] Figure 11 (a) is a change curve of the memristor state variable in the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0050] Figure 11 (b) is a synaptic plasticity mechanism curve realized by the inhibitory synaptic plasticity mechanism biomimetic circuit according to the present application;

[0051] Figure 12 is the change of synaptic conductance under different △t of the inhibitory synaptic plasticity mechanism biomimetic circuit based on memristor proposed in the application;

[0052] Figure 13 is the schematic diagram of the excitatory synaptic plasticity mechanism biomimetic circuit based on memristor proposed in the application;

[0053] Figure 14 is the change curve of output signal pulse width under different reference voltages Vthr in the synaptic enhancement and inhibition module of the excitatory synaptic plasticity mechanism biomimetic circuit proposed in the application;

[0054] Figure 15 (a) is the change curve of the state variable of the memristor in the excitatory synaptic plasticity mechanism biomimetic circuit proposed in the application;

[0055] Figure 15 (b) is the synaptic plasticity mechanism curve realized by the excitatory synaptic plasticity mechanism biomimetic circuit proposed in the application;

[0056] Figure 16 is the change of synaptic conductance under different △t of the excitatory synaptic plasticity mechanism biomimetic circuit based on memristor proposed in the application. DETAILED DESCRIPTION

[0057] A synaptic plasticity mechanism biomimetic circuit based on memristor is proposed, which is first directed to the synaptic plasticity mechanism, that is, the change rule of synaptic weight, and the change of synaptic weight depends on the timing change of presynaptic and postsynaptic neuron signals. This change rule is called Spike-timing Dependent Plasticity (STDP), and a synaptic STDP mechanism model is proposed.

[0058] The biological excitatory synaptic plasticity mechanism model and the biological inhibitory synaptic plasticity mechanism model are included, and the biological excitatory synaptic plasticity mechanism can be represented by formula (1) and formula (2):

[0059]

[0060] wherein, is the change amount of excitatory synaptic weight; as Figure 1 (a) shows, Δt=t pre -t post is the pulse time interval of presynaptic excitatory neuron Pre-E and postsynaptic excitatory neuron Post-E, when Pre-E fires a pulse before Post-E, it is defined as Δt<0, and vice versa Δt>0; τ + =τ -=20ms represents the time constant; and Describe separately Current weight of the synapse According to the results of biological experiments, usually and The relationship between the two is satisfactory α is the asymmetry parameter; and are the learning rates when the presynaptic and postsynaptic spikes arrive, respectively; μ represents the effect of the weight change on the current weight degree of dependence.

[0061] When α=1, When the excitatory synaptic plasticity mechanism described The curve of the change with Δt is as follows: Figure 1 As shown. It can be seen that when Pre-E releases pulses before Post-E, Explaining excitatory synaptic weights Increase, on the contrary, decreases; in addition, as |Δt| becomes smaller, the excitatory synaptic weight The greater the change.

[0062] The biological inhibitory synaptic plasticity mechanism model is expressed by equations (3) and (8):

[0063]

[0064] When the presynaptic neuron i fires a spike:

[0065]

[0066] When the postsynaptic neuron j fires a spike:

[0067]

[0068] in, is the change in excitatory synaptic weight; τ isp is the decay time constant of the inhibitory synaptic plasticity mechanism trace variable, η is the learning rate, is the inhibition factor, and ρ0 represents the target firing rate of the postsynaptic neuron in Hz.

[0069] Biological inhibitory synaptic plasticity mechanisms such as Figure 2 As shown in Figure 2, it can be seen that each pair of presynaptic and postsynaptic pulses with different firing timings but the same firing time interval |Δt| produces almost the same change in the synaptic weight. In addition, when the firing times of the two neurons before and after the synapse are close to each other, making |Δt| less than the steady-state window t wispWhen the discharge time is close to the pre-synaptic neuron firing time, |Δt| is less than the steady state window t LTP (Δw IE > 0) and when the discharge time is far away from the pre-synaptic neuron firing time, |Δt| is greater than the steady state window t wisp When the discharge time is close to the pre-synaptic neuron firing time, |Δt| is less than the steady state window t LTD, and the synaptic weight change amount tends to a fixed value.

[0070] According to the above mechanism, as Figure 3 The application provides a design method of a synapse plasticity mechanism biomimetic circuit based on a memristor.

[0071] First, the amplitude of the positive voltage pulse applied to the memristor synapse is determined, and the amplitude must exceed the working threshold of the memristor, and a memristor synapse conductance update module is designed according to the amplitude to control the output of the positive and negative voltage pulses.

[0072] Second, a voltage pulse generation circuit triggered by the time interval △t of the pre-synaptic and post-synaptic neuron pulses is designed to realize the generation of a positive pulse voltage signal for enhancing or inhibiting the memristor synapse conductance, and the pulse width PW of the positive pulse voltage signal is modulated by △t. The circuit module for enhancing the memristor synapse conductance is referred to as a synapse enhancement module, and the circuit module for inhibiting the memristor synapse conductance is referred to as a synapse inhibition circuit module.

[0073] When designing the excitatory synapse plasticity mechanism biomimetic circuit, the relationship between △t and the pulse width PW of the positive pulse voltage signal needs to meet the following conditions: when △t < 0, the synapse enhancement circuit module is triggered to start working, and as |△t| decreases, the pulse width of the output voltage pulse becomes wider; when △t > 0, the synapse inhibition circuit module is triggered to start working, and as |△t| decreases, the pulse width of the output voltage pulse becomes wider.

[0074] When designing the inhibitory synapse plasticity mechanism biomimetic circuit, the relationship between △t and the pulse width PW of the positive pulse voltage signal needs to meet the following conditions: when |△t| is less than the steady state window t wisp , the synapse enhancement circuit module is triggered to start working, and as |△t| decreases, the pulse width of the output voltage pulse becomes wider; when |△t| is greater than the steady state window t wisp , the synapse inhibition circuit module is triggered to start working, and as |△t| increases, the pulse width of the output voltage pulse increases and finally fixes to a certain value.

[0075] Third, the output of the synaptic enhancement circuit module and the synaptic inhibition circuit module is connected with the memristor synaptic conductance update module, when the synaptic enhancement circuit module has a voltage pulse signal output, the conductance update module outputs a positive pulse with the same pulse width as the voltage pulse signal; on the contrary, when the synaptic inhibition circuit module has a voltage pulse signal output, the conductance update module outputs a negative pulse with the same pulse width as the voltage pulse signal.

[0076] Fourth, the memristor synaptic conductance update module is connected with the memristor synapse, and the memristor synapse is set to be in the same initial state, and the change of △t obtains the memristor conductance variable △G(△t) curve.

[0077] Fifth, the biological excitatory synaptic plasticity mechanism model and the inhibitory synaptic plasticity mechanism model are used to fit the △G(△t) curve, if the fitting is successful, it indicates that the pre-synaptic and post-synaptic neuron pulse waveform meets the requirements of the bionic circuit design, and the design is completed. Otherwise, the parameters of the enhancement circuit module, the inhibition circuit module or the memristor synaptic conductance update module are adjusted again, and the second step is continued to be executed.

[0078] As shown in Figure 4 The bionic circuit of the inhibitory synaptic plasticity mechanism in the synaptic plasticity mechanism bionic circuit based on the memristor includes a synaptic enhancement module, a synaptic inhibition module, a steady state window control module, a synaptic conductance update module and a memristor synapse unit, wherein the synaptic enhancement module and the synaptic inhibition module are both voltage pulse generation circuits triggered by △t, and generate positive pulse voltage signals for enhancing and inhibiting the conductance of the memristor synapse respectively, and the pulse width of the positive pulse voltage signal is controlled by △t; the steady state window control module is used to generate a voltage pulse enable signal for controlling the synaptic enhancement module and the synaptic inhibition module, so that the steady state window is always t wisp = set value, which is set to 20 μs in the embodiment, when |△t|≤20 μs, the steady state window control module generates an Enable_Enhance signal to make the synaptic enhancement module work, and at the same time, makes the synaptic inhibition module stop working; when |△t|>20 μs, the steady state window control module generates an Enable_Inhibite signal to make the synaptic inhibition module work, and at the same time, makes the synaptic enhancement module stop working. The synaptic conductance update module is used to output a voltage pulse for changing the conductance of the memristor synapse, when the enhancement circuit module has a voltage pulse signal output, the conductance update module outputs a positive pulse with the same pulse width as the voltage pulse signal; on the contrary, when the inhibition circuit module has a voltage pulse signal output, the conductance update module outputs a negative pulse with the same pulse width as the voltage pulse signal. The positive pulse and the negative pulse are signals measured with Mem- as the negative electrode and Mem+ as the positive electrode, and the absolute value of the amplitude is equal to the positive voltage pulse amplitude set in step 1).

[0079] The circuit principle diagram of the synaptic enhancement module is as shown in Figure 5As shown, the module includes two enhanced signal generation circuits, Enhance1 and Enhance2, corresponding to -20μs≤△t<0 and 0<△t≤20μs, respectively. When the steady-state window control module outputs Enable_Enhance1, the module outputs the Enhance1 enhanced signal; when the steady-state learning window control module outputs Enable_Enhance2, the module outputs the Enhance2 enhanced signal. The presynaptic neuron signal Pre is connected to the 2-input end of the first NAND gate through a parallel resistor R8 and a capacitor C5, the enable signal Pre_enable is connected to the first inverter through a parallel resistor R10, the output of the first inverter is connected to the 1-input end of the first NAND gate, the output of the first NAND gate is connected to the gate of a P-channel transistor M1, the source of M1 is connected to a 5V power supply, and the drain of M1 is connected to a resistor R1, a capacitor C1, and the 3-pin of a four-way analog switch U2, respectively; the 2-pin of U2 is connected to the 3-pin of a four-way analog switch U1, the 1-pin of U2 is connected to the steady-state window control module and receives the signal Enable_Enhance1; the 1-pin of U1 receives the postsynaptic neuron signal Post, the 2-pin of U1 is connected to a resistor R2, a capacitor C2, and the same direction input end of a first comparator, respectively, and the other ends of R2 and C2 are grounded; the reverse input end of the first comparator receives a reference voltage Vthr, the positive power supply pin of the first comparator is connected to a 5V power supply and is connected to the output end through a resistor R5, the negative power supply pin of the first comparator is grounded, the output end of the first comparator is connected to a capacitor C9 in parallel and serves as an output end of the synaptic enhancement module, outputting the signal Enhance1;

[0080] The output end of the second inverter is connected with the 4 input end of the second NAND gate, the output end of the second NAND gate is connected with the gate of the P-channel effect transistor M2, the source of M2 is connected with 5V power supply, and the drain of M2 is connected with the resistance R3, the capacitor C3 and the 6 pin of the four-way analog switch U2 respectively; the 7 pin of U2 is connected with the 6 pin of the four-way analog switch U1, the 8 pin of U2 is connected with the steady state window control module and receives the signal Enable_Enhance1; the 8 pin of U1 receives the presynaptic neuron signal Pre, the 7 pin of U1 is connected with the resistance R4, the capacitor C4 and the same direction input end of the second comparator respectively, and the other end of R4 and C4 is grounded; the reverse input end of the second comparator receives the reference voltage Vthr, the positive power supply pin of the second comparator is connected with 5V power supply, and is connected with the output end through the resistance R98, the negative power supply pin of the second comparator is grounded, the output end of the second comparator is connected with the capacitor C10 in parallel, and serves as another output end of the synaptic enhancement module, and outputs the signal Enhance2.

[0081] When the presynaptic neuron pulse signal Pre reaches the input end of the bionic circuit earlier than the postsynaptic neuron pulse signal Post (△t<0), the presynaptic neuron pulse signal Pre and the enable signal Pre_enable after passing through the inverter enter the first NAND gate and output low level, the P-channel effect transistor is opened, at this time, the current flows from the source to the drain of the P-channel effect transistor M1, the capacitor C1 is charged, the Post_enable reaches high level, the NAND gate of the synaptic inhibition module outputs high level, the P-channel effect transistor M2 is turned off, and then the Enhance2 signal generation circuit stops working; when the signal Pre ends, M1 is cut off, C1 is discharged through R1, when the enable signal Enable_Enhance1 is high level and the postsynaptic neuron signal Post is input, because C1 is greater than C2, C1 charges C2, when the voltage between the two ends of C2 is greater than Vthr, the output signal Enhance1 of the synaptic enhancement module is high level, until the Post action ends, C2 is discharged through R2 until the voltage between the two ends is less than Vthr, then the output Enhance1=0; according to the above working principle, as |△t| increases, the C1 discharge time is longer, the voltage obtained by C2 is smaller, and therefore the pulse width of the output enhancement signal Enhance is smaller. The signal generation process principle of Ehance2 is the same, wherein the enable signal and the input signal are Enable_Enhance2 and Post respectively.

[0082] The circuit principle diagram of the steady state window control module is as follows Figure 6As shown, the module includes two parts, Pre and Post arrival of steady-state window control circuit, output control synapse enhancement module and synapse inhibition module signal Enable_Enhance1, Enable_Enhance2, Enable_Inhibite1 and Enable_Inhibite2.

[0083] The pre-synaptic neuron signal Pre input is connected to the 3 port of the third inverter and the 3 port of the fourth inverter respectively, the output of the third inverter is connected to the gate of the P-channel transistor M3, the source of M3 is connected to the 5V power supply, the drain of M3 is connected to the capacitor C31, the resistor R31 and the same direction input of the third comparator respectively, the other end of C31 and R31 is grounded; the reverse input of the third comparator is connected to the reference voltage Vthr40μs, the positive power pin is connected to the 5V power supply and connected to the output of the third comparator through the resistor R32, the negative power pin is grounded, the output of the third comparator is connected to the 1 port of the first XOR gate after being connected to the capacitor C32 in parallel, the 2 port of the first XOR gate receives the signal Enable_Enhance1, the output of the first XOR gate outputs the signal Enable_Inhibite1; the output of the fourth NAND gate is connected to the gate of the P-channel transistor M4, the source of M4 is connected to the 5V power supply, the drain of M4 is connected to the capacitor C41, the resistor R41 and the same direction input of the fourth comparator respectively, the other end of C41 and R41 is grounded; the reverse input of the fourth comparator is connected to the reference voltage Vthr20μs, the positive power pin is connected to the 5V power supply and connected to the output of the fourth comparator through the resistor R42, the negative power pin is grounded, the output of the fourth comparator is connected to the capacitor C42 to output the signal Enable_Enhance1;

[0084] The post-synaptic neuron signal Post is connected to the 3-port of the fifth inverter and the 3-port of the sixth inverter respectively, the output of the fifth inverter is connected to the gate of the P-channel transistor M5, the source of M5 is connected to the 5V power supply, the drain of M5 is connected to the capacitor C51, the resistor R51 and the non-inverted input of the fifth comparator respectively, the other end of C51 and R51 is grounded; the inverted input of the fifth comparator is connected to the reference voltage Vthr40μs, the positive power supply pin is connected to the 5V power supply and connected to the output of the fifth comparator through the resistor R52, the negative power supply pin is grounded, the output of the fifth comparator is connected to the 1-port of the second XOR gate through the capacitor C52 in parallel, the 2-port of the second XOR gate receives the signal Enable_Enhance2, the output of the second XOR gate is connected to the signal Enable_Inhibite2 through the capacitor C95 in parallel; the output of the sixth NAND gate is connected to the gate of the P-channel transistor M6, the source of M6 is connected to the 5V power supply, the drain of M6 is connected to the capacitor C61, the resistor R61 and the non-inverted input of the sixth comparator respectively, the other end of C61 and R61 is grounded; the inverted input of the sixth comparator is connected to the reference voltage Vthr20μs, the positive power supply pin is connected to the 5V power supply and connected to the output of the sixth comparator through the resistor R62, the negative power supply pin is grounded, the output of the sixth comparator is connected to the signal Enable_Enhance2 through the capacitor C62 in parallel.

[0085] In the circuit, the processing process of the two input signals is consistent. Taking the arrival of Pre as an example to illustrate the control principle of the steady state window. When the presynaptic pulse Pre arrives, it arrives at the gates of P-channel transistors M3 and M4 after inversion, P-channel transistors M3 and M4 are turned on, and capacitors C31 and C41 begin to charge. When the action of Pre ends, M3 and M4 are turned off, and C31 and C41 begin to discharge. The output voltage is processed by the comparator circuit to generate a 40μs pulse width square wave signal delta_40μs and a 20μs pulse width synaptic enhancement module enable signal Enable_Enhance1. Enable_Enhance1 and delta_40μs are XOR operated to output a synaptic inhibition module enable signal Enable_Inhibite1 with a pulse width of 20μs and falling behind Enable_Enhance1 signal by 20μs. Figure 7 The enable signal waveform output by the steady state window control module when the Pre signal is input into the biomimetic circuit is shown. It can be seen that Enable_Enhance1 and Enable_Inhibite1 signals jointly constrain the steady state window.

[0086] As Figure 8The synaptic inhibition module comprises two inhibitory signal Inhibite1 and Inhibite2 generation circuits corresponding to the Pre and Post arrival respectively, and the implementation principle is the same.

[0087] The input end of the presynaptic neuron signal Pre is connected with the 1 port of the seventh inverter and the 3 port of the eighth inverter respectively, the output end of the seventh inverter is connected with the gate of the P-channel transistor M7, the source of M7 is connected with the 5V power supply, the drain of M7 is connected with the resistor R71, the capacitor C71 and the inverting input end of the seventh comparator respectively, the other end of C71 and R71 is grounded; the non-inverting input end of the seventh comparator receives the reference voltage VthrContrl, the positive power supply pin is connected with the 5V voltage and connected with the output end of the seventh comparator through the resistor R72, the negative power supply pin is grounded, the output end of the seventh comparator is connected with the 2 port of the third XOR gate; the 1 port of the third XOR gate receives the signal Enable_Enhance2, the output end of the third XOR gate is connected with the 2 port of the first AND gate; the 1 port of the first AND gate receives the signal Enable_Inhibite2, the output end of the first AND gate outputs the signal Inhibite_PW2; the output end of the eighth inverter is connected with the gate of the P-channel transistor M8, the source of M8 is connected with the 5V power supply, the drain of M8 is connected with the resistor R81, the capacitor C81 and the 3 pin of the four-way analog switch U3 respectively, the other end of R81 and C81 is grounded; the 2 pin of U3 is connected with the resistor R82, the capacitor C82 and the non-inverting input end of the eighth comparator respectively, the inverting input end of the eighth comparator receives the reference voltage Vthr_Inhibite, the positive power supply pin of the eighth comparator is connected with the 5V voltage and connected with the output end of the eighth comparator through the resistor R83, the output end of the eighth comparator is connected with the capacitor C83 in parallel to output the signal Inhibite1, the other end of C83 is grounded;

[0088] The post-synaptic neuron signal Post is connected to the 3rd port of the 9th inverter and the 3rd port of the 10th inverter respectively; the output of the 9th inverter is connected to the gate of the P-channel transistor M9, the source of M9 is connected to 5V voltage, the drain of M9 is connected to the resistor R91, the capacitor C91 and the 6th pin of the four-way analog switch U3 respectively, the other ends of R91 and C91 are grounded; the 7th pin of U3 is connected to the resistor R92, the capacitor C92 and the non-inverting input of the 9th comparator respectively, the other ends of R92 and C92 are grounded; the inverting input of the 9th comparator receives the reference voltage Vthr_Inhibite, the positive power pin of the 9th comparator is connected to 5V voltage and connected to the output of the 9th comparator through the resistor R93, the negative power pin is grounded, the output of the 9th comparator is connected to the capacitor C93 in parallel and outputs the signal Inhibite2, the other end of C93 is grounded; the output of the 10th inverter is connected to the gate of the P-channel transistor M10, the source of M10 is connected to 5V voltage, the drain of M10 is connected to the capacitor C101, the resistor R101 and the inverting input of the 10th comparator respectively, the other ends of C101 and R101 are grounded; the non-inverting input of the 10th comparator receives the reference voltage VthrContrl, the positive power pin of the 10th comparator is connected to 5V voltage and connected to the output of the 10th comparator through the resistor R102, the negative power pin is grounded, the output of the 10th comparator is connected to the capacitor C102 in parallel and connected to the 2nd port of the fourth XOR gate, the 1st port of the fourth XOR gate receives the signal Enable_Enhance1, the output of the fourth XOR gate is connected to the 5th port of the second AND gate, the 4th port of the second AND gate receives the signal Enable_Inhibite1, the output of the second AND gate outputs the signal Inhibite_PW1; the 1st pin of U3 receives the signal Inhibite_PW1, the 16th pin receives the post-synaptic neuron signal Post, the 9th pin receives the pre-synaptic neuron signal Pre, the 8th pin receives the signal Inhibite_PW2, the 14th pin is connected to the drain of M7, the 11th pin is connected to the drain of M10, the 10th and 15th pins are grounded.

[0089] As Figure 8When Pre reaches the input of the synaptic inhibition module, M7 is opened, and capacitor C71 starts to charge. When the action of Pre ends, M7 is closed, and C71 starts to discharge slowly through resistor R71. When Post reaches, the second switch of four-way analog switch U3 is opened, so that the positive electrode of C71 is connected to the ground, and C71 discharges quickly, thus making PreHHH generate a positive pulse after Pre reaches and before Post reaches. The signal generates a flip signal HomeControl2 through the comparator, and then HomeControl2 is XORed with Enable_Enhance2 and ANDed with Enable_Inhibite2 to form a control signal Inhibit_PW2 for controlling the pulse width of the output signal Inhibite2 of the synaptic inhibition module, as shown in Figure 9 When Inhibit_PW2 is at a high level, the fourth switch of analog switch U3 is opened, and C91 charges C92 quickly. When the voltage of C92 is greater than Vthr_Inhibite, Inhibite2 outputs a high level. When the action of Post ends, C92 starts to discharge through resistor R92. When the voltage of C92 is less than Vthr_Inhibite, Inhibite2 outputs a low level. The generation principle of the output signal Inhibite1 of the synaptic inhibition module is the same as that of Inhibite2.

[0090] As Figure 5 The synaptic conductance update module includes two ADG442 analog switch chips for controlling the direction and amplitude of the pulse input to the memristor synapse.

[0091] The 1 and 16 pins of four-way analog switch U4 receive the Enhance1 signal, the 8 and 9 pins of U4 receive the Enhance2 signal, the 3 and 11 pins of U4 are connected to a 2V power supply, the 14 and 6 pins are connected to the ground, and the 15 and 7 pins are used as output terminals to output the signal Mem-.

[0092] The 1 and 16 pins of four-way analog switch U5 receive the Inhibite1 signal, the 8 and 9 pins of U4 receive the Inhibite2 signal, the 3 and 11 pins of U4 are connected to a 0.13V power supply, the 14 and 6 pins are connected to the ground, and the 15 and 7 pins are used as output terminals to output the signal Mem+.

[0093] When the enhance signals Enhance1 and Enhance2 are input, then the 2V voltage stimulus is input to the positive electrode of the memristor according to the width of the enhance signals, and the negative electrode is grounded; when the inhibit signals Inhibite1 and Inhibite2 are input, then the 0.13V voltage stimulus is input to the negative electrode of the memristor according to the width of the inhibit signals.

[0094] It can be known from the functions of the above-mentioned modules that the pulse width of the inhibit signals Inhibite1 and Inhibite2 is controlled by the reference voltage Vthr_Inhibite, and the setting At is traversed in the range of [-40, 40]us with a step length of 1us for simulation, as shown in Figure 10 The curves of the change of the pulse width PW of the inhibit signals Inhibite1 and Inhibite2 with At under different Vthr_Inhibite are shown. The left side of the straight line of At=0 is the curve of the change of the pulse width of Inhibite1 signal, and the right side is the curve of the change of the pulse width of Inhibite2 signal. It can be seen that the pulse widths of the inhibit signals Inhibite1 and Inhibite2 both increase with the increase of |At|, and finally remain at a fixed value, and the maximum pulse width of the pulse width of the inhibit signals Inhibite1 and Inhibite2 is smaller with the increase of Vthr_Inhibite. In order to obtain a suitable synaptic plasticity learning rate and learning window, Vthr_Inhibite=0.5V is set in the embodiment. Further, the change range of At is set to [-40, 40]us, the change step length is 1us, and the single simulation time is 50us, and the change curves of the state variable of the memristor and the change amount AG(At) of the memristor synaptic conductance are obtained by traversing At, as shown in Figure 11 .

[0095] Further, as shown in Figure 11 (a), when |At|≤20us, the state variable x of the memristor changes more significantly with the decrease of |At|, and when |At|>20us, the state variable x of the memristor changes more significantly with the increase of |At|. When the actions of Pre and Post end, the state variable of the memristor remains at a fixed value due to the memory characteristic of the memristor. According to the fixed value and the relationship expression of the state variable of the memristor and the conductance, the change amount AG(At) of the conductance of the memristor can be calculated, as shown in Figure 11 (b). Through derivation of the inhibitory synaptic plasticity mechanism expressions (3)-(8), an equivalent expression is obtained, as shown in formula (9). Further, by fitting the PSpice simulation data of the bionic circuit by using formula (9), it is found that when A + =A - =0.1 and τ += 7.5 μs, τ- = 12 μs, ΔG0= 0.007, ΔG1= 0.02, expression (9) can well fit the simulation experimental data Figure 11 (b) orange line), indicating that the biomimetic circuit realizes the function of inhibitory synaptic plasticity mechanism.

[0096]

[0097] As shown in Figure 12 , the Pre and Post signals with different time intervals Δt are continuously input to the input end of the biomimetic circuit, further verifying the case of continuous change of the memristive synaptic conductance in the time domain.

[0098] Figure 12 (a) and (b) respectively show the Pre pulse train and the Post pulse train input to the input end of the biomimetic circuit. With the ①-③ Pre as the reference, the Post lag time is less than 20 μs. It can be found by observing the Enhance1 signal output by the synaptic enhancement module (c) that the longer the Post lag time, the narrower the pulse width of Enhance1, and the smaller the increase of the memristive conductance before the action of Enhance1 (e, the yellow line part superimposed on the memristive conductance change curve). This result is consistent with the case of Δt <-20 μs in (b). Figure 12 With the ①-③ Post as the reference, the ②-④ Pre lag time is 45 μs, 40 μs and 32 μs, respectively, all of which are greater than 20 μs. It can be found by observing the Inhibite1 signal output by the synaptic inhibition module (d) that the shorter the Pre lag time, the narrower the pulse width of Inhibite1, and the smaller the decrease of the memristive conductance before the action of Inhibite1 (e, the purple line part superimposed on the memristive conductance change curve). This result is consistent with the case of Δt >20 μs in (b). Figure 12 Figure 12 In addition, with the ④-⑦ Pre as the reference, the Post is input after it, indicating that the time interval between it and the corresponding Post signal is greater than or equal to 40 μs. Therefore, it can be found by observing the Inhibite2 signal output by the synaptic inhibition module (d) that the pulse width of Inhibite2 is the same, and the decrease of the memristive conductance before the action of Inhibite2 is the same (e, the green line part superimposed on the memristive conductance change curve). Figure 12 Figure 12 Figure 12 Figure 12 Figure 13

[0099] ​​​​​​The embodiment of the memristor-based excitatory synaptic plasticity mechanism simulation circuit comprises a synaptic potentiation module, a synaptic depression module, a synaptic conductance update module and a memristor synapse unit. The synaptic potentiation module and the synaptic depression module are triggered by a voltage pulse generation circuit of △t, and generate positive pulse voltage signals for enhancing or depressing the memristor synapse conductance, respectively. The pulse width PW of the positive pulse voltage signals is modulated by △t. The synaptic conductance update module is used for outputting a voltage pulse for changing the memristor synapse conductance. When the potentiation circuit module has a voltage pulse signal output, the conductance update module outputs a positive pulse with the same pulse width as the voltage pulse signal; otherwise, when the depression circuit module has a voltage pulse signal output, the conductance update module outputs a negative pulse with the same pulse width as the voltage pulse signal.

[0100] As shown in the figure, Pre_enable and Post_enable are enable signals for starting the synaptic potentiation module and the synaptic depression module, respectively, and the initial values are both set to 0V. When Pre reaches the input end of the simulation circuit earlier than Post, Post_enable becomes high, so that the synaptic depression module stops working; otherwise, Pre_enable becomes high, so that the synaptic potentiation module stops working. Figure 14

[0101] The working principle of the excitatory synaptic plasticity mechanism simulation circuit is as follows:

[0102] When Pre reaches the input end of the simulation circuit earlier than Post (△t < 0), the high-level output of Pre and the initial signal of Pre_enable jointly act on the NAND gate to output a low level, so that the P-channel transistor is turned on, the capacitor C1 starts to charge, and Post_enable quickly reaches a high level, so that the NAND gate of the synaptic depression module outputs a high level, the P-channel transistor M2 is turned off, and the synaptic depression module stops working. When the action of Pre ends, M1 is turned off, the capacitor C1 is discharged through R1, and when Post reaches, the first switch of the four-way analog switch U1 is turned on. Since C2 is smaller than C1, C1 charges C2. When the voltage across C2 is greater than Vthr, the synaptic potentiation module outputs an enhancement signal Enhance with a high level, until the action of Post ends, C2 is discharged through R2 until the voltage across C2 is less than Vthr, and then Enhance = 0. According to the above working principle, as |△t| increases, the discharge time of C1 is longer, the voltage obtained by C2 is smaller, and therefore the pulse width of the output enhancement signal Enhance is smaller. Similarly, when Post reaches the input end of the simulation circuit earlier than Pre (△t > 0), the synaptic depression module starts to work, and as |△t| increases, the pulse width of the output inhibition signal Inhibite of the synaptic depression module is smaller.

[0103] ​When the Enhance signal is input to the synaptic conductance update module circuit, the synaptic conductance update module outputs a positive pulse with an amplitude of 2V and a pulse width same as that of the Enhance signal, and applies the positive pulse to the positive electrode of the memristor, at this time the negative electrode of the memristor is grounded, thereby increasing the memristor conductance; when the Inhibite signal is input to the synaptic conductance update module circuit, the synaptic conductance update module outputs a negative pulse with an amplitude of 2V and a pulse width same as that of the Inhibite signal, and applies the negative pulse to the negative electrode of the memristor, at this time the positive electrode of the memristor is grounded, thereby decreasing the memristor conductance.

[0104] Since the conductance state switching time scale of the memristor is μs level, it is necessary to reasonably set R1-R4, C1-C4 and the negative input voltage Vthr of the comparator, so that the pulse width PW of the △t modulated Enhance and Inhibite signals is also in the μs level scale. Through simulation, it is found that when the values of R1-R4 and C1-C4 are certain, the adjustment of PW can be realized by adjusting the value of Vthr alone.

[0105] Set △t to traverse simulation in the range of [-40, 40] μs with a step length of 1 μs, Figure 15 The curves of the pulse width PW of Enhance and Inhibite changing with △t under different Vthr are shown. The left branch is the change of the PW of Enhance signal, and the right branch is the change of the PW of Inhibite signal. It can be seen that the PW change curves corresponding to different Vthr are symmetrical about the △t=0 straight line, and the PW value is larger as |△t| decreases; as Vthr increases, the maximum value of PW decreases, and the minimum value of PW tends to 0. For example, when Vthr=1.2V, the maximum value of PW is only 7.24 μs, and the minimum value is 0.

[0106] In order to obtain appropriate synaptic plasticity learning rate and learning window, this paper sets Vthr=0.5V. Next, set the change range of △t to [-40, 40] μs with a step length of 1 μs in PSpice, and the single simulation time is 50 μs, and the change curves of the state variable of the memristor and the change amount △G(△t) of the memristor conductance are obtained by traversing △t, as shown in Figure 15 .

[0107] As shown in Figure 15 (a), as |△t| decreases, the state variable x of the memristor changes more significantly. When the action of Pre and Post ends, due to the memory characteristic of the memristor, the state variable of the memristor remains at a fixed value over time. According to the fixed value and the relationship expression between the state variable of the memristor and the conductance, the change amount △G(△t) of the memristor conductance can be calculated, as shown in Figure 16(b) shown. By fitting the Pspice simulation data with the expression (1) of the biological excitatory synaptic learning mechanism, it is found that when A+=A-=0.1, τ + =τ - =8μs in expression (1), expression (1) can well fit the Pspice simulation data of the bionic circuit, indicating that the bionic circuit realizes the excitatory synaptic plasticity mechanism.

[0108] Next, the Pre and Post signals with different time intervals Δt are continuously input to the input end of the bionic circuit, to further verify the case of continuous change of the memristive synaptic conductance in the time domain, as shown in Figure 16 .

[0109] Figure 16 The above and middle figures respectively show the Pre pulse train and the Post pulse train input to the input end of the bionic circuit, and the time interval Δt of Pre and Post is-2μs, -4μs, -6μs, 2μs, 4μs, 6μs from left to right. ​ The lower figure shows the change of the memristive synaptic conductance with time, and it can be seen that the longer the Post lags behind the Pre, the smaller the increase of the memristive synaptic conductance; the longer the Pre lags behind the Post, the smaller the decrease of the memristive synaptic conductance, which conforms to the change rule of the biological excitatory synaptic plasticity in the time domain, and further indicates the effectiveness of the circuit in realizing the excitatory synaptic plasticity function.

Claims

1. A bionic circuit of synaptic plasticity mechanism based on memristor, characterized in that: The bionic circuit is divided into an excitatory synaptic plasticity mechanism bionic circuit and an inhibitory synaptic plasticity mechanism bionic circuit; the excitatory synaptic plasticity mechanism bionic circuit includes a synaptic enhancement module, a synaptic inhibition module, a synaptic conductance update module and a memristive synaptic unit; the inhibitory synaptic plasticity mechanism bionic circuit includes a synaptic enhancement module, a synaptic inhibition module, a steady-state window control module, a synaptic conductance update module and a memristive synaptic unit; The steady-state window module generates a voltage pulse enable signal for controlling the synaptic enhancement module and the synaptic inhibition module based on the arrival order and time interval of pre- and post-synaptic neuron signals. The synaptic enhancement module and the synaptic inhibition module respectively generate positive pulse voltage signals for enhancing and inhibiting the conductance of the memristive synapse. The synaptic conductance update module receives the positive pulse voltage signals output by the synaptic enhancement module and the synaptic inhibition module, and then outputs a voltage pulse that changes the conductance of the memristive synapse.

2. The memristor-based synaptic plasticity mechanism bionic circuit according to claim 1, characterized in that: The synaptic enhancement module of the inhibitory synaptic plasticity mechanism bionic circuit includes two enhancement signal generation circuits, Enhance1 and Enhance2, corresponding to the situations of -20μs≤△t<0 and 0<△t≤20μs respectively; The presynaptic neuron signal Pre input terminal is connected in parallel with the resistor R8 and the capacitor C5 and then connected to the 2 input terminal of the first NAND gate. The enable signal Pre_enable input terminal is connected in parallel with the resistor R10 and then connected to the first inverter. The output terminal of the first inverter is connected to the 1 input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the gate of the P-channel effect transistor M1. The source of the M1 is connected to the 5V power supply. The drain of the M1 is respectively connected to the resistor R1, the capacitor C1 and the 3 pin of the four-way analog switch U2; the 2 pin of U2 is connected to the 3 pin of the four-way analog switch U1, and the 1 pin of U2 is connected to the steady-state window The control module is connected and receives the signal Enable_Enhance1; the pin 1 of U1 receives the postsynaptic neuron signal Post, and the pin 2 of U1 is respectively connected to the resistor R2, the capacitor C2 and the non-inverting input terminal of the first comparator, and the other ends of R2 and C2 are grounded; the inverting input terminal of the first comparator receives the reference voltage Vthr, the positive power supply pin of the first comparator is connected to a 5V power supply, and a resistor R5 is connected between the positive power supply pin and the output terminal, the negative power supply pin of the first comparator is grounded, and the output terminal of the first comparator is connected in parallel with the capacitor C9 and serves as an output terminal of the synaptic enhancement module, outputting the signal Enhance1; The postsynaptic neuron signal Post input terminal is connected in parallel with the resistor R7 and the capacitor C6 and then connected to the 5 input terminal of the second NAND gate. The enable signal Post_enable input terminal is connected in parallel with the resistor R6 and then connected to the second inverter. The output terminal of the second inverter is connected to the 4 input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the gate of the P-channel effect transistor M2. The source of M2 is connected to the 5V power supply. The drain of M2 is respectively connected to the resistor R3, the capacitor C3 and the 6 pin of the four-way analog switch U2; the 7 pin of U2 is connected to the 6 pin of the four-way analog switch U1, and the 8 pin of U2 is connected to the steady-state window The control module is connected and receives the signal Enable_Enhance1; the 8-pin of U1 receives the presynaptic neuron signal Pre, and the 7-pin of U1 is respectively connected to the resistor R4, the capacitor C4 and the non-inverting input end of the second comparator, and the other ends of R4 and C4 are grounded; the reverse input end of the second comparator receives the reference voltage Vthr, the positive power supply pin of the second comparator is connected to the 5V power supply, and the resistor R98 is connected between the positive power supply pin and the output end, the negative power supply pin of the second comparator is grounded, the output end of the second comparator is connected in parallel with the capacitor C10, and serves as another output end of the synaptic enhancement module, outputting the signal Enhance2.

3. The memristor-based synaptic plasticity mechanism bionic circuit according to claim 1, characterized in that: The steady-state window control module of the inhibitory synaptic plasticity mechanism bionic circuit is responsible for generating a voltage pulse enable signal by receiving presynaptic and postsynaptic neuron signals, thereby controlling the working states of the synaptic enhancement module and the synaptic inhibition module. The specific circuit is as follows: The presynaptic neuron signal Pre input terminal is respectively connected to the 3-port of the third inverter and the 3-port of the fourth inverter, the output terminal of the third inverter is connected to the gate of the P-channel effect transistor M3, the source of the M3 is connected to the 5V power supply, the drain of the M3 is respectively connected to the capacitor C31, the resistor R31 and the non-inverting input terminal of the third comparator, and the other ends of the C31 and R31 are grounded; the reverse input terminal of the third comparator is connected to the reference voltage Vthr40μs, the positive power supply pin is connected to the 5V power supply and is connected to the output terminal of the third comparator through the resistor R32, the negative power supply pin is grounded, the output terminal of the third comparator is connected in parallel with the capacitor C32 and then connected to the 1-port of the first XOR gate, and the 2-port of the first XOR gate receives the signal E enable_Enhance1, the output end of the first XOR gate outputs a signal Enable_Inhibite1; the output end of the fourth NAND gate is connected to the gate of the P-channel effect transistor M4, the source of the M4 is connected to a 5V power supply, the drain of the M4 is connected to a capacitor C41, a resistor R41, and a non-inverting input end of a fourth comparator, respectively, and the other ends of C41 and R41 are grounded; the inverting input end of the fourth comparator is connected to a reference voltage Vthr20μs, the positive power supply pin is connected to a 5V power supply and is connected to the output end of the fourth comparator via a resistor R42, and the negative power supply pin is grounded. The output end of the fourth comparator is connected in parallel with the capacitor C42 to output the signal Enable_Enhance1; The postsynaptic neuron signal Post input terminal is respectively connected to the 3-port of the fifth inverter and the 3-port of the sixth inverter, the output terminal of the fifth inverter is connected to the gate of the P-channel effect transistor M5, the source of the M5 is connected to the 5V power supply, the drain of the M5 is respectively connected to the capacitor C51, the resistor R51 and the non-inverting input terminal of the fifth comparator, and the other ends of the C51 and R51 are grounded; the reverse input terminal of the fifth comparator is connected to the reference voltage Vthr40μs, the positive power supply pin is connected to the 5V power supply and is connected to the output terminal of the fifth comparator through the resistor R52, the negative power supply pin is grounded, the output terminal of the fifth comparator is connected in parallel with the capacitor C52 and then connected to the 1-port of the second XOR gate, and the 2-port of the second XOR gate receives the signal Enab The output of the second XOR gate is connected in parallel with a capacitor C95 and outputs a signal Enable_Inhibite2. The output of the sixth NAND gate is connected to the gate of a P-channel effect transistor M6, the source of M6 is connected to a 5V power supply, the drain of M6 is connected to a capacitor C61, a resistor R61, and a non-inverting input of a sixth comparator, respectively, and the other ends of C61 and R61 are grounded. The inverting input of the sixth comparator is connected to a reference voltage Vthr20μs, the positive power supply pin is connected to a 5V power supply and is connected to the output of the sixth comparator via a resistor R62, and the negative power supply pin is grounded. The output of the sixth comparator is connected in parallel with a capacitor C62 and outputs the signal Enable_Enhance2.

4. The memristor-based synaptic plasticity mechanism bionic circuit according to claim 1, characterized in that: The synaptic inhibition module of the inhibitory synaptic plasticity mechanism bionic circuit includes two inhibitory signal Inhibite1 and Inhibite2 generation circuits; The input end of the presynaptic neuron signal Pre is respectively connected to the 1 port of the seventh inverter and the 3 port of the eighth inverter, the output end of the seventh inverter is connected to the gate of the P-channel effect transistor M7, the source of M7 is connected to the 5V power supply, and the drain of M7 is respectively connected to the resistor R71, the capacitor C71 and the inverting input end of the seventh comparator, and the other ends of C71 and R71 are grounded; the non-inverting input end of the seventh comparator receives the reference voltage VthrContrl, the positive power supply pin is connected to the 5V voltage and is connected to the output end of the seventh comparator through the resistor R72, the negative power supply pin is grounded, and the output end of the seventh comparator is connected to the 2 port of the third XOR gate; the 1 port of the third XOR gate receives the signal Enable_Enhance2, and the output end of the third XOR gate is connected to the 2 port of the first AND gate; the 1 port of the first AND gate receives Signal Enable_Inhibite2, the output of the first AND gate outputs signal Inhibite_PW2; the output of the eighth inverter is connected to the gate of the P-channel effect transistor M8, the source of M8 is connected to a 5V power supply, and the drain of M8 is connected to a resistor R81, a capacitor C81, and pin 3 of the four-way analog switch U3, respectively. The other ends of R81 and C81 are grounded; pin 2 of U3 is connected to a resistor R82, a capacitor C82, and a non-inverting input of an eighth comparator, respectively. The inverting input of the eighth comparator receives a reference voltage Vthr_Inhibite. The positive power supply pin of the eighth comparator is connected to a 5V voltage and is connected to the output of the eighth comparator via a resistor R83. The output of the eighth comparator is connected in parallel with capacitor C83 to output signal Inhibit1, and the other end of C83 is grounded; The postsynaptic neuron signal Post input terminal is connected to the 3-port of the ninth inverter and the 3-port of the tenth inverter respectively; the output terminal of the ninth inverter is connected to the gate of the P-channel effect transistor M9, the source of M9 is connected to the 5V voltage, the drain of M9 is connected to the resistor R91, the capacitor C91 and the 6-pin of the four-way analog switch U3 respectively, and the other ends of R91 and C91 are grounded; the 7-pin of U3 is connected to the resistor R92, the capacitor C92 and the non-inverting input terminal of the ninth comparator respectively, and the other ends of R92 and C92 are grounded; the inverting input terminal of the ninth comparator receives the reference voltage Vthr_Inhibite, the positive power supply pin of the ninth comparator is connected to the 5V power supply and is connected to the output terminal of the ninth comparator through the resistor R93, the negative power supply pin is grounded, the output terminal of the ninth comparator is connected in parallel with the capacitor C93 to output the signal Inhibite2, and the other end of C93 is grounded; The output end of the comparator is connected to the gate of the P-channel effect transistor M10, the source of M10 is connected to a 5V voltage, the drain of M10 is respectively connected to a capacitor C101, a resistor R101, and an inverting input end of a tenth comparator, and the other ends of C101 and R101 are grounded; the non-inverting input end of the tenth comparator receives a reference voltage VthrContrl, the positive power supply pin of the tenth comparator is connected to a 5V voltage and is connected to the output end of the tenth comparator via a resistor R102, and the negative power supply pin is grounded, the output end of the tenth comparator is connected in parallel with the capacitor C102 and then connected to port 2 of a fourth XOR gate, port 1 of the fourth XOR gate receives a signal Enable_Enhance1, the output end of the fourth XOR gate is connected to port 5 of a second AND gate, port 4 of the second AND gate receives a signal Enable_Inhibite1, and the output end of the second AND gate outputs a signal Inhibite_PW1; Pin 1 of U3 receives the signal Inhibite_PW1, pin 16 receives the postsynaptic neuron signal Post, pin 9 receives the presynaptic neuron signal Pre, pin 8 receives the signal Inhibite_PW2, pin 14 is connected to the drain of M7, pin 11 is connected to the drain of M10, and pins 10 and 15 are grounded.

5. The memristor-based synaptic plasticity mechanism bionic circuit according to claim 1, characterized in that: The synaptic conductance update module of the inhibitory synaptic plasticity mechanism bionic circuit is specifically as follows: Pins 1 and 16 of the four-way analog switch U4 receive the Enhance1 signal, pins 8 and 9 of the U4 receive the Enhance2 signal, pins 3 and 11 of the U4 are connected to a 2V power supply, pins 14 and 6 are grounded, and pins 15 and 7 serve as output terminals to output the signal Mem-. Pins 2 and 10 of the U4 are connected in parallel with a resistor R13 and a capacitor C8, and serve as output terminals to output the signal Mem+; Pins 1 and 16 of the four-way analog switch U5 receive the Inhibite1 signal, pins 8 and 9 of the U4 receive the Inhibite2 signal, pins 3 and 11 of the U4 are connected to a 0.13V power supply, pins 14 and 6 are grounded, and pins 15 and 7 serve as output terminals to output the signal Mem+. Pins 2 and 10 of the U4 are connected in parallel with resistor R16 and capacitor C12, and serve as output terminals to output the signal Mem-.

6. The memristor-based synaptic plasticity mechanism bionic circuit according to claim 1, characterized in that: The four-way analog switches used in the bionic circuit are all ADG442 four-way analog switches, with a VDD pin externally connected to a 15V voltage, a VSS pin externally connected to a -15V voltage, and a ground pin connected to ground.

7. A memristor-based synaptic plasticity mechanism bionic circuit according to claims 1-6, characterized in that: The circuit design method comprises the following steps: 1) Determine the amplitude of the positive voltage pulse applied to the memristor synapse, which must exceed the operating threshold of the memristor, and design a memristor synapse conductance update module based on this amplitude to control the output of positive and negative voltage pulses; 2) Design a voltage pulse generation circuit triggered by the time interval Δt between pre- and post-synaptic neuron pulses, including a synaptic enhancement circuit and a synaptic inhibition circuit, to generate a positive pulse voltage signal for enhancing or inhibiting the conductance of the memristive synapse, with the pulse width PW of the positive pulse voltage signal modulated by Δt; 3) connecting the outputs of the synaptic enhancement circuit module and the synaptic inhibition circuit module to the memristive synaptic conductance update module. When the synaptic enhancement circuit module outputs a voltage pulse signal, the conductance update module outputs a positive pulse with the same pulse width as the voltage pulse signal. Conversely, when the synaptic inhibition circuit module outputs a voltage pulse signal, the conductance update module outputs a negative pulse with the same pulse width as the voltage pulse signal. The positive and negative pulses are signals measured with Mem- as the negative pole and Mem+ as the positive pole, and the absolute values ​​of their amplitudes are equal to the positive voltage pulse amplitude set in step 1). 4) Connecting the memristive synapse conductance update module to the memristive synapse, setting the memristive synapse to the same initial state, and changing Δt to obtain a memristive conductance variable ΔG(Δt) curve; 5) Use the biological excitatory synaptic plasticity mechanism model and the inhibitory synaptic plasticity mechanism model to fit the △G(△t) curve. If the fit is successful, it means that the pre- and post-synaptic neuron pulse waveforms meet the requirements of the bionic circuit design, and the design is complete; otherwise, readjust the parameters of the enhancement circuit module, inhibition circuit module, or memristive synaptic conductance update module and proceed to the second step.

8. The memristor-based synaptic plasticity mechanism bionic circuit according to claim 7, characterized in that: When designing the excitatory synaptic plasticity mechanism bionic circuit, the relationship between Δt and the pulse width PW of the positive pulse voltage signal must meet the following conditions: when Δt<0, the synaptic enhancement circuit module is triggered to start working, and as |Δt| decreases, the pulse width of the output voltage pulse becomes wider; when Δt>0, the synaptic inhibition circuit module is triggered to start working, and as |Δt| decreases, the pulse width of the output voltage pulse becomes wider; When designing a bionic circuit for inhibitory synaptic plasticity, the relationship between △t and the pulse width PW of the positive pulse voltage signal must meet the following conditions: when |△t| is less than the steady-state window t wisp When |△t| is greater than the steady-state window t wisp When , the synaptic inhibition circuit module is triggered to start working, and as |△t| increases, the pulse width of the output voltage pulse increases and is finally fixed to a certain value.

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