Hardware accelerator, die, multi-die collaboration system and method

Abstract

The embodiment of the invention provides a hardware accelerator, a bare chip, a multi-bare-chip cooperation system and a multi-bare-chip cooperation method, the hardware accelerator is applied to a first bare chip in the multi-bare-chip cooperation system, the hardware accelerator comprises a synchronization control module used for generating and processing synchronization signal output data, and the synchronization signal is used for controlling synchronization state jump among multiple bare chips; and the synchronous transceiving module is used for receiving the synchronous signal output data sent by the synchronous control module and sending the received synchronous signal input data sent by other bare chips to the synchronous control module. According to the embodiment of the invention, on the basis of not changing a chip architecture, a neural network computing platform with higher computing power and excellent cooperative computing capability is realized through a DIE technology.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of multi-die cooperation, and in particular to a hardware accelerator, a die, a multi-die cooperation system and a method. BACKGROUND

[0002] Generally, the performance improvement of a single-chip NPU (Neural Processing Unit) is limited by factors such as chip area and process technology. With the increasing demand for computing power, a single chip is difficult to meet the needs of some high-end application scenarios, such as artificial intelligence computing in large data centers and ultra-high performance computing, which require extreme computing power. Moreover, once the design of a single-chip NPU is completed, its functions are relatively fixed, and it is difficult to perform large-scale functional expansion or upgrade. Therefore, it cannot be well applied to complex application scenarios that require multiple functions to work together and have high requirements for computing and storage capabilities, such as high-end servers and professional graphics processing workstations. SUMMARY

[0003] In view of this, embodiments of the present disclosure provide a hardware accelerator, a die, a multi-die cooperation system and a method to at least solve or alleviate the above problems.

[0004] According to a first aspect of embodiments of the present disclosure, a hardware accelerator is provided, which is applied to a first die in a multi-die cooperation system. The hardware accelerator comprises: a synchronization control module, configured to generate and process synchronization signal output data, the synchronization signal being used to control the synchronization state transition between multiple dies; and a synchronization transceiver module, configured to receive the synchronization signal output data sent by the synchronization control module, and send synchronization signal input data sent by other dies to the synchronization control module.

[0005] According to a second aspect of embodiments of the present disclosure, a die is provided, which applies the hardware accelerator of the first aspect.

[0006] According to a third aspect of embodiments of the present disclosure, a multi-die cooperation system is provided, which comprises a first die and a second die, and the hardware accelerator of the first aspect is run on the first die and the second die.

[0007] According to a fourth aspect of embodiments of the present disclosure, a hardware acceleration method is provided, which is applied to a first die in a multi-die cooperation system. The method comprises: generating and processing synchronization signal output data, the synchronization signal being used to control the synchronization state transition between multiple dies; and receiving the synchronization signal output data, and sending synchronization signal input data sent by other dies to the synchronization control module.

[0008] According to a fifth aspect of the embodiments of the present disclosure, a hardware acceleration method is provided, applied to a multi-die cooperative system including a first die and a second die, and the method comprises: the first die generates synchronization signal output data, enters a pause state and records a second die identifier, and sends the synchronization signal output data to the second die; after the second die receives the synchronization signal output data, the second die returns response synchronization signal input data; and the first die jumps to a working state according to the response synchronization signal input data.

[0009] According to the hardware accelerator scheme provided by the embodiments of the present disclosure, the synchronization control module of the hardware accelerator generates and processes synchronization signal output data, and the synchronization signal is used to control the synchronization state jump between the multiple dies. The synchronization control module sends the synchronization signal output data to the synchronization transceiver module, and the synchronization transceiver module sends the received synchronization signal input data sent by other dies to the synchronization control module. The embodiments of the present disclosure realize a neural network computing platform with greater computing power and excellent cooperative computing capability through the multi-die (DIE) technology without changing the chip architecture. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0011] Figure 1 is a structural schematic diagram of a hardware accelerator according to an embodiment of the present disclosure; Figure 2 is a structural schematic diagram of a hardware accelerator according to another embodiment of the present disclosure; Figure 3 is an example diagram of synchronization signal input data of a hardware accelerator according to another embodiment of the present disclosure; Figure 4 is a structural schematic diagram of a synchronization control module of a hardware accelerator according to another embodiment of the present disclosure; Figure 5 is a structural schematic diagram of a front-end unit of a hardware accelerator according to another embodiment of the present disclosure; Figure 6 is a schematic diagram of a finite state machine of a hardware accelerator according to another embodiment of the present disclosure; Figure 7 is a structural schematic diagram of a global synchronization unit of a hardware accelerator according to another embodiment of the present disclosure; Figure 8is a structural diagram of a synchronization bus unit of a hardware accelerator according to an embodiment of the present disclosure; Figure 9 is a structural diagram of a synchronization transceiver module of a hardware accelerator according to an embodiment of the present disclosure; Figure 10 is a state machine diagram of a protocol conversion unit of a hardware accelerator according to an embodiment of the present disclosure; Figure 11 is an application scenario diagram of a hardware accelerator according to an embodiment of the present disclosure; Figure 12 is a diagram of a die according to an embodiment of the present disclosure; Figure 13 is a diagram of a multi-die cooperative system according to an embodiment of the present disclosure; Figure 14 is a flowchart of a hardware acceleration method according to an embodiment of the present disclosure; Figure 15 is a flowchart of a hardware acceleration method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be interpreted as being limited to the embodiments set forth herein, but rather, the embodiments are provided so that the present disclosure can be more thoroughly and completely understood. It should be understood that the drawings of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0013] It should be noted that the titles of any sections / subsections provided herein are not limiting. Various embodiments are described throughout this document, and any type of embodiment can be included under any section / subsection. Furthermore, embodiments described in any section / subsection can be combined with any other embodiment described in the same section / subsection and / or a different section / subsection in any manner.

[0014] In the description of embodiments of the present disclosure, the term "includes" and its derivatives, such as "including," should be understood in an open, inclusive sense, that is, "including, but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "an embodiment" should be understood as "at least one embodiment." The term "some embodiments" should be understood as "at least some embodiments." Other explicit and implicit definitions can also be included below. The terms "first," "second," etc. can refer to different or the same objects. Other explicit and implicit definitions can also be included below.

[0015] The embodiments of the present disclosure may involve user data, data acquisition and / or use, etc. These aspects shall comply with the corresponding laws, regulations and relevant provisions. In the embodiments of the present disclosure, all data collection, acquisition, processing, processing, forwarding, use, etc. are carried out on the premise that the user is aware of and confirms them. Accordingly, when implementing the various embodiments of the present disclosure, the types, scope of use, and usage scenarios of the data or information that may be involved should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with the relevant laws and regulations. The specific notification and / or authorization method may vary according to the actual situation and application scenario, and the scope of the present disclosure is not limited in this respect.

[0016] Where this specification and the solutions in the examples involve the processing of personal information, such processing will be conducted with a legitimate basis (e.g., with the consent of the personal information subject or as necessary for the performance of a contract) and only within the prescribed or agreed scope. A user's refusal to process personal information other than that required for basic functions will not affect their use of these functions.

[0017] First, some nouns or terms that appear in the process of describing the embodiments of the present disclosure are subject to the following explanations.

[0018] Bare die (DIE): refers to the chip that has not yet been packaged after the wafer manufacturing process is completed.

[0019] Die-to-die (Die2Die): A high-speed communication interface technology used to connect multiple dies (chips) in the same package.

[0020] Advanced Extensible Interface (AXI): A scalable interface protocol used to enable high-speed data transfer between modules in a system-on-chip (SoC).

[0021] The following describes in detail the encoding scheme of the transmission identifier provided by the embodiment of the present disclosure in conjunction with the accompanying drawings.

[0022] Hardware Accelerator See also Figure 1 An embodiment of the present disclosure provides a hardware accelerator, applied to a first die in a multi-die collaborative system, the hardware accelerator comprising: The synchronization control module 11 is used to generate and process synchronization signal output data. The synchronization signal is used to control the synchronization state jump between multiple bare chips.

[0023] The synchronous transceiver module 12 is configured to receive the synchronous signal output data sent by the synchronous control module 11 , and send the synchronous signal input data received from other bare chips to the synchronous control module 11 .

[0024] The embodiment of the present disclosure realizes the cooperation between multiple dies through the synchronization control module 11 and the synchronization transceiver module 12. The multiple dies are integrated together, and each die can independently perform calculation, thereby realizing large-scale parallel calculation. The multi-die NPU can flexibly expand the calculation capability according to actual needs, and call different computing resources according to different tasks, and is more flexible and expandable. The embodiment of the present disclosure reduces the design cost and complexity, and improves the chip yield.

[0025] In addition, the multi-die NPU can make each die be the same design, reduce the chip area and design difficulty, and further reduce the cost and implementation difficulty.

[0026] Referring to Figure 2 In some specific implementations of the embodiment of the present disclosure, the hardware accelerator further includes: The network-on-chip module 13 is configured to connect the synchronization control module 11 and the synchronization transceiver module 12 through a network-on-chip protocol.

[0027] The neural network processor 14 is configured to interact with the synchronization control module 11 and send a control instruction to the synchronization control module 11 to generate synchronization signal output data. The configuration bus module 15 is configured to set a control instruction buffer of the synchronization control module 11 and configure a transmission address of the synchronization transceiver module 12.

[0028] In some specific implementations of the embodiment of the present disclosure, the synchronization control module sends the synchronization signal output data to the synchronization transceiver module through a synchronization output bus, the synchronization transceiver module receives the synchronization signal input data sent by other dies through a synchronization input bus, and the synchronization signal output data and the synchronization signal input data both include a source identification (Source ID), a target identification (Destination ID), and a transmission type, and are handshake through a valid signal (vld) and an acknowledgement signal (ack).

[0029] vld (Valid): valid signal, indicating that the data of the sending end (such as the synchronization signal input data sent by the synchronization input bus) is valid and ready to be received. ack (Acknowledge): acknowledgement signal, indicating that the receiving end has successfully received the data. Handshake (handshake): a communication protocol that ensures data between the sending end and the receiving end.

[0030] Source identification (Source ID): indicating the identification of the die (such as VIP0, VIP1) that sends the synchronization signal.

[0031] Target identification (Destination ID): indicating the identification of the target die (such as VIP0, VIP1) of the synchronization signal.

[0032] Transmission type: indicates the type or purpose of the synchronization signal, which can be used to distinguish different synchronization operations (such as triggering the release of a pause, state jumping, etc.).

[0033] Specifically, the source identifier is used to indicate the sending die of the data, the target identifier is used to indicate the receiving die of the data (i.e., whether the die is the target die corresponding to the data), and the transmission type is used to indicate the specific type of the data.

[0034] In some specific implementations of the embodiments of the present disclosure, referring to Figure 3 , the present embodiment is an example of inputting data for a synchronization signal, which also includes the category of the identifier and supports 16 categories. The present embodiment of the present disclosure only takes one type as an example and sets it to 0. The present embodiment of the present disclosure will not repeat the other fields.

[0035] In some specific implementations of the embodiments of the present disclosure, referring to Figure 4 , the synchronization control module 11 includes: The front-end unit 111 (FE) is configured to generate synchronization signal output data and control the synchronization state jump of the first die according to the control instruction corresponding to the received synchronization signal input data.

[0036] The global synchronization unit 112 is configured to synchronize and clock the synchronization signal input data and the synchronization signal output data.

[0037] The synchronization bus unit 113 is configured to process the synchronization signal output data and determine whether the synchronization signal input data corresponds to the first die.

[0038] The present embodiment of the present disclosure generates and processes the synchronization signal output data through the front-end unit 111, the synchronization bus unit 113, and the global synchronization unit 112, and controls the synchronization state jump of the first die according to the control signal corresponding to the synchronization input data.

[0039] In some specific implementations of the embodiments of the present disclosure, referring to Figure 5 , the front-end unit 111 includes: The finite state machine 1111 includes a read state (FE_OUT_CMD_READ_ST), a pause state (FE_OUT_CMD_STALL_CHIP_ST), and a pre-pause state (FE_OUT_PRE_STALL_ST), and is configured to generate a pop-up signal according to the control instruction corresponding to the received synchronization signal input data.

[0040] Specifically, the information carried by the synchronization signal tells the target die (the second die) the operation it needs to perform and the state it needs to enter.

[0041] The synchronization signal includes: Read sync signal: control instruction for entering the read state from the current state.

[0042] Stall sync signal: control instruction for entering the stall state from the current state. The read state is a state for generating the eject signal and entering the pre-stall state after receiving a valid pre-stall instruction. The stall state is a state for returning the first die to the idle state after responding to the sync signal. The pre-stall state is a transition state that jumps to the stall state.

[0043] A first-in-first-out buffer 1112 is configured to store the eject signal received from the finite state machine 1111 and provide a valid pre-stall instruction for the finite state machine 1111.

[0044] A control instruction buffer 1113 is configured to store and output the sync signal output data and output the control instruction to the first-in-first-out buffer 1112.

[0045] Referring to Figure 6 When the control instruction received by the front-end unit 111 is a pre-stall (stall_fe) instruction, the finite state machine 1111 enters the pre-stall state (FE_OUT_PRE_STALL_ST) from the read state (FE_OUT_CMD_READ_ST). When the control instruction received again is a stall (stall_chip_fe) instruction, the finite state machine 1111 enters the stall state (FE_OUT_CMD_STALL_CHIP_ST) from the pre-stall state (FE_OUT_PRE_STALL_ST) and records which die needs to release the stall state of the first die. After the first die receives the sync signal response (fe_out_stall) from the corresponding die, the first die enters the read state (FE_OUT_CMD_READ_ST) and exits the stall state (FE_OUT_CMD_STALL_CHIP_ST).

[0046] Specifically, referring to Figure 7 The global sync unit 112 includes: A receive input register (rcv input reg) 1123 is configured to receive the sync signal input data sent by the other die and sent by the sync bus unit 113.

[0047] A receive buffer (rcv buffer) 1122 is configured to buffer the sync signal input data.

[0048] A receive first-in-first-out queue (rcv afifo) 1121 is configured to receive the sync signal input data and complete the asynchronous-to-synchronous conversion, so that the sync input data can be used in the first die.

[0049] The asynchronous-to-synchronous conversion and the processing of the synchronous input data are performed within the die using a standard circuit structure.

[0050] The receiving FIFO queue 1121 sends the synchronous input data that can be used in the first die to the finite state machine 1111 of the front end unit 111 to generate control instructions corresponding to the synchronization signal to control the synchronization state jump between multiple dies.

[0051] The sending first-in-first-out queue (fe fifo) 1124 is used to receive the synchronous signal output data sent by the finite state machine 1111 of the front-end unit 111 and complete the synchronous to asynchronous conversion, so that the synchronous output data can be sent to other bare chips.

[0052] The synchronous-to-asynchronous conversion and whether the synchronous output data can be sent to other bare chips are processed using a standard circuit structure.

[0053] The sending buffer (fe buffer) 1125 is used to buffer the synchronization signal output data.

[0054] The output register (fe output reg) 1126 is used to send the synchronization signal output data to the synchronous bus unit 113 .

[0055] In some specific implementations of the embodiments of the present disclosure, the synchronization bus unit 113 is specifically configured to: Process the synchronization signal output data and transmit it to the synchronization transceiver module; Receive synchronization signal input data, and if it is determined by comparing the target identifier that it does not correspond to the first bare chip, forward it to other bare chips; if it is determined to correspond to the first bare chip, send a control instruction to the front-end module to control the synchronization state jump of the bare chip.

[0056] Specifically, the target identifier is used to determine whether the first die corresponds to the received synchronization signal input data.

[0057] See also Figure 8 , the synchronous bus unit 113 includes: The first data synchronization or buffer trigger 1131 is used to receive a synchronization signal and output data via a synchronization output bus.

[0058] The arbiter (ARB) 1133 is configured to receive the synchronization signal output data sent by the first data synchronization or cache trigger 1131 and send the synchronization signal output data to the synchronization transceiver module 12 through the output buffer (Send Buffer) 1134, so that the synchronization transceiver module 12 can send the data to other bare chips.

[0059] The arbiter (ARB) 1133 is further configured to determine whether the synchronization signal input data corresponds to the first die according to the target identifier of the received synchronization signal input data, and send the synchronization signal input data to the buffer 1132 for storage if the synchronization signal input data corresponds to the first die.

[0060] The second data synchronization or buffer trigger 1135 is configured to send the synchronization signal input data buffered in the buffer (RVC Buffer) 1132 to the global synchronization unit 112.

[0061] Specifically, the front-end unit 111 of the first die VIP0 generates synchronization signal output data (such as sema0to1), and the synchronization bus unit 113 transmits the synchronization signal output data to the synchronization transceiver module 12 through the arbiter 1133 and the output buffer 1134, and finally sends the synchronization signal output data to the second die VIP1. After the synchronization bus unit 113 of the second die VIP1 receives the synchronization signal input data (sema0to1) of the first die VIP0 and confirms that the target identifier is the second die, the synchronization signal input data is sent to the front-end unit 111 through the global synchronization unit 112, triggering state jump (such as from the pause state to the working state). If the target identifier does not match, the second die VIP1 forwards the synchronization signal input data to the third die VIP2.

[0062] The synchronization bus unit 113 of the embodiment of the present disclosure avoids multi-path synchronization signal conflict through the arbiter 1133, and ensures correct transmission of data according to priority or target. The output buffer 1134 serves as a sending buffer and supports temporary storage and forwarding of synchronization signals, especially when cross-die transmission or target die mismatch occurs. When the target identifier of the synchronization signal input data corresponds to the current die, the control instruction of the synchronization signal input data triggers the state machine of the front-end unit 111 to jump (such as releasing the pause state, see Figure 6 The pause state of the state machine jumps to the pre-pause state). The synchronization signal output data and the synchronization signal input data both include a source identifier, a target identifier, and a transmission type, and are handshake through a valid signal (vld) and an acknowledgement signal (ack).

[0063] In some specific implementations of the embodiment of the present disclosure, referring to Figure 9 The synchronization transceiver module 12 includes: The configuration interface unit 121 is configured to receive synchronization signal input data sent by other dies and configure transmission addresses of the other dies.

[0064] The protocol conversion unit 122 is configured to receive a transmission address of the other die and generate a bus signal of an advanced extensible interface bus protocol (AXI) according to the transmission address.

[0065] Specifically, the configuration interface unit 121 sends the synchronization signal input data sent by the other die to the arbitrator 1133 of the synchronization bus unit 113, and the arbitrator 1133 determines whether the synchronization signal input data corresponds to the first die according to the target identifier of the received synchronization signal input data.

[0066] The protocol conversion unit 122 sends the bus signal of the advanced extensible interface bus protocol to the other die.

[0067] The present embodiment realizes data encapsulation and transmission through the configuration interface unit 121 and the protocol conversion unit 122, and guarantees the efficiency and accuracy of data transmission.

[0068] Specifically, referring to Figure 10 , the state machine of the protocol conversion unit 122 includes: An idle state (IDLE) is a suspended processing operation until a valid signal is output.

[0069] A write driving state (W_DRIVEW) is a driving write address and control signal.

[0070] After receiving the valid signal (sema_out_vld), the state machine jumps to the write driving state. In this state, the protocol conversion unit 122 sends the address pre-configured in the register to the advanced extensible interface bus protocol bus.

[0071] A write handshake state (W_HANDS) is a state for sending write data and waiting for a ready signal.

[0072] When the protocol conversion unit 122 detects that the write preparation ready (awready) signal is pulled high (i.e., sema_axi_awready), the state machine jumps to the write handshake state. In this state, the protocol conversion unit 122 sends data to the advanced extensible interface bus protocol bus and waits for the write ready (wready) signal to be pulled high (i.e., wready_over=wready).

[0073] A write waiting state (W_WAIT) is a state for waiting for the write response channel to be prepared.

[0074] When the write ready (wready) signal is pulled high (i.e., wready_over=wready), the state machine enters the write waiting state. This state is used to wait for the write response (B channel).

[0075] Write End State (W_END) - This state is entered when the write response valid signal or the bypass signal is asserted to complete the transfer.

[0076] The Write Wait state jumps directly to the Write End state. In the Write End state, the protocol conversion unit 122 waits for the bvalid signal to be asserted on the B channel or the reg_axi_bchannel_bypass signal to be asserted. This indicates that the protocol conversion unit 122 is waiting for confirmation of the completion of the write operation or is bypassing the process of waiting for the response through some mechanism.

[0077] Write Wait (awready) - This is a signal in the Advanced eXtensible Interface Bus protocol that indicates that the master device can send the write address.

[0078] Write Wait (wready) - This is a signal in the Advanced eXtensible Interface Bus protocol that indicates that the master device can send the write data.

[0079] Write Operation Complete (bvalid) - This is a signal in the Advanced eXtensible Interface Bus protocol that indicates that the write operation has been completed and the slave device is ready to send the write response.

[0080] Configuration Signal (reg_axi_bchannel_bypass) - This is a register signal that controls whether to bypass the waiting for the B channel response.

[0081] Figure 11 For a complete multi-die synchronization process, the multi-die includes a first die VIP0, a second die VIP1, a third die VIP(n-1), and a fourth die VIP(n).

[0082] When the first die VIP0, the second die VIP1, the third die VIP(n-1), and the fourth die VIP(n) obtain the control instruction, the front-end unit 111 of the first die VIP0 receives the control instruction fe_pe_sema, which causes the first die VIP0 to enter a stall state and send a first synchronization signal to the die that needs to be synchronized, while recording the transmission target identifier. When the first die VIP0 receives the synchronization signal sema1to0, the first die VIP0 enters a work state.

[0083] For the second die VIP1, according to the instruction, the second die VIP1 can be made to enter a stall state, but no synchronization signal output data is output. When the synchronization signal sema0to1 sent by the first die VIP0 is received, the state machine of the second die VIP1 re-flashes to the next stall state, and sends the synchronization signal sema1to2 to the third die VIP(n-1) in this stage. When the synchronization signal sema2to1 sent by the third die VIP(n-1) is received, the state jumps to the working state, and the synchronization signal sema1to0 is sent to the first die VIP0.

[0084] Referring to Figure 12 The embodiment of the disclosure also provides a die, and the first die applies the hardware accelerator of any one of the above.

[0085] Referring to Figure 13 The embodiment of the disclosure also provides a multi-die cooperative system, comprising a first die and a second die, and the first die and the second die both run the hardware accelerator of any one of the above.

[0086] Referring to Figure 14 The embodiment of the disclosure also provides a hardware acceleration method, applied to a first die in a multi-die cooperative system, and the method comprises the following steps: Step S1: generating and processing synchronization signal output data, the synchronization signal being used for controlling synchronization state jumping between dies.

[0087] Step S2: receiving the synchronization signal output data, and sending the synchronization signal input data sent by other dies to the synchronization control module.

[0088] According to the hardware accelerator scheme provided by the embodiment of the disclosure, the hardware accelerator is applied to a first die in a multi-die cooperative system, and a synchronization control module of the hardware accelerator generates and processes synchronization signal output data, the synchronization signal being used for controlling synchronization state jumping between dies. The synchronization control module sends the synchronization signal output data to a synchronization transceiver module, and the synchronization transceiver module sends synchronization signal input data sent by other dies to the synchronization control module. The embodiment of the disclosure realizes a neural network computing platform with greater computing power and excellent cooperative computing capability by using a multi-die (DIE) technology without changing a chip architecture.

[0089] Referring to Figure 15 The embodiment of the disclosure also provides a hardware acceleration method, applied to a multi-die cooperative system comprising a first die and a second die, and the method comprises the following steps: Step T1: the first die generates synchronization signal output data, enters a stall state, records a second die identifier, and sends the synchronization signal output data to the second die. Step T2: After the second die receives the synchronous signal output data, return the response synchronous signal input data; Step T3: The first die jumps to the working state according to the response synchronous signal input data.

[0090] According to the hardware accelerator scheme provided by the embodiment of the present disclosure, the hardware accelerator is applied to the first die in the multi-die cooperative system, and a synchronization control module of the hardware accelerator generates and processes synchronous signal output data. The synchronization signal is used to control the synchronization state jump between the multiple dies. The synchronization control module sends the synchronous signal output data to a synchronization transceiver module, and the synchronization transceiver module sends the received synchronous signal input data sent by other dies to the synchronization control module. The embodiment of the present disclosure realizes a neural network computing platform with greater computing power and excellent cooperative computing capability through the multi-die (DIE) technology without changing the chip architecture.

[0091] It should be understood that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts of each embodiment can be referred to each other, and each embodiment focuses on the difference from other embodiments. Especially, for the method embodiment, since it is basically similar to the method described in the device and system embodiment, the description is relatively simple, and the related parts can refer to the part of the description of other embodiments.

[0092] It should be understood that the above describes specific embodiments of the present disclosure. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different than the order in which they are recited in the embodiments and still achieve desirable results. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In some implementations, multitasking and parallel processing can be advantageous or necessary.

[0093] It should be understood that the elements described herein in singular form or shown in the figures only as one do not mean that the number of the elements is limited to one. In addition, the modules or elements described or shown herein as separate can be combined into a single module or element, and the modules or elements described or shown herein as single can be split into multiple modules or elements.

[0094] It should also be understood that the terms and expressions used herein are used only to describe and not to limit one or more embodiments of the present disclosure. The use of such terms and expressions does not mean that any illustration and description (or part thereof) is excluded. It should be recognized that various modifications can exist and should be included in the scope of the claims. Other modifications, changes and replacements can also exist. Accordingly, the claims should be considered to cover all these equivalents.

Claims

1. A hardware accelerator, wherein: The hardware accelerator is applied to a first die in a multi-die collaborative system, and the hardware accelerator includes: A synchronization control module, configured to generate and process synchronization signal output data, wherein the synchronization signal is used to control synchronization state jumps between multiple dies; The synchronous transceiver module is used to receive the synchronization signal output data sent by the synchronization control module, and send the synchronization signal input data received from other bare chips to the synchronization control module.

2. The hardware accelerator according to claim 1, wherein: The synchronization control module sends the synchronization signal output data to the synchronization transceiver module through the synchronization output bus, and the synchronization transceiver module receives the synchronization signal input data sent by other bare chips through the synchronization input bus. The synchronization signal output data and the synchronization signal input data both include: source identification, target identification, transmission type, and handshake through valid signals and response signals.

3. The hardware accelerator according to claim 2, wherein: The synchronization control module includes: A front-end unit, configured to generate the synchronization signal output data and control the synchronization state jump of the first bare chip according to a control instruction corresponding to the received synchronization signal input data; A global synchronization unit for synchronizing and clocking the synchronization signal input data and the synchronization signal output data The synchronous bus unit is configured to process the synchronous signal output data and determine whether the synchronous signal input data corresponds to the first die.

4. The hardware accelerator according to claim 3, wherein: The front-end unit comprises: A finite state machine, comprising: a read state, a pause state, and a pre-pause state, for generating an eject signal according to a control instruction corresponding to the received synchronization signal input data; a first-in-first-out buffer for storing the eject signal received from the finite state machine and providing a valid pre-pause instruction to the finite state machine; a control instruction buffer, configured to store and output the synchronization signal output data, and output control instructions to the first-in-first-out buffer; The read state is entered into the pre-pause state after the eject signal is generated and a valid pre-pause instruction is received; the pause state is entered into after waiting for a response to the synchronization signal and returning the first die to the read state; the pre-pause state is a transition state, which jumps to the pause state.

5. The hardware accelerator according to claim 4, wherein: The synchronous bus unit is specifically used for: Processing the synchronization signal output data and transmitting it to the synchronization transceiver module; The synchronization signal input data is received, and if it is determined by comparing the target identifier that it does not correspond to the first die, it is forwarded to other die; if it is determined that it corresponds to the first die, a control instruction is sent to the front-end module to control the synchronization state jump of the die. The hardware accelerator according to claim 5 , wherein: The synchronous transceiver module includes: A configuration interface unit is configured to receive synchronization signal input data sent by the other bare chips and configure a transmission address of the other bare chips; The protocol conversion unit is configured to receive the transmission address of the other die and generate a bus signal of the Advanced Extensible Interface bus protocol according to the transmission address.

7. The hardware accelerator according to claim 6, wherein: The state machine of the protocol conversion unit includes: Write drive status, which is the drive write address and control signal; Write handshake state, which is to send write data and wait for ready signal; Write wait state, ready for waiting for write response channel; The write end state is waiting for the write response valid signal or bypass signal to complete the transfer.

8. A bare chip, wherein The die applies the hardware accelerator according to any one of claims 1 to 7.

9. A multi-die collaborative system, wherein: The multi-die collaborative system includes a first die and a second die, and the hardware accelerator according to any one of claims 1 to 7 runs on both the first die and the second die.

10. A hardware acceleration method, applied to a first die in a multi-die collaborative system, wherein: The method comprises: Generate and process synchronization signal output data, wherein the synchronization signal is used to control the synchronization state jump between multiple bare chips; The synchronization signal output data is received, and the synchronization signal input data received from other bare chips is sent to the synchronization control module.

11. A hardware acceleration method, wherein: The method is applied to a multi-die collaborative system, including a first die and a second die, and includes: The first die generates synchronization signal output data, enters a pause state and records the second die identifier, and sends the synchronization signal output data to the second die; After receiving the synchronization signal output data, the second bare chip returns the response synchronization signal input data; The first bare chip jumps to a working state according to the response synchronization signal input data.

Images