Image noise reduction method and device based on bus controllable noise reduction circuit and electronic equipment

Abstract

The invention provides an image noise reduction method and device based on a bus controllable noise reduction circuit and electronic equipment, and relates to the technical field of image processing, and the method comprises the steps: carrying out the logic splicing processing of brightness data in an input image, storing the spliced data in a data ping-pong form, and determining target input data; performing mirror image edge filling processing on the target input data, determining mirror image edge filling data, and matching a corresponding target noise reduction mode from a preset noise reduction mode set according to an image processing scene of the input image; and performing block similarity calculation processing on the mirror image edge filling data based on the target noise reduction mode, determining a noise reduction coefficient, and calculating a noise reduction value by using the noise reduction coefficient and the mirror image edge filling data so as to perform circuit noise reduction processing according to the noise reduction value. According to the invention, the noise reduction effect of the high-definition image can be obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, and in particular to an image denoising method and device based on a bus-controllable denoising circuit and electronic equipment. BACKGROUND

[0002] At present, the related technology proposes that the existing denoising circuit usually adopts a fixed mode of an 11x11 search window and a 3x3 block matching, calculates the pixel similarity weight based on the norm distance and the target distance through a Gaussian mixture model, but the scene adaptability of the above scheme is poor, and a single matching mode is difficult to adapt to scenes with large light differences (such as night / day), and the similarity weight calculation model is complex, thereby causing the circuit area to be too large to be mass-produced, and further causing high hardware resource consumption, in addition, the above scheme also has data boundary error, and unprocessed image edge data is easy to affect the denoising precision. SUMMARY

[0003] Therefore, the purpose of the present application is to provide an image denoising method and device based on a bus-controllable denoising circuit and electronic equipment, which can significantly improve the denoising effect of high-definition images.

[0004] In a first aspect, an image denoising method based on a bus-controllable denoising circuit is provided, which includes: performing logical splicing processing on the luminance data in the input image, and storing the spliced data in the form of data ping-pong to determine the target input data; performing mirror edge filling processing on the target input data to determine the mirror edge filling data, and matching the corresponding target denoising mode from the preset denoising mode set according to the image processing scene of the input image; performing block similarity calculation processing on the mirror edge filling data based on the target denoising mode to determine the denoising coefficient, and calculating the denoising value using the denoising coefficient and the mirror edge filling data to perform circuit denoising processing according to the denoising value.

[0005] In one embodiment, the step of performing logical splicing processing on the luminance data in the input image and storing the spliced data in the form of data ping-pong to determine the target input data includes: performing point splicing processing on the luminance data in groups of four data, and using the form of data ping-pong to alternately store the spliced data using two buffer areas to obtain thirteen rows of row storage data, and determining the row storage data as the target input data.

[0006] In an embodiment, the step of determining the mirror padding data by performing mirror padding processing on the target input data comprises: performing mirror padding processing on the target input data in the up-down direction, performing mirror rotation with the upper mirror symmetry line and the lower mirror symmetry line as the center to determine the first mirror padding data of the upper and lower parts; performing mirror padding processing on the target input data and the first mirror padding data in the left-right direction, performing mirror rotation with the left mirror symmetry line and the right mirror symmetry line as the center to determine the second mirror padding data of the left and right parts, and determining the target input data, the first mirror padding data and the second mirror padding data as the mirror padding data.

[0007] In an embodiment, the step of matching the target denoising mode from the preset denoising mode set according to the image processing scene of the input image comprises: determining the five-by-five block region processing mode as the target denoising mode when the light brightness of the image processing scene is less than a preset threshold; and determining the three-by-three block region processing mode as the target denoising mode when the light brightness of the image processing scene is not less than the preset threshold.

[0008] In an embodiment, the step of determining the denoising coefficient by performing block similarity calculation processing on the mirror padding data based on the target denoising mode comprises: determining the center block and the non-center block set by traversing the thirteen-by-thirteen search window constructed by the mirror padding data based on the block region size corresponding to the target denoising mode; and determining the denoising coefficient by comparing the brightness value of each non-center block in the non-center block set with the brightness value of the center block.

[0009] In an embodiment, after the step of determining the center block and the non-center block set, the step comprises: respectively storing the brightness value of each non-center block through a serial circuit to use one block data for denoising coefficient calculation in the same period.

[0010] In an embodiment, the step of calculating the denoising value using the denoising coefficient and the mirror padding data and performing circuit denoising processing according to the denoising value comprises: determining the denoising value by dividing the sum of the product of the denoising coefficient and the mirror padding data by the sum of the denoising coefficient based on a preset denoising processing model and a buffer structure.

[0011] In a second aspect, the embodiment of the present application further provides an image noise reduction device based on a bus controllable noise reduction circuit, which comprises: a row storage control module, which performs logical splicing processing on luminance data in an input image, stores the spliced data in a data ping-pong form to determine target input data; a mirror edge filling module, which performs mirror edge filling processing on the target input data to determine mirror edge filling data, and matches a corresponding target noise reduction mode from a preset noise reduction mode set according to an image processing scene of the input image; and a noise reduction calculation module, which performs block similarity calculation processing on the mirror edge filling data based on the target noise reduction mode, determines a noise reduction coefficient, and calculates a noise reduction value by using the noise reduction coefficient and the mirror edge filling data to perform circuit noise reduction processing according to the noise reduction value.

[0012] In a third aspect, the embodiment of the present application further provides an electronic device, which comprises a processor and a memory, the memory stores computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the method of any one of the first aspect.

[0013] In a fourth aspect, the embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions, when invoked and executed by a processor, cause the processor to implement the method of any one of the first aspect.

[0014] The embodiment of the present application brings the following beneficial effects:

[0015] The image noise reduction method, device and electronic device based on a bus controllable noise reduction circuit provided by the embodiment of the present application can significantly improve the noise reduction effect of a high-definition image.

[0016] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. The objects and other advantages of the present application can be realized and attained by the structure particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more apparent, the following will specifically describe a preferred embodiment in combination with the accompanying drawings. The present application is described in greater detail by way of specific embodiments as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A schematic structural diagram of a bus-controllable noise reduction circuit provided by an embodiment of the present invention;

[0020] Figure 2 A schematic flow chart of an image noise reduction method based on a bus-controllable noise reduction circuit provided by an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of a flow chart of a row storage processing method provided by an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a timing rotation of a row storage provided by an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of a five-by-five block area processing mode provided in an embodiment of the present invention;

[0024] Figure 6 A schematic diagram of a three-by-three block area processing mode provided in an embodiment of the present invention;

[0025] Figure 7 A schematic diagram of an alternate point sampling method provided by an embodiment of the present invention;

[0026] Figure 8 A schematic diagram of a serial circuit implementation method provided by an embodiment of the present invention;

[0027] Figure 9 A schematic diagram of an elastic buffer structure provided by an embodiment of the present invention;

[0028] Figure 10 A schematic structural diagram of an image noise reduction device based on a bus-controllable noise reduction circuit provided by an embodiment of the present invention;

[0029] Figure 11 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be described below in detail with embodiments. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0031] At present, the existing noise reduction circuit usually adopts a fixed mode of a 11x11 search window and a 3x3 block matching, calculates the pixel similarity weight based on the norm distance and the target distance through a Gaussian mixture model, but the scene adaptability of the above scheme is poor, and a single matching mode is difficult to adapt to scenes with large light differences (such as night / day), and the similarity weight calculation model is complex, thereby causing the circuit area to be too large to be mass-produced, and further causing the hardware resource consumption to be high, in addition, the above scheme also has data boundary error, and the unprocessed image edge data is easy to affect the noise reduction precision, based on this, the image noise reduction method, device and electronic equipment based on the bus controllable noise reduction circuit provided by the present application can support the matching mechanism of two block modes, make the circuit application environment wider, and use the buffer structure method to replace the existing linear interpolation method to do division, reduce more circuit area, in addition, the mirror edge filling technology is used in the circuit to reduce the noise reduction error, and the step-by-step edge filling is used to reduce the row buffer area, so that the noise reduction effect of the high-definition image can be significantly improved.

[0032] In order to facilitate the understanding of the present embodiment, first, a kind of image noise reduction method based on bus controllable noise reduction circuit disclosed by the present application embodiment is introduced in detail, which is applied to bus controllable noise reduction circuit, bus controllable noise reduction circuit is used to configure different parameters and switch different noise reduction modes through bus, based on Figure 1 The structure diagram of the bus controllable noise reduction circuit is shown, the present application embodiment introduces the image noise reduction method based on bus controllable noise reduction circuit in detail, referring to Figure 2 The flowchart of the image noise reduction method based on bus controllable noise reduction circuit is shown, the method mainly includes the following steps S202 to S206:

[0033] Step S202, the luminance data in the input image is subjected to logical splicing processing, and the spliced data is stored in the form of data ping-pong, and the target input data is determined, wherein the data ping-pong is used for the luminance data, and the row delay processing is carried out, so that multiple rows of data are taken out for processing at the same time period, the principle of ping-pong buffer (i.e., data ping-pong) is to realize the smooth flow of data transmission by alternately using two buffer areas, so as to improve the efficiency and stability of the system, in one embodiment, referring to Figure 3A flowchart of a line storage processing method is shown. The luminance data can be point spliced in groups of four data, and the spliced data is alternately stored using two buffers in a ping-pong manner to obtain thirteen lines of line storage data. The line storage data is determined as target input data. The luminance data is logically spliced and stored in the line buffer without encoding.

[0034] Specifically, the input data is stored in a point splicing and line buffer ping-pong manner to obtain the required 13 lines of data. The data is stored and read in groups of four spliced data (the number of spliced data can be controlled by the bus, and the minimum number of spliced data is two). The data is read four points at a time instead of one point at a time, and the data is read before it is written. Therefore, only 12 line buffers are used in the horizontal direction, saving one line buffer. See Figure 4 A timing rotation diagram of line storage is shown. The pre-edge writing part can reduce the logic of the subsequent circuit edge control part.

[0035] In actual applications, one line of data is 1920 8-bit data. Because the reading and writing is single-ported, only reading or writing can be performed at a time. If 13 lines of data need to be processed at the same time, 13 1920*8 line buffers are required. If a point splicing method is used, only 4 points are read at a time or 4 points are written at a time. The data is read before it is written. The data of the current line can be read first, and then written after a few points. This avoids data being overwritten and ensures the integrity of the required data. According to area synthesis, the memory area of 1920*8 is larger than that of 480*32. Figure 4 A timing rotation diagram of line storage is shown.

[0036] In step S204, the target input data is mirror edge processing, the mirror edge data is determined, and the corresponding target noise reduction mode is matched from the preset noise reduction mode set according to the image processing scene of the input image. In one embodiment, the target input data is mirror edge processing in the up-down direction, and the first mirror edge data of the upper and lower parts is determined by mirror rotation about the upper mirror symmetry line and the lower mirror symmetry line. The target input data and the first mirror edge data are mirror edge processing in the left-right direction, and the second mirror edge data of the left and right parts is determined by mirror rotation about the left mirror symmetry line and the right mirror symmetry line. The target input data, the first mirror edge data, and the second mirror edge data are determined as the mirror edge data.

[0037] Specifically, 13 lines of stored data can be read out, and the data can be padded in the vertical direction by mirror padding. The purpose of reducing the row cache area can be achieved by step-by-step padding. For example, when the original data received by the circuit is 2*2 data, mirror padding is first performed in the upper and lower directions, and the original data is rotated with the upper mirror symmetry line and the lower mirror symmetry line as the center to obtain the padded data of the upper and lower areas; then the obtained data is rotated with the left mirror symmetry line and the right mirror symmetry line as the center to obtain the padded data of the left and right areas (when padding left and right, the data of the upper and lower padding areas need to be padded together. The reason for padding the upper and lower edges first and then the left and right edges is that the data needs to be stored first when processing multiple lines of video data. If the left and right edges are padded first, the data of one line will increase, resulting in a larger memory area for storing the data). Therefore, the image effect obtained by the circuit noise reduction processing can be better through mirror padding.

[0038] Further, when matching the corresponding target noise reduction mode from the preset noise reduction mode set, see Figure 5 The schematic diagram of a five-by-five block area processing mode is shown. When the light brightness of the image processing scene is less than a preset threshold, the five-by-five block area processing mode is determined as the target noise reduction mode. Figure 6 The diagram shows a three-by-three block area processing mode. When the light brightness of the image processing scene is not less than a preset threshold, the three-by-three block area processing mode is determined as the target noise reduction mode. The difference between the two modes lies in the size of the search window and the amount of block area data processing. The 5*5 block area processing mode is mainly used for image processing in dark scenes such as night and cloudy days, because the image effect of dark scenes is poor and more image data is required for processing; the 3*3 block area processing mode is suitable for normal daytime scenes with better light. The image effect received by the circuit is better, and less image data needs to be processed for noise reduction. The block area size can be adjusted according to the bus configuration parameter control module.

[0039] Step S206, based on the target noise reduction mode, block similarity calculation processing is performed on the mirrored edge-filled data to determine the noise reduction coefficient, and the noise reduction value is calculated using the noise reduction coefficient and the mirrored edge-filled data to perform circuit noise reduction processing according to the noise reduction value, wherein the circuit noise reduction processing is to reduce noise for the brightness of the image. In one embodiment, the block similarity calculation is to calculate the corresponding filter coefficient (i.e., the noise reduction coefficient). The embodiment of the present invention also provides an implementation method of circuit noise reduction, and the specific details are as follows (1) to (3):

[0040] (1) Based on the size of the block region corresponding to the target noise reduction mode, traverse the 13*13 search window constructed by the mirror edge data to determine the center block and the non-center block set. The 13*13 search window means that 13*13 image data need to be processed at one time. The front 13 refers to 13 rows of image data, and the rear 13 refers to that 13 points of data need to be processed in each row. The 5*5 block region is the 5*5 data selected in the search window for calculating the noise reduction coefficient. As shown in Figure 5 , the 5*5 block with the center point s1 is moved one point at a time to the 5*5 block with the center point sn, and then moved to the next time. In this way, the non-center blocks are obtained. In the calculation of the 5*5 block with s1 as the center (i.e., the non-center block) and the 5*5 block with Y as the center (i.e., the center block), a filter coefficient can be finally obtained. This filter coefficient is the proportion of s1 data in this block in this 13*13 search window. The center point Y represents the original image data, and the points around it are the block regions of the block. The block region formed is called the center block, and S1-Sn are the center points of the similar blocks of the center block. S1 represents the first point in the 11*11 region centered on the center Y of the search window.

[0041] In an embodiment, referring to the schematic diagram of a point-by-point sampling method shown in Figure 7 , the value range of n is as shown in Figure 7 . The blocks with horizontal lines in the figure are the value points of the similar block center points Sn. By using the point-by-point sampling method, the number of blocks that need to be calculated can be reduced.

[0042] (2) Respectively store the luminance values corresponding to each non-center block through a serial circuit to calculate the noise reduction coefficient using one block data in the same period, and compare the luminance values corresponding to each non-center block in the non-center block set with the luminance value corresponding to the center block to determine the noise reduction coefficient. In an embodiment, referring to Figure 8As shown in a schematic diagram of a serial circuit implementation method, in order to realize the operation of two similar blocks, 3*3 data (5*5 data) of two blocks need to appear in the same period on the circuit, but this way will cause the circuit area to increase, therefore, a serial way is adopted, taking the first of two blocks as an example, the points in the non-central block are periodically input in the original way, the points in the central block are all stored by registers, and then the points of the non-central block and the stored points of the central block are compared, that is, the filter value obtained by normally comparing the luminance of 121 non-central blocks and the luminance of the central block is calculated, and by using the serial way, the luminance is stored as a1, a2,..., a15, and then the luminance of the non-central block is compared with the luminance of the central block, so that the calculation of the noise reduction coefficient can be completed by using only one block data in the same period.

[0043] (3) Based on the preset noise reduction processing model and the buffer structure, the sum of the product of the noise reduction coefficient and the mirror edge supplement data is divided by the sum of the noise reduction coefficient to determine the noise reduction value, wherein:

[0044]

[0045] In an embodiment, since the circuit cannot directly perform division, and the linear interpolation division and the register storage division data way consume a large area, the buffer structure is used to store the division data, as shown in Figure 9 As shown in a schematic diagram of an elastic buffer structure, the division data to be used is stored in the buffer structure, and in the process of circuit noise reduction, ∑(noise reduction coefficient) is used as an address, so that the value of the corresponding point can be given through the buffer structure at any time.

[0046] In summary, the application can support two block mode matching mechanisms, so that the circuit application environment is wider, and the buffer structure is used to replace the existing linear interpolation division to reduce more circuit area, in addition, the mirror edge supplement technology is used in the circuit to reduce the noise reduction error, and the step-by-step edge supplement is used to reduce the row buffer area, so that the noise reduction effect of the high-definition image can be significantly improved.

[0047] For the image noise reduction method based on the bus controllable noise reduction circuit provided by the foregoing embodiment, an image noise reduction device based on the bus controllable noise reduction circuit is provided, which is applied to the bus controllable noise reduction circuit, as shown in Figure 10 As shown in a structural schematic diagram of an image noise reduction device based on the bus controllable noise reduction circuit, the device comprises the following parts:

[0048] The row storage control module 1002 performs logical splicing processing on the luminance data in the input image, and stores the spliced data in the form of data ping-pong to determine the target input data.

[0049] The mirror edge filling module 1004 performs mirror edge filling processing on the target input data to determine mirror edge filling data, and matches a corresponding target denoising mode from a preset denoising mode set according to an image processing scene of the input image.

[0050] The denoising calculation module 1006 performs block similarity calculation processing on the mirror edge filling data based on the target denoising mode to determine a denoising coefficient, and calculates a denoising value using the denoising coefficient and the mirror edge filling data, so as to perform circuit denoising processing according to the denoising value.

[0051] The image denoising device based on the bus controllable denoising circuit provided by the embodiments of the present application can significantly improve the denoising effect of high-definition images.

[0052] In one implementation, when performing logical splicing processing on the luminance data in the input image and storing the spliced data in the form of data ping-pong to determine the target input data, the row storage control module 1002 is further configured to: perform point splicing processing on the luminance data in groups of four data, and alternately store the spliced data using two buffer areas in the form of data ping-pong to obtain thirteen rows of row storage data, and determine the row storage data as the target input data.

[0053] In one implementation, when performing mirror edge filling processing on the target input data to determine mirror edge filling data, the mirror edge filling module 1004 is further configured to: perform mirror edge filling processing on the target input data in the up-down direction, perform mirror rotation around the upper mirror symmetry line and the lower mirror symmetry line to determine first mirror edge filling data of the upper and lower parts; perform mirror edge filling processing on the target input data and the first mirror edge filling data in the left-right direction, perform mirror rotation around the left mirror symmetry line and the right mirror symmetry line to determine second mirror edge filling data of the left and right parts, and determine the target input data, the first mirror edge filling data and the second mirror edge filling data as the mirror edge filling data.

[0054] In one implementation, when matching a corresponding target denoising mode from a preset denoising mode set according to an image processing scene of the input image, the mirror edge filling module 1004 is further configured to: when the light brightness of the image processing scene is less than a preset threshold, determine a five-by-five block region processing mode as the target denoising mode; and when the light brightness of the image processing scene is not less than the preset threshold, determine a three-by-three block region processing mode as the target denoising mode.

[0055] In an implementation, when the step of performing block similarity calculation on the mirror padding data based on the target noise reduction mode to determine the noise reduction coefficient is performed, the noise reduction calculation module 1006 is further configured to: based on the size of the block area corresponding to the target noise reduction mode, traverse a 13*13 search window constructed by the mirror padding data to determine the center block and the non-center block set; compare the luminance value of each non-center block in the non-center block set with the luminance value of the center block to determine the noise reduction coefficient.

[0056] In an implementation, after the step of determining the center block and the non-center block set is performed, the noise reduction calculation module 1006 is further configured to: store the luminance value of each non-center block through a serial circuit respectively to perform noise reduction coefficient calculation using one block data in the same period.

[0057] In an implementation, when the step of calculating the noise reduction value by using the noise reduction coefficient and the mirror padding data to perform circuit noise reduction processing according to the noise reduction value is performed, the noise reduction calculation module 1006 is further configured to: based on a preset noise reduction processing model and a buffer structure, divide the sum of the product of the noise reduction coefficient and the mirror padding data by the sum of the noise reduction coefficient to determine the noise reduction value.

[0058] The device provided by the embodiments of the present application has the same implementation principle and technical effects as the foregoing method embodiments. For brevity, the part not mentioned in the device embodiment part can be referred to the corresponding content in the foregoing method embodiments.

[0059] The electronic device provided by the embodiments of the present application includes a processor and a storage device. The storage device stores a computer program. When the computer program is run by the processor, the method of any one of the embodiments described above is executed.

[0060] Figure 11 The structure schematic diagram of the electronic device provided by the embodiments of the present application is shown in the figure. The electronic device 100 includes a processor 110, a memory 111, a bus 112 and a communication interface 113. The processor 110, the communication interface 113 and the memory 111 are connected through the bus 112. The processor 110 is configured to execute the executable modules stored in the memory 111, such as a computer program.

[0061] The memory 111 can include a high-speed random access memory (RAM) and can also include a non-volatile memory, such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 113 (which can be wired or wireless). The Internet, wide area network, local area network, metropolitan area network, etc. can be used.

[0062] Bus 112 can be an ISA bus, a PCI bus, or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 11 Only one bidirectional arrow is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0063] The memory 111 is configured to store a program, and the processor 110 executes the program after receiving an execution instruction. The method executed by the device for defining the flow process according to any of the foregoing embodiments of the application can be applied to the processor 110 or implemented by the processor 110.

[0064] The processor 110 can be an integrated circuit chip with processing capability. In the implementation process, each step of the foregoing method can be completed by an integrated logic circuit of hardware in the processor 110 or an instruction in the form of software. The processor 110 described above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; or can be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiments of the application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, or other mature storage media in the art. The storage medium is located in the memory 111, and the processor 110 reads information in the memory 111 and combines hardware to complete the steps of the foregoing method.

[0065] The computer program product of the readable storage medium provided by the embodiments of the application includes a computer readable storage medium storing program codes, and the program codes include instructions for executing the method described in the foregoing method embodiments. For specific implementation, reference can be made to the foregoing method embodiments, which will not be described here.

[0066] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes instructions for making a computer device (which can be a personal computer, an electronic device, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0067] Finally, it should be noted that: the above-described embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit them. The protection scope of the present application is not limited to this. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily think of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed by the present application, or make equivalent replacements to some of the technical features. The modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An image noise reduction method based on a bus-controllable noise reduction circuit, characterized in that: The method comprises: Perform logical splicing processing on the brightness data in the input image, and store the spliced ​​data in the form of data ping-pong to determine the target input data; Performing mirror edge filling processing on the target input data to determine mirror edge filling data, and matching a corresponding target noise reduction mode from a preset noise reduction mode set according to an image processing scenario of the input image; The mirrored edge-filled data is subjected to block similarity calculation processing based on the target noise reduction mode to determine a noise reduction coefficient, and a noise reduction value is calculated using the noise reduction coefficient and the mirrored edge-filled data to perform circuit noise reduction processing according to the noise reduction value.

2. The image noise reduction method based on a bus-controllable noise reduction circuit according to claim 1, characterized in that: The step of performing logical splicing processing on the brightness data in the input image, storing the spliced ​​data in a data ping-pong format, and determining the target input data includes: The brightness data is point-spliced ​​in groups of four data, and the spliced ​​data is alternately stored in two buffers in a data ping-pong format to obtain thirteen rows of row-stored data, which are then determined as the target input data.

3. The image noise reduction method based on a bus-controllable noise reduction circuit according to claim 1, characterized in that: The step of performing mirror edge padding processing on the target input data to determine the mirror edge padding data includes: Perform mirror edge filling processing on the target input data in the upper and lower directions, perform mirror rotation around the upper and lower mirror symmetry lines, and determine first mirror edge filling data of the upper and lower parts; The target input data and the first mirror-padded data are mirror-padded in the left and right directions, mirror-rotated with the left mirror symmetry line and the right mirror symmetry line as the center, and the second mirror-padded data of the left and right parts are determined. The target input data, the first mirror-padded data and the second mirror-padded data are determined as the mirror-padded data.

4. The image noise reduction method based on a bus-controllable noise reduction circuit according to claim 1, characterized in that: The step of matching a corresponding target noise reduction mode from a preset noise reduction mode set according to an image processing scenario of the input image comprises: When the light brightness of the image processing scene is less than a preset threshold, determining a five-by-five block area processing mode as the target noise reduction mode; When the light brightness of the image processing scene is not less than a preset threshold, a three-by-three block area processing mode is determined as the target noise reduction mode.

5. The image noise reduction method based on a bus-controllable noise reduction circuit according to claim 1, characterized in that: The step of performing block similarity calculation processing on the mirror edge-filling data based on the target noise reduction mode to determine the noise reduction coefficient includes: Based on the block area size corresponding to the target noise reduction mode, traverse the thirteen by thirteen search window constructed by the mirrored edge-filling data to determine the center block and the non-center block set; The brightness values ​​corresponding to each non-central block in the non-central block set are compared with the brightness value corresponding to the central block to determine the noise reduction coefficient.

6. The image noise reduction method based on a bus-controllable noise reduction circuit according to claim 5, characterized in that: After the steps of determining the set of central blocks and non-central blocks, including: The brightness values ​​corresponding to each of the non-central blocks are stored respectively through a serial circuit, so that a block of data is used to calculate the noise reduction coefficient in the same cycle.

7. The image noise reduction method based on a bus-controllable noise reduction circuit according to claim 1, characterized in that: The step of calculating a noise reduction value by using the noise reduction coefficient and the mirror edge padding data, and performing circuit noise reduction processing according to the noise reduction value, comprises: Based on a preset noise reduction processing model and a buffer structure, the noise reduction value is determined by dividing the sum of the products of the noise reduction coefficient and the mirror edge padding data by the sum of the noise reduction coefficients.

8. An image noise reduction device based on a bus-controllable noise reduction circuit, characterized in that: The device comprises: The row memory control module performs logical splicing processing on the brightness data in the input image and stores the spliced ​​data in the form of data ping-pong to determine the target input data; a mirror edge filling module, performing mirror edge filling processing on the target input data, determining mirror edge filling data, and matching a corresponding target noise reduction mode from a preset noise reduction mode set according to an image processing scenario of the input image; The noise reduction calculation module performs block similarity calculation processing on the mirrored edge-filled data based on the target noise reduction mode to determine a noise reduction coefficient, and calculates a noise reduction value using the noise reduction coefficient and the mirrored edge-filled data to perform circuit noise reduction processing according to the noise reduction value.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the method according to any one of claims 1 to 7.

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