Gate drive circuit and display panel

Abstract

The invention provides a gate drive circuit and a display panel, and the gate drive circuit comprises cascaded multi-stage first gate drive sub-circuits, and a control module in each first gate drive sub-circuit controls (pulls down or pulls up) a signal (potential) of a first node according to a starting signal and a first voltage signal of the stage. The effective level of the signal of the first node is related to the ineffective level of the starting signal of the stage, and when the signal of the first node is the effective level, the output module controls (pulls down or pulls up) the first grid signal to be the ineffective level according to a second voltage signal (the amplitude is different from the amplitude of the first voltage signal); the ith-stage starting signal received by the ith-stage first gate driving sub-circuit is the (i-k) th-stage first gate signal, i is greater than 1, k is less than i and greater than 0, and the risk of waveform abnormity of the first gate signal is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] The GOA (Gate-driver On Array) technology is conducive to the design of the narrow frame of the gate driving circuit and the display panel, and thus is widely applied. However, in the existing GOA circuit, due to the poor transmission ability of some transistors to signals, the potential of some nodes in the GOA circuit cannot reach the required potential, so that the waveform of the gate signal output by the GOA circuit is abnormal. SUMMARY

[0003] Embodiments of the present application provide a gate driving circuit and a display panel to solve the problem that the waveform of the gate signal output by the GOA circuit is abnormal due to the characteristic difference of different transistors in the existing GOA circuit.

[0004] Embodiments of the present application provide a gate driving circuit, which comprises a plurality of cascaded first gate driving sub-circuits, and each first gate driving sub-circuit comprises:

[0005] a control module electrically connected to a start line, a first voltage line and a first node of the current stage, for controlling the signal of the first node of the current stage according to the start signal transmitted by the start line and the first voltage signal transmitted by the first voltage line, the voltage value of the effective level corresponding to the signal of the first node of the current stage being related to the invalid level of the start signal of the current stage;

[0006] an output module electrically connected to the first node and a second voltage line, for controlling the first gate signal of the current stage to be the corresponding invalid level according to the second voltage signal transmitted by the second voltage line when the signal of the first node is the corresponding effective level;

[0007] wherein the start signal of the i-th stage received by the first gate driving sub-circuit of the i-th stage is the first gate signal of the i-k-th stage output by the first gate driving sub-circuit of the i-k-th stage, i is a positive integer greater than 1, and k is a positive integer less than i;

[0008] wherein the first voltage signal is used to pull down the potential of the first node, and the second voltage signal is used to pull down the level of the first gate signal to the corresponding invalid level, or the first voltage signal is used to pull up the potential of the first node, and the second voltage signal is used to pull up the level of the first gate signal to the corresponding invalid level;

[0009] wherein the amplitude of the first voltage signal is different from the amplitude of the second voltage signal.

[0010] The embodiment of the present application further provides a display panel, comprising a display area and a first non-display area and a second non-display area located at two adjacent sides of the display area, and a third non-display area is arranged between the first non-display area and the second non-display area.

[0011] The gate drive circuit as described in any of the above is arranged in the first non-display area and the third non-display area, and further comprises a plurality of cascaded second gate drive sub-circuits, each of which is electrically connected to a fourth voltage line for transmitting a fourth voltage signal, and is used to pull down or pull up a level of a second gate signal of the second gate drive sub-circuit according to the fourth voltage signal.

[0012] The first voltage line, the second voltage line and the fourth voltage line are further arranged in the first non-display area.

[0013] The second non-display area is provided with a second voltage bus electrically connected to the second voltage line, a fourth voltage bus electrically connected to the fourth voltage line, and a connection line electrically connected between the second voltage bus and the fourth voltage bus to electrically connect the second voltage bus and the fourth voltage bus.

[0014] The present application provides a gate drive circuit and a display panel, comprising a plurality of cascaded first gate drive sub-circuits, each of which comprises a control module for controlling (pulling down or pulling up) a signal (of a potential) of a first node of the first gate drive sub-circuit according to a start signal of the first gate drive sub-circuit and a first voltage signal transmitted by a first voltage line, and the voltage value of the corresponding effective level of the signal of the first node is related to an ineffective level of the start signal of the first gate drive sub-circuit; an output module for controlling (pulling down or pulling up) a first gate signal of the first gate drive sub-circuit to a corresponding ineffective level according to a second voltage signal transmitted by a second voltage line when the signal of the first node is the corresponding effective level; the start signal of the i-th first gate drive sub-circuit received by the i-th first gate drive sub-circuit is the first gate signal of the i-k-th first gate drive sub-circuit output by the output of the i-k-th first gate drive sub-circuit, i is a positive integer greater than 1, and k is a positive integer less than i, and the amplitude of the first voltage signal is set to be different from the amplitude of the second voltage signal to meet the requirement that the voltage value of the corresponding ineffective level of the first gate signal output by the first gate drive sub-circuit controlled thereby meets the requirement, thereby reducing the risk of abnormal waveform of the first gate signal. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The driving architecture diagram of the display panel provided by the embodiment of the present application is shown.

[0016] Figure 2A circuit diagram of the first gate driving sub-circuit provided for the embodiment of the present application.

[0017] Figure 3 A timing diagram of part of the signals in the first gate driving sub-circuit provided for the comparative example and the embodiment of the present application.

[0018] Figure 4 A circuit layout diagram of a partial area of the display panel provided for the embodiment of the present application.

[0019] Figure 5 A circuit layout diagram of a partial area of the display panel provided for the comparative example of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person skilled in the art without any creative work fall within the protection scope of the present application. In this document, the phrase "embodiments" means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears at various places in the specification is not necessarily all referring to the same embodiment, nor is it necessarily referring to only one alternative embodiment. It is explicitly and implicitly understood by a person skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] It should be noted that the "effective level" in the present application can be understood as the potential in the signal for controlling the opening of the corresponding device, which can be the corresponding high potential or low potential.

[0022] The embodiments of the present application provide a gate driving circuit and a display panel comprising the same, which include but are not limited to the following embodiments and combinations of the following embodiments.

[0023] In some embodiments, the gate driving circuit is combined with Figure 1 , Figure 2 and Figure 4As shown, the gate drive circuit 10 comprises a plurality of cascaded first gate drive sub-circuits Nscan_T2, each of which comprises: a control module 301 electrically connected to an enable line of the current stage, a first voltage line (connected to a first voltage bus L1) and a first node P of the current stage, configured to control a signal of the first node P of the current stage according to an enable signal S transmitted by the enable line of the current stage and a first voltage signal V1 transmitted by the first voltage line (connected to the first voltage bus L1), the signal of the first node P of the current stage corresponding to a voltage value of an effective level related to an ineffective level of the enable signal S of the current stage; and an output module 302 electrically connected to the first node P and a second voltage line (connected to a second voltage bus L2), configured to control a first gate signal Gate1 of the current stage to be a corresponding ineffective level according to a second voltage signal V2 transmitted by the second voltage line (connected to the second voltage bus L2) when the signal of the first node P is the corresponding effective level.

[0024] In the above formula, the enable signal S received by at least the first stage of the first gate drive sub-circuit Nscan_T2 is a frame start signal STV; the enable signal S received by the i-th stage of the first gate drive sub-circuit Nscan_T2 is the first gate signal Gate1(i-k) output by the i-k-th stage of the first gate drive sub-circuit Nscan_T2, i is a positive integer greater than 1, and k is a positive integer less than i.

[0025] When i=2, k can be 1, the enable signal S received by the first stage and the second stage of the first gate drive sub-circuit Nscan_T2 is the frame start signal STV, and the enable signal S received by each of the third stage to the last stage of the first gate drive sub-circuit Nscan_T2 is the first gate signal Gate1 of the previous 1 stage respectively;

[0026] When i=3, k can be 1 or 2, the enable signal S received by the first stage and the second stage of the first gate drive sub-circuit Nscan_T2 is the frame start signal STV, and the enable signal S received by each of the third stage to the last stage of the first gate drive sub-circuit Nscan_T2 is the first gate signal Gate1 of the previous 1 or 2 stages respectively;

[0027] That is, when i is larger, k can also have more values, the enable signal S received by the first stage to the i-1-th stage of the first gate drive sub-circuit Nscan_T2 is the frame start signal STV, and the enable signal S received by each of the i-th stage to the last stage of the first gate drive sub-circuit Nscan_T2 is the first gate signal Gate1 of the previous k stages respectively.

[0028] In the above formula, the enable signal S received by at least the first stage of the first gate drive sub-circuit Nscan_T2 is a frame start signal STV; the enable signal S received by the i-th stage of the first gate drive sub-circuit Nscan_T2 is the first gate signal Gate1(i-k) output by the i-k-th stage of the first gate drive sub-circuit Nscan_T2, i is a positive integer greater than 1, and k is a positive integer less than i. Figure 2As shown, the first voltage signal V1 (e.g. a first low voltage signal VGL) is used to pull down the potential of the first node P, and the second voltage signal V2 (e.g. a second low voltage signal VGL') is used to pull down the level of the first gate signal Gate1 to the corresponding invalid level, or the first voltage signal V1 is used to pull up the potential of the first node P, and the second voltage signal V2 is used to pull up the level of the first gate signal Gate1 to the corresponding invalid level; wherein the voltage value of the first voltage signal V1 (taking the first low voltage signal VGL as an example) is different from the voltage value of the second voltage signal V2 (taking the second low voltage signal VGL' as an example).

[0029] As can be known from the above, for the first gate drive sub-circuit Nscan_T2, the i-th level start signal S received by the first gate drive sub-circuit Nscan_T2 is the i-k-th level first gate signal Gate1(i-k) output by the i-k-th level first gate drive sub-circuit Nscan_T2, and the control module 301 can control the signal of the first node P of the current level according to the start signal S of the current level and the first voltage signal V1, and then when the signal of the first node P is the corresponding valid level, the output module 302 can control the first gate signal Gate1 of the current level to be the corresponding invalid level according to the second voltage signal V2, that is, the voltage value of the first voltage signal V1 may affect the level of the signal of the first node P (i.e. may affect the valid level of the signal of the first node P), that is, it does not necessarily affect the invalid level of the first gate signal Gate1 of the current level, but the voltage value of the second voltage signal V2 affects the invalid level of the first gate signal Gate1 of the current level, and then affects the voltage value of the valid level of the signal of the first node P of the k levels after the first gate signal Gate1 of the current level, and then affects the voltage value of the corresponding invalid level of the first gate signal Gate1 of the k levels after the current level.

[0030] That is, the voltage value of the invalid level of the i-k-th level first gate signal Gate1(i-k) affects the voltage value of the corresponding invalid level of the i-th level first gate signal Gate1(i) output by the i-th level first gate drive sub-circuit Nscan_T2, but the voltage value of the first voltage signal V1 does not necessarily affect the voltage value of the corresponding invalid level of the i-th level first gate signal Gate1(i).

[0031] It can be understood that, in the embodiment, the voltage value of the second voltage signal V2 (for example, the second low voltage signal VGL') is set to be different from the voltage value of the first voltage signal V1 (for example, the first low voltage signal VGL), so that the voltage value of the second voltage signal V2 can be set according to the requirement of the corresponding invalid level of the first gate signal Gate1 of the current stage, and the voltage value of the first voltage signal V1 can also be set according to the requirement of the valid level or the invalid level of the signal of the first node P, so that the voltage value of the second voltage signal V2 is not limited by the requirement of the voltage value of the first voltage signal V1, and the voltage value of the invalid level of the first gate signal Gate1 output by the first gate drive sub-circuit Nscan_T2 controlled by the second voltage signal V2 can meet the requirement, thereby reducing the risk of abnormal waveform of the first gate signal Gate1.

[0032] In some embodiments, as shown in FIGS. 3A and 3B, the control module 301 is further electrically connected to the second voltage line (connected to the second voltage bus L2) for controlling the signal of the first node P according to the start signal S, the first voltage signal V1 and the second voltage signal V2 (for example, the second low voltage signal VGL') transmitted by the second voltage line (connected to the second voltage bus L2). Figure 2 and Figure 4 As shown in FIGS. 3A and 3B, the control module 301 is further electrically connected to the third voltage line (connected to the third voltage bus L3) for controlling the signal of the first node P according to the start signal S, the first voltage signal V1 and the third voltage signal V3 (for example, the high voltage signal VGH) transmitted by the third voltage line (connected to the third voltage bus L3); one of the first voltage signal V1 (for example, the first low voltage signal VGL) and the third voltage signal V3 is used to pull down the potential of the first node P, and the other is used to pull up the potential of the first node P; the voltage value of the second voltage signal V2 (for example, the second low voltage signal VGL') and the voltage value of the first voltage signal V1 are both less than or greater than the voltage value of the third voltage signal V3; the absolute value of the difference between the voltage value of the second voltage signal V2 and the voltage value of the third voltage signal V3 is greater than the difference between the voltage value of the first voltage signal V1 and the voltage value of the third voltage signal V3.

[0033] That is, the signal of the first node P in the embodiment is also affected by the third voltage signal V3, and the voltage values of the first voltage signal V1 and the third voltage signal V3 can be different, for example, the first voltage signal V1 with a smaller amplitude can pull down the potential of the first node P, and the third voltage signal V3 with a larger amplitude can pull up the potential of the first node P, or vice versa, and the relationship between the two is not limited here.

[0034] As can be known from the above description, the second voltage signal V2 transmitted by the second voltage line (connected to the second voltage bus L2) is used to control the first gate signal Gate1 of the current stage to be the corresponding invalid level, and the invalid level of the first gate signal Gate1 here can be the high level or the low level corresponding to the signal.

[0035] In this embodiment, the voltage value of the second voltage signal V2 and the voltage value of the first voltage signal V1 are both less than or greater than the voltage value of the third voltage signal V3, that is, the second voltage signal V2 and the first voltage signal V1 both act to pull down or pull down the level of the corresponding signal, and the effects of the two are opposite to the effect of the third voltage signal V3 on the level of the signal they act on.

[0036] Furthermore, the absolute value of the difference between the voltage value of the second voltage signal V2 and the voltage value of the third voltage signal V3 is greater than the difference between the voltage value of the first voltage signal V1 and the voltage value of the third voltage signal V3. That is, compared with the first voltage signal V1, the voltage value of the second voltage signal V2 is further away from the voltage value of the third voltage signal V3, so that the second voltage signal V2 pulls down or pulls up the level of the corresponding signal (that is, the invalid level corresponding to the first gate signal Gate1 of this stage) to a greater extent than the first voltage signal V1, so that the invalid level corresponding to the first gate signal Gate1 of this stage can be closer to its ideal potential, thereby reducing the risk of abnormal waveform of the first gate signal Gate1.

[0037] In some embodiments, as Figure 2 As shown, the first voltage signal V1 is used to pull down the potential of the first node P to a corresponding invalid level, the second voltage signal V2 is used to pull down the level of the first gate signal Gate1 to a corresponding invalid level, and the third voltage signal V3 is used to pull up the potential of the first node P to a corresponding valid level; wherein, the output module 302 is used to output the second voltage signal V2 as the first gate signal Gate1 of this stage when the signal of the first node P is a corresponding valid level, so that the invalid level corresponding to the first gate signal Gate1 of this stage is equal to the voltage value of the second voltage signal V2.

[0038] Specifically, this embodiment takes the example in which the voltage value of the second voltage signal V2 (for example, the second low voltage signal VGL') and the voltage value of the first voltage signal V1 (for example, the first low voltage signal VGL) are both less than the voltage value of the third voltage signal V3 (for example, the high voltage signal VGH), that is, the second voltage signal V2 and the first voltage signal V1 are used to pull down the level of the first gate signal Gate1 and the potential of the first node P, respectively.

[0039] Correspondingly, when the signal at the first node P is the corresponding valid level (the corresponding high level or low level), the output module 302 can output the second voltage signal V2 as the first gate signal Gate1 of this stage, that is, the voltage value of the second voltage signal V2 is the voltage value of the invalid level (that is, the corresponding low potential) corresponding to the first gate signal Gate1 of this stage.

[0040] As discussed above, the voltage value of the second voltage signal V2 and the voltage value of the first voltage signal V1 are both less than the voltage value of the third voltage signal V3; and the absolute value of the difference between the voltage value of the second voltage signal V2 and the voltage value of the third voltage signal V3 is greater than or equal to 17 volts and less than or equal to 20 volts. That is, for the voltage value of the second voltage signal V2 which has a larger difference from the voltage value of the third voltage signal V3, it is 17 volts to 20 volts less than the voltage value of the third voltage signal V3.

[0041] For example, the voltage value of the third voltage signal V3 (e.g., the high voltage signal VGH) can be 6 volts to 15 volts, and here 9.2 volts is taken as an example, the voltage value of the first voltage signal V1 (e.g., the first low voltage signal VGL) can be -7.3 volts, and the voltage value of the second voltage signal V2 (e.g., the second low voltage signal VGL’) is 1.2 volts to 3.5 volts less than the voltage value of the first voltage signal V1, that is, the voltage value of the second voltage signal V2 can be -10.8 volts to -8.5 volts, thereby realizing that the voltage value of the second voltage signal V2 can be 17.7 volts to 20 volts less than the voltage value of the third voltage signal V3.

[0042] In some embodiments, as shown in Figure 2 The control module 301 is also electrically connected to the second node Q of the current stage, for controlling the signal of the second node Q of the current stage according to the start signal S and the first voltage signal V1 of the current stage; and the output module 302 includes: a first output unit 202 electrically connected to the second node Q and a first signal line, for controlling the first gate signal Gate1 of the current stage to be at least a corresponding active level according to a first signal S1 (e.g., a first clock signal CK) transmitted by the first signal line when the signal of the second node Q is at a corresponding active level; and a second output unit 204 electrically connected to the first node P and the second voltage line (connected to the second voltage bus L2), for controlling the first gate signal Gate1 of the current stage to be a corresponding inactive level according to the second voltage signal V2 when the signal of the first node P is at a corresponding active level.

[0043] That is, the active level of the first gate signal Gate1 of the current stage is generated and output according to the first signal S1 when the first output unit 202 is turned on, and the inactive level of the first gate signal Gate1 of the current stage is generated and output according to the second voltage signal V2 when the second output unit 204 is turned on.

[0044] In some embodiments, as shown in Figure 2 and Figure 3As shown, the first signal S1 (for example, a first clock signal CK) is a periodic signal, the level of the first signal S1 alternates between a first level a1 with a larger amplitude and a second level a2 with a smaller amplitude, the voltage value of the second level a2 and the voltage value of the second voltage signal V2 (for example, a second low voltage signal VGL') are both smaller than the voltage value of the first level a1; wherein the voltage value of the effective level of the first gate signal Gate1 is the same as the voltage value of the first level a1.

[0045] As can be known from the above description, the voltage value of the second voltage signal V2 is the voltage value of the invalid level (i.e., the corresponding low potential) corresponding to the first gate signal Gate1 of the current stage, and the voltage value of the second level a2 and the voltage value of the second voltage signal V2 (for example, a second low voltage signal VGL') are both smaller than the voltage value of the first level a1, so it can be considered that the voltage values of the second level a2 and the second voltage signal V2 are relatively close (both are smaller), and it can be considered that the level of the first signal S1 as the second level a2 can also be the invalid level (i.e., the corresponding low potential) corresponding to the first gate signal Gate1 of the current stage, and the level of the first signal S1 as the first level a1 can be the effective level (i.e., the corresponding high potential) corresponding to the first gate signal Gate1 of the current stage.

[0046] In some embodiments, in combination with Figure 2 and Figure 4 As shown, the control module 301 includes: a pull-up control module 201, an input end of the pull-up control module 201 is electrically connected to the start line of the current stage, a control end of the pull-up control module 201 is electrically connected to a second signal line for transmitting a second signal S2 (for example, a second clock signal XCK), and an output end of the pull-up control module 201 is electrically connected to a third node K; a pull-down control module 203, an input end of the pull-down control module 203 is electrically connected to the first voltage line (connected to the first voltage bus L1) and the third voltage line (connected to the third voltage bus L3), a control end of the pull-down control module 203 is electrically connected to the third node K, and an output end of the pull-down control module 203 is electrically connected to the first node P; a voltage stabilizing module 205, an input end of the voltage stabilizing module 205 is electrically connected to the first voltage line (connected to the first voltage bus L1) and the third voltage line (connected to the third voltage bus L3), a control end of the voltage stabilizing module 205 is electrically connected to the first node P, and an output end of the voltage stabilizing module 205 is electrically connected to the second node Q.

[0047] The level of the second signal S2 (for example, a second clock signal XCK) can also alternately be a third level a3 with a larger amplitude and a fourth level a4 with a smaller amplitude. The amplitude of the third level a3 can be equal to the amplitude of the first level a1, and the amplitude of the fourth level a4 can be equal to the amplitude of the second level a2. Further, the period of the second signal S2 can be equal to the period of the first signal S1.

[0048] Specifically, the pull-up control module 201 can be controlled by the second signal S2 to transmit the start signal S of the current stage to the third node K of the current stage in a corresponding period. The pull-down control module 203 can be controlled by the signal of the third node K of the current stage to transmit the first voltage signal V1 and the second voltage signal V2 to the first node P in a time-sharing manner. Further, the voltage stabilizing module 205 can be controlled by the signal of the first node P to transmit the first voltage signal V1 or the third voltage signal V3 to the second node Q.

[0049] As shown in Figure 2 For ease of description, the pull-up control module 201 includes a first transistor T1, the pull-down control module 203 includes a second transistor T2 and a third transistor T3, the voltage stabilizing module 205 includes a fourth transistor T4, a fifth transistor T5 and an eighth transistor T8, the first output unit 202 includes a sixth transistor T6 and a first capacitor C1, and the second output unit 204 includes a seventh transistor T7. As an example, the connection relationship of the above-mentioned multiple transistors and the first capacitor C1 can refer to, but is not limited to, the circuit diagram as shown in Figure 2 As shown in

[0050] As shown in Figure 3 As shown in Figure 2 As shown in

[0051] In the first stage t1, the frame start signal STV and the second clock signal XCK are both corresponding active levels, so that the active level of the first clock signal CK is transmitted to the third node K. At this time, the fifth transistor T5 is turned on, so that the active level of the first clock signal CK is also transmitted to the second node Q. However, at this time, the first clock signal CK is a corresponding inactive potential, so that the first gate signal Gate1(1) of the first stage is a corresponding inactive potential. At the same time, the signal SP(1) of the first node P becomes a corresponding inactive potential through the inverting action of the pull-down control module 203, so that the seventh transistor T7 is cut off.

[0052] In the second stage t2, the second clock signal XCK becomes the corresponding invalid potential so that the first transistor T1 is turned off, but the signal SQ(1) of the second node Q maintains the previous valid level so that the sixth transistor T6 is maintained in the on state, the first clock signal CK becomes the corresponding valid level and outputs the valid level as the first gate signal Gate1(1), and the level of the signal SQ(1) of the second node Q is further raised by the action of the first capacitor C1 so that the fifth transistor T5 is turned off, while the signal SK(1) of the third node K is maintained at the previous valid level, and the signal SP(1) of the first node P becomes the corresponding invalid potential;

[0053] In the third stage t3, compared with the second stage t2, the first clock signal CK becomes the corresponding invalid potential, so the first gate signal Gate1(1) becomes the corresponding invalid potential, and the level of the signal SQ(1) of the second node Q is also correspondingly reduced by the action of the first capacitor C1;

[0054] In the fourth stage t4, the difference from the first stage t1 is that the frame start signal STV is the corresponding invalid potential, so the signal SK(1) of the third node K and the signal SQ(1) of the second node Q are both the corresponding invalid potential, and the signal SP(1) of the first node P is the corresponding valid level by the inverting action of the pull-down control module 203, so the seventh transistor T7 is turned on to output the first low voltage signal VGL as the first gate signal Gate1(1);

[0055] In the fifth stage t5, the signal SQ(1) of the second node Q and the signal SK(1) of the third node K are both maintained at the previous invalid potential, the signal SP(1) of the first node P is maintained at the corresponding valid level, and the first gate signal Gate1(1) is still the same as the first low voltage signal VGL.

[0056] Similarly, for the first gate drive sub-circuit Nscan_T2 of the second stage, the corresponding five working stages described above can also be included.

[0057] It should be noted that, in combination with Figure 2 and Figure 3As shown, since the signal transmission capability of the fourth transistor T4 is greater than that of the first transistor T1 and the eighth transistor T8, after the high-voltage signal VGH is written to the third node K due to the conduction of the fourth transistor T4 during the first stage t1 to the third stage t3, in the comparative example, since no interference is added (it can be considered that the first low-voltage signal VGL is the same as the second low-voltage signal VGL'), the invalid potential corresponding to the frame start signal STV in the fourth stage t4 cannot be well transmitted to the third node K to pull down its potential, thereby causing the signal SP(1) of the first node P to be unable to be well converted into the corresponding valid level. Therefore, the seventh transistor T7 cannot be well conducted and cannot well output the first low-voltage signal VGL to pull down the potential of the first gate signal Gate1(1) (refer to the dotted line part). In particular, in the stage where the first node P is suspended, such as the fifth stage t5, the potential of the first gate signal Gate1(1) will be pulled up due to coupling due to the action of the first capacitor C1.

[0058] Among them, for the first gate driving sub-circuit Nscan_T2 of the first stage, since the invalid potential of the frame start signal STV can be set lower to compensate for the insufficient signal transmission capability of the first transistor T1, the potential of the first gate signal Gate1 (1) is abnormally pulled up to a lesser extent since the fourth stage t4; and for the first gate driving sub-circuit Nscan_T2 (for example, the second stage) controlled by the first gate signal Gate1 of a previous stage, since the potential of the first gate signal Gate1 of a previous stage has been abnormally pulled up since the fourth stage t4, the superposition effect will cause the first transistor T1 of the current stage to be abnormally pulled up from the fourth stage t4. Since the segment t4 is still not properly turned on, the level of the signal SK(2) at the third node K cannot be properly pulled down (refer to the dotted line portion) from the corresponding fourth stage t4, and the level of the signal SP(2) at the first node P cannot be properly pulled up (refer to the dotted line portion), and the level of the signal SQ(2) at the second node Q cannot be properly pulled down (refer to the dotted line portion), and the seventh transistor T7 cannot be properly turned on. Instead, the sixth transistor T6 is turned on, causing the first gate signal Gate1(1) to have multiple pulses corresponding to the waveform of the first clock signal CK, thereby causing the invalid potential of the first gate signal Gate1(1) to be abnormal.

[0059] In the embodiment of the present invention, combined with Figure 2 and Figure 3As shown, taking the seventh transistor T7 as an example, since the voltage value of the first low voltage signal VGL is set to be less than the voltage value of the second low voltage signal VGL’p’, the voltage value of the first low voltage signal VGL can compensate for the phenomenon of insufficient conduction of the seventh transistor T7 due to the level of the signal SP(2) of the first node P being unable to be well pulled up from the fourth stage t4, so that the conduction of the seventh transistor T7 and the eighth transistor T8 can both be increased, thereby reducing the risk of conduction of the sixth transistor T6 and improving the reliability of the invalid potential of the first gate signal Gate1(1).

[0060] In some embodiments, in combination with Figure 1 and Figure 4 As shown, the gate drive circuit 10 further includes a plurality of cascaded second gate drive sub-circuits Nscan_T3, each of which is electrically connected to a fourth voltage line (connected to a fourth voltage bus L4) for transmitting a fourth voltage signal V4 (for example, a second low voltage signal VGL’), which is used to pull down the level of the second gate signal Gate2 of the current stage; wherein the second voltage line (connected to the second voltage bus L2) and the fourth voltage line (connected to the fourth voltage bus L4) are in electrical communication.

[0061] In combination with the above discussion, Figure 4 Compared with Figure 5 As shown in the comparative example, instead of being controlled by the first voltage signal V1 transmitted by the first voltage line (connected to the first voltage bus L1), the output module 302 is controlled by the second voltage signal V2 transmitted by the second voltage line (connected to the second voltage bus L2), thereby reducing the risk of abnormal waveform of the first gate signal Gate1.

[0062] On this basis, the embodiment takes into account that the fourth voltage signal V4 controlled by the second gate drive sub-circuit Nscan_T3 in the gate drive circuit 10 is also used to pull down the level of the second gate signal Gate2 of the current stage, and in combination with the foregoing discussion, the second voltage signal V2 is also used to pull down the level of the first gate signal Gate1 to the corresponding invalid level, so both of them can be set to the second low voltage signal VGL’, thus as Figure 4 As shown, the second voltage line (connected to the second voltage bus L2) and the fourth voltage line (connected to the fourth voltage bus L4) can be in electrical communication through the connection line L0, so as to form a current path therebetween, thereby reducing the types of signal lines.

[0063] In some embodiments, as Figure 1As shown, the gate driving circuit 10 further comprises a plurality of cascaded third gate driving sub-circuits EM2_T, each of which is electrically connected to a fifth voltage line for transmitting a fifth voltage signal, and is used for pulling down the level of the third gate signal Gate3 of the corresponding stage; wherein the fifth voltage line is electrically connected to the first voltage line (connected to the first voltage bus L1) or the second voltage line (connected to the second voltage bus L2).

[0064] Similarly, the embodiment considers that the fifth voltage signal controlled by the third gate driving sub-circuit EM2_T in the gate driving circuit 10 is also used for pulling down the level of the third gate signal Gate3 of the corresponding stage, and since the first voltage signal V1 and the second voltage signal V2 in the first gate driving sub-circuit Nscan_T2 are both used for pulling down the level of the corresponding signal, in order to reduce the types of signal lines, the fifth voltage signal is set to be the same as at least one of the first voltage signal V1 and the second voltage signal V2 in the embodiment, so as to realize the sharing of the signal lines and reduce the types of signal lines.

[0065] In combination Figure 1 and Figure 4 As shown, the display panel 100 of the embodiment comprises a display area A (which internally comprises a plurality of pixels Pi), a first non-display area B1 and a second non-display area B2 located on the two adjacent sides of the display area A, and a third non-display area B3 interposed between the first non-display area B1 and the second non-display area B2; the gate driving circuit 10 as described in any of the above is arranged in the first non-display area B1 and the third non-display area B3, and further comprises a plurality of cascaded second gate driving sub-circuits Nscan_T3, each of which is electrically connected to a fourth voltage line (connected to a fourth voltage bus L4) for transmitting a fourth voltage signal V4, and is used for at least pulling down or pulling up the level of the second gate signal Gate2 of the corresponding stage according to the fourth voltage signal V4; the first voltage line (connected to the first voltage bus L1), the second voltage line (connected to the second voltage bus L2) and the fourth voltage line (connected to the fourth voltage bus L4) are further arranged in the first non-display area B1; the second voltage bus L2 electrically connected to the second voltage line, the fourth voltage bus L4 electrically connected to the fourth voltage line, and a connection line L0 electrically connected between the second voltage bus L2 and the fourth voltage bus L4 to electrically connect the second voltage bus L2 and the fourth voltage bus L4 are arranged in the second non-display area B2.

[0066] Specifically, as Figure 4As shown, taking the third non-display area B3 as an example, part of the plurality of transistors in the control module 301 of the first gate driving sub-circuit Nscan_T2 can be connected to an upper first voltage bus L1 through a first voltage line, and another part can be connected to a lower first voltage bus L1 through another first voltage line. The two first voltage buses L1 can be electrically connected through a first connection line L01. The plurality of transistors in the control module 301 can also be electrically connected to a third voltage bus L3 through a second connection line L02 to receive a third voltage signal V3 (for example, a high voltage signal VGH). The transistors in the output module 302 of the first gate driving sub-circuit Nscan_T2 can be connected to an upper second voltage bus L2 through a second voltage line. Part of the plurality of transistors in the second gate driving sub-circuit Nscan_T3 can be connected to an upper fourth voltage bus L4 through a fourth voltage line, and another part can be connected to a lower fourth voltage bus L4 through a fourth voltage line. The second voltage bus L2 and the upper fourth voltage bus L4 are electrically connected through a connection line L0. The upper fourth voltage bus L4 and the lower fourth voltage bus L4 are electrically connected through an initial connection line L0'.

[0067] Further, in combination with Figure 1 and Figure 4 As shown, the display panel 100 further includes a plurality of first gate lines GL1 located in the display area A and the third non-display area B3. Each first gate line GL1 is used to transmit a corresponding first gate signal Gate1. Each first gate line GL1 also extends to a corresponding first non-display area B1 or a corresponding second non-display area B2 to be electrically connected to a corresponding first gate driving sub-circuit Nscan_T2. The connection line L0 and the plurality of first gate lines GL1 are arranged in the same layer. The first gate line GL1 located in the second non-display area B2 includes a bending portion WL for accommodating the connection line L0 and having a spacing with the connection line L0.

[0068] On the one hand, in comparison with Figure 4 and Figure 5 As shown, Figure 5This is a circuit layout diagram of the third non-display area B3 provided in the comparative example. In the comparative example, since the transistors in both the output module 302 and the control module 301 of the first gate drive sub-circuit Nscan_T2 are loaded with the first voltage signal V1 (for example, the first low voltage signal VGL), the transistors in the output module 302 can be connected to the uppermost first voltage bus L1 through the first voltage line, and some of the multiple transistors in the control module 301 can be connected to the second upper first voltage bus L1 through the first voltage line, and the uppermost first voltage bus L1 and the second upper first voltage bus L1 can be electrically connected through the third connection line L03.

[0069] Since in the embodiment Figure 4 In the embodiment, the transistor in the output module 302 of the first gate driving sub-circuit Nscan_T2 is connected to the second voltage bus L2 instead of the first voltage bus L1, so there is no need to set the above-mentioned third connection line L03 (or no current path is formed in the third connection line L03) to electrically disconnect the second voltage bus L2 and the first voltage bus L1.

[0070] On the other hand, in the embodiment Figure 5 In the embodiment, since the third connection line L03, the first connection line L01 and the second connection line L02 are all disposed in different layers from the first gate line GL1, the first gate line GL1 may intersect with any one of the three.

[0071] However, in the embodiment Figure 4 In the embodiment, since the connection line L0 and the plurality of first gate lines GL1 are arranged on the same layer, and the connection line L0 generally extends in the same direction as the third connection line L03, the first connection line L01, and the second connection line L02, in order to avoid the first gate line GL1 from intersecting with the connection line L0 and causing a short circuit, the first gate line GL1 is, for example, protruded downward to form a bent portion WL that can bypass the connection line L0 to avoid contact with the connection line L0; and the above-mentioned initial connection line L0' is generally arranged on a different layer from the connection line L0, that is, on a different layer from the first gate line GL1, so even if the first gate line GL1 intersects with the initial connection line L0', a short circuit between the two will not occur.

[0072] The gate drive circuit and display panel provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a cascaded multi-stage first gate driving sub-circuit, wherein the first gate driving sub-circuit comprises: a control module, electrically connected to the start line, the first voltage line, and the first node of the current stage, configured to control the signal of the first node of the current stage according to the start signal transmitted by the start line of the current stage and the first voltage signal transmitted by the first voltage line, wherein the voltage value of the valid level corresponding to the signal of the first node of the current stage is related to the invalid level of the start signal of the current stage; an output module, electrically connected to the first node and the second voltage line, for controlling the first gate signal of the current stage to a corresponding invalid level according to a second voltage signal transmitted by the second voltage line when the signal of the first node is at a corresponding valid level; The i-th stage start signal received by the i-th stage first gate driving sub-circuit is the ik-th stage first gate signal output by the ik-th stage first gate driving sub-circuit, where i is a positive integer greater than 1, and k is a positive integer less than i. The first voltage signal is used to pull down the potential of the first node, and the second voltage signal is used to pull down the level of the first gate signal to a corresponding invalid level; or the first voltage signal is used to pull up the potential of the first node, and the second voltage signal is used to pull up the level of the first gate signal to a corresponding invalid level; The amplitude of the first voltage signal is different from the amplitude of the second voltage signal.

2. The gate drive circuit according to claim 1, wherein: The control module is also electrically connected to the third voltage line, and is used to control the signal of the first node of the current stage according to the start signal of the current stage, the first voltage signal and the third voltage signal transmitted by the third voltage line; wherein one of the first voltage signal and the third voltage signal is used to pull down the potential of the first node, and the other is used to pull up the potential of the first node, and the voltage value of the second voltage signal and the voltage value of the first voltage signal are both smaller than or greater than the voltage value of the third voltage signal; The absolute value of the difference between the voltage value of the second voltage signal and the voltage value of the third voltage signal is greater than the absolute value of the difference between the voltage value of the first voltage signal and the voltage value of the third voltage signal.

3. The gate drive circuit according to claim 2, wherein: The first voltage signal is used to pull down the potential of the first node to a corresponding invalid level, the second voltage signal is used to pull down the level of the first gate signal to a corresponding invalid level, and the third voltage signal is used to pull up the potential of the first node to a corresponding valid level; The output module is configured to output the second voltage signal as the first gate signal of this stage when the signal of the first node is at the corresponding valid level, so that the invalid level corresponding to the first gate signal of this stage is equal to the amplitude of the second voltage signal.

4. The gate driving circuit according to claim 3, wherein: The second gate driving sub-circuit of each stage is electrically connected to a fourth voltage line for transmitting a fourth voltage signal, wherein the fourth voltage signal is used to pull down the level of the second gate signal Gate2 of the current stage; Wherein, the second voltage line is electrically connected to the fourth voltage line.

5. The gate driving circuit according to claim 4, wherein: The device further comprises a plurality of cascaded third gate driving sub-circuits, wherein each stage of the third gate driving sub-circuit is electrically connected to a fifth voltage line for transmitting a fifth voltage signal, wherein the fifth voltage signal is used to pull down the level of the third gate signal Gate3 of the current stage; The fifth voltage line is electrically connected to the first voltage line, or the fifth voltage line is electrically connected to the second voltage line.

6. The gate driving circuit according to claim 3, wherein: The voltage value of the second voltage signal and the voltage value of the first voltage signal are both smaller than the voltage value of the third voltage signal; The absolute value of the difference between the voltage value of the second voltage signal and the voltage value of the third voltage signal is greater than or equal to 17 volts and less than or equal to 20 volts.

7. The gate driving circuit according to claim 3, wherein: The control module is also electrically connected to the second node of the current stage, and is used to control the signal of the second node of the current stage according to the start signal of the current stage and the first voltage signal; The output module includes: a first output unit, electrically connected to the second node and the first signal line, for transmitting the first signal transmitted by the first signal line to control the first gate signal of the current stage to be at least the corresponding valid level when the signal of the second node is at the corresponding valid level; The second output unit is electrically connected to the first node and the second voltage line, and is used to control the first gate signal of this stage to a corresponding invalid level according to the second voltage signal when the signal of the first node is a corresponding valid level.

8. The gate driving circuit according to claim 7, wherein: The first signal is a periodic signal, the level of the first signal alternates between a first level and a second level, and the voltage value of the second level and the voltage value of the second voltage signal are both smaller than the voltage value of the first level; The voltage value of the effective level of the first gate signal is the same as the voltage value of the first level.

9. The gate driving circuit according to claim 7, wherein: The control module includes: a pull-up control module, wherein an input end of the pull-up control module is electrically connected to the start line of the current stage, a control end of the pull-up control module is electrically connected to a second signal line for transmitting a second signal, an output end of the pull-up control module is electrically connected to a third node, and the pull-up control module is used to control the start signal of the current stage to be transmitted to the third node according to the second signal; a pull-down control module, wherein an input end of the pull-down control module is electrically connected to the first voltage line and the third voltage line, a control end of the pull-down control module is electrically connected to the third node, an output end of the pull-down control module is electrically connected to the first node, and the pull-down control module is configured to control the time-sharing transmission of the first voltage signal and the third voltage signal to the first node according to a signal of the third node; A voltage stabilization module, wherein the input end of the voltage stabilization module is electrically connected to the first voltage line and the third voltage line, the control end of the voltage stabilization module is electrically connected to the first node, and the output end of the voltage stabilization module is electrically connected to the second node, and the voltage stabilization module is used to control the time-sharing transmission of the first voltage signal and the third voltage signal to the second node according to the signal of the first node.

10. A display panel, characterized in that: It includes a display area and a first non-display area and a second non-display area located on both sides of the display area, wherein a third non-display area is sandwiched between the first non-display area and the second non-display area; The gate drive circuit according to any one of claims 1 to 9 is provided in the first non-display area and the third non-display area, the gate drive circuit further comprising a cascade of multiple stages of second gate drive sub-circuits, each stage of the second gate drive sub-circuit being electrically connected to a fourth voltage line for transmitting a fourth voltage signal, the second gate drive sub-circuit being at least configured to pull down or pull up a level of a second gate signal of the stage according to the fourth voltage signal; The first non-display area is further provided with the first voltage line, the second voltage line and the fourth voltage line; The second non-display area is provided with a second voltage bus electrically connected to the second voltage line, a fourth voltage bus electrically connected to the fourth voltage line, and a connecting line electrically connected between the second voltage bus and the fourth voltage bus to ensure electrical conduction between the second voltage bus and the fourth voltage bus.

11. The display panel according to claim 10, wherein: Also includes: a plurality of first gate lines, located at least in the display area and the third non-display area, each first gate line being configured to transmit a corresponding first gate signal, and each first gate line further extending to a corresponding first non-display area or a corresponding second non-display area to be electrically connected to a corresponding first gate driving sub-circuit; The connecting line and the plurality of first gate lines are arranged in the same layer, and the first gate line located in the second non-display area includes a bent portion, which is used to accommodate the connecting line and has a gap between the bent portion and the connecting line.

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