Memory device with conductive plate short-circuit repair

Abstract

The invention relates to a memory device with conductive plate shorting repair. Some embodiments include devices and methods of operating the devices. One of the devices includes: conductive plates adjacent to each other; a memory cell associated with the conductive plate; drivers coupled to the conductive plates such that one of the drivers is associated with one of the conductive plates; and a short circuit coupled between a first one of the conductive plates and a second one of the conductive plates.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to memory devices with conductive plate short repair. BACKGROUND

[0002] Many electronic devices (e.g., cellular phones and computers) have memory devices for storing information. Some memory devices have conductive plates to provide voltage to portions of memory cells. During fabrication of a memory device, a short (e.g., a circuit defect) can occur in a portion of the memory device that includes the conductive plates. This short can cause the memory device to be discarded, thereby reducing yield and increasing costs associated with fabrication of such memory devices. SUMMARY

[0003] Aspects of the present disclosure relate to an apparatus comprising: conductive plates adjacent to each other; memory cells associated with the conductive plates; drivers coupled to the conductive plates such that one of the drivers is associated with one of the conductive plates; and a short coupled between a first one of the conductive plates and a second one of the conductive plates.

[0004] Another aspect of the present disclosure relates to an apparatus comprising: a group of conductive plates, each of the group of conductive plates including a number of conductive plates, the number of conductive plates being greater than two; a data line associated with each of the conductive plates of each of the group of conductive plates; a memory cell associated with the data line; a short coupled between a first conductive plate and a second conductive plate of one of the group of conductive plates; a first multiplexer, each of the first multiplexers being associated with a respective one of the group of conductive plates and including an input coupled to the data line associated with each of the conductive plates of the respective one of the group of conductive plates; a second multiplexer including an input coupled to outputs of the first multiplexers; and a sense circuit coupled to an output of the second multiplexer.

[0005] Yet another aspect of the present disclosure relates to a method comprising: accessing a first memory cell of a memory device during a memory operation of the memory device, the first memory cell being associated with a first one of conductive plates of the memory device, the first one of the conductive plates being shorted to a second one of the conductive plates, the second one of the conductive plates being associated with a second memory cell of the memory device, and the first memory cell and the second memory cell including ferroelectric memory cells; coupling a first data line associated with the first memory cell to a sense circuit during the memory operation; and decoupling a second data line associated with the second memory cell from the sense circuit during the memory operation. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 An apparatus in the form of a memory device is shown in accordance with some embodiments described herein.

[0007] Figure 2A A memory device including a conductive plate and associated memory cells is shown in accordance with some embodiments described herein.

[0008] Figure 2B A portion of a memory device including memory cells, drivers (cell plate drivers), and transistors is shown in accordance with some embodiments described herein. Figure 2A

[0009] Figure 3 A memory device including a group of conductive plates (a group of conductive plates) is shown in accordance with some embodiments described herein.

[0010] Figure 4 A memory device including a group of conductive plates and a multiplexer is shown in accordance with some embodiments described herein.

[0011] Figure 5 is a flow diagram of an example method for operating a memory device in accordance with some embodiments described herein.

[0012] Figure 6 An apparatus in the form of a system is shown in accordance with some embodiments described herein. DETAILED DESCRIPTION

[0013] The technology described herein relates to memory devices having conductive plates and configurations to repair short circuits that can occur between the conductive plates. In examples, the technology described herein provides ways to use at least some of the portions of a memory device that are damaged due to such short circuits. The memory device also includes redundant (spare) memory portions to replace (e.g., repair) the damaged portions. The technology described herein can improve yield and reduce costs associated with fabrication of the described memory devices. Reference is made below to Figures 1 to 6 Further improvements and benefits of the described technology are discussed.

[0014] Figure 1 A block diagram of an apparatus in the form of a memory device 100 including volatile memory cells is shown in accordance with some embodiments described herein. The memory device 100 includes a memory array (or memory arrays) 101, which can contain memory cells 102. The memory cells 102 can be organized into memory banks 1190 through 119 i ​Each of the banks can include a number of memory cells 102. The memory device 100 can include a volatile memory device or a non-volatile memory device. Examples of the memory device 100 include a dynamic random access memory (DRAM) device, a ferroelectric random access memory (FeRAM) device, or other types of random access memory (RAM) devices.

[0015] In an example, if a supply power (e.g., a supply voltage Vcc) is disconnected from the memory device 100, information stored in the memory cells 102 of the memory device 100 can be lost (e.g., invalidated). In another example, the memory device 100 can retain values of information stored in the memory cells 102 even if the supply power is disconnected from the memory device 100.

[0016] In this description, the supply voltage Vcc is referred to as representing some voltage levels; however, they are not limited to a supply voltage (e.g., Vcc) of a memory device (e.g., the memory device 100). For example, if the memory device (e.g., the memory device 100) has an internal voltage generator (not shown in Figure 1 ) that generates an internal voltage based on the supply voltage Vcc, this internal voltage can be used instead of the supply voltage Vcc.

[0017] In a physical structure of the memory device 100, each of the memory cells 102 can include a transistor (e.g., an access transistor) and a storage element. The storage element can include a capacitor or other storage elements different from a capacitor. Each of the memory cells 102 can be configured to store information that can represent at most one bit (e.g., a single bit having a binary 0 (“0”) or a binary 1 (“1”)) or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

[0018] As shown in Figure 1 , the memory device 100 can include storage lines 104 (e.g., “word lines”) and data lines 105. The data lines 105 can include digit lines (also referred to as bit lines). The memory device 100 can use signals on the access lines 104 (e.g., word line signals) to access the memory cells 102 and use signals on the data lines 105 to provide information (e.g., data) to be stored in the memory cells 102 (e.g., to be written to or programmed in the memory cells 102) or read from (e.g., sensed) the memory cells 102.

[0019] The memory device 100 can include an address register 106 to receive signals (e.g., row address signals and column address signals) ADDR R to ADDRX The information ADDR is associated with an address of a memory cell 102 of the memory device 100. The memory device 100 can include row access circuitry 108 (e.g., an X decoder) and column access circuitry 109 (e.g., a Y decoder) operable to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 can determine which memory cells 102 are to be accessed during a memory operation. The memory device 100 can perform a write operation to store information in the memory cells 102 and perform a read operation to read (e.g., sense) information (e.g., previously stored information) in the memory cells 102.

[0020] The memory device 100 can receive supply voltages, including a supply voltage Vcc and Vss on lines 191 and 192, respectively. The supply voltage Vss can operate at a ground potential (e.g., have a value of approximately 0 volts). The supply voltage Vcc can include an external voltage supplied to the memory device 100 from an external power source, such as a battery or alternating current to direct current (AC-DC) converter circuitry.

[0021] As shown in Figure 1 The memory device 100 can include memory control circuitry 110, including components (e.g., software, firmware, hardware, or any combination of these components) that control memory operations (e.g., read and write operations) of the memory device 100 based on control signals on conductive lines (e.g., control lines) of a bus (e.g., a command bus) 107 of the memory device 100. Examples of signals on conductive lines of the bus 107 include a row access strobe signal RAS*, a column access strobe signal CAS*, a write enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock enable signal CKE. These signals can be part of signals provided to a DRAM device or a FeRAM (e.g., the memory device 100). Different combinations of these signals can form different commands provided to the memory device 100. Examples of commands (e.g., provided to the memory device 100 from a memory controller) on conductive lines of the bus 107 include a read command, a write command, and other commands associated with a memory device (e.g., a DRAM device or a FeRAM device).

[0022] As shown in Figure 1As shown in the middle, memory device 100 can include conductive lines (e.g., global data lines) of a bus (e.g., a data bus) 112 that can carry signals DQ0 through DQN. The conductive lines of bus 112 can be part of a data bus of memory device 100. In a read operation, the value (e.g., “0” or “1”) of the information (read from memory cells 102) provided to the conductive lines of bus 112 in the form of signals DQ0 through DQN can be based on the value of the signal on data line 105. In a write operation, the value (e.g., “0” or “1”) of the information provided to data line 105 (to be stored in memory cells 102) can be based on the values of signals DQ0 through DQN on the conductive lines of bus 112.

[0023] Memory device 100 can include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Column access circuitry 109 can selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Selection circuitry 115 can respond to signals on line 114 to select signals on data line 105. The signals on data line 105 can represent the value of information stored in memory cells 102 (e.g., during a write operation) or the value of information read (e.g., sensed) from memory cells 102 (e.g., during a read operation).

[0024] I / O circuitry 116 can operate to provide information read from memory cells 102 to the conductive lines of bus 112 (e.g., during a read operation) and to provide information (e.g., provided by an external device) from the conductive lines of bus 112 to data line 105 (e.g., during a write operation) to be stored in memory cells 102. The conductive lines of bus 112 can include nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 can reside. Other devices external to memory device 100 can communicate with memory device 100 through conductive buses 107, 112, and 118. Examples of other devices external to memory device 100 can include a hardware memory controller (e.g., memory controller 630 Figure 6 ) or a hardware processor (e.g., processor 615 of Figure 6 ).

[0025] Memory device 100 can include other components, Figure 1 not shown in the middle to avoid obscuring the example embodiments described herein. At least a portion of memory device 100 and the operation of memory device 100 can include structures and operations similar to or the same as any of the memory devices described below with reference to Figures 2A to 6 .

[0026] Figure 2AA portion of a memory device 200 including conductive plates PLO to PL i and associated memory cells 202 in accordance with some embodiments described herein is shown. The memory device 200 can correspond to Figure 1 the memory device 100. For example, the memory device 200 can include a memory array (or a number of memory arrays) 201, which can form a portion of Figure 1 the memory array 101 (or can correspond to Figure 1 the memory array 101) of the memory device 100.

[0027] As shown in Figure 2A , the memory device 200 can include conductive plates PLO to PL i adjacent to each other, memory cells 202 organized (e.g., formed) in memory cell groups 2020 to 202 i with respective conductive plates and respective memory cell groups, and data lines (e.g., digit lines or bit lines) dOx and access lines (e.g., word lines) WLO to WLm associated with the respective conductive plates and the respective memory cell groups. Each of the data lines DL0 to DL X and each of the access lines WLO to WLm can include (may be formed of) a conductive material (e.g., a metal or other conductive material). Each of the conductive plates PLO to PL i may include a conductive material (e.g., a metal or other conductive material). As shown in Figure 2A , each conductive plate (of the conductive plates PLO to PL i ) is associated with the memory cells 202 of a memory cell group (of the memory cell groups 2020 to 202 i ). For simplicity, Figure 2A details of the memory cell groups 202 i-1 and 202 i are not shown in

[0028] In this description, a conductive plate (e.g., the conductive plate PLO) can also be referred to as a cell plate (e.g., the cell plate PLO) or a memory cell plate (e.g., the memory cell plate PLO). The conductive plates PLO to PL i are separate from each other. A conductive plate associated with a particular memory cell group (one of the memory cell groups 2020 to 202 i may be shared by the memory cells 202 of that particular memory cell group (e.g., can be a common conductive plate for the memory cells).

[0029] For simplicity, Figure 2A each of the conductive plates PL i-1 and PL i is shown as a box. However, the conductive plates PLi-1 and PL i Each of the conductive plates PL0 and PL1 can be associated with circuit elements (e.g., memory cells, data lines, and access lines) like other conductive plates of the memory device 200 (e.g., conductive plates PL0 and PL1).

[0030] Figure 2A The example showing access lines WL0 to WLm associated with a group of memory cells (group of memory cells 202) can be separate from access lines WL0 to WLm associated with another group of memory cells (another group of memory cells 202). Alternatively, the access lines WL0 to WLm can be shared by two or more groups of memory cells.

[0031] The memory device 200 can include sensing circuitry 215 and transistors (e.g., column select transistors) Tsel0 to Tsel X between the sensing circuitry 215 and data lines DL0 to DL X associated with respective groups of memory cells (e.g., columns of memory cells 202). Each of the data lines DL0 to DL X may include a conductive material (e.g., a metal or other conductive material). The transistors Tsel0 to Tsel i may be controlled (e.g., turned on or off) by corresponding signals (e.g., select signals) SEL0 to SEL X Each of the groups of memory cells 2020 to 202 i and associated conductive plates PL0 to PL i may share the sensing circuitry 215.

[0032] The transistors Tsel0 to Tsel X associated with respective groups of memory cells can be referred to as groups of transistors. Figure 2A The example shows four groups of transistors (each group of transistors including transistors Tsel0 to Tsel X ) associated with respective groups of memory cells. The data lines DL0 to DL X associated with respective groups of memory cells can be referred to as groups of data lines. Figure 2A The example shows four groups of data lines (each group of data lines including data lines DL0 to DL X ).

[0033] In a memory operation (e.g., a read operation), the transistors Tsel0 to Tsel X may be turned on one group of transistors at a time. This allows the data lines DL0 to DL X to be coupled to the sensing circuitry 215 one group of data lines at a time. When a group of data lines (e.g., data lines DL0 to DLX ) is coupled to the sensing circuit 215, other data line groups (eg, memory cell groups 2021 to 202 i Associated data lines DL0 to DL X ) is decoupled from the sensing circuit 215. The memory control circuit system of the memory device 200 (e.g., similar to Figure 1 The memory control circuitry 110 of the memory device may be configured to selectively couple groups of data lines to the sensing circuitry 215 and decouple groups of data lines from the sensing circuitry 215.

[0034] like Figure 2A As shown in FIG. 1 , memory device 200 may include a plurality of conductive plates coupled to respective conductive plates PL0 through PL1 in a one-to-one configuration (one-to-one relationship). i Driver (driver circuit) 2250 to 225 i In this one-to-one configuration, a driver (e.g., driver 2250) coupled to a corresponding conductive plate (e.g., conductive plate PL0) is not shared with (is not coupled to) another conductive plate (or other conductive plates) of the memory device 200. For example, Figure 2A As shown in FIG. 2 , driver 2250 is coupled to conductive plate PL0 and is not coupled to conductive plates PL1 through PL2. i (Not with conductive plates PL1 to PL i Therefore, the driver 2250 can be used to apply a voltage to the conductive plate PL0 and is not used to apply a voltage to the other conductive plates PL1 to PL i As described in more detail below, drivers 2250 to 225 i With conductive plates PL0 to PL i The one-to-one configuration allows the memory device 200 to operate correctly in a memory operation (eg, a read operation) although the conductive plates PL0 to PL i A short circuit may occur.

[0035] exist Figure 2A In the example, the signal (eg, control signal) CTL DR0 to CTL DRi The corresponding signals in the activating (eg, turning on) or deactivating (eg, turning off) the drivers 2250 to 225 i Drivers 2250 to 2254 may be individually activated (eg, turned on) or deactivated (eg, turned off) depending on whether a voltage should be applied to the respective conductive plates. i The memory control circuitry of the memory device 200 (e.g., similar to Figure 1 The memory control circuitry 110 of the memory device may be configured to selectively activate or deactivate the driver 225.

[0036] When the corresponding driver is turned on, the conductive plates PL0 to PL i For example, when driver 2250 is turned on, a voltage (e.g., a positive voltage) may be applied to conductive plate PL0. In another example, when driver 2251 is turned on, a voltage (e.g., a positive voltage) may be applied to conductive plate PL1.

[0037] When the corresponding driver is turned off, (conductive plate PL0 to PL i The conductive plate PL1 in the memory device 200 can be placed in a floating state (e.g., floatable) during memory operation. In the floating state, the conductive plate is neither coupled to a voltage source (e.g., voltage Vcc) through a corresponding driver (e.g., through a transistor (not shown) included in the corresponding driver) nor coupled to a ground connection (e.g., voltage Vss) through the corresponding driver. For example, during memory operation of the memory device 200, the conductive plate PL1 can be placed in a floating state (floatable) by deactivating (e.g., not turning on) the driver 2251. In this example, when the driver 2250 is turned off, the conductive plate PL1 is not coupled to a voltage source (e.g., a positive voltage) or a ground connection (e.g., voltage Vss).

[0038] like Figure 2A As shown in FIG. 1 , each memory cell 202 may include a transistor (eg, a row access transistor) T and a memory element 202E (eg, a row access transistor). Figure 2B For simplicity, Figure 2A The labels (e.g., 202E) of the memory elements of each memory cell 202 are omitted. The conductive plates associated with a particular memory cell group can form part of the memory elements of the memory cells of that particular memory cell group. For example, conductive plate PL0 can form part of the memory elements of memory cells 202 of memory cell group 2020. In another example, conductive plate PL1 can form part of the memory elements of memory cells 202 of memory cell group 2021.

[0039] Figure 2B A circuit diagram including memory cell 202, driver 2250, and transistor Tsel0 is shown according to some embodiments described herein. Figure 2A A portion of the memory device 200. Figure 2BAs shown in the middle, the memory cell 202 can include a memory element 202E coupled to the conductive plate PLO. The memory element 202E can include a plate (e.g., a top plate) 202T, a plate (e.g., a bottom plate) 202B, a material (e.g., an insulating material, not shown) between the plates 202T and 202B. The plate 202T can be coupled to (e.g., can be part of) the conductive plate PLO. The plate 202B can be coupled to a terminal (e.g., a source or a drain) of the transistor T. The transistor T can have a terminal (e.g., a drain or a source) coupled to the data line DLO through the transistor SEL0.

[0040] The plates 202T and 202B and the material between the plates 202T and 202B can form a capacitor C of the memory element 202E of the memory cell 202. The conductive plate PLO can form part of the plate 202 of the memory element 202E. In an example, the material between the plates 202T and 202B of the capacitor C can include a ferroelectric material, such that the capacitor C is a ferroelectric capacitor. Thus, in an example, the memory cell 202 is a ferroelectric memory cell (e.g., a FeRAM memory cell) and the memory device 200 is a FeRAM device. A FeRAM device (e.g., the memory device 200) can have a similar device architecture as a volatile memory device (e.g., a DRAM). However, due to the use of a ferroelectric capacitor (e.g., the capacitor C of the memory cell 202) to store information, a FeRAM device can have non-volatile properties. Thus, a FeRAM device (e.g., the memory device 200) can have improved performance compared to other non-volatile and volatile memory devices.

[0041] In Figure 2B The memory element 202E can be configured to store information by charging or discharging the capacitor C. The capacitor C can be charged or discharged to store different states to reflect different values (e.g., digital values) of information to be stored in the memory cell 202. The memory cell 202 can be configured to store one bit of information or more than one bit of information.

[0042] In the example in which capacitor C is a ferroelectric capacitor, information can be stored in memory cell 202 by applying a voltage across capacitor C in a write operation. In a write operation, transistors T and Tselo can be turned on to access memory cell 202 and to couple plate 202B of capacitor C to data line DL0. The value of the voltage across capacitor C (to reflect the value of the information to be stored in memory cell 202) can be selected by controlling the voltage on conductive plate PLo and the voltage on data line DL0. Driver 2250 can be activated (e.g., turned on) to apply the voltage to plate 202T through conductive plate PLo. In an example write operation (e.g., to store a logic "0" in memory cell 202), a higher voltage (e.g., a positive voltage) can be applied to conductive plate PLo and a lower voltage (e.g., a ground potential) can be applied to data line DL0. In another example write operation (e.g., to store a logic "1" in memory cell 202), a lower voltage (e.g., a ground potential) can be applied to conductive plate PLo and a higher voltage (e.g., a positive voltage) can be applied to data line DL0.

[0043] A read operation can be performed to read information (previously stored information) from memory cell 202. In a read operation, transistors T and Tselo can be turned on to access memory cell 202. Driver 2250 can be activated to apply a voltage to conductive plate PLo, thereby applying a voltage to plate 202T (which is coupled to conductive plate PLo). Depending on the state (stored state) of capacitor C, a signal can be generated on data line DL0. Figure 2A Sense circuit 215 (e.g., a sense amplifier of sense circuit 215) can be operable to compare the signal (e.g., voltage) on data line DL0 to a reference signal (e.g., a reference voltage, not shown). The result of the comparison can be used to determine the value of the information (e.g., a logic "0" or a logic "1") stored in memory cell 202. For example, if the voltage on data line DL0 is greater than the reference voltage, the value of the information stored in memory cell 202 is determined to be a logic "1." In another example, if the voltage on data line DL0 is less than the reference voltage, the value of the information stored in memory cell 202 is determined to be a logic "0."

[0044] In Figure 2A , other memory cells 202 of memory array 201 can operate in a similar or same manner as memory cell 202 described above with reference to Figure 2B . For example, in Figure 2A , in a write operation to store information in a memory cell 202 associated with access line WLo of memory cell group 2020, access line WLo and data lines DL0-DL XThe memory cells 202 associated with the access line WL0 of the memory cell group 2020 can be accessed (e.g., selected) to store information in the memory cells 202. The driver 2250 can be activated to apply a voltage to the conductive plate PL0. The voltage on a particular one of the data lines DL0 to DL X The memory cells 202 associated with the access line WL0 of the memory cell group 2020 can be activated to store information in the memory cells 202. The driver 2250 can be activated to apply a voltage to the conductive plate PL0. The voltage on a particular one of the data lines DL0 to DL X and coupled to the sense circuit 215.

[0045] The driver 2250 can be activated to apply a voltage to the conductive plate PL0. The voltage can also be applied to the data lines DL0 to DL X associated with the memory cell group 2020. The voltage on a particular one of the data lines DL0 to DL X associated with the memory cell group 2020 can have a value based on a value of information to be stored in the memory cells 202 coupled to the particular data line. In this example write operation, the access lines WL1 to WLm of the memory cell group 2020 can be deactivated (not selected) so that the memory cells 202 associated with the access lines WL1 to WLm of the memory cell group 2020 are unselected memory cells (not selected to store information).

[0046] Storing information in the memory cells 202 associated with the access lines WL1 to WLm of the memory cell group 2020 can be performed in a similar manner as those memory cells 202 associated with the access line WL0 of the memory cell group 2020. In a write operation, one of the access lines WL0 to WLm of the memory cell group 2020 can be activated (selected) at a time to store information in the memory cells 202 associated with the selected access line.

[0047] To read information stored in the memory cells 202 associated with the access line WL0 of the memory cell group 2020, the access line WL0 and the data lines DL0 to DL X The memory cells 202 associated with the access line WL0 of the memory cell group 2020 can be accessed (e.g., selected) to store information in the memory cells 202. The driver 2250 can be activated to apply a voltage to the conductive plate PL0. The voltage on a particular one of the data lines DL0 to DL XThe voltage on a particular data line in the memory array 200 can have a value that is based on the value of information stored in the memory cells 202 coupled to that particular data line. The sense circuitry 215 can be operable to determine the value of the information (e.g., a logical “0” or a logical “1”) stored in each memory cell 202 of the memory cell group 2020 (the selected memory cells). In this example read operation, the access lines WL1 through WLm of the memory cell group 2020 can be deactivated (not selected) so that the memory cells 202 associated with the access lines WL1 through WLm of the memory cell group 2020 are unselected memory cells (not selected to read information therefrom).

[0048] In Figure 2A the transistor Tsel0 through Tsel X associated with different memory cell groups (different conductive plates) can not be turned on concurrently (e.g., at the same time). For example, in a read operation to read the memory cells 202 of the memory cell group 2020, the transistors Tsel0 through Tsel X of the memory cell group 2020 are turned on. However, the transistors Tsel0 through Tsel i associated with the memory cell group 2021 through the memory cell group 202 X are turned off. Thus, in a read operation, the data lines DL0 through DL X associated with one memory cell group are coupled to the sense circuitry 215 (through the turned on transistors Tsel0 through Tsel X ) and the data lines DL0 through DL X associated with the other memory groups are decoupled from the sense circuitry 215 (not coupled to the sense circuitry 215).

[0049] Figure 2A An example of a short 222 coupled between the conductive plates PL0 and PL1 is shown. The conductive plates PL0 and PL1 are adjacent to each other (e.g., immediately adjacent to each other). The short 222 is an unintended element (e.g., unintended conductive path (e.g., current path)) in the memory device 200 that can be a result of a random defect introduced to the memory device 200 during or after fabrication. The short 222 can form a conductive path that can cause current to flow between the conductive plate PL0 and the conductive plate PL1. The short 222 can be identified (e.g., discovered) during testing of the memory device 200 during or after fabrication of the memory device 200. After the short 222 is identified, one of the conductive plate PL0 and the conductive plate PL1 and associated circuit elements (e.g., memory cells 202) can be selected (e.g., designated) as a damaged portion (not used to store information). The other conductive plates and circuit elements (e.g., memory cells 202) can still be considered as normal (not damaged) portions. For example, inFigure 2A In this example, the conductive plate PL1 and its associated circuit elements (e.g., memory cells 202 in the memory cell group 2021) can be selected (e.g., designated) as a defective portion. Thus, in this example, the memory cells 202 in the memory cell group 2021 are not used to store information. In this example, the conductive plate PLO and its associated circuit elements (e.g., memory cells 202 in the memory cell group 2020) can be considered a normal portion. Thus, in this example, the memory cells 202 in the memory cell group 2020 can still be used to store information.

[0050] In Figure 2A In the memory device 200, the conductive plates PL0-PL i and its associated circuit elements (e.g., memory cells, data lines, access lines, and cell plate drivers) can be selected as a redundant portion of the memory device 200. For example, the conductive plate PL i and its associated circuit elements can be the redundant portion. Thus, the conductive plate PL i may be referred to as a redundant conductive plate. The memory device 200 can use the redundant portion to replace (e.g., repair) a defective portion of the memory device 200. The defective portion can be a portion of a main memory array (e.g., a regular memory array) of the memory device 200. For example, the conductive plates PL0-PL i-1 and its associated circuit elements (e.g., memory cells, data lines, access lines, and cell plate drivers) can be included in the main memory array of the memory device 200. In this example, the conductive plate PL i and its associated circuit elements (e.g., in a redundant memory array of the memory device 200) can be used to replace the defective portion (which includes the conductive plate PL0) in the main memory array.

[0051] The memory device 200 can be configured to replace memory operations (e.g., write and read operations) associated with a defective portion (e.g., the portion including the conductive plate PL1 in the above example) with operations associated with a conductive plate (e.g., a redundant conductive plate) PL i The memory control circuitry of the memory device 200 (e.g., similar to the memory control circuitry 110 of the memory device 100) can be configured to replace the memory operations associated with the defective portion with the memory operations associated with the redundant conductive plate PL Figure 1The memory control circuitry 110 of the memory device 200 can be configured (e.g., programmed) to store address information (e.g., addresses of physical locations) of memory cells (e.g., columns of memory cells 202) associated with the defective portion of the conductive plate. Then, based on the stored address information, the memory control circuitry of the memory device 200 can replace (e.g., by re-routing) memory operations (e.g., write and read operations) involving memory cells associated with the defective portion of the conductive plate with memory operations (e.g., write and read operations) of memory cells associated with the redundant portion of the conductive plate.

[0052] In the example described above, the conductive plate PL1 is selected (e.g., designated) as the defective conductive plate. In this example, memory operations (e.g., write or read operations) involving the conductive plate PL1 (defective conductive plate) can be replaced (e.g., repaired) with memory operations (e.g., write or read operations) involving the conductive plate PL i (e.g., redundant conductive plate). For example, a write operation to store information in the memory cells 202 associated with the conductive plate PL1 can be replaced with a write operation to the memory cells 202 associated with the conductive plate PL i (e.g., redundant conductive plate). For example, a write operation to store information in the memory cells 202 associated with the conductive plate PL1 can be replaced with a write operation to the memory cells 202 associated with the conductive plate PL i (e.g., redundant conductive plate). For example, in a read operation, the memory device 200 can receive a read command to read information at an address associated with the memory cells 202 associated with the conductive plate PL1. In response to the read command, the memory device 200 can perform a read operation to read information from the memory cells associated with the conductive plate PL i (e.g., redundant conductive plate) instead of from the memory cells associated with the conductive plate PL1. Then, the memory device 200 can provide the information read from the memory cells associated with the conductive plate PL i (e.g., redundant conductive plate) instead of from the memory cells associated with the conductive plate PL1. Then, the memory device 200 can provide the information read from the memory cells associated with the conductive plate PL

[0053] In the above example where conductive plate PL1 is selected (e.g., designated) as the defective conductive plate (due to short 222), conductive plate PLO and the associated circuit elements (e.g., memory cell group 2020) can be configured to operate in a normal manner as a normal part (non-defective part) of memory device 200. Thus, conductive plate PLO and the associated circuit elements (e.g., memory cell group 2020) are not replaced by a redundant part of memory device 200. The memory cells 202 of memory cell group 2020 (associated with conductive plate PLO) can be used to store information (in a write operation) by applying appropriate voltages to conductive plate PLO and data lines IdO-x associated with memory cell group 2020.

[0054] The following technique can be used to perform a read operation to read information from memory cell group 2020. For example, in response to a read command to read information from memory cells 202 associated with access line WLO of memory cell group 2020, memory device 200 can activate access line WLO and data lines DL0-DLx associated with memory cell group 2020. Memory device 200 can activate (e.g., turn on) driver 2250 to apply a positive voltage to conductive plate PLO. Memory device 200 can deactivate (e.g., turn off) driver 2251 to place conductive plate PL1 in a floating state. Alternatively, memory device 200 can activate (e.g., turn on) driver 2251 to apply a positive voltage to conductive plate PLO. The voltages applied to conductive plates PLO and PL1 (by respective activation of drivers 2250 and 2251) can be the same. X Access (e.g., select) memory cells 202 associated with access line WLO of memory cell group 2020. Driver 2250 can be activated (e.g., turned on) to apply a positive voltage to conductive plate PLO. Driver 2251 can be deactivated (e.g., turned off) to place conductive plate PL1 in a floating state. Alternatively, driver 2251 can be activated (e.g., turned on) to apply a positive voltage to conductive plate PLO. The voltages applied to conductive plates PLO and PL1 (by respective activation of drivers 2250 and 2251) can be the same.

[0055] In the above read operation, signal SEL0 can be activated (e.g., provided with a positive voltage) to turn on transistors Tsel0-Tsel X associated with data lines DL0-DLx of memory cell group 2020. Signal SEL1-SEL X may be deactivated so that transistors Tsel0-Tsel X of associated memory cell groups 2021-202 X are not turned on. Thus, in this example, data lines (non-selected data lines) DL0-DLx of associated memory cell groups 2021-202 i are not coupled to sense circuit 215. Thus, memory cells 202 of associated memory cell groups 2021-202 i are not accessed (e.g., selected) in the read operation. X Thus, in this example, data lines (non-selected data lines) DL0-DLx of associated memory cell groups 2021-202 i are not coupled to sense circuit 215. Thus, memory cells 202 of associated memory cell groups 2021-202 Xnot coupled to the sense circuit 215. In an example, the unselected data lines (e.g., the data lines associated with the memory cell groups 2021-202 i The associated data lines DL0-DL X may be coupled to a ground potential (e.g., a voltage Vss). Since the data lines DL0-DL X associated with the memory cell groups 2021 are not coupled to the sense circuit 215, information (if any) stored in the memory cells 202 of the memory cell groups 2021 is ignored (e.g., not sensed by the sense circuit 215).

[0056] As described above, the data lines DL0-DL X associated with the selected memory cells of the memory cell group 2020 are coupled to the sense circuit 215. The sense circuit 215 is operable to determine a value (e.g., a logical "0" or a logical "1") of information stored in each memory cell 202 (the selected memory cells) of the memory cell group 2020 based on a signal (e.g., a voltage value).

[0057] Figure 3 A memory device 300 including groups of conductive plates 301, 302, and 303 is shown in accordance with some embodiments described herein. As Figure 3 shown in Figure 3 three groups of conductive plates 301, 302, and 303 are shown. However, the memory device 300 can have more than three groups of conductive plates. Figure 3 An example in which each of the groups of conductive plates 301, 302, and 303 includes eight conductive plates PL0-PL7 is shown. However, the number of conductive plates of the groups of conductive plates 301, 302, and 303 can be different than eight.

[0058] In Figure 3 each of the conductive plates PL0-PL7 can be associated with circuit elements including memory cells 202, data lines DL0-DL X , access lines WL0-WLm, and sense circuits 215, respectively, as Figure 2A shown in Figure 3 some such circuit elements are not shown in

[0059] As Figure 3 shown in Figure 2A each of the groups of conductive plates 301, 302, and 303 can include a driver (driver circuit) 225, each of which can be associated with a driver 2250-225 ione of the Figures is similar or identical. As Figure 3 As shown in Figure 3 In the example of

[0060] Figure 3 An example of a short 222' is shown, which can be similar or identical to the short 222 of Figure 2A As shown in Figure 3 In the example of Figure 3 In the example of Figure 3 In the example of Figure 2A

[0061] In the memory device 300, the conductive plate group 303 and its associated circuit elements (e.g., memory cells, data lines, access lines, and cell plate drivers) can be included in a redundant portion (e.g., a redundant (spare) memory array portion) 312 of the memory device 300. The conductive plate group 303 and its associated circuit elements can be used to replace (e.g., repair) a damaged portion in the main memory array 310 of the memory device 300. In the example of Figure 3 In the example of

[0062] As shown in Figure 3 ​As shown in the middle, the group of conductive plates 303 of the redundancy portion 312 can have the same number of conductive plates (e.g., eight conductive plates PL0-PL7) as each of the groups of conductive plates 301 and 302 included in the main memory portion 310. The groups of conductive plates 301, 302, and 303 can be organized in the same pattern from conductive plate PL0 to PL7. The relative physical locations (and addresses) of the conductive plates PL0-PL7 (and associated circuit elements) of a group of conductive plates (e.g., group of conductive plates 301) in the memory portion 310 can be the same as the relative physical locations (and addresses) of the conductive plates PL0-PL7 (and associated circuit elements) of a group of conductive plates (e.g., group of conductive plates 303) in the redundancy portion 312. The relative physical locations and addresses can simplify memory operations (e.g., write and read operations) associated with replacing a damaged portion in the memory portion 310. For example, in the instance of FIG. 3B, because the conductive plate PL1 and its associated circuit elements are designated as the damaged portion, the conductive plate PL1 and its associated circuit elements in the redundancy portion 312 can be used as the replacement portion. Figure 3

[0063] In a write operation intended to store information in a memory cell (not shown in Figure 3 ) associated with the conductive plate PL1 of the group of conductive plates 301, the memory device 300 can be operable to store the information in a memory cell (not shown in Figure 3 ) associated with the conductive plate PL1 in the redundancy portion 312, rather than in a memory cell associated with the conductive plate PL1 in the group of conductive plates 301, because the conductive plate PL1 of the group of conductive plates 301 is damaged. Thus, in a read operation intended to read information from a memory cell associated with the conductive plate PL1 of the group of conductive plates 301, the memory device 300 can be operable to read the information from a memory cell associated with the conductive plate PL1 in the redundancy portion 312, rather than from a memory cell associated with the conductive plate PL1 of the group of conductive plates 301.

[0064] Write and read operations to a memory cell (not shown) associated with the conductive plate PL1 of the group of conductive plates 301 can be similar to write and read operations to a memory cell 202 associated with the conductive plate PL1 of the group of conductive plates 2020 of Figure 2A .

[0065] Figure 4 A memory device 400 including groups of conductive plates 401-406, multiplexers 411-416, and multiplexer 420 is shown in accordance with some embodiments described herein. Figure 4 ​An example is shown in which the number of conductive plate groups 401 to 406 is six and the number of multiplexers 411 to 416 is also six. However, the number of conductive plate groups and associated multiplexers may vary. Figure 4 An example is shown in which each conductive plate group includes eight conductive plates. However, the number of conductive plates in each conductive plate group may vary. Figure 4 In the example of FIG. 4 , the memory device 400 may include conductive plates PL0 to PL 47 There are 48 conductive plates in total (6 conductive plate groups and 8 conductive plates in each conductive plate group). 47 Each of can contain Figure 2A The associated circuit elements (eg, memory cells, data lines, access lines, and cell plane drivers) of each conductive plate (eg, conductive plate PL0) are connected to the conductive plate.

[0066] The memory device 400 may include a redundant portion, which may include a conductive plate PL 47 and associated circuit elements (e.g., memory cells and data lines, access lines, and cell plate drivers). 47 The redundant portion can be used to replace a short circuit (e.g., like a short circuit) in the conductive plate of the memory device 400. Figure 2A The damaged portion is caused by the short circuit 222 in FIG.

[0067] like Figure 4 As shown in FIG, each conductive plate is associated with a group of N data lines (where N is an integer) that are parallel data lines (N parallel data lines). The group of N data lines is similar to Figure 2A Data lines DL0 to DL X group.

[0068] exist Figure 4 , each of the multiplexers 411 to 416 is associated with one of the conductive plate groups 401 to 406. Each of the multiplexers 411 to 416 may be a P:1 multiplexer, where P represents (equals) the number of conductive plates in a conductive plate group. Figure 4An example is shown in which each of multiplexers 411-416 is an 8: 1 multiplexer because the number of conductive plates in a group of conductive plates (e.g., conductive plates PLO-PL7) is 8 (e.g., P = 8). Each of multiplexers 411-416 can include inputs (e.g., input nodes) coupled to a group of N data lines associated with each conductive plate of a respective group of conductive plates. Each of multiplexers 411-416 can include an output (e.g., an output node) that can include a group of N conductive lines (N parallel data lines). During a read operation, each of multiplexers 411-416 can select information at its inputs (multiplexer inputs or MUX inputs) from a particular group of N data lines (in the 8 groups of N data lines). Then, each of multiplexers 411-416 can pass the information (selected information) to its output (multiplexer output or MUX output). The particular group of N data lines is associated with a selected conductive plate (e.g., PLO) of a group of conductive plates (e.g., conductive plate group 401). The selected conductive plate (e.g., conductive plate PLO) is associated with a selected memory cell during a memory operation (e.g., a read operation) of memory device 400.

[0069] Multiplexer 420 can include inputs (e.g., input nodes) coupled to a group of N conductive lines at the outputs of multiplexers 411-416. Multiplexer 420 can include an output (e.g., an output node) that can include a group of N conductive lines (N parallel data lines). Multiplexer 420 can be an M: 1 multiplexer, where M represents (equals) the number of groups of conductive plates. Figure 4 An example is shown in which multiplexer 420 is a 6: 1 multiplexer because the number of groups of conductive plates (e.g., conductive plate groups 401-406) is 6 (e.g., M = 6). Multiplexer 420 can operate to select information at its inputs from a particular group of N conductive lines (in the 6 groups of N conductive lines) and pass the information to its output.

[0070] Memory device 400 can include sensing circuitry 435 coupled to the N conductive lines at the output of multiplexer 420. Sensing circuitry 435 can operate to determine a value (e.g., a logical “0” or a logical “1”) of information read from memory cells associated with conductive plates PLO-PL 47

[0071] Memory device 400 can perform a memory operation (e.g., a read operation) from memory cells associated with conductive plates PLO-PL 47 ​The read operation of the associated memory cell to read information is similar to the read operation. Figure 4 An example of a short circuit 222" between conductive plates PL0 and PL1 is shown. However, if short circuit 222" does not exist in memory device 400, memory device 400 can directly connect conductive plates PL0 to PL1. 46 The associated selected memory cell reads information.

[0072] exist Figure 4 In the example of FIG. 2 , in the case of a short circuit 222 ″, the memory device 400 may be configured as described above with reference to FIG. Figure 2A and Figure 3 For example, if the memory device 400 has a short circuit between conductive plates PL0 and PL1, then conductive plate PL1 and associated circuit elements can be selected (e.g., designated) as the damaged portion. In this example, conductive plate PL 47 and its associated circuit elements (e.g., memory cells) can be used to replace conductive plate PL1 and its associated circuit elements (e.g., memory cells). In this example, reading information from the memory cells associated with conductive plates PL0 and PL1 can be similar to reading information from the memory cells associated with conductive plates PL0 and PL1. Figure 2A Information is read from memory cells associated with conductive plates PL0 and PL1 of memory device 200.

[0073] The techniques described above can improve yield and reduce costs associated with the fabrication of the memory devices described herein, such as memory devices 100, 200, 300, and 400. Additionally, the structure and configuration of the memory devices described herein, such as memory devices 100, 200, 300, and 400, allow for appropriate memory operations (e.g., read and write operations) as described above, which may be impractical for some conventional memory devices.

[0074] Figure 5 is a flow chart of an example method 500 for operating a memory device according to some embodiments described herein. The method 500 may be performed by an apparatus (eg, memory device 100, 200, or 300) and / or a system (eg, Figure 6 The system 600 in FIG. Figure 5 As shown in , method 500 may include activities (eg, operations) 510 , 520 , and 530 .

[0075] Activity 510 can include accessing a first memory cell of a memory device during a memory operation of the memory device. The first memory cell is associated with a first conductive plate of conductive plates of the memory device. The first conductive plate is shorted to a second conductive plate of the conductive plates. The second conductive plate is associated with a second memory cell of the memory device. The first and second memory cells include ferroelectric memory cells.

[0076] Activity 520 can include coupling a first data line associated with the first memory cell to a sense circuit during the memory operation.

[0077] Activity 530 can include decoupling a second data line associated with the second memory cell from the sense circuit during the memory operation.

[0078] The method 500 described above can include fewer or more activities than those shown in Figure 5 The method 500 can include additional activities (e.g., operations) associated with an apparatus (e.g., the memory devices 100, 200, 300, and 400) and / or system (e.g., the system 600 in Figure 6 The method 500 can provide similar improvements and advantages as those described above with respect to the memory devices (e.g., the memory devices 100, 200, 300, and 400). Figures 2A to 3 The method 500 can provide similar improvements and advantages as those described above with respect to the memory devices (e.g., the memory devices 100, 200, 300, and 400).

[0079] Figure 6 An apparatus in the form of a system (e.g., an electronic system) 600, in accordance with some embodiments described herein, is shown. The system 600 can be considered a machine. The system (e.g., machine) 600 can include or be included in a computer, cellular phone, or other electronic system. As shown in Figure 6 The system 600 can include components (e.g., devices) located on a circuit board (e.g., PCB) 602, as shown in

[0080] The system 600 can be configured to perform one or more of the methods and / or operations described herein. At least one of the components of the system 600 (e.g., at least one of the processor 615, the memory device 620, the memory controller 630, the graphics controller 640, and the I / O controller 650) can include at least one of the devices described herein. For example, the memory device 620 can include one of the memory devices 100, 200, 300, and 400.

[0081] In Figure 6 The processor 615 can include a general-purpose processor or an application-specific integrated circuit (ASIC). The processor 615 can include a central processing unit (CPU) and processing circuitry. The graphics controller 640 can include a graphics processing unit (GPU) and processing circuitry. The memory device 620 can include a FeRAM device, a DRAM device, a static random access memory (SRAM) device, a flash memory device, a phase change memory, or a combination of these memory devices, or other types of memory. Figure 6 An example is shown in which the memory device 620 is a standalone memory device separate from the processor 615. In an alternative structure, the memory device 620 and the processor 615 can be located on the same IC chip (e.g., semiconductor die or IC die). In this alternative structure, the memory device 620 is an embedded memory in the processor 615, such as an embedded DRAM (eDRAM), an embedded SRAM (eSRAM), an embedded flash memory, or another type of embedded memory.

[0082] The storage device 660 can include a drive unit (e.g., a hard disk drive (HDD), a solid-state drive (SSD), or another mass storage device). The storage device 660 can include machine-readable media 662 and processing circuitry. The machine-readable media 662 can store one or more sets of data structure or instructions 664 (e.g., software) embodying any one or more of the techniques or functions described herein or used by any one or more of the techniques or functions described herein. The instructions 664 can also reside completely, or at least partially, within the memory device 620, the memory controller 630, the processor 615, or the graphics controller 640 during execution thereof by the system (e.g., machine) 600.

[0083] In examples, one or any combination of the processor 615, the memory device 620, the memory controller 630, the graphics controller 640, and the storage device 660 can constitute a machine-readable medium. Non-limiting examples of machine-readable media can include solid-state memories and optical and magnetic media. Specific examples of machine-readable media can include non-volatile memory, such as semiconductor memory devices (e.g., EPROM or EEPROM), and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROM and DVD-ROM disks.

[0084] As examples, Figure 6 The machine-readable medium 662 is shown as a single medium. However, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store the instructions 664. Additionally, the term "machine-readable medium" can include any medium that is capable of storing, encoding, or carrying instructions for execution by the system 600 and that cause the system 600 to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. In some examples, a machine-readable medium can include a non-transitory machine-readable medium. In some examples, a machine-readable medium can include a machine-readable medium that is not a transitory propagating signal.

[0085] The display 652 can include a liquid crystal display (LCD), a touch screen (e.g., capacitive or resistive touch screen), or another type of display. The pointing device 656 can include a mouse, a touch pad, or another type of pointing device. In some configurations, the system 600 need not include a display. Thus, in such configurations, the display 652 can be omitted from the system 600.

[0086] The antenna 658 can include one or more directional or omnidirectional antennas, including, for example, a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a microstrip antenna, or other types of antennas suitable for transmission and reception of radio frequency (RF) signals. In some configurations, the system 600 need not include an antenna. Thus, in such configurations, the antenna 658 can be omitted from the system 600.

[0087] The I / O controller 650 can include a communication module for wired or wireless communication (e.g., communication through the one or more antennas 658). Such wireless communication can include communication according to WiFi communication techniques, Long Term Evolution (LTE-A) communication techniques, fifth generation (5G) wireless systems or variants or derivatives thereof, 6G mobile network systems or variants or derivatives thereof, 6G New Radio (NR) systems or variants or derivatives thereof, or other cellular service standards, or other communication techniques.

[0088] The I / O controller 650 can also include a module to allow the system 600 to communicate with other devices or systems in accordance with one or more of the following standards or specifications (e.g., I / O standards or specifications), including Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt interface, Peripheral Component Interconnect Express (PCIe), Ethernet, and others.

[0089] The connector 655 can include terminals (e.g., pins) to allow the system 600 to receive connections (e.g., electrical connections) from external devices (or systems). This can allow the system 600 to communicate (e.g., exchange information) with such devices (or systems) through the connector 655. The connector 655 and at least a portion of the bus 670 can include electrically conductive wires that comply with at least one of the USB, DP, HDMI, Thunderbolt interface, PCIe, Ethernet, and other specifications.

[0090] As an example, Figure 6 The components (e.g., devices) of the system 600 are shown arranged separately from one another. For example, each of the processor 615, the memory device 620, the memory controller 630, the graphics controller 640, and the I / O controller 650 can be included in (e.g., formed in or on) separate integrated circuit (IC) chips (e.g., separate semiconductor dies or separate IC dies). In some configurations of the system 600, two or more components of the system 600 (e.g., the processor 615, the memory device 620, the graphics controller 640, and the I / O controller 650) can be included in (e.g., formed in or on) the same IC chip (e.g., the same semiconductor die), forming a SoC or, alternatively, a SiP.

[0091] The above-described descriptions of the apparatuses (e.g., the memory devices 100, 200, 300, and 400, and the system 600) are intended to provide a general understanding of the structure of different embodiments and are not intended to provide a complete description of all elements and features that can be utilized in the apparatuses described herein.

[0092] The above-described ways of implementing the apparatuses described above with reference to Figures 1 to 6Any of the described components. Thus, the devices (e.g., memory devices 100, 200, 300, and 400, and system 600) can all be characterized as "a number of modules" (or "module") herein. Such modules can include hardware circuitry, single and / or multi-processor circuitry, memory circuitry, software program modules and objects, and / or firmware, and combinations thereof, as desired and / or needed for particular implementations of various embodiments. For example, such modules can be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitance-inductance simulation packages, power / heat dissipation simulation packages, signal transmission-reception simulation packages, and / or combinations of software and hardware for operating or simulating operation of various potential embodiments.

[0093] The devices and methods described above can include high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application specific modules including multi-layer and multi-chip modules, and combinations thereof. Such devices can further include subcomponents such as, for example, a microprocessor and / or other processing circuitry, a storage medium such as code and / or data, a user interface, and various input / output devices such as a display, a keyboard, a mouse, and the like.

[0094] The descriptions of the devices (e.g., memory devices 100, 200, 300, and 400, and system 600) and methods (e.g., method 500 and methods of operating memory devices 100, 200, 300, and 400, and system 600) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of the devices that can make use of the structures described herein. The devices herein refer to, for example, a device (e.g., any of memory devices 100, 200, 300, and 400) or a system (e.g., an electronic product that can include any of memory devices 100, 200, 300, and 400, and system 600).

[0095] The above-described ways of implementing the devices described above with reference to Figures 1 to 6Any of the described components. Thus, a device (e.g., memory devices 100, 200, 300, and 400, and system 600) or portions of each of these memory devices described above can all be characterized as "a number of modules" (or "module") herein. Such modules can include hardware circuitry, single and / or multi-processor circuitry, memory circuitry, software program modules and objects, and / or firmware, and combinations thereof, as desired and / or needed for particular implementations of various embodiments. For example, such modules can be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitance-inductance simulation packages, power / heat dissipation simulation packages, signal transmission-reception simulation packages, and / or combinations of software and hardware for operating or simulating operation of various potential embodiments.

[0096] The memory devices (e.g., memory devices 100, 200, 300, and 400, and system 600) described herein can be included in a device (e.g., electronic circuitry), such as a high-speed computer, communications, and signal processing circuitry, a single or multi-processor module, a single or multiple embedded processors, a multi-core processor, a message information switch, and a special purpose module including multiple layers of multiple chip modules. Such devices can further include as subcomponents within a variety of other devices (e.g., electronic systems), such as televisions, cell phones, personal computers (e.g., laptops, desktops, handheld PCs, tablet PCs, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and other devices.

[0097] The above references Figures 1 to 6 The described embodiments include devices and methods of operating the devices. One of the devices includes electrically conductive plates adjacent to each other, memory cells associated with the electrically conductive plates, drivers coupled to the electrically conductive plates such that one of the drivers is associated with one of the electrically conductive plates, and a short coupled between a first one of the electrically conductive plates and a second one of the electrically conductive plates. Other embodiments include additional devices and methods.

[0098] In the detailed description and in the claims, the term "on," as used with respect to two or more elements (e.g., materials) indicates that at least some contact between elements (e.g., materials). The term "above" indicates close proximity, but can have one or more additional intervening elements (e.g., materials) such that contact is possible but not necessary. Neither "on" nor "above" implies any directionality as used herein unless otherwise specified.

[0099] In the detailed description and in the claims, a list of items joined by the term "at least one of" can mean any single one of the listed items. The phrase "at least one of" can mean, for example, A or B, or A and B. In another example, if items A and B are listed, the phrase "at least one of A and B" can mean A, or B, or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" can mean A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0100] In the detailed description and in the claims, a list of items joined by the term "one of' can mean any single one of the listed items. The phrase "one of' can mean, for example, A or B, but not both. In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" can mean A, or B, or C, but not A and B, or A and C, or B and C.

[0101] In the detailed description and in the claims, the terms "first," "second," "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0102] The above description and drawings illustrate and describe the subject matter of the present disclosure to enable a person skilled in the art to make and use embodiments of the subject matter. Other embodiments can be implemented and come within the scope of the present disclosure. The examples are representative and do not limit the scope of the subject matter. Parts and features of some embodiments can be included in, or substituted for, parts and features of other embodiments. Many other embodiments will be apparent to those of ordinary skill in the art, in view of the foregoing description and drawings.

Claims

1. A device comprising: conductive plates, which are adjacent to each other; a memory cell associated with the conductive plate; drivers coupled to the conductive plates such that one of the drivers is associated with one of the conductive plates; and A short circuit is coupled between a first one of the conductive plates and a second one of the conductive plates.

2. The apparatus of claim 1, wherein the memory cell comprises a ferroelectric memory cell and the conductive plate forms part of a memory element of the memory cell.

3. The apparatus of claim 1, wherein the conductive plates are organized into conductive plate groups, each of the conductive plate groups including more than two of the conductive plates.

4. The apparatus according to claim 3, further comprising: a first data line associated with the first conductive plate; and A second data line is associated with the second conductive plate.

5. The apparatus of claim 1, wherein one of the conductive plates is configured to replace the second conductive plate.

6. The apparatus of claim 1, wherein the conductive plates are organized into conductive plate groups, each of the conductive plate groups including more than two of the conductive plates, and a conductive plate of one of the conductive plate groups is configured to replace the second conductive plate.

7. The apparatus of claim 1 , further comprising control circuitry to: activating a first driver of the drivers during a memory operation, wherein the first driver is coupled to the first conductive plate; and A second one of the drivers is deactivated during the memory operation, wherein the second driver is coupled to the second conductive plate.

8. The apparatus of claim 1 , further comprising control circuitry to: coupling a data line associated with the first conductive plate to a sensing circuit during memory operations; and A data line associated with the second conductive plate is decoupled from the sensing circuit during the memory operation.

9. The apparatus of claim 1, wherein the first conductive plate is adjacent to the second conductive plate.

10. A device comprising: a conductive plate group, each of the conductive plate groups comprising a number of conductive plates, the number of conductive plates being greater than 2; a data line associated with each of the conductive plates of each of the groups of conductive plates; a memory cell associated with the data line; a short circuit coupled between a first conductive plate and a second conductive plate of one of the conductive plate groups; first multiplexers, each of the first multiplexers being associated with a respective one of the groups of conductive plates and including an input coupled to the data line associated with each of the conductive plates of the respective group of conductive plates; a second multiplexer comprising an input coupled to the output of the first multiplexer; and A sensing circuit is coupled to the output of the second multiplexer. The apparatus of claim 10 , wherein one of the conductive plates is a redundant conductive plate.

12. The apparatus of claim 10, wherein each of the first multiplexers is a P:1 multiplexer, and P represents the number of conductive plates in each of the conductive plate groups.

13. The apparatus of claim 12, wherein the second multiplexer is an M:1 multiplexer, and M represents the number of the conductive plate groups.

14. The apparatus of claim 10, further comprising a number of drivers coupled to the number of conductive plates in each of the conductive plate groups, wherein the number of drivers is equal to a total number of conductive plates of the conductive plate groups.

15. The apparatus of claim 10, wherein each of the memory cells comprises a ferroelectric capacitor coupled to a conductive plate of the number of conductive plates in one of the conductive plate groups.

16. A method comprising: accessing a first memory cell of a memory device during a memory operation of the memory device, the first memory cell being associated with a first one of the conductive plates of the memory device, the first conductive plate being shorted to a second one of the conductive plates, the second conductive plate being associated with a second memory cell of the memory device, and the first and second memory cells comprising ferroelectric memory cells; coupling a first data line associated with the first memory cell to a sensing circuit during the memory operation; and A second data line associated with the second memory cell is decoupled from the sensing circuit during the memory operation.

17. The method according to claim 16, further comprising: activating a first driver coupled to the first conductive plate during the memory operation; and A second driver coupled to the second conductive plate is deactivated during the memory operation.

18. The method of claim 16, further comprising: activating a first driver coupled to the first conductive plate during the memory operation; and A second driver coupled to the second conductive plate is activated during the memory operation.

19. The method of claim 16, wherein: coupling the first data line includes turning on a first transistor coupled between a sensing circuit and the first data line associated with the first memory cell during the memory operation; and Decoupling the second data line includes turning off a second transistor coupled between the sensing circuit and the second data line associated with the second memory cell during the memory operation.

20. The method of claim 16, further comprising: receiving a command to read information at an address associated with the second memory location; and Information is read from a third memory cell in response to the command and the address, the third memory cell being associated with a third one of the conductive plates of the memory device.

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