SRAM circuit structure
By introducing a heating element and a temperature control unit into the SRAM circuit, the temperature is monitored and adjusted in real time, which solves the high power consumption problem in the read and write modes of the SRAM unit, achieves reduced power consumption and improved device performance stability.
Patent Information
- Application Number
- CN202510884843.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-28
- Publication Date
- 2025-10-17
AI Technical Summary
Traditional SRAM cells consume high power in read and write modes, especially in high-density storage arrays. Self-heating effects lead to device performance degradation and reliability issues.
An SRAM circuit structure is designed, which includes an SRAM unit, a heating element and a temperature control unit. The temperature is monitored by a temperature sensor, and the processor determines the working status. The control switch and power supply provide current to the heating element to adjust the temperature and reduce the power consumption in the read and write modes.
Through the combined action of the heating element and the self-heating effect, the conductivity of the transistor is improved, the voltage requirements for read and write operations are reduced, and the power consumption of the SRAM cell is significantly reduced, while the power consumption in the retention mode is reduced.
Smart Images
Figure CN120808837A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of SRAM (Static Random Access Memory), in particular to a SRAM circuit structure. BACKGROUND
[0002] SRAM is a widely used memory in integrated circuits, with advantages such as high-speed read-write and high stability. With the continuous shrinking of process nodes, the power consumption of SRAM cells becomes a key challenge in design. Traditional SRAM cells require high voltage and current in read-write mode, resulting in increased power consumption, especially in high-density memory arrays, where power consumption is particularly prominent.
[0003] In recent years, self-heating effect (SHE) has attracted widespread attention in semiconductor devices. Self-heating effect refers to the local heat generated by current passing through during device operation, resulting in an increase in device temperature. In traditional design, self-heating effect is usually considered a negative impact, as it can lead to device performance degradation or reliability problems. How to utilize self-heating effect has become a technical problem to be solved. SUMMARY
[0004] The present application provides a SRAM circuit structure to solve the technical problem of high power consumption of SRAM cells in read-write mode.
[0005] To solve the above technical problems, the present application provides a SRAM circuit structure, comprising a SRAM cell, a heating element and a temperature control unit; the temperature control unit comprises a temperature sensor, an analog-to-digital converter, a processor, a switch and a power supply;
[0006] The temperature sensor is connected to the SRAM cell or the heating element;
[0007] The processor is connected to the SRAM cell, the analog-to-digital converter and the switch, respectively;
[0008] The switch, the power supply and the heating element form a series loop;
[0009] The heating element is arranged inside or outside the SRAM cell;
[0010] The temperature sensor sends the detected temperature to the processor through the analog-to-digital converter; the processor is used to judge the working state of the SRAM cell, and adjusts the state of the switch according to the working state of the SRAM cell and the temperature detected by the temperature sensor, so that the temperature detected by the temperature sensor is less than the preset temperature.
[0011] Preferably, the heating element is arranged inside the SRAM cell; the SRAM cell comprises a plurality of NMOS tubes, and at least one of the NMOS tubes is arranged with a heating element inside.
[0012] Preferably, the heating element is arranged below the channel of the NMOS tube.
[0013] Preferably, each of the NMOS tubes is arranged with a heating element inside.
[0014] Preferably, each of the heating elements corresponds to a temperature control unit, and one end of the heating element is connected to the corresponding temperature sensor.
[0015] Preferably, the other end of the heating element is connected to the source or drain of the corresponding NMOS tube.
[0016] Preferably, the SRAM cell comprises a 6T SRAM, and the 6T SRAM comprises two pull-up PMOS tubes, two pull-down NMOS tubes, and two transfer NMOS tubes.
[0017] Preferably, the power supply is an adjustable current source.
[0018] Preferably, the heating element is a resistance heating wire.
[0019] Preferably, the heating element is made of a thermoelectric material.
[0020] The present application provides an SRAM circuit structure, which comprises an SRAM cell, a heating element, and a temperature control unit. The temperature control unit comprises a temperature sensor, an analog-to-digital converter, a processor, a switch, and a power supply. The processor can determine the working state of the SRAM cell, and the temperature sensor can monitor the temperature of the SRAM cell or the heating element in real time. When the SRAM cell is in a read-write mode and the temperature detected by the temperature sensor is less than a preset temperature, the processor controls the switch to be closed, the power supply provides current to the heating element, and the heating element generates heat. Under the combined action of the heat generated by the heating element and the heat generated by the self-heating effect of the SRAM cell, the conductivity of the transistors in the SRAM cell is significantly improved, and the voltage applied to the SRAM cell for read-write operation can be significantly reduced, thereby reducing the power consumption of the SRAM cell in the read-write mode. When the SRAM cell is in a holding mode, the processor controls the switch to be opened, and the power supply does not provide current to the heating element, so that the heating element does not generate heat. At this time, the power consumption of the power supply can be reduced. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 is a circuit schematic diagram of an SRAM circuit structure provided by an embodiment of the present application.
[0022] Figure 2 Figure 1 is a schematic diagram of a heating element and a temperature control unit connected according to an embodiment of the present application.
[0023] Figure 3 Figure 2 is a schematic diagram of power consumption before and after improvement of a 6T SRAM according to an embodiment of the present application.
[0024] Reference signs are as follows:
[0025] Temperature control unit - 11;
[0026] Temperature sensor - 111, analog-to-digital converter - 112, processor - 113, switch - K, power supply - S. DETAILED DESCRIPTION
[0027] In order to make the purpose, advantages and features of the present application clearer, a SRAM circuit structure according to the present application is further described below in combination with the drawings. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to conveniently and clearly assist the purpose of describing the embodiments of the present application.
[0028] In the description of the present application, the terms "first", "second", and the like are added for the convenience of description and reference, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features with "first", "second", and the like are explicitly or implicitly included one or more of the features.
[0029] As shown in Figure 1 and Figure 2 , the present embodiment provides a SRAM circuit structure, which comprises a SRAM unit, a heating element (including R1-R4) and a temperature control unit 11; the temperature control unit 11 comprises a temperature sensor 111, an analog-to-digital converter 112, a processor 113, a switch K and a power supply S; the temperature sensor 111 is connected with the SRAM unit or the heating element; the processor 113 is connected with the SRAM unit, the analog-to-digital converter 112 and the switch K respectively; the switch K, the power supply S and the heating element form a series loop; the heating element is arranged inside or outside the SRAM unit; the temperature sensor 111 sends the detected temperature to the processor 113 through the analog-to-digital converter 112; the processor 113 is used to judge the working state of the SRAM unit, and adjusts the state of the switch K according to the working state of the SRAM unit and the temperature detected by the temperature sensor 111, so that the temperature detected by the temperature sensor 111 is less than a preset temperature.
[0030] The processor 113 can determine the working state of the SRAM unit according to the voltage on the word line WL of the SRAM unit. When the voltage on the word line WL is low, it indicates that the SRAM unit is in the holding mode. When the voltage on the word line WL is high, it indicates that the SRAM unit is in the read-write mode. The analog-to-digital converter 112 can convert the analog quantity output by the temperature sensor 111 into a digital quantity and then send it to the processor 113. The preset temperature can be set according to the material of the SRAM unit, for example, 80℃. If the temperature is too high, the SRAM unit will be burned out. If the temperature is too low, the purpose of reducing the power consumption of the SRAM unit cannot be achieved. Figure 3 The power consumption comparison diagram before and after the improvement of the 6T SRAM when reading and writing 1-bit data is shown in FIG. 6. Figure 3 It can be seen that the improved 6T SRAM can significantly reduce the power consumption in the read-write mode.
[0031] The embodiment provides an SRAM circuit structure, which comprises an SRAM unit, a heating element and a temperature control unit 11. The temperature control unit 11 comprises a temperature sensor 111, an analog-to-digital converter 112, a processor 113, a switch K and a power supply S. The processor 113 can determine the working state of the SRAM unit. The temperature sensor 111 can monitor the temperature of the SRAM unit or the heating element in real time. When the SRAM unit is in the read-write mode and the temperature detected by the temperature sensor 111 is less than the preset temperature, the processor 113 controls the switch K to be closed, the power supply S provides current to the heating element, and the heating element generates heat. Under the combined action of the heat generated by the heating element and the heat generated by the self-heating effect of the SRAM unit, the conductivity of the transistor in the SRAM unit is significantly improved. The voltage applied to the SRAM unit for read-write operation can be significantly reduced, thereby reducing the power consumption of the SRAM unit in the read-write mode. When the SRAM unit is in the holding mode, the processor 113 controls the switch K to be opened, and the power supply S does not provide current to the heating element, so that the heating element does not generate heat. At this time, the power consumption of the power supply S can be reduced.
[0032] Preferably, the heating element is arranged in the SRAM unit; the SRAM unit comprises a plurality of N-channel metal-oxide-semiconductor (NMOS) tubes, and at least one of the NMOS tubes is internally provided with the heating element. The volume of the NMOS tube in the SRAM unit is generally larger than that of the P-channel metal-oxide-semiconductor (PMOS) tube. The heating element is integrated in the NMOS tube, which facilitates the implementation of the production process.
[0033] Preferably, the heating element is arranged below the channel of the NMOS tube. There is a space of appropriate size below the channel, i.e. below the gate, and the micro heating element can be embedded in this position.
[0034] Preferably, as shown in Figure 1 each of the heating elements is arranged below the channel of the NMOS tube. Figure 1 The NMOS tube in the SRAM unit includes N1, N2, N3, and N4, and a heating element can be arranged at each of the four positions. The heating element includes R1, R2, R3, and R4. This design can improve the heating efficiency.
[0035] Preferably, as shown in Figure 1 and Figure 2 each of the heating elements corresponds to a temperature control unit 11, and one end of the heating element is connected to the corresponding temperature sensor 111. Each heating element corresponds to a temperature control unit 11, so that the temperature of each heating unit can be monitored in real time by the corresponding temperature sensor 111, and the communication state of each heating unit with the power supply S is adjusted in real time by the corresponding processor 113, so that the temperature of each heating element can be accurately controlled.
[0036] Preferably, as shown in Figure 1 the other end of the heating element is connected to the source or drain of the corresponding NMOS tube. The other end of the heating element in the NMOS tube is connected to the source or drain of the NMOS tube, which can improve the heating efficiency and does not affect the storage function of the SRAM unit.
[0037] Preferably, as shown in Figure 1 the SRAM unit includes a 6T (Transistor, transistor) SRAM, which includes two pull-up PMOS tubes, two pull-down NMOS tubes, and two transmission NMOS tubes. 6T SRAM means that the storage unit includes 6 transistors, and 6T SRAM usually also includes word line WL, bit line BL, bit line BL_bar, working voltage VDD, and ground terminal VSS. The SRAM circuit structure provided in this embodiment can be obtained by adding a heating element and a temperature control unit 11 on the basis of a 6T SRAM. In other embodiments, the SRAM unit can include an 8T SRAM or a 10T SRAM storage unit.
[0038] Preferably, as shown in Figure 2 the power supply S is an adjustable current source. The output of the adjustable current source can be adjusted according to the optimal working temperature of the SRAM unit. When the optimal working temperature of the SRAM unit is high, the current value output by the adjustable current source can be high; when the optimal working temperature of the SRAM unit is low, the current value output by the adjustable current source can be low.
[0039] Preferably, the heating element is an electric resistance heating wire. The electric resistance heating wire can realize fast heating of the SRAM unit.
[0040] Preferably, the heating element is made of a thermoelectric material. The heating element made of the thermoelectric material can realize fast heating of the SRAM unit.
[0041] In summary, the present application provides an SRAM circuit structure, which comprises an SRAM unit, a heating element and a temperature control unit 11. The temperature control unit 11 comprises a temperature sensor 111, an analog-to-digital converter 112, a processor 113, a switch K and a power supply S. The processor 113 can determine the working state of the SRAM unit, and the temperature sensor 111 can monitor the temperature of the SRAM unit or the heating element in real time. When the SRAM unit is in a read-write mode and the temperature detected by the temperature sensor 111 is less than a preset temperature, the processor 113 controls the switch K to be closed, the power supply S provides current to the heating element, and the heating element generates heat. Under the combined action of the heat generated by the heating element and the heat generated by the self-heating effect of the SRAM unit, the conductivity of the transistor in the SRAM unit is significantly improved, the voltage applied to the SRAM unit for read-write operation can be significantly reduced, and thus the power consumption of the SRAM unit in the read-write mode is reduced. When the SRAM unit is in a holding mode, the processor 113 controls the switch K to be opened, and the power supply S does not provide current to the heating element, so that the heating element does not generate heat. At this time, the power consumption of the power supply S can be reduced.
[0042] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or modification made by a person of ordinary skill in the art based on the above disclosure is within the protection scope of the present application.
Claims
1. An SRAM circuit structure, characterized in that: It includes an SRAM unit, a heating element and a temperature control unit; the temperature control unit includes a temperature sensor, an analog-to-digital converter, a processor, a switch and a power supply; The temperature sensor is connected to the SRAM unit or the heating element; The processor is connected to the SRAM unit, the analog-to-digital converter, and the switch respectively; The switch, the power supply and the heating element form a series circuit; The heating element is arranged inside or outside the SRAM unit; The temperature sensor sends the detected temperature to the processor through the analog-to-digital converter; the processor is used to determine the working state of the SRAM unit and adjust the state of the switch according to the working state of the SRAM unit and the temperature detected by the temperature sensor, so that the temperature detected by the temperature sensor is less than a preset temperature.
2. The SRAM circuit structure according to claim 1, wherein: The heating element is arranged inside the SRAM unit; the SRAM unit includes a plurality of NMOS transistors, and a heating element is arranged inside at least one of the NMOS transistors.
3. The SRAM circuit structure according to claim 2, wherein: The heating element is arranged below the channel of the NMOS transistor.
4. The SRAM circuit structure according to claim 2, wherein: A heating element is respectively arranged inside each of the NMOS tubes.
5. The SRAM circuit structure according to claim 4, wherein: Each heating element corresponds to a temperature control unit, and one end of the heating element is connected to the corresponding temperature sensor.
6. The SRAM circuit structure according to claim 5, wherein: The other end of the heating element is connected to the source or drain of the corresponding NMOS tube.
7. The SRAM circuit structure according to claim 1, wherein: The SRAM unit includes a 6T SRAM, and the 6T SRAM includes two pull-up PMOS transistors, two pull-down NMOS transistors, and two transmission NMOS transistors.
8. The SRAM circuit structure according to claim 1, wherein: The power supply is an adjustable current source.
9. The SRAM circuit structure according to claim 1, wherein: The heating element is a resistance heating wire.
10. The SRAM circuit structure according to claim 1, wherein: The heating element is made of thermoelectric material.