Memory device and operating method thereof

Abstract

The invention discloses a memory device and an operating method thereof. A memory device may include: a memory bank including memory cells; a bank buffer connected to the memory cells of the bank through bit lines; and an operation controller. The operation controller may control the bank buffer to store a result of performing a read operation on the memory cell corresponding to the first address in response to a first read command input from an external controller; performing a write operation of storing data in a memory cell corresponding to a second address in response to a write command from an external controller, the memory cell corresponding to the second address and the memory cell corresponding to the first address sharing a bit line; and when a second address corresponding to a second read command after the write operation is performed matches the first address, control the bank buffer to provide the stored result to the external controller as a response to the second read command.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0046653, filed on April 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a memory device and a method of operating the memory device. Background Art

[0004] Memory devices can include volatile memory devices that lose stored data when power is interrupted, and nonvolatile memory devices that retain stored data even when power is interrupted. Each memory cell in the memory device can have a specific logic state depending on the physical / chemical properties of the material forming the memory cell. Memory cells containing chalcogenide materials can have the following characteristics: slower operating speed than dynamic random access memory (DRAM) but greater capacity (integration density) than DRAM, and smaller capacity (integration density) than NAND flash memory but faster operating speed than NAND flash memory. Summary of the Invention

[0005] Various embodiments of the present disclosure are directed to memory devices with extended useful life and methods of operating the same.

[0006] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory bank including memory cells; a memory bank buffer connected to the memory cells of the memory bank via bit lines; and an operation controller configured to control the memory bank buffer to store a result of performing a read operation on a memory cell corresponding to a first address among the memory cells of the memory bank in response to a first read command input from an external controller; perform a write operation to store data in a memory cell corresponding to a second address among the memory cells of the memory bank in response to a write command received from the external controller, the memory cell corresponding to the second address and the memory cell corresponding to the first address sharing a bit line; and when an address corresponding to a second read command input from the external controller after performing the write operation matches the first address, control the memory bank buffer to provide the result of performing the read operation stored in the memory bank buffer to the external controller as a response to the second read command.

[0007] Embodiments of the disclosure can provide a memory device. The memory device can include a memory bank including memory cells each having one of a set state or a reset state, a word line controller configured to control a plurality of word lines connected to the memory cells of the memory bank, a bit line controller including a memory bank buffer connected to the memory cells of the memory bank through a plurality of bit lines, and an operation controller configured to control the memory cells of the memory bank, the word line controller, and the bit line controller in response to a command received from an external controller. The memory bank buffer can include a read buffer including read data latches connected to the plurality of bit lines, respectively, and a write buffer including write data latches commonly connected to the plurality of bit lines with the read data latches.

[0008] Embodiments of the disclosure can provide a method of operating a memory device. The method can include receiving a first read command requesting data stored in a memory cell corresponding to a first address among a plurality of memory cells included in the memory device, in response to the first read command, performing a read operation of sensing the data stored in the memory cell corresponding to the first address, receiving a write command indicating that the data is to be stored in a memory cell corresponding to a second address among the memory cells, the memory cell corresponding to the second address and the memory cell corresponding to the first address sharing a bit line, in response to the write command, performing a write operation of storing the data in the memory cell corresponding to the second address, after the write operation is performed, receiving a second read command requesting the data stored in the memory cell corresponding to the first address, and in response to the second read command, outputting a result of the read operation performed in response to the first read command as a response to the second read command. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a diagram for describing a data storage device including a memory device according to an embodiment of the disclosure.

[0010] Figure 2 is a diagram for describing a data storage device including a memory device according to an embodiment of the disclosure. Figure 1 is a diagram for describing a memory device of

[0011] Figure 3A , Figure 3B and Figure 3C are diagrams for describing voltages applied during a write operation and a read operation of a memory device according to an embodiment of the disclosure.

[0012] Figure 4 is a diagram for describing a data input / output method of a memory device according to an embodiment of the disclosure.

[0013] Figure 5 is a diagram for describing an operation principle of a bank buffer and an operation controller according to an embodiment of the present disclosure.

[0014] Figure 6 is a diagram for describing a read operation according to an embodiment of the present disclosure.

[0015] Figure 7 is a flowchart of a method of operating a memory device according to an embodiment of the present disclosure.

[0016] Figure 8 is a diagram for describing a read operation according to an embodiment of the present disclosure.

[0017] Figure 9 is a flowchart of a method of operating a memory device according to an embodiment of the present disclosure.

[0018] Figure 10 is a diagram illustrating a controller according to an embodiment of the present disclosure.

[0019] Figure 11 is a block diagram illustrating a user system applying a data storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The specific structural or functional descriptions introduced in the present specification of the embodiments of the present disclosure are provided as examples to describe embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be practiced in various forms, and should not be interpreted as being limited to the embodiments described in the present specification.

[0021] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated, so that those skilled in the art to which the present disclosure pertains can easily practice the technical spirit of the present disclosure.

[0022] Figure 1 is a diagram for describing a data storage device including a memory device according to an embodiment of the present disclosure.

[0023] Referring to Figure 1 , the data storage device 50 can include the memory device 100 and the controller 200. The data storage device 50 can be a device that stores data under the control of a host 400 such as a mobile phone, a smart phone, a notebook computer, a laptop computer, a game machine, a smart TV (TV), a tablet PC, or an in-vehicle infotainment system. In an embodiment, the data storage device 50 can be a device that stores data in a remote location such as a server or a data center and is controlled by the host 400 through wired / wireless communication.

[0024] The data storage device 50 can interface with the host 400 through various communication methods, and can be implemented as various devices according to the interface connection method. For example, the data storage device 50 can be implemented as any one of various types of storage devices such as a solid state drive (SSD), an embedded multimedia card (eMMC), a secure digital card of an SD, mini-SD, or micro-SD type, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a high-speed PCI (PCI-E) card-type storage device, a compact flash (CF) card, and a smart media card.

[0025] In an embodiment, the data storage device 50 can be manufactured as any one of various types of package forms. For example, the data storage device 50 can be manufactured as any one of various types of package forms such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and a wafer level package (WSP).

[0026] The memory device 100 can store data. The memory device 100 can operate in response to a control of the controller 200. The memory device 100 can include a plurality of memory cells that store data.

[0027] Each of the memory cells can store one bit of data or a plurality of bits of data.

[0028] The memory cells can be accessed in units of a preset size according to a type of the memory device. The unit of accessing the memory cells can be different for each operation. For example, for a write operation that stores data in each memory cell, a read operation that senses data stored in each memory cell, and an erase operation that erases data stored in each memory cell, the memory cells can be accessed in units of different sizes.

[0029] In an embodiment, the memory device 100 can be a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth generation low power double data rate (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus DRAM (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive RAM (RRAM), a phase change memory (PCM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer torque RAM (STT-RAM).

[0030] Generally, memory cells included in the memory device 100 form an array including memory cells storing data and selectors selecting the memory cells.

[0031] In a DRAM, a capacitor is used as a memory cell, and a transistor is used as a selector. In the case of a NAND flash memory device, a transistor selecting a memory cell in units of strings is used as a selector.

[0032] The memory device 100 can include a single cell including a chalcogenide-based material and two electrodes. In an embodiment, in the memory device 100, the chalcogenide-based material can also be referred to as a dual functional material (DFM). The DFM can have a threshold voltage, as in the case of a bidirectional threshold switch (OTS) material used as a selector in a phase change memory (PCM).

[0033] The DFM is different from the OTS, the threshold voltage of which does not change, whereas the threshold voltage of the DFS can change during a bidirectional write operation. This change allows the DFM to be used as a memory cell, and the DFM can be used as both a memory cell and a selector through a bidirectional write operation. A memory device using the DFM can be a selector-only memory (SOM) device or a self-selecting memory (SSM) device.

[0034] In this specification, it will be described based on the memory device 100 being a kind of phase change memory including a SOM cell, which is a memory cell including a chalcogenide-based material.

[0035] The memory device 100 can receive a command and an address from the controller 200, and can access a region of the array of memory cells selected by the address. The memory device 100 can perform an operation indicated by the command on the region selected by the address. For example, the memory device 100 can perform a write operation (a program operation), a read operation, and an erase operation. During the program operation, the memory device 100 can write data to the region selected by the address. During the read operation, the memory device 100 can sense data from the region selected by the address. During the erase operation, the memory device 100 can erase data stored in the region selected by the address.

[0036] The controller 200 can control the entire operation of the data storage device 50.

[0037] When power is applied to the data storage device 50, the controller 200 can run firmware (FW). The data storage device 50 can convert an address provided by the host 400 to an address used by the memory device 100.

[0038] The controller 200 can control the memory device 100 to perform a write operation, a read operation, or an erase operation in response to a request received from the host 400. During the write operation, the controller 200 can provide a write command, an address, and data to the memory device 100. During the read operation, the controller 200 can provide a read command and an address to the memory device 100. During the erase operation, the controller 200 can provide an erase command and an address to the memory device 100.

[0039] In an embodiment, the controller 200 can independently generate a command, an address, and data regardless of whether a request is received from the host 400, and can transmit the command, the address, and the data to the memory device 100. For example, the controller 200 can control the memory device 100 to perform various background operations to maintain performance of the memory device 100.

[0040] In an embodiment, the controller 200 can include an error correction code (ECC) processor. Alternatively, the ECC processor can be included in the data storage device 50 as a chip or a device separate from the controller 200. The ECC processor can detect and correct errors included in data obtained from the memory device 100 through a read operation. In an embodiment, the number of bits that can be corrected by the ECC processor can be limited.

[0041] Figure 2 is a diagram of a memory device for describing a memory device according to an embodiment of the disclosure. Figure 1

[0042] Referring to Figure 2 , the memory device 100 can include a memory cell array 110, a word line controller 120, a bit line controller 130, an operation controller 140, and an input / output (IO) controller 150. According to an embodiment, the memory device 100 can include a selection controller 160.

[0043] The memory cell array 110 can include memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines. Each memory cell can be connected to one word line and one bit line. In an embodiment, each memory cell can contain a chalcogenide-based dual functional material (DFM). The memory cell can store a logic state according to a physical / chemical characteristic or property of the DFM.

[0044] In an embodiment, the memory cell can be a SOM cell or a self-selecting memory (SSM) cell.

[0045] The memory cell can be in a state corresponding to one of a set state or a reset state. The set state and the reset state can have opposite polarities.

[0046] ​In an embodiment, the set state can represent a logic "0" and the reset state can represent a logic "1". Alternatively, conversely, the set state can represent a logic "1" and the reset state can represent a logic "0".

[0047] The logic state of the memory cell can be detected through a read operation. The logic state of the memory cell can be based on a polarity of a voltage applied to the DFM forming the memory cell. In an embodiment, the logic state of the memory cell can be based at least in part on a direction of a current applied to the memory cell during a write operation or a polarity of a voltage applied to the memory cell.

[0048] In this specification, for convenience of description, the set state can be defined as a logic "1" state storing data "1", and the reset state can be defined as a logic "0" state storing data "0".

[0049] In an embodiment, the threshold voltage of the memory cell in the set state can be higher than the threshold voltage of the memory cell in the reset state.

[0050] The word line controller 120 can provide a word line voltage to the memory cells included in the memory cell array 110 through a plurality of word lines WL1 to WL M The word line controller 120 can provide a word line voltage to the memory cells included in the memory cell array 110 through a plurality of word lines WL1 to WL

[0051] The bit line controller 130 can provide a bit line voltage to the memory cells included in the memory cell array 110 through a plurality of bit lines BL1 to BL N The bit line controller 130 can provide a bit line voltage to the memory cells included in the memory cell array 110 through a plurality of bit lines BL1 to BL

[0052] In one embodiment, the bit line controller 130 can include a sense amplifier (Sense AMP) that senses data stored in the memory cell through the bit line. In addition, the bit line controller 130 can include a latch that stores the sensed data.

[0053] The operation controller 140 can control the word line controller 120 and the bit line controller 130 so that an operation can be performed on the memory cell array. Each of the word line controller 120 and the bit line controller 130 can provide a voltage to the memory cell array under the control of the operation controller 140.

[0054] The IO controller 150 can perform data communication with the controller 200 described with reference to Figure 1 In detail, the IO controller 150 can receive a command, an address, or data from the controller 200 and transmit data stored in the memory cell or the internal register to the controller 200.

[0055] The selection controller 160 can select a memory cell to be accessed through a plurality of selection lines SL1 to SL NControl signals for selecting a memory cell are provided. In the case of a memory cell using a DFM, a separate control signal for selection can not be required, but according to an embodiment, the memory device 100 can be configured to provide a selection signal for selecting a memory cell. According to an embodiment, the selection controller 160 can be omitted.

[0056] Figure 3A 、 Figure 3B and Figure 3C are graphs for describing voltages applied during a write operation and a read operation of a memory device according to an embodiment of the disclosure.

[0057] Figure 3A is a graph illustrating voltages applied to a word line and a bit line connected to each memory cell during a write operation in a write set state. Figure 3B is a graph illustrating voltages applied to a word line and a bit line connected to a memory cell during a write operation in a write reset state. Figure 3C is a graph illustrating voltages applied to a word line and a bit line connected to a memory cell during a read operation of sensing a write state of the memory cell, that is, reading data stored in the memory cell.

[0058] To write a set state (that is, to write data "0") to a memory cell, referring to Figure 2 The operation controller 140 can control the bit line controller 130 and the word line controller 120 to apply a positive voltage to the bit line and a negative voltage to the word line during a time period of a period t1 to t2, respectively. Here, the potential applied between the bit line and the word line can be a write voltage Vwrite. The write voltage Vwrite can have a voltage level capable of turning on the memory cell.

[0059] To write a reset state (that is, to write data "1") to a memory cell, referring to Figure 2 The operation controller 140 can control the bit line controller 130 and the word line controller 120 to apply a negative voltage to the bit line and a positive voltage to the word line during a time period of a period t3 to t4, respectively. Here, the potential applied between the bit line and the word line can be a write voltage Vwrite. The write voltage Vwrite can have a voltage level capable of turning on the memory cell.

[0060] In an embodiment, the voltage applied to the word line and the bit line to write a set state to the memory cell and the voltage applied to the word line and the bit line to write a reset state to the memory cell can have the same magnitude and different polarities.

[0061] During a read operation, referring to Figure 2The described operation controller 140 can apply the same voltage regardless of the logic state of the memory cell. In detail, the operation controller 140 can control the bit line controller 130 and the word line controller 120 to apply a negative voltage to the bit line and a positive voltage to the word line during the time period of t5 to t6, respectively. The voltage level of a read voltage Vread, which is the voltage applied during the read operation, can be lower than the voltage level of the write voltage Vwrite. Table 1 below shows the sensing result based on the polarity of the read voltage Vread applied during the read operation and the logic state of the memory cell.

[0062] Table 1

[0063]

[0064] After the read voltage is applied, the sensing AMP included in the bit line controller 130 can sense the state of the memory cell. When the memory cell is in the set state, as a result of performing the read operation, the result of sensing the memory cell can indicate that the memory cell is detected as an on cell. The memory cell as the on cell indicates that it is turned on according to the read voltage, and can be identified as a state of logic "1". When the memory cell is in the reset state, as a result of performing the read operation, the result of sensing the memory cell can indicate that the memory cell is detected as an off cell. The memory cell as the off cell indicates that it is turned off according to the read voltage, and can be identified as a state of logic "0".

[0065] Figure 4 is a diagram for describing a data input / output method of a memory device according to an embodiment of the disclosure.

[0066] Referring to Figure 4 , referring to Figure 2 The memory cell array 110 included in the described memory device 100 can include a first bank Bank 1 and a second bank Bank 2. Each bank can include a plurality of memory cells. The memory cell array 110 can be divided in units of banks. Although Figure 4 Although it is shown that the memory cell array 110 is divided into two banks, the number of banks included in the memory device 100 can be two or more. For example, the memory device 100 can include a memory cell array 110 formed of four or eight banks.

[0067] Each bank can be a unit capable of independently performing an operation. Each bank can also be referred to as a plane. Here, the term "unit capable of independently performing an operation" can mean a unit capable of simultaneously performing a write operation, a read operation, and an erase operation.

[0068] The bit line controller 130 can include a bank buffer provided for each bank. In detail, the memory cells included in the first bank Bank 1 can be connected to the first bank buffer Bank Buffer 1 through the respective bit lines connected thereto. In the same manner, the memory cells included in the second bank Bank 2 can be connected to the second bank buffer Bank Buffer 2 through the respective bit lines connected thereto.

[0069] The memory cells connected to the first bank buffer Bank Buffer 1 and the memory cells connected to the second bank buffer Bank Buffer 2 can independently perform operations. For example, the memory cells connected to the first bank buffer Bank Buffer 1 can perform a write operation, and the memory cells connected to the second bank buffer Bank Buffer 2 can perform a read operation. Alternatively, even if the same type of operation is performed, the first bank buffer Bank Buffer 1 and the second bank buffer Bank Buffer 2 can respectively perform operations on cells corresponding to different addresses.

[0070] Each of the first bank buffer Bank Buffer 1 and the second bank buffer Bank Buffer 2 can temporarily store data to be stored in the memory cells, or can temporarily store data sensed from the memory cells during a read operation. In detail, each of the first bank buffer Bank Buffer 1 and the second bank buffer Bank Buffer 2 can be connected to the respective memory cells through the bit lines, and can include a latch configured to latch data sensed from the connected memory cells, or a latch configured to temporarily store data to be stored in the memory cells.

[0071] The I / O controller 150 can provide data received from the controller 200 described above to the first bank buffer Bank Buffer 1 and the second bank buffer Bank Buffer 2. Alternatively, the I / O controller 150 can transfer data received from the first bank buffer Bank Buffer 1 and the second bank buffer Bank Buffer 2 to the controller 200, in the opposite direction. Figure 1 The I / O controller 150 can provide data received from the controller 200 described above to the first bank buffer Bank Buffer 1 and the second bank buffer Bank Buffer 2. Alternatively, the I / O controller 150 can transfer data received from the first bank buffer Bank Buffer 1 and the second bank buffer Bank Buffer 2 to the controller 200, in the opposite direction.

[0072] In the same manner as independently operating the first bank buffer Bank Buffer 1 131-1 and the second bank buffer Bank Buffer 2 131-2, the I / O controller 150 can provide data received from the second bank buffer Bank Buffer 2 to the controller 200 in a case where data is provided to the first bank buffer Bank Buffer 1. Alternatively, conversely, the I / O controller 150 can provide data received from the first bank buffer Bank Buffer 1 to the controller 200 in a case where data is provided to the second bank buffer Bank Buffer 2.

[0073] Figure 5 is a diagram for describing the operation principle of a bank buffer and an operation controller according to an embodiment of the disclosure.

[0074] Referring to Figure 2 , Figure 4 and Figure 5 , the first word line, the second word line, and the third word line can be connected to respective memory cells included in the first bank. Memory cells connected to the same word line can form one page. A write operation of storing data in the memory cells and a read operation of sensing (acquiring) data stored in the memory cells can be performed in units of a page.

[0075] Memory cells connected to different word lines can be commonly connected to the same bit line. Accordingly, when one page is selected and a write operation or a read operation is performed on the page, another page cannot be simultaneously selected or an operation cannot be performed on the other page.

[0076] The first bank buffer 131-1 can include a plurality of write data latches and a plurality of read data latches. Each bit line can be commonly connected to one respective write data latch and one respective read data latch. The write data latch can be used during a write operation of storing data in the memory cells connected to the bit line. The read data latch can be used during a read operation of sensing data stored in the memory cells.

[0077] In detail, during a write operation, each of the memory cells can be written to have one of a set state or a reset state based on data stored in a plurality of write data latches. During a read operation, data sensed from the corresponding memory cells can be stored in a plurality of read data latches based on voltages applied to the word line and the bit line.

[0078] Since it is not possible to perform an operation on two or more pages at the same time, the plurality of write data latches and the plurality of read data latches included in the bank buffer can always have data to be stored during a last write operation and result data of a last read operation.

[0079] According to embodiments of the disclosure, a memory cell including a chalcogenide-based DFM can have weaknesses related to reliability such as cycle endurance, read disturb, drift, retention, etc. In particular, unlike other memory elements, in the case of a memory cell including a chalcogenide-based DFM, read stress affects the lifespan of the memory cell rather than the integrity of the data. That is, the number of read operations that can be performed can be limited.

[0080] In more detail, the number of read operations that can be performed over the lifespan of the memory device can be limited in the set state and the reset state. In particular, in the case of the reset state, since the time tRC between read operations performed on the same memory cell is short, stress caused by the effects of read disturb can increase.

[0081] Accordingly, there is a need for an algorithm to prevent repeated read operations on the same memory cell in a short period of time.

[0082] The operation controller 140 can include a command processor 141 and an address storage device 142.

[0083] The command processor 141 can receive a command from an external controller (e.g., the controller 200) and can control the overall operation of the memory device 100 to execute the command.

[0084] In an embodiment, the command processor 141 can determine whether a command received from the external controller is a read command. When the command received from the external controller is a write command, write data received together with the write command can be stored in a write data latch Write Data Latch of the first memory bank buffer 131-1. Hereinafter, the command processor 141 can perform a write operation based on data stored in the write data latch Write Data Latch such that a write target memory cell has one of a set state or a reset state.

[0085] When the received command is a read command, the command processor 141 can determine whether a read address received together with the read command is identical to an address stored in the address storage 142.

[0086] When the received read address is not identical to the address stored in the address storage 142, a read operation of sensing data stored in a memory cell corresponding to the received read address can be performed.

[0087] If the read operation is performed, data stored in a memory cell corresponding to the received read address can be stored in a read data latch Read Data Latch. When the read operation is completed, the command processor 141 can store an address for which the read operation has been performed in the address storage 142. Accordingly, an address for which the read operation has been completed can be stored in the address storage 142. The read data latch Read Data Latch can retain data sensed from the address stored in the address storage 142.

[0088] When the received read address is identical to the address stored in the address storage 142, a result of a previously performed read operation can be used. In this case, the command processor 141 can provide data already stored in the read data latch Read Data Latch as a response to the received read command without performing a read operation.

[0089] In various embodiments, the command processor 141 can store an address for which a write operation has been performed in the address storage 142 even during a write operation, not a read operation. Accordingly, an address for which the write operation has been completed can be stored in the address storage 142. The write data latch Write Data Latch can retain data stored in a memory cell corresponding to the address for which the write operation has been performed.

[0090] If a read command for the same address is received after the write operation is performed, the data received during the previously performed write operation can be used. In this case, the command processor 141 can provide the data stored in the write data latch as a response to the received read command without performing the read operation.

[0091] Figure 6 is a diagram for describing a read operation according to an embodiment of the disclosure.

[0092] Referring to Figure 6 , a command sequence received from a controller when each command is performed and data stored in a read buffer and a write buffer included in a bank buffer are shown. The write buffer can include write data latches Write Data Latch connected to respective bit lines. The read buffer can include read data latches Read Data Latch connected to respective bit lines.

[0093] In Figure 6 , the memory device receives commands from an external controller (e.g., the controller 200) in the order of a first command CMD1, a second command CMD2, a third command CMD3, and a fourth command CMD4, and a page X, a page Y, and a page Z all belong to the same bank. That is, memory cells belonging to the page X, the page Y, and the page Z are connected to different word lines, respectively. In addition, some of the memory cells belonging to the page X, the page Y, and the page Z can be commonly connected to the same bit line, thereby sharing the write buffer and the read buffer.

[0094] The first command CMD1 can be a read command requesting data stored in the page X. In this case, the write buffer can be empty, and page X data Px1 to Px8, which are results of sensing data stored in the page X, can be stored in the read buffer. The memory device can store an address of the page X for which the read operation is completed.

[0095] The second command CMD2 can be a write command instructing to store data in the page Y.

[0096] The bank buffer can include a write buffer and a read buffer separately provided. During a write operation, data stored in the read buffer can be maintained. During a read operation, data stored in the write buffer can be maintained. Accordingly, the page X data Px1 to Px8, which are data of the page X for which the read operation is performed in response to the first command CMD1, can be maintained to be stored in the read buffer.

[0097] The page Y data Py1 to Py8 of the data to be stored in the page Y in response to the second command CMD2 can be stored in the write buffer. From the stored data, the logical state of the memory cell included in the page Y as a write target memory cell can be determined. The memory device can perform a write operation on the page Y.

[0098] The third command CMD3 can be a read command requesting data stored in the page X. The memory device can check that the input third command CMD3 is not a write command but a read command for the same address as the page X, which is the address for which the previous read operation has been completed. The memory device can provide the page X data Px1 to Px8 stored in the read buffer as a response to the third command CMD3, instead of performing a read operation on the page X in response to the third command CMD3. Since the third command CMD3 is a read command, the page Y data Py1 to Py8 stored in the write buffer can be maintained.

[0099] The fourth command CMD4 can be a read command requesting data stored in the page Z.

[0100] The memory device can check that the input fourth command CMD4 is not a write command but a read command for the page Z different from the page X corresponding to the address for which the previous read operation has been completed. The memory device can discard the page X data Px1 to Px8 stored in the read buffer in order to perform a read operation on the page Z (refer to "Release page X data" in Figure 6 The memory device can perform a read operation on the page Z and the page Z data Pz1 to Pz8 can be stored in the read buffer as a result of sensing data stored in the page Z. The memory device can store the address of the page Z for which the read operation has been completed. Since the fourth command CMD4 is a read command, the page Y data Py1 to Py8 stored in the write buffer can be maintained.

[0101] Figure 7 is a flowchart for describing a method of operating a memory device according to an embodiment of the disclosure.

[0102] Referring to Figure 7 In operation S701, the memory device can receive a command from a controller.

[0103] In operation S703, the memory device can determine whether the received command is a read command. When the received command is a read command, the memory device can proceed to operation S707, and when the received command is a write command rather than a read command, the memory device can proceed to operation S705.

[0104] In operation S705, the memory device can perform a write operation in response to the received write command. In detail, the memory device can store write data input together with the write command in a write buffer included in the bank buffer. The write buffer can include a write data latch connected to each bit line. From the data stored in the write data latch, a logic state of a write target memory cell can be determined. The memory device can perform a write operation to write the determined logic state of the write target memory cell.

[0105] In operation S707, the memory device can determine whether the address received with the input read command is the same as the address for which the previous read operation has been performed. When it is determined that the received address is not the same as the previous address, the memory device can perform operations S709 to S713. When it is determined that the received address is the same as the previous address, the memory device can proceed to operation S715.

[0106] In operation S709, the memory device can release the read buffer. In detail, the memory device can discard (or release) data stored in the read buffer included in the bank buffer. The read buffer can include a read data latch connected to each bit line.

[0107] In operation S711, the memory device can perform a read operation on the received address. A negative voltage and a positive voltage can be respectively applied to a word line and a bit line connected to a memory cell corresponding to the received address. When the read voltages are applied, a logic state of the memory cell can be stored in the read data latch connected to the bit line of the memory cell, respectively.

[0108] In operation S713, the memory device can output read data stored in the read data latch to the data controller.

[0109] In operation S715, the memory device can not perform a read operation on the received address. That is, a result of performing a read operation on data stored in a memory cell corresponding to the previous address can already be stored in the read data latch. Accordingly, the memory device can output a response to the read command by completely outputting the data stored in the read data latch without performing a read operation.

[0110] Figure 8 is a diagram for describing a read operation according to an embodiment of the disclosure.

[0111] Referring to Figure 8 , a command sequence received from a controller when each command is executed and data stored in a read buffer and a write buffer included in a bank buffer are shown. The write buffer can include write data latches connected to respective bit lines. The read buffer can include read data latches connected to respective bit lines.

[0112] In Figure 8 , the memory device receives commands from an external controller (e.g., the controller 200) in the order of a first command CMD1, a second command CMD2, a third command CMD3, and a fourth command CMD4, and a page X, a page Y, and a page Z all belong to the same bank. That is, memory cells belonging to the page X, the page Y, and the page Z are connected to different word lines, respectively. In addition, some of the memory cells belonging to the page X, the page Y, and the page Z can be commonly connected to the same bit line, thereby sharing a write buffer and a read buffer.

[0113] The first command CMD1 can be a read command requesting data stored in the page X. In this case, the write buffer can be empty, and page X data Px1 to Px8 as a result of sensing data stored in the page X can be stored in the read buffer. The memory device can store an address of the page X for which the read operation is completed.

[0114] The second command CMD2 can be a write command instructing to store data in the page Y.

[0115] The bank buffer can include a write buffer and a read buffer separately provided. During a write operation, data stored in the read buffer can be maintained. During a read operation, data stored in the write buffer can be maintained. Accordingly, the page X data Px1 to Px8, which are data of the page X for which the read operation is performed in response to the first command CMD1, can be maintained to be stored in the read buffer.

[0116] Page Y data Py1 to Py8 as data to be stored in the page Y in response to the second command CMD2 can be stored in the write buffer. From the stored data, a logical state of a memory cell included in the page Y as a write target memory cell can be determined. The memory device can perform a write operation on the page Y. The memory device can store an address of the page Y for which the write operation is performed.

[0117] The third command CMD3 may be a read command requesting data stored in Page Z. The memory device may check that the input third command CMD3 is not a write command but a read command for an address different from the address of Page X, the address of which a previous read operation has been completed. The memory device may discard Page X data Px1 to Px8 already stored in the read buffer in order to perform a read operation on Page Z (refer to Figure 8 ). Thereafter, the memory device may perform a read operation on Page Z, and Page Z data Pz1 to Pz8 may be stored in the read buffer as a result of sensing the data stored in Page Z. The memory device may store the address of Page Z for which the read operation has been completed. The memory device may output Page Z data Pz1 to Pz8 in response to a third command CMD3. Since the third command CMD3 is a read command, the Page Y data Py1 to Py8 stored in the write buffer may be retained.

[0118] The fourth command CMD4 may be a read command requesting data stored in page Y.

[0119] The memory device may check whether the input fourth command CMD4 is not a write command but a read command for an address different from the address of page Z for which a previous read operation has been completed. Furthermore, the memory device may check whether page Y corresponds to an address for which a previous write operation has been performed. Therefore, the memory device may recognize that the write buffer stores the same data as that stored in page Y.

[0120] The memory device may discard the page Z data Pz1 to Pz8 stored in the read buffer (refer to Figure 8 ” in the “Release Page Z Data”), thereby outputting the Page Y data stored in the write buffer as a result of performing a read operation without performing a read operation on Page Y. Subsequently, the memory device may store the Page Y data Py1 to Py8 stored in the write buffer in the read buffer.

[0121] According to the reference Figure 8 The described embodiment has the following effect: when a read command is received for the same address as data stored in the write buffer and the read buffer, the data can be directly output without performing a read operation.

[0122] Figure 9 is a flowchart for describing a method of operating a memory device according to an embodiment of the present disclosure.

[0123] Reference Figure 9 , in operation S901, the memory device may receive a command from a controller.

[0124] In operation S903, the memory device can determine whether the received command is a read command. When the received command is a read command, the memory device can proceed to operation S907, and when the received command is a write command other than a read command, the memory device can proceed to operation S905.

[0125] In operation S905, the memory device can perform a write operation in response to the received write command. In detail, the memory device can store write data input together with the write command in a write buffer included in the bank buffer. The write buffer can include a write data latch Write Data Latch connected to each bit line. From the data stored in the write data latch Write Data Latch, a logic state of a write target memory cell can be determined. The memory device can perform a write operation to write the determined logic state of the write target memory cell.

[0126] In operation S907, the memory device can determine whether an address received together with the input read command is the same as an address for which a previous read operation has been performed. When it is determined that the received address is not the same as the previous address, the memory device can proceed to operation S911. When it is determined that the received address is the same as the previous address, the memory device can proceed to operation S909.

[0127] In operation S911, the memory device can determine whether an address received together with the input read command is the same as an address for which a previous write operation has been performed. When it is determined that the received address is not the same as the previous address, the memory device can proceed to operation S917. When it is determined that the received address is the same as the previous address, the memory device can proceed to operation S913.

[0128] In operation S913, the memory device can not perform a read operation on the received address. That is, data used during a write operation to store data in a memory cell corresponding to the previous address can have already been stored in the write data latch Write Data Latch. Accordingly, the memory device can output a response to the read command by completely outputting the data stored in the write data latch Write Data Latch without performing a read operation.

[0129] In operation S915, the memory device can transfer the data stored in the write buffer to the read buffer. The write buffer can include write data latches connected to the respective bit lines. The memory device can transfer the data stored in the write data latches to the read data latches and store the received address.

[0130] In operation S917, the memory device can release the read buffer. In detail, the memory device can discard (or release) the data stored in the read buffer included in the bank buffer. The read buffer can include read data latches connected to the respective bit lines.

[0131] In operation S919, the memory device can perform a read operation on the received address. A negative voltage and a positive voltage can be respectively applied to a word line and a bit line connected to a memory cell corresponding to the received address. When the read voltages are applied, the logic state of the memory cell can be stored in the read data latches through the bit lines respectively connected to the memory cell.

[0132] In operation S921, the memory device can output the read data stored in the read data latches to the data controller and store the received address.

[0133] According to the embodiments of the disclosure described with reference to Figures 6 to 9 According to the embodiments of the disclosure described with reference to

[0134] Figure 10 FIG. 1 is a diagram illustrating a memory device according to an embodiment of the disclosure.

[0135] According to the embodiments of the disclosure described with reference to Figure 10, the memory controller 800 may include a processor 810, a random access memory (RAM) 820, an error correction (ECC) circuit 830, a host interface 840, a read-only memory (ROM) 850, and a memory interface 860. The memory controller 800 may correspond to the reference Figure 1 The controller 200 is described.

[0136] The processor 810 may control the overall operations of the memory controller 800. The RAM 820 may be used as a buffer memory, a cache memory, or a working memory of the memory controller 800.

[0137] The ROM 850 may store various types of information required to operate the memory controller 800 in the form of firmware.

[0138] The memory controller 800 may communicate with an external device (eg, the host 400 , an application processor, etc.) through the host interface 840 .

[0139] The memory controller 800 may communicate with the memory device 100 through the memory interface 860. The memory controller 800 may transmit commands CMD, addresses ADDR, control signals CTRL, etc. to the memory device 100 through the memory interface 860 and receive data DATA from the memory device 100.

[0140] Figure 11 is a block diagram illustrating a user system to which the data storage device according to an embodiment of the present disclosure is applied.

[0141] Reference Figure 11 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0142] The application processor 4100 may run components included in the user system 4000, an operating system (OS), or a user program. In embodiments, the application processor 4100 may include a controller, an interface, a graphics engine, and the like for controlling the components included in the user system 4000. The application processor 4100 may be formed as a system on chip (SoC).

[0143] The memory module 4200 can be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 can include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 can be packaged based on a package on package (POP) and then can be disposed as a single semiconductor package.

[0144] The network module 4300 can communicate with an external device. In an embodiment, the network module 4300 can support wireless communication such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMax, WLAN, UWB, Bluetooth, or Wi-Fi. In an embodiment, the network module 4300 can be included in the application processor 4100.

[0145] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transfer data stored in the storage module 4400 to the application processor 4100. In an embodiment, the storage module 4400 can be implemented as a non-volatile semiconductor memory device such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory having a three-dimensional (3D) structure. In an embodiment, the storage module 4400 can correspond to the data storage device 50 described above with reference to FIG. 1. Alternatively, in various embodiments, the storage module 4400 can be disposed as a removable storage medium (removable drive) such as a memory card or an external drive of the user system 4000. Figure 1 The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transfer data stored in the storage module 4400 to the application processor 4100. In an embodiment, the storage module 4400 can be implemented as a non-volatile semiconductor memory device such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory having a three-dimensional (3D) structure. In an embodiment, the storage module 4400 can correspond to the data storage device 50 described above with reference to FIG. 1. Alternatively, in various embodiments, the storage module 4400 can be disposed as a removable storage medium (removable drive) such as a memory card or an external drive of the user system 4000.

[0146] In an embodiment, the storage module 4400 can include a plurality of non-volatile memory devices, each of which can operate in the same manner as the memory device 100 described above with reference to FIG. 1. The storage module 4400 can operate in the same manner as the data storage device 50 described above with reference to FIG. 1. Figure 1 In an embodiment, the storage module 4400 can include a plurality of non-volatile memory devices, each of which can operate in the same manner as the memory device 100 described above with reference to FIG. 1. The storage module 4400 can operate in the same manner as the data storage device 50 described above with reference to FIG. 1. Figure 1 In an embodiment, the storage module 4400 can include a plurality of non-volatile memory devices, each of which can operate in the same manner as the memory device 100 described above with reference to FIG. 1. The storage module 4400 can operate in the same manner as the data storage device 50 described above with reference to FIG. 1.

[0147] The user interface 4500 can include an interface that inputs data or instructions to the application processor 4100 or outputs data to an external device. In an embodiment, the user interface 4500 can include a user input interface such as a keypad, a key button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 can include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0148] Embodiments of the present disclosure can provide a memory device with an extended lifespan and a method of operating the same. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A memory device comprising: a memory bank including memory cells; a bank buffer connected to the memory cells of the bank via bit lines; as well as Operation Controller: controlling the bank buffer to store a result of performing a read operation on a memory cell corresponding to a first address among memory cells of the bank in response to a first read command input from an external controller; performing a write operation of storing data in a memory cell corresponding to a second address among the memory cells of the memory bank in response to a write command received from the external controller, the memory cell corresponding to the second address and the memory cell corresponding to the first address sharing a bit line; and When an address corresponding to a second read command input from the external controller after performing the write operation matches the first address, the memory buffer is controlled to provide the result of the read operation stored in the memory buffer to the external controller as a response to the second read command.

2. The memory device according to claim 1, wherein The memory bank buffer comprises: a read buffer including read data latches respectively connected to the bit lines; and A write buffer includes a write data latch commonly connected to the bit line with the read data latch.

3. The memory device according to claim 2, wherein The operation controller includes: a command processor that processes a command received from the external controller; and The address storage device stores the address at which the read operation is completed.

4. The memory device according to claim 3, wherein The command processor controls the bank buffer to discard data stored in the write buffer in response to the write command.

5. The memory device according to claim 3, wherein When an address corresponding to the second read command does not match the first address, the command processor controls the bank buffer to discard data stored in the read buffer. The memory device according to claim 5 , wherein: The command processor: controlling the read buffer to store a result of a read operation performed on a memory cell corresponding to an address corresponding to the second read command; and An address corresponding to the second read command is stored in the address storage device.

7. The memory device according to claim 3, wherein: When an address corresponding to the second read command matches the first address, the command processor controls the read buffer to output data stored in the read buffer as a response to the second read command.

8. The memory device according to claim 3, wherein The command processor skips a read operation corresponding to the second read command when the address corresponding to the second read command matches the first address.

9. The memory device according to claim 3, wherein: The command processor retains the data stored in the read buffer when the address corresponding to the second read command matches the first address.

10. The memory device according to claim 1, wherein During the read operation, the operation controller: applying a negative voltage to word lines commonly connected to memory cells corresponding to the first address; as well as A positive voltage is applied to the bit line.

11. The memory device according to claim 1, wherein Each of the memory cells in the memory bank includes a chalcogenide-based material.

12. A memory device comprising: a memory bank comprising memory cells, each memory cell having one of a set state or a reset state; a word line controller to control a plurality of word lines connected to the memory cells of the memory bank; a bitline controller including a bank buffer connected to the memory cells of the bank via a plurality of bitlines; as well as an operation controller that controls the memory cells of the memory bank, the word line controller, and the bit line controller in response to a command received from an external controller, Wherein, the memory bank buffer comprises: a read buffer including read data latches respectively connected to the plurality of bit lines; and A write buffer includes a write data latch commonly connected to the plurality of bit lines with the read data latch.

13. The memory device according to claim 12, wherein: During a read operation on a memory cell among the memory cells of the memory bank, the operation controller: applying a negative voltage to word lines commonly connected to memory cells corresponding to a read target address; as well as A positive voltage is applied to the plurality of bit lines.

14. The memory device according to claim 12, wherein: During a write operation of writing the set state into a memory cell among the memory cells, the operation controller: applying a negative voltage to word lines commonly connected to memory cells corresponding to a write target address; as well as A positive voltage is applied to the plurality of bit lines.

15. The memory device according to claim 12, wherein: During a write operation of writing the reset state to a memory cell among the memory cells, the operation controller: applying a positive voltage to word lines commonly connected to memory cells corresponding to a write target address; as well as A negative voltage is applied to the plurality of bit lines.

16. The memory device according to claim 12, wherein: The operation controller includes: a command processor that processes a command received from the external controller; and The address storage device stores the address of the completed read operation.

17. The memory device according to claim 16, wherein: The command processor controls the read buffer: storing a result of performing a read operation on a memory cell corresponding to a first address among the memory cells of the memory bank in response to a first read command input from the external controller; as well as retaining the data stored in the read buffer in a case where a write operation of storing data in a memory cell corresponding to a second address among the memory cells of the memory bank is performed in response to a write command received from the external controller, the memory cell corresponding to the second address and the memory cell corresponding to the first address sharing a bit line, The command processor stores the first address in the address storage device.

18. The memory device according to claim 17, wherein: When an address corresponding to a second read command input after performing the write operation matches the first address, the command processor controls the read buffer to output data stored in the read buffer as a response to the second read command.

19. The memory device according to claim 17, wherein: When an address corresponding to a second read command input after performing the write operation does not match the first address, the command processor: controlling the read buffer to discard data stored in the read buffer; as well as A read operation of sensing data stored at an address corresponding to the second read command is performed.

20. The memory device of claim 12, wherein: Each of the memory cells of the memory bank includes a chalcogenide-based material.

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