EFuse memory and circuit structure thereof
By introducing tracking bit lines and internal clock modes in eFuse memory, the problems of read failure and power waste of unprogrammed memory cells are solved, adaptive internal clock control is achieved, the service life of the memory cells is extended, and circuit design is simplified.
Patent Information
- Application Number
- CN202510890720.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-28
- Publication Date
- 2025-10-17
AI Technical Summary
Existing eFuse memories have the problem of read failure of unprogrammed storage cells, and serious power consumption waste during low-frequency reading. In addition, long-term reading current causes resistance to increase, causing unprogrammed cells to be misread as programmed cells.
A tracking bit line (TKBL) is introduced into the eFuse memory to generate an internal clock pattern through the tracking bit line. Combining the tracking unit and the load unit, adaptive internal clock width adjustment is achieved, which reduces the read time and power consumption and avoids the use of resistor and capacitor delay modules.
Adaptive internal clock control is achieved under different process angles and bit line load conditions, which reduces read power consumption, extends the service life of the memory cell, and simplifies the circuit design process.
Smart Images
Figure CN120808848A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to an eFuse memory and a circuit structure thereof. BACKGROUND
[0002] The eFuse memory is an embedded non-volatile memory, and the data '1' is written by fusing a resistor in a storage unit through a large current (generally in the order of mA).
[0003] The data reading module of the eFuse memory is generally composed of a current mirror type sensitive amplifier (SA). As shown in Figure 1 Figure 1 is a full clock reading waveform diagram, that is, the current waveform of one reading period. The current mirror in the SA applies a reading current to each bit line (BL). The unprogrammed storage unit has a low voltage division on the BL, and the programmed storage unit has a high voltage division on the BL. Finally, the data '0' or '1' is read out by the SA through a judgment module. The reading speed of the data '0' is fast, and the reading speed of the data '1' is relatively slow due to the need to charge the BL. The specific reading speed depends on the device performance of the process platform, the material and morphology of the resistance wire, the size of the reference current, the capacitance of the bit line and other conditions. Generally, the reading can be completed in the order of about 10ns.
[0004] The eFuse memory does not need high-frequency reading when applied at the chip level, and is often applied at a frequency of about 10MHz or lower. The width of the external clock period is more than 100ns. If the enable signal of the SA is synchronized with the width of the external clock, the time after the data '1' is read out is wasted for the data reading operation. For a 32-bit or even higher bit width output eFuse memory, the average current of the sensitive amplifier when turned on can reach the order of 10mA. In power-sensitive applications, these wasted reading power consumptions are very detrimental to the customer's application. In addition, although the reading current flowing through the resistance wire is not large during the reading operation, the accumulated current for a long time also causes the resistance to increase due to the effect of electromigration, which eventually leads to the misreading of the data '1' of the unprogrammed storage unit. This failure is irreversible.
[0005] It should be noted that the information disclosed in the background section of the present application is only intended to deepen the understanding of the general background of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. SUMMARY
[0006] The purpose of the present application is to provide an eFuse memory and a circuit structure thereof to solve the problem of reading failure of unprogrammed storage units in the existing eFuse memory.
[0007] To solve the above technical problems, the present application provides an eFuse memory circuit structure, comprising:
[0008] a plurality of first storage units, each of the first storage units comprising a first transistor and a first fuse resistor, the drain of the first transistor being connected to one end of the first fuse resistor, the source of the first transistor being grounded, the gate of the first transistor being connected to a first word line, the other end of the first fuse resistor being connected to a first bit line, and the first word line being connected to a first sensitive amplifier;
[0009] a column of second storage units connected to a tracking bit line, the second storage units comprising a load unit and at least one tracking unit, the tracking unit comprising a second transistor and a second fuse resistor, the load unit comprising a third transistor and a third fuse resistor, the drain of the second transistor being connected to one end of the second fuse resistor, the other end of the second fuse resistor being connected to the tracking bit line, the tracking bit line being connected to a tracking sensitive amplifier, the gate of the third transistor being grounded, the drain of the third transistor being connected to one end of the third fuse resistor, the other end of the third fuse resistor being connected to the tracking bit line, and the gate of the second transistor being connected to a tracking word line.
[0010] Preferably, the second fuse resistor in the tracking unit is a large-value tracking resistor, the resistance value of which is between the upper limit of the determination resistor for reading '1' data and the statistical lower limit of the actual fuse resistor after programming.
[0011] Preferably, the eFuse memory circuit structure further comprises:
[0012] In the read mode, the rising edge of the enable signal of the data reading module is triggered by the rising edge of the external clock, the falling edge of the enable signal of the data reading module is controlled by the internal signal, and the width of the internal clock can be different from that of the external clock, the data reading can be completed and the data reading module can be turned off before the external clock ends.
[0013] Preferably, the width of the internal clock is determined by the feedback signal generated by the tracking bit line.
[0014] Preferably, the load unit comprises a plurality of third transistors and a plurality of third fuse resistors.
[0015] Preferably, the gate of the second transistor of part of the load units is connected to a test word line, and in the test mode, the selected load units are tested and programmed and read as unit-width data test operations.
[0016] Preferably, one tracking unit is connected to the tracking bit line.
[0017] Preferably, at least two or more tracking units are connected to the tracking bit line, and the resistance values of the second fuse resistors are different to adjust the width of the internal clock.
[0018] Preferably, further comprising:
[0019] The internal clock control module receives the rising edge of the clock to generate the rising edge of the sense amplifier enable signal, tracks the sense amplifier to charge the tracking bit line and finally read out the '1' signal, and generates a feedback signal back to the internal clock control module to generate the falling edge of the sense amplifier enable signal to turn off all the sense amplifiers.
[0020] Based on the same inventive idea, the application also provides an eFuse memory comprising the eFuse memory circuit structure.
[0021] Compared with the prior art, the eFuse memory circuit structure has the following advantages:
[0022] The application introduces a tracking bit line by adding a column of second storage units connected to the tracking bit line in the eFuse memory, realizes the internal clock mode of read operation, and compared with the internal clock mode generated by fixed resistance and capacitance, the tracking bit line technology can cover the influence of different bit line loads, different process angles, etc. on the width of the internal clock, simplifies the design process of the circuit and layout, while ensuring the reliability of the data readout of all output bits at the end of the internal clock, the width of the internal clock generated by the tracking bit line is shorter, which can greatly reduce the data readout power consumption and prolong the readout number of the storage unit. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 is a full clock read waveform schematic diagram;
[0024] Figure 2 is a waveform schematic diagram of the RC delay circuit generating the internal clock;
[0025] Figure 3 is a schematic diagram of the ARRAY introducing the TKBL in an embodiment of the application;
[0026] Figure 4 is a waveform of the BL charging voltage corresponding to different fuse resistances in an embodiment of the application;
[0027] Figure 5 is a waveform schematic diagram of the TKBL feedback control internal clock in an embodiment of the application;
[0028] Figure 6 is a TKBL schematic diagram with MR mode in an embodiment of the application;
[0029] Figure 7 is a waveform schematic diagram of the TKBL feedback internal clock in an embodiment of the application with MR mode;
[0030] Figure 8 is a schematic diagram of a TKBL with TR function in an embodiment of the present application;
[0031] In the figure,
[0032] 100 - first storage unit; 110 - first fuse resistor;
[0033] 120 - first transistor; 200 - tracking unit;
[0034] 210 - second fuse resistor; 220 - second transistor;
[0035] 300 - load unit. DETAILED DESCRIPTION
[0036] To make the objects, advantages and features of the present application clearer, the eFuse memory and its circuit structure according to the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and all use non-precise proportions, only to facilitate, clearly assist the purpose of explaining the embodiments of the present application. It should be understood that the drawings of the specification do not necessarily show the specific structure of the present application in proportion, and the illustrative features used to illustrate some principles of the present application in the drawings will also be slightly simplified. The specific design features of the present application disclosed herein include, for example, specific sizes, directions, positions and shapes, which will be determined in part by the specific application and use environment to be applied and used. In the following described embodiments, sometimes the same reference signs are used between different drawings to represent the same parts or parts with the same function, and the repeated description is omitted. In this specification, similar reference signs and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0037] In addition, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.
[0038] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.
[0039] To solve the problem of reading failure of unprogrammed storage units in eFuse memory, the current common technology is to generate a delay of about 10 ns by a resistance-capacitance delay module, and use this fixed delay as the internal clock of the memory to turn off the sensitive amplifier module. However, this method has some disadvantages. Since the word line selection tube in each storage unit is large in size, the bit line load capacitance of a large-capacity memory is huge, and there is a long time to charge the bit line during reading operation, but the bit line load capacitance of a small-capacity memory is small, and the reading operation can be completed in a very short time, so different delay times are required for eFuse memories of different capacities. Moreover, as the mature process node enters the advanced process node, the size of the delay module is not as small as other modules, resulting in a larger proportion of the layout of the entire layout. In addition, the delay time generated by the commonly used small drive tube with large load delay circuit is easily affected by process fluctuations, operating voltage, temperature and other factors, such as Figure 2 , as shown in Figure 2 is a waveform diagram of the internal clock generated by the RC delay circuit. In order to ensure that the internal clock of sufficient width can be generated in different process corners to ensure the read margin, the internal clock corresponding to the chip of the process corner that is too slow is too slow, resulting in wasted power consumption and the influence of read current on the fuse during the read period.
[0040] The core idea of the present application is to provide an eFuse memory circuit structure, which can solve the problem of reading failure of unprogrammed storage units in eFuse memory, and also avoid the significant increase in layout area of the introduced internal clock control circuit, and prolong the service life of the eFuse memory.
[0041] To achieve the above idea, the present application provides an eFuse memory circuit structure, which is described in detail as follows. Figures 3 to 8One embodiment of an eFuse memory circuit structure is disclosed. The eFuse memory circuit structure includes a plurality of first memory cells 100, each of the first memory cells 100 including a first transistor 120 and a first fuse resistor 110, a drain of the first transistor 120 connected to one end of the first fuse resistor 110, a source of the first transistor 120 connected to ground, a gate of the first transistor 120 connected to a first word line, and the other end of the first fuse resistor 110 connected to a first bit line (BL). A plurality of second memory cells connected to a tracking bit line (TKBL) includes a load cell 300 and at least one tracking cell 200, the tracking cell 200 including a second transistor 220 and a second fuse resistor 210, the load cell 300 including a third transistor and a third fuse resistor, a drain of the second transistor connected to one end of the second fuse resistor 210, the other end of the second fuse resistor 210 connected to the tracking bit line, the tracking bit line connected to a tracking sense amplifier (TKSA), a gate of the third transistor connected to ground, a drain of the third transistor connected to one end of the third fuse resistor, the other end of the third fuse resistor connected to the tracking bit line, and a gate of the second transistor connected to a tracking word line (TKWL).
[0042] Referring to Figure 3 As shown, the plurality of first memory cells 100 form a memory cell array (ARRAY). The memory cell array includes n columns of normal BLs and x rows of normal WLs, x and n being positive integers, a plurality of first transistors 120, and a plurality of first fuse resistors 110. The first transistors 120 include NMOS transistors. A plurality of second memory cells is added to the memory cell array (ARRAY) and connected to a tracking bit line (or a copy bit line, hereinafter referred to as TKBL). The second memory cells connected to the TKBL have the same circuit structure and layout environment as the memory cells in the memory cell array, and thus the TKBL has the same load and parasitic resistance and capacitance as the BL. The TKBL can well simulate the charging process of the BL during a read operation.
[0043] The storage unit mounted on the TKBL is divided into a load unit 300 (DMBC) and a tracking unit 200 (TKBC) simulating the behavior of the fuse after burning. The tracking unit 200 includes a second transistor 220 and a second fuse resistor 210, and the load unit 300 includes a third transistor and a third fuse resistor. The drain of the second transistor is connected to one end of the second fuse resistor 210, the other end of the second fuse resistor 210 is connected to the tracking bit line, the tracking bit line is connected to the tracking sense amplifier (TKSA), the gate of the third transistor is grounded, the drain of the third transistor is connected to one end of the third fuse resistor, the other end of the third fuse resistor is connected to the tracking bit line, and the gate of the second transistor is connected to the tracking word line (TKWL). The second transistor 220 and the third transistor each include an NMOS transistor. The selection word line of the DMBC is grounded or pulled down to avoid affecting the charging of the TKBL when the same row WL is turned on. The TKBC is located farthest from the read module in the TKBL, and at this time the charging path of the TKBL is full load, which can simulate the charging process of the row farthest from the read module in the ARRAY during the read operation. The selection word line of the TKBC is connected to the TKWL, and in the mode of reading period and enabling internal clock, the TKBC is synchronously selected with the first storage unit 100. Since the eFuse memory switches the WL with the address in the read period and is not triggered by the external clock, the TKWL can be set to a constant open state.
[0044] Further comprising: in the read mode, the rising edge of the enable signal of the data read module is triggered by the rising edge of the external clock, the falling edge of the enable signal of the data read module is controlled by the internal signal, and the width of the enable signal of the data read module can be not the same as that of the external clock, and the data read can be completed and the data read module can be turned off before the external clock ends. The width of the internal clock is determined by the feedback signal generated by the tracking bit line. The read module connected to the TKBL is the same sense amplifier (SA) as the normal read module. After the rising edge of the external clock in the read period is input, the control module (SACTL) of the internal clock generates the rising edge of the SA enable signal (SAEN) to turn on a whole row of SA modules and start charging the normal BL through the output current of the current mirror. The voltage change during the charging of the BL is related to the output current of the current mirror, the BL load, the parasitic capacitance resistance, and the resistance of the fuse. Referring to the formula, the output current of the current mirror is related to the width of the internal clock. The width of the internal clock is determined by the feedback signal generated by the tracking bit line. Figure 4 As shown, Figure 4For the case of fixed read current and BL load, the effect of different fuse resistance on the BL charging speed is shown. For the unprogrammed '0' memory cell, the fuse resistance is in the range of 10-100 ohms (related to the fuse material and size), and the BL reaches the target voltage and keeps constant after a short charging process. The voltage is the product of the current mirror output current and the fuse resistance, which is lower than the threshold voltage for the SA read '1', so the output is '0'. For the programmed '1' memory cell, the fuse resistance is usually in the range of mega-ohms, and the lower limit of the statistical significance is in the range of 100,000 ohms. For the fuse resistance in this range, the current through the fuse and the WL gate to the ground is almost 0, so the BL is in the linear charging state with the constant current from the current mirror, and the voltage time slope is very similar. When the BL voltage approaches the output upper limit of the current mirror, the BL voltage rises gradually to the stable voltage. If the fuse resistance is smaller, about 1,000 ohms, the BL has a small current through the fuse to the ground during the charging process, so the BL voltage rising slope is slower.
[0045] In the actual SA design, the voltage threshold for the BL read '1' is usually designed in the BL linear charging area to ensure that the read '1' window better covers different process windows. Therefore, for a fixed design size of the SA, the read '1' time is only related to the BL load and parasitic capacitance. Since the TKBL can well simulate the BL load and parasitic capacitance, the charging slope of the TKBL during the read operation is also consistent with the BL. For different capacities of the ARRAY, the charging of the TKBL can be kept synchronized with the normal BL. The second fuse resistance 210 in the tracking unit 200 is a large resistance tracking resistance, and the resistance size is between the upper limit of the read '1' data determination resistance and the statistical lower limit of the actual fuse resistance after programming. In actual design, assuming that the measured minimum resistance of the '1' cell after programming is more than 10,000 ohms, the second fuse resistance 210 in the TKBL can be replaced with a resistance in the range of 1,000 ohms to 10,000 ohms, so that the TKBL read '1' charging speed is slightly slower than the BL, leaving a certain margin for the internal clock of the read operation.
[0046] In addition, since the TKBL is generally at the boundary of the memory array, under the effect of the layout parasitic delay, the TKSA connected to the TKBL is finally turned on, ensuring that the TKBL starts charging after all normal BLs start charging. When the voltage rises to the threshold voltage of the TKSA read '1', all other normal BLs corresponding to the SA have completed the read '1' action (the read '0' action is completed earlier), the TKSA generates a feedback signal STEND back to the internal clock control module, and a falling edge of the SAEN is generated through simple logic, so that the SA module of all BLs is turned off, and the output data is locked in the data output module, completing a read cycle, Figure 5The figure shows the waveform of the read cycle after the feedback signal is introduced to control the clock. Compared with the resistor-capacitor delay circuit in the prior art, the internal clock generated by TKBL has smaller fluctuations with the process.
[0047] Depending on the ARRAY capacity, the number of memory cells mounted on the BL can range from as few as 4 to as many as 256. The actual BL charging time to read a '1' varies from 1ns to 50ns (the specific value is determined by the process node). The biggest advantage of generating the internal clock through TKBL is that simply by calling the designed TKBL submodule and placing it next to the ARRAY, adaptive internal clock width adjustment can be achieved. Furthermore, the delay time generated by traditional resistors and capacitors is significantly affected by the device's process corner, which does not match the degree to which the current mirror output current is affected by process corners. To ensure yield and reliability, the design of the internal clock width requires considering different process corner combinations and performing Monte Carlo simulations, which increases the design difficulty. However, with TKBL technology, because all current mirrors and SAs are designed identically and the device process corner offsets are consistent, the internal clock width is theoretically guaranteed to be sufficient but not excessive, reducing design difficulty while increasing design reliability.
[0048] Ginseng Figure 3 and Figure 5 As shown in FIG. 1 , as an example of use, the tracking bit line is connected to a tracking unit 200. The TKBL feedback controls the internal clock waveform.
[0049] Ginseng Figure 6 and Figure 7 As shown, as another example of use, at least two or more tracking units 200 are connected to the tracking bit line, and the resistance values of the second fuse resistor 210 are different to adjust the width of the internal clock. Two or more tracking units 200 can be connected to the tracking bit line, and tracking resistors of different sizes can be connected to adjust the width of the internal clock, which can be used to test and screen out chips with weak data reliability. TKBC can be made into two different resistance levels TKBC0 / TKBC1, and an external input signal MR is added to screen out weak '1' storage cells. When MR='1', TKWL1 selects TKBC1 with a large resistance. As shown Figure 7 As shown, in this mode, the TKBL charging slope is greater, the internal clock time is shorter, and the read '1' condition for normal memory cells is more stringent. After the entire memory is programmed, customers can test the data write accuracy in MR mode. If all read data pass, it can be assumed that all stored '1' data is sufficiently stable. Downstream customers can use the more relaxed read '1' condition to ensure sufficient reliability when reading data normally.
[0050] As another example of use, the gate of the NMOS transistor of the partial load unit is connected to the test word line, and in the test mode, the test burn-in reading is selected to perform the test operation as unit width data. The load unit 300 includes a plurality of third transistors and a plurality of third fuse resistors, and the gate of the third transistor of the partial load unit is connected to the test word line, and in the test mode, the test burn-in reading is selected to perform the test operation as unit width data. The test mode is switched to the external clock reading mode, and the external input signal ETM is added. When ETM=’1’, the feedback signal STEND is disabled, and the falling edge of SAEN is triggered by the falling edge of the external clock. In this mode, the width of SAEN is synchronized with the external clock, and the time of applying the reading current to the storage unit is also synchronized with the external clock. At this time, the time of the external clock is pulled to be long enough, and combined with reliability evaluation tests such as high-temperature operation life (HTOL), the reliability of the stored data under the pressure of long-term reading current can be tested, thereby deducing the read number life of the memory.
[0051] Referring to Figure 8 As a fourth example of use, as shown, since a whole TKBL is introduced to simulate the load of the BL, these storage units as loads can also be used as the first storage unit 100 to read and write data. As shown, Figure 8 As shown, some DMBCs can be selected to connect the WL grounded or pulled down to the selected TRWL controlled by other input signals, so that the column of storage units can be selected to perform unit width reading and writing operations, and the output of TKSA is connected to another output signal TQ. When entering the TR mode, TKWL will no longer open the TKBC to discharge the BL, and STEND will no longer feedback the end signal of SAEN, and the memory will work in the external clock mode. When using the eFuse memory for the first time, if the voltage, time and other conditions of burn-in are not familiar, the test burn-in and reading of these storage units can be selected to determine the appropriate machine burn-in conditions, and at the same time, the capacity of normal storage units will not be wasted. In addition, some short data can also be stored in these storage units, including but not limited to chip number, production time, encryption key, module function enable / disable and other information.
[0052] The above examples of use are within the scope of protection of the present patent, and are not limited to the basic principle of introducing a tracking bit line to realize an internal clock, and other additional functions are added by using the tracking bit line.
[0053] The embodiment introduces a tracking bit line in the eFuse memory, realizes an internal clock mode of read operation, and compared with an internal clock mode of delay generated by a fixed resistance capacitor, the tracking bit line technology can cover the influence of different bit line loads, different process angles and the like on the internal clock width, simplifies the design process of the circuit and the layout, guarantees the reliability of the internal clock end when all output bits have completed data readout, the internal clock width generated by the tracking bit line is shorter, data readout power consumption can be reduced to a greater extent, and the readout number of life of the storage unit is prolonged.
[0054] To realize the above idea, the embodiment further discloses an eFuse memory including the eFuse memory circuit structure as described above.
[0055] In summary, the above embodiment describes different configurations of the eFuse memory and the circuit structure thereof in detail. Of course, the above description is only a description of the preferred embodiment of the present application, and does not limit the scope of the present application in any way. The present application includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can easily deduce other embodiments from the above embodiments. Any modification or change made by those skilled in the art according to the above disclosure is within the protection scope of the claims.
Claims
1. An eFuse memory circuit structure, characterized in that: include: a plurality of first memory cells, each of the first memory cells comprising a first transistor and a first fuse resistor, wherein a drain of the first transistor is connected to one end of the first fuse resistor, a source of the first transistor is grounded, a gate of the first transistor is connected to a first word line, the other end of the first fuse resistor is connected to a first bit line, and the first word line is connected to a first sense amplifier; A column of second storage units is connected to the tracking bit line. The second storage units include a load unit and at least one tracking unit. The tracking unit includes a second transistor and a second fuse resistor. The load unit includes a third transistor and a third fuse resistor. The drain of the second transistor is connected to one end of the second fuse resistor, and the other end of the second fuse resistor is connected to the tracking bit line. The tracking bit line is connected to a tracking sensitive amplifier. The gate of the third transistor is grounded, the drain of the third transistor is connected to one end of the third fuse resistor, and the other end of the third fuse resistor is connected to the tracking bit line. The gate of the second transistor is connected to the tracking word line.
2. The eFuse memory circuit structure according to claim 1, wherein: The second fuse resistor in the tracking unit is a tracking resistor with a large resistance, and the resistance value is between the upper limit of the determination resistance for reading '1' data and the statistical lower limit of the fuse resistance after actual programming.
3. The eFuse memory circuit structure according to claim 1, wherein: Also includes: In the reading mode, the rising edge of the enable signal of the data reading module is triggered by the rising edge of the external clock, and the falling edge of the enable signal of the data reading module is controlled by the internal signal and may not be the same width as the external clock. The data reading can be completed and the data reading module can be closed before the external clock ends.
4. The eFuse memory circuit structure according to claim 3, wherein: The internal clock width is determined by the feedback signal generated by the tracking bit line.
5. The eFuse memory circuit structure according to claim 1, wherein: The load unit includes a plurality of third transistors and a plurality of third fuse resistors.
6. The eFuse memory circuit structure according to claim 5, wherein: The gates of the second transistors of some load units are connected to the test word line, and in the test mode, test programming and reading are selected as the test operation of the unit width data.
7. The eFuse memory circuit structure according to claim 1, wherein: A tracking unit is connected to the tracking bit line.
8. The eFuse memory circuit structure according to claim 1, wherein: At least two or more tracking units are connected to the tracking bit line, and the resistance values of the second fuse resistors are different to adjust the width of the internal clock.
9. The eFuse memory circuit structure according to claim 1, wherein: Also includes: The internal clock control module receives the rising edge of the clock signal and generates the rising edge of the sense amplifier enable signal. The tracking sense amplifier charges the tracking bit line and finally reads the '1' signal, and generates a feedback signal back to the internal clock control module, generating the falling edge of the sense amplifier enable signal and turning off all sense amplifiers.
10. An eFuse memory, characterized in that: include: The eFuse memory circuit structure according to any one of claims 1 to 9.